sb1250-mac.c 71 KB

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  1. /*
  2. * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation; either version 2
  7. * of the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. *
  19. * This driver is designed for the Broadcom SiByte SOC built-in
  20. * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
  21. */
  22. #include <linux/module.h>
  23. #include <linux/kernel.h>
  24. #include <linux/string.h>
  25. #include <linux/timer.h>
  26. #include <linux/errno.h>
  27. #include <linux/ioport.h>
  28. #include <linux/slab.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/skbuff.h>
  33. #include <linux/init.h>
  34. #include <linux/bitops.h>
  35. #include <asm/processor.h> /* Processor type for cache alignment. */
  36. #include <asm/io.h>
  37. #include <asm/cache.h>
  38. /* This is only here until the firmware is ready. In that case,
  39. the firmware leaves the ethernet address in the register for us. */
  40. #ifdef CONFIG_SIBYTE_STANDALONE
  41. #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
  42. #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
  43. #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
  44. #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
  45. #endif
  46. /* These identify the driver base version and may not be removed. */
  47. #if 0
  48. static char version1[] __devinitdata =
  49. "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
  50. #endif
  51. /* Operational parameters that usually are not changed. */
  52. #define CONFIG_SBMAC_COALESCE
  53. #define MAX_UNITS 4 /* More are supported, limit only on options */
  54. /* Time in jiffies before concluding the transmitter is hung. */
  55. #define TX_TIMEOUT (2*HZ)
  56. MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
  57. MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
  58. /* A few user-configurable values which may be modified when a driver
  59. module is loaded. */
  60. /* 1 normal messages, 0 quiet .. 7 verbose. */
  61. static int debug = 1;
  62. module_param(debug, int, S_IRUGO);
  63. MODULE_PARM_DESC(debug, "Debug messages");
  64. /* mii status msgs */
  65. static int noisy_mii = 1;
  66. module_param(noisy_mii, int, S_IRUGO);
  67. MODULE_PARM_DESC(noisy_mii, "MII status messages");
  68. /* Used to pass the media type, etc.
  69. Both 'options[]' and 'full_duplex[]' should exist for driver
  70. interoperability.
  71. The media type is usually passed in 'options[]'.
  72. */
  73. #ifdef MODULE
  74. static int options[MAX_UNITS] = {-1, -1, -1, -1};
  75. module_param_array(options, int, NULL, S_IRUGO);
  76. MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
  77. static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1};
  78. module_param_array(full_duplex, int, NULL, S_IRUGO);
  79. MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
  80. #endif
  81. #ifdef CONFIG_SBMAC_COALESCE
  82. static int int_pktcnt = 0;
  83. module_param(int_pktcnt, int, S_IRUGO);
  84. MODULE_PARM_DESC(int_pktcnt, "Packet count");
  85. static int int_timeout = 0;
  86. module_param(int_timeout, int, S_IRUGO);
  87. MODULE_PARM_DESC(int_timeout, "Timeout value");
  88. #endif
  89. #include <asm/sibyte/sb1250.h>
  90. #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  91. #include <asm/sibyte/bcm1480_regs.h>
  92. #include <asm/sibyte/bcm1480_int.h>
  93. #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
  94. #include <asm/sibyte/sb1250_regs.h>
  95. #include <asm/sibyte/sb1250_int.h>
  96. #else
  97. #error invalid SiByte MAC configuation
  98. #endif
  99. #include <asm/sibyte/sb1250_scd.h>
  100. #include <asm/sibyte/sb1250_mac.h>
  101. #include <asm/sibyte/sb1250_dma.h>
  102. #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  103. #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2))
  104. #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
  105. #define UNIT_INT(n) (K_INT_MAC_0 + (n))
  106. #else
  107. #error invalid SiByte MAC configuation
  108. #endif
  109. /**********************************************************************
  110. * Simple types
  111. ********************************************************************* */
  112. typedef enum { sbmac_speed_auto, sbmac_speed_10,
  113. sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
  114. typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
  115. sbmac_duplex_full } sbmac_duplex_t;
  116. typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
  117. sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
  118. typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
  119. sbmac_state_broken } sbmac_state_t;
  120. /**********************************************************************
  121. * Macros
  122. ********************************************************************* */
  123. #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
  124. (d)->sbdma_dscrtable : (d)->f+1)
  125. #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
  126. #define SBMAC_MAX_TXDESCR 32
  127. #define SBMAC_MAX_RXDESCR 32
  128. #define ETHER_ALIGN 2
  129. #define ETHER_ADDR_LEN 6
  130. #define ENET_PACKET_SIZE 1518
  131. /*#define ENET_PACKET_SIZE 9216 */
  132. /**********************************************************************
  133. * DMA Descriptor structure
  134. ********************************************************************* */
  135. typedef struct sbdmadscr_s {
  136. uint64_t dscr_a;
  137. uint64_t dscr_b;
  138. } sbdmadscr_t;
  139. typedef unsigned long paddr_t;
  140. /**********************************************************************
  141. * DMA Controller structure
  142. ********************************************************************* */
  143. typedef struct sbmacdma_s {
  144. /*
  145. * This stuff is used to identify the channel and the registers
  146. * associated with it.
  147. */
  148. struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */
  149. int sbdma_channel; /* channel number */
  150. int sbdma_txdir; /* direction (1=transmit) */
  151. int sbdma_maxdescr; /* total # of descriptors in ring */
  152. #ifdef CONFIG_SBMAC_COALESCE
  153. int sbdma_int_pktcnt; /* # descriptors rx/tx before interrupt*/
  154. int sbdma_int_timeout; /* # usec rx/tx interrupt */
  155. #endif
  156. volatile void __iomem *sbdma_config0; /* DMA config register 0 */
  157. volatile void __iomem *sbdma_config1; /* DMA config register 1 */
  158. volatile void __iomem *sbdma_dscrbase; /* Descriptor base address */
  159. volatile void __iomem *sbdma_dscrcnt; /* Descriptor count register */
  160. volatile void __iomem *sbdma_curdscr; /* current descriptor address */
  161. /*
  162. * This stuff is for maintenance of the ring
  163. */
  164. sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */
  165. sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */
  166. struct sk_buff **sbdma_ctxtable; /* context table, one per descr */
  167. paddr_t sbdma_dscrtable_phys; /* and also the phys addr */
  168. sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */
  169. sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */
  170. } sbmacdma_t;
  171. /**********************************************************************
  172. * Ethernet softc structure
  173. ********************************************************************* */
  174. struct sbmac_softc {
  175. /*
  176. * Linux-specific things
  177. */
  178. struct net_device *sbm_dev; /* pointer to linux device */
  179. spinlock_t sbm_lock; /* spin lock */
  180. struct timer_list sbm_timer; /* for monitoring MII */
  181. struct net_device_stats sbm_stats;
  182. int sbm_devflags; /* current device flags */
  183. int sbm_phy_oldbmsr;
  184. int sbm_phy_oldanlpar;
  185. int sbm_phy_oldk1stsr;
  186. int sbm_phy_oldlinkstat;
  187. int sbm_buffersize;
  188. unsigned char sbm_phys[2];
  189. /*
  190. * Controller-specific things
  191. */
  192. void __iomem *sbm_base; /* MAC's base address */
  193. sbmac_state_t sbm_state; /* current state */
  194. volatile void __iomem *sbm_macenable; /* MAC Enable Register */
  195. volatile void __iomem *sbm_maccfg; /* MAC Configuration Register */
  196. volatile void __iomem *sbm_fifocfg; /* FIFO configuration register */
  197. volatile void __iomem *sbm_framecfg; /* Frame configuration register */
  198. volatile void __iomem *sbm_rxfilter; /* receive filter register */
  199. volatile void __iomem *sbm_isr; /* Interrupt status register */
  200. volatile void __iomem *sbm_imr; /* Interrupt mask register */
  201. volatile void __iomem *sbm_mdio; /* MDIO register */
  202. sbmac_speed_t sbm_speed; /* current speed */
  203. sbmac_duplex_t sbm_duplex; /* current duplex */
  204. sbmac_fc_t sbm_fc; /* current flow control setting */
  205. unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
  206. sbmacdma_t sbm_txdma; /* for now, only use channel 0 */
  207. sbmacdma_t sbm_rxdma;
  208. int rx_hw_checksum;
  209. int sbe_idx;
  210. };
  211. /**********************************************************************
  212. * Externs
  213. ********************************************************************* */
  214. /**********************************************************************
  215. * Prototypes
  216. ********************************************************************* */
  217. static void sbdma_initctx(sbmacdma_t *d,
  218. struct sbmac_softc *s,
  219. int chan,
  220. int txrx,
  221. int maxdescr);
  222. static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
  223. static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
  224. static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
  225. static void sbdma_emptyring(sbmacdma_t *d);
  226. static void sbdma_fillring(sbmacdma_t *d);
  227. static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
  228. static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
  229. static int sbmac_initctx(struct sbmac_softc *s);
  230. static void sbmac_channel_start(struct sbmac_softc *s);
  231. static void sbmac_channel_stop(struct sbmac_softc *s);
  232. static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
  233. static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
  234. static uint64_t sbmac_addr2reg(unsigned char *ptr);
  235. static irqreturn_t sbmac_intr(int irq,void *dev_instance);
  236. static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
  237. static void sbmac_setmulti(struct sbmac_softc *sc);
  238. static int sbmac_init(struct net_device *dev, int idx);
  239. static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
  240. static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
  241. static int sbmac_open(struct net_device *dev);
  242. static void sbmac_timer(unsigned long data);
  243. static void sbmac_tx_timeout (struct net_device *dev);
  244. static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
  245. static void sbmac_set_rx_mode(struct net_device *dev);
  246. static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  247. static int sbmac_close(struct net_device *dev);
  248. static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
  249. static int sbmac_mii_probe(struct net_device *dev);
  250. static void sbmac_mii_sync(struct sbmac_softc *s);
  251. static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
  252. static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
  253. static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
  254. unsigned int regval);
  255. /**********************************************************************
  256. * Globals
  257. ********************************************************************* */
  258. static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
  259. /**********************************************************************
  260. * MDIO constants
  261. ********************************************************************* */
  262. #define MII_COMMAND_START 0x01
  263. #define MII_COMMAND_READ 0x02
  264. #define MII_COMMAND_WRITE 0x01
  265. #define MII_COMMAND_ACK 0x02
  266. #define BMCR_RESET 0x8000
  267. #define BMCR_LOOPBACK 0x4000
  268. #define BMCR_SPEED0 0x2000
  269. #define BMCR_ANENABLE 0x1000
  270. #define BMCR_POWERDOWN 0x0800
  271. #define BMCR_ISOLATE 0x0400
  272. #define BMCR_RESTARTAN 0x0200
  273. #define BMCR_DUPLEX 0x0100
  274. #define BMCR_COLTEST 0x0080
  275. #define BMCR_SPEED1 0x0040
  276. #define BMCR_SPEED1000 BMCR_SPEED1
  277. #define BMCR_SPEED100 BMCR_SPEED0
  278. #define BMCR_SPEED10 0
  279. #define BMSR_100BT4 0x8000
  280. #define BMSR_100BT_FDX 0x4000
  281. #define BMSR_100BT_HDX 0x2000
  282. #define BMSR_10BT_FDX 0x1000
  283. #define BMSR_10BT_HDX 0x0800
  284. #define BMSR_100BT2_FDX 0x0400
  285. #define BMSR_100BT2_HDX 0x0200
  286. #define BMSR_1000BT_XSR 0x0100
  287. #define BMSR_PRESUP 0x0040
  288. #define BMSR_ANCOMPLT 0x0020
  289. #define BMSR_REMFAULT 0x0010
  290. #define BMSR_AUTONEG 0x0008
  291. #define BMSR_LINKSTAT 0x0004
  292. #define BMSR_JABDETECT 0x0002
  293. #define BMSR_EXTCAPAB 0x0001
  294. #define PHYIDR1 0x2000
  295. #define PHYIDR2 0x5C60
  296. #define ANAR_NP 0x8000
  297. #define ANAR_RF 0x2000
  298. #define ANAR_ASYPAUSE 0x0800
  299. #define ANAR_PAUSE 0x0400
  300. #define ANAR_T4 0x0200
  301. #define ANAR_TXFD 0x0100
  302. #define ANAR_TXHD 0x0080
  303. #define ANAR_10FD 0x0040
  304. #define ANAR_10HD 0x0020
  305. #define ANAR_PSB 0x0001
  306. #define ANLPAR_NP 0x8000
  307. #define ANLPAR_ACK 0x4000
  308. #define ANLPAR_RF 0x2000
  309. #define ANLPAR_ASYPAUSE 0x0800
  310. #define ANLPAR_PAUSE 0x0400
  311. #define ANLPAR_T4 0x0200
  312. #define ANLPAR_TXFD 0x0100
  313. #define ANLPAR_TXHD 0x0080
  314. #define ANLPAR_10FD 0x0040
  315. #define ANLPAR_10HD 0x0020
  316. #define ANLPAR_PSB 0x0001 /* 802.3 */
  317. #define ANER_PDF 0x0010
  318. #define ANER_LPNPABLE 0x0008
  319. #define ANER_NPABLE 0x0004
  320. #define ANER_PAGERX 0x0002
  321. #define ANER_LPANABLE 0x0001
  322. #define ANNPTR_NP 0x8000
  323. #define ANNPTR_MP 0x2000
  324. #define ANNPTR_ACK2 0x1000
  325. #define ANNPTR_TOGTX 0x0800
  326. #define ANNPTR_CODE 0x0008
  327. #define ANNPRR_NP 0x8000
  328. #define ANNPRR_MP 0x2000
  329. #define ANNPRR_ACK3 0x1000
  330. #define ANNPRR_TOGTX 0x0800
  331. #define ANNPRR_CODE 0x0008
  332. #define K1TCR_TESTMODE 0x0000
  333. #define K1TCR_MSMCE 0x1000
  334. #define K1TCR_MSCV 0x0800
  335. #define K1TCR_RPTR 0x0400
  336. #define K1TCR_1000BT_FDX 0x200
  337. #define K1TCR_1000BT_HDX 0x100
  338. #define K1STSR_MSMCFLT 0x8000
  339. #define K1STSR_MSCFGRES 0x4000
  340. #define K1STSR_LRSTAT 0x2000
  341. #define K1STSR_RRSTAT 0x1000
  342. #define K1STSR_LP1KFD 0x0800
  343. #define K1STSR_LP1KHD 0x0400
  344. #define K1STSR_LPASMDIR 0x0200
  345. #define K1SCR_1KX_FDX 0x8000
  346. #define K1SCR_1KX_HDX 0x4000
  347. #define K1SCR_1KT_FDX 0x2000
  348. #define K1SCR_1KT_HDX 0x1000
  349. #define STRAP_PHY1 0x0800
  350. #define STRAP_NCMODE 0x0400
  351. #define STRAP_MANMSCFG 0x0200
  352. #define STRAP_ANENABLE 0x0100
  353. #define STRAP_MSVAL 0x0080
  354. #define STRAP_1KHDXADV 0x0010
  355. #define STRAP_1KFDXADV 0x0008
  356. #define STRAP_100ADV 0x0004
  357. #define STRAP_SPEEDSEL 0x0000
  358. #define STRAP_SPEED100 0x0001
  359. #define PHYSUP_SPEED1000 0x10
  360. #define PHYSUP_SPEED100 0x08
  361. #define PHYSUP_SPEED10 0x00
  362. #define PHYSUP_LINKUP 0x04
  363. #define PHYSUP_FDX 0x02
  364. #define MII_BMCR 0x00 /* Basic mode control register (rw) */
  365. #define MII_BMSR 0x01 /* Basic mode status register (ro) */
  366. #define MII_PHYIDR1 0x02
  367. #define MII_PHYIDR2 0x03
  368. #define MII_K1STSR 0x0A /* 1K Status Register (ro) */
  369. #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
  370. #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
  371. #define ENABLE 1
  372. #define DISABLE 0
  373. /**********************************************************************
  374. * SBMAC_MII_SYNC(s)
  375. *
  376. * Synchronize with the MII - send a pattern of bits to the MII
  377. * that will guarantee that it is ready to accept a command.
  378. *
  379. * Input parameters:
  380. * s - sbmac structure
  381. *
  382. * Return value:
  383. * nothing
  384. ********************************************************************* */
  385. static void sbmac_mii_sync(struct sbmac_softc *s)
  386. {
  387. int cnt;
  388. uint64_t bits;
  389. int mac_mdio_genc;
  390. mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
  391. bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
  392. __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
  393. for (cnt = 0; cnt < 32; cnt++) {
  394. __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
  395. __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
  396. }
  397. }
  398. /**********************************************************************
  399. * SBMAC_MII_SENDDATA(s,data,bitcnt)
  400. *
  401. * Send some bits to the MII. The bits to be sent are right-
  402. * justified in the 'data' parameter.
  403. *
  404. * Input parameters:
  405. * s - sbmac structure
  406. * data - data to send
  407. * bitcnt - number of bits to send
  408. ********************************************************************* */
  409. static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
  410. {
  411. int i;
  412. uint64_t bits;
  413. unsigned int curmask;
  414. int mac_mdio_genc;
  415. mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
  416. bits = M_MAC_MDIO_DIR_OUTPUT;
  417. __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
  418. curmask = 1 << (bitcnt - 1);
  419. for (i = 0; i < bitcnt; i++) {
  420. if (data & curmask)
  421. bits |= M_MAC_MDIO_OUT;
  422. else bits &= ~M_MAC_MDIO_OUT;
  423. __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
  424. __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
  425. __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
  426. curmask >>= 1;
  427. }
  428. }
  429. /**********************************************************************
  430. * SBMAC_MII_READ(s,phyaddr,regidx)
  431. *
  432. * Read a PHY register.
  433. *
  434. * Input parameters:
  435. * s - sbmac structure
  436. * phyaddr - PHY's address
  437. * regidx = index of register to read
  438. *
  439. * Return value:
  440. * value read, or 0 if an error occurred.
  441. ********************************************************************* */
  442. static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
  443. {
  444. int idx;
  445. int error;
  446. int regval;
  447. int mac_mdio_genc;
  448. /*
  449. * Synchronize ourselves so that the PHY knows the next
  450. * thing coming down is a command
  451. */
  452. sbmac_mii_sync(s);
  453. /*
  454. * Send the data to the PHY. The sequence is
  455. * a "start" command (2 bits)
  456. * a "read" command (2 bits)
  457. * the PHY addr (5 bits)
  458. * the register index (5 bits)
  459. */
  460. sbmac_mii_senddata(s,MII_COMMAND_START, 2);
  461. sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
  462. sbmac_mii_senddata(s,phyaddr, 5);
  463. sbmac_mii_senddata(s,regidx, 5);
  464. mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
  465. /*
  466. * Switch the port around without a clock transition.
  467. */
  468. __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
  469. /*
  470. * Send out a clock pulse to signal we want the status
  471. */
  472. __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
  473. __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
  474. /*
  475. * If an error occurred, the PHY will signal '1' back
  476. */
  477. error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN;
  478. /*
  479. * Issue an 'idle' clock pulse, but keep the direction
  480. * the same.
  481. */
  482. __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
  483. __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
  484. regval = 0;
  485. for (idx = 0; idx < 16; idx++) {
  486. regval <<= 1;
  487. if (error == 0) {
  488. if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN)
  489. regval |= 1;
  490. }
  491. __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
  492. __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
  493. }
  494. /* Switch back to output */
  495. __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
  496. if (error == 0)
  497. return regval;
  498. return 0;
  499. }
  500. /**********************************************************************
  501. * SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
  502. *
  503. * Write a value to a PHY register.
  504. *
  505. * Input parameters:
  506. * s - sbmac structure
  507. * phyaddr - PHY to use
  508. * regidx - register within the PHY
  509. * regval - data to write to register
  510. *
  511. * Return value:
  512. * nothing
  513. ********************************************************************* */
  514. static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
  515. unsigned int regval)
  516. {
  517. int mac_mdio_genc;
  518. sbmac_mii_sync(s);
  519. sbmac_mii_senddata(s,MII_COMMAND_START,2);
  520. sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
  521. sbmac_mii_senddata(s,phyaddr, 5);
  522. sbmac_mii_senddata(s,regidx, 5);
  523. sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
  524. sbmac_mii_senddata(s,regval,16);
  525. mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
  526. __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
  527. }
  528. /**********************************************************************
  529. * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
  530. *
  531. * Initialize a DMA channel context. Since there are potentially
  532. * eight DMA channels per MAC, it's nice to do this in a standard
  533. * way.
  534. *
  535. * Input parameters:
  536. * d - sbmacdma_t structure (DMA channel context)
  537. * s - sbmac_softc structure (pointer to a MAC)
  538. * chan - channel number (0..1 right now)
  539. * txrx - Identifies DMA_TX or DMA_RX for channel direction
  540. * maxdescr - number of descriptors
  541. *
  542. * Return value:
  543. * nothing
  544. ********************************************************************* */
  545. static void sbdma_initctx(sbmacdma_t *d,
  546. struct sbmac_softc *s,
  547. int chan,
  548. int txrx,
  549. int maxdescr)
  550. {
  551. /*
  552. * Save away interesting stuff in the structure
  553. */
  554. d->sbdma_eth = s;
  555. d->sbdma_channel = chan;
  556. d->sbdma_txdir = txrx;
  557. #if 0
  558. /* RMON clearing */
  559. s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
  560. #endif
  561. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
  562. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
  563. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
  564. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
  565. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
  566. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
  567. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
  568. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
  569. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
  570. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
  571. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
  572. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
  573. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
  574. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
  575. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
  576. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
  577. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
  578. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
  579. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
  580. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
  581. __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
  582. /*
  583. * initialize register pointers
  584. */
  585. d->sbdma_config0 =
  586. s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
  587. d->sbdma_config1 =
  588. s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
  589. d->sbdma_dscrbase =
  590. s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
  591. d->sbdma_dscrcnt =
  592. s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
  593. d->sbdma_curdscr =
  594. s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
  595. /*
  596. * Allocate memory for the ring
  597. */
  598. d->sbdma_maxdescr = maxdescr;
  599. d->sbdma_dscrtable = (sbdmadscr_t *)
  600. kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL);
  601. /*
  602. * The descriptor table must be aligned to at least 16 bytes or the
  603. * MAC will corrupt it.
  604. */
  605. d->sbdma_dscrtable = (sbdmadscr_t *)
  606. ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t));
  607. memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
  608. d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
  609. d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
  610. /*
  611. * And context table
  612. */
  613. d->sbdma_ctxtable = (struct sk_buff **)
  614. kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
  615. memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
  616. #ifdef CONFIG_SBMAC_COALESCE
  617. /*
  618. * Setup Rx/Tx DMA coalescing defaults
  619. */
  620. if ( int_pktcnt ) {
  621. d->sbdma_int_pktcnt = int_pktcnt;
  622. } else {
  623. d->sbdma_int_pktcnt = 1;
  624. }
  625. if ( int_timeout ) {
  626. d->sbdma_int_timeout = int_timeout;
  627. } else {
  628. d->sbdma_int_timeout = 0;
  629. }
  630. #endif
  631. }
  632. /**********************************************************************
  633. * SBDMA_CHANNEL_START(d)
  634. *
  635. * Initialize the hardware registers for a DMA channel.
  636. *
  637. * Input parameters:
  638. * d - DMA channel to init (context must be previously init'd
  639. * rxtx - DMA_RX or DMA_TX depending on what type of channel
  640. *
  641. * Return value:
  642. * nothing
  643. ********************************************************************* */
  644. static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
  645. {
  646. /*
  647. * Turn on the DMA channel
  648. */
  649. #ifdef CONFIG_SBMAC_COALESCE
  650. __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
  651. 0, d->sbdma_config1);
  652. __raw_writeq(M_DMA_EOP_INT_EN |
  653. V_DMA_RINGSZ(d->sbdma_maxdescr) |
  654. V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
  655. 0, d->sbdma_config0);
  656. #else
  657. __raw_writeq(0, d->sbdma_config1);
  658. __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
  659. 0, d->sbdma_config0);
  660. #endif
  661. __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
  662. /*
  663. * Initialize ring pointers
  664. */
  665. d->sbdma_addptr = d->sbdma_dscrtable;
  666. d->sbdma_remptr = d->sbdma_dscrtable;
  667. }
  668. /**********************************************************************
  669. * SBDMA_CHANNEL_STOP(d)
  670. *
  671. * Initialize the hardware registers for a DMA channel.
  672. *
  673. * Input parameters:
  674. * d - DMA channel to init (context must be previously init'd
  675. *
  676. * Return value:
  677. * nothing
  678. ********************************************************************* */
  679. static void sbdma_channel_stop(sbmacdma_t *d)
  680. {
  681. /*
  682. * Turn off the DMA channel
  683. */
  684. __raw_writeq(0, d->sbdma_config1);
  685. __raw_writeq(0, d->sbdma_dscrbase);
  686. __raw_writeq(0, d->sbdma_config0);
  687. /*
  688. * Zero ring pointers
  689. */
  690. d->sbdma_addptr = NULL;
  691. d->sbdma_remptr = NULL;
  692. }
  693. static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
  694. {
  695. unsigned long addr;
  696. unsigned long newaddr;
  697. addr = (unsigned long) skb->data;
  698. newaddr = (addr + power2 - 1) & ~(power2 - 1);
  699. skb_reserve(skb,newaddr-addr+offset);
  700. }
  701. /**********************************************************************
  702. * SBDMA_ADD_RCVBUFFER(d,sb)
  703. *
  704. * Add a buffer to the specified DMA channel. For receive channels,
  705. * this queues a buffer for inbound packets.
  706. *
  707. * Input parameters:
  708. * d - DMA channel descriptor
  709. * sb - sk_buff to add, or NULL if we should allocate one
  710. *
  711. * Return value:
  712. * 0 if buffer could not be added (ring is full)
  713. * 1 if buffer added successfully
  714. ********************************************************************* */
  715. static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
  716. {
  717. sbdmadscr_t *dsc;
  718. sbdmadscr_t *nextdsc;
  719. struct sk_buff *sb_new = NULL;
  720. int pktsize = ENET_PACKET_SIZE;
  721. /* get pointer to our current place in the ring */
  722. dsc = d->sbdma_addptr;
  723. nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
  724. /*
  725. * figure out if the ring is full - if the next descriptor
  726. * is the same as the one that we're going to remove from
  727. * the ring, the ring is full
  728. */
  729. if (nextdsc == d->sbdma_remptr) {
  730. return -ENOSPC;
  731. }
  732. /*
  733. * Allocate a sk_buff if we don't already have one.
  734. * If we do have an sk_buff, reset it so that it's empty.
  735. *
  736. * Note: sk_buffs don't seem to be guaranteed to have any sort
  737. * of alignment when they are allocated. Therefore, allocate enough
  738. * extra space to make sure that:
  739. *
  740. * 1. the data does not start in the middle of a cache line.
  741. * 2. The data does not end in the middle of a cache line
  742. * 3. The buffer can be aligned such that the IP addresses are
  743. * naturally aligned.
  744. *
  745. * Remember, the SOCs MAC writes whole cache lines at a time,
  746. * without reading the old contents first. So, if the sk_buff's
  747. * data portion starts in the middle of a cache line, the SOC
  748. * DMA will trash the beginning (and ending) portions.
  749. */
  750. if (sb == NULL) {
  751. sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
  752. if (sb_new == NULL) {
  753. printk(KERN_INFO "%s: sk_buff allocation failed\n",
  754. d->sbdma_eth->sbm_dev->name);
  755. return -ENOBUFS;
  756. }
  757. sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
  758. /* mark skbuff owned by our device */
  759. sb_new->dev = d->sbdma_eth->sbm_dev;
  760. }
  761. else {
  762. sb_new = sb;
  763. /*
  764. * nothing special to reinit buffer, it's already aligned
  765. * and sb->data already points to a good place.
  766. */
  767. }
  768. /*
  769. * fill in the descriptor
  770. */
  771. #ifdef CONFIG_SBMAC_COALESCE
  772. /*
  773. * Do not interrupt per DMA transfer.
  774. */
  775. dsc->dscr_a = virt_to_phys(sb_new->data) |
  776. V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
  777. #else
  778. dsc->dscr_a = virt_to_phys(sb_new->data) |
  779. V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
  780. M_DMA_DSCRA_INTERRUPT;
  781. #endif
  782. /* receiving: no options */
  783. dsc->dscr_b = 0;
  784. /*
  785. * fill in the context
  786. */
  787. d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
  788. /*
  789. * point at next packet
  790. */
  791. d->sbdma_addptr = nextdsc;
  792. /*
  793. * Give the buffer to the DMA engine.
  794. */
  795. __raw_writeq(1, d->sbdma_dscrcnt);
  796. return 0; /* we did it */
  797. }
  798. /**********************************************************************
  799. * SBDMA_ADD_TXBUFFER(d,sb)
  800. *
  801. * Add a transmit buffer to the specified DMA channel, causing a
  802. * transmit to start.
  803. *
  804. * Input parameters:
  805. * d - DMA channel descriptor
  806. * sb - sk_buff to add
  807. *
  808. * Return value:
  809. * 0 transmit queued successfully
  810. * otherwise error code
  811. ********************************************************************* */
  812. static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
  813. {
  814. sbdmadscr_t *dsc;
  815. sbdmadscr_t *nextdsc;
  816. uint64_t phys;
  817. uint64_t ncb;
  818. int length;
  819. /* get pointer to our current place in the ring */
  820. dsc = d->sbdma_addptr;
  821. nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
  822. /*
  823. * figure out if the ring is full - if the next descriptor
  824. * is the same as the one that we're going to remove from
  825. * the ring, the ring is full
  826. */
  827. if (nextdsc == d->sbdma_remptr) {
  828. return -ENOSPC;
  829. }
  830. /*
  831. * Under Linux, it's not necessary to copy/coalesce buffers
  832. * like it is on NetBSD. We think they're all contiguous,
  833. * but that may not be true for GBE.
  834. */
  835. length = sb->len;
  836. /*
  837. * fill in the descriptor. Note that the number of cache
  838. * blocks in the descriptor is the number of blocks
  839. * *spanned*, so we need to add in the offset (if any)
  840. * while doing the calculation.
  841. */
  842. phys = virt_to_phys(sb->data);
  843. ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
  844. dsc->dscr_a = phys |
  845. V_DMA_DSCRA_A_SIZE(ncb) |
  846. #ifndef CONFIG_SBMAC_COALESCE
  847. M_DMA_DSCRA_INTERRUPT |
  848. #endif
  849. M_DMA_ETHTX_SOP;
  850. /* transmitting: set outbound options and length */
  851. dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
  852. V_DMA_DSCRB_PKT_SIZE(length);
  853. /*
  854. * fill in the context
  855. */
  856. d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
  857. /*
  858. * point at next packet
  859. */
  860. d->sbdma_addptr = nextdsc;
  861. /*
  862. * Give the buffer to the DMA engine.
  863. */
  864. __raw_writeq(1, d->sbdma_dscrcnt);
  865. return 0; /* we did it */
  866. }
  867. /**********************************************************************
  868. * SBDMA_EMPTYRING(d)
  869. *
  870. * Free all allocated sk_buffs on the specified DMA channel;
  871. *
  872. * Input parameters:
  873. * d - DMA channel
  874. *
  875. * Return value:
  876. * nothing
  877. ********************************************************************* */
  878. static void sbdma_emptyring(sbmacdma_t *d)
  879. {
  880. int idx;
  881. struct sk_buff *sb;
  882. for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
  883. sb = d->sbdma_ctxtable[idx];
  884. if (sb) {
  885. dev_kfree_skb(sb);
  886. d->sbdma_ctxtable[idx] = NULL;
  887. }
  888. }
  889. }
  890. /**********************************************************************
  891. * SBDMA_FILLRING(d)
  892. *
  893. * Fill the specified DMA channel (must be receive channel)
  894. * with sk_buffs
  895. *
  896. * Input parameters:
  897. * d - DMA channel
  898. *
  899. * Return value:
  900. * nothing
  901. ********************************************************************* */
  902. static void sbdma_fillring(sbmacdma_t *d)
  903. {
  904. int idx;
  905. for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
  906. if (sbdma_add_rcvbuffer(d,NULL) != 0)
  907. break;
  908. }
  909. }
  910. /**********************************************************************
  911. * SBDMA_RX_PROCESS(sc,d)
  912. *
  913. * Process "completed" receive buffers on the specified DMA channel.
  914. * Note that this isn't really ideal for priority channels, since
  915. * it processes all of the packets on a given channel before
  916. * returning.
  917. *
  918. * Input parameters:
  919. * sc - softc structure
  920. * d - DMA channel context
  921. *
  922. * Return value:
  923. * nothing
  924. ********************************************************************* */
  925. static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
  926. {
  927. int curidx;
  928. int hwidx;
  929. sbdmadscr_t *dsc;
  930. struct sk_buff *sb;
  931. int len;
  932. for (;;) {
  933. /*
  934. * figure out where we are (as an index) and where
  935. * the hardware is (also as an index)
  936. *
  937. * This could be done faster if (for example) the
  938. * descriptor table was page-aligned and contiguous in
  939. * both virtual and physical memory -- you could then
  940. * just compare the low-order bits of the virtual address
  941. * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
  942. */
  943. curidx = d->sbdma_remptr - d->sbdma_dscrtable;
  944. hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
  945. d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
  946. /*
  947. * If they're the same, that means we've processed all
  948. * of the descriptors up to (but not including) the one that
  949. * the hardware is working on right now.
  950. */
  951. if (curidx == hwidx)
  952. break;
  953. /*
  954. * Otherwise, get the packet's sk_buff ptr back
  955. */
  956. dsc = &(d->sbdma_dscrtable[curidx]);
  957. sb = d->sbdma_ctxtable[curidx];
  958. d->sbdma_ctxtable[curidx] = NULL;
  959. len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
  960. /*
  961. * Check packet status. If good, process it.
  962. * If not, silently drop it and put it back on the
  963. * receive ring.
  964. */
  965. if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
  966. /*
  967. * Add a new buffer to replace the old one. If we fail
  968. * to allocate a buffer, we're going to drop this
  969. * packet and put it right back on the receive ring.
  970. */
  971. if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
  972. sc->sbm_stats.rx_dropped++;
  973. sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
  974. } else {
  975. /*
  976. * Set length into the packet
  977. */
  978. skb_put(sb,len);
  979. /*
  980. * Buffer has been replaced on the
  981. * receive ring. Pass the buffer to
  982. * the kernel
  983. */
  984. sc->sbm_stats.rx_bytes += len;
  985. sc->sbm_stats.rx_packets++;
  986. sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
  987. /* Check hw IPv4/TCP checksum if supported */
  988. if (sc->rx_hw_checksum == ENABLE) {
  989. if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
  990. !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
  991. sb->ip_summed = CHECKSUM_UNNECESSARY;
  992. /* don't need to set sb->csum */
  993. } else {
  994. sb->ip_summed = CHECKSUM_NONE;
  995. }
  996. }
  997. netif_rx(sb);
  998. }
  999. } else {
  1000. /*
  1001. * Packet was mangled somehow. Just drop it and
  1002. * put it back on the receive ring.
  1003. */
  1004. sc->sbm_stats.rx_errors++;
  1005. sbdma_add_rcvbuffer(d,sb);
  1006. }
  1007. /*
  1008. * .. and advance to the next buffer.
  1009. */
  1010. d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
  1011. }
  1012. }
  1013. /**********************************************************************
  1014. * SBDMA_TX_PROCESS(sc,d)
  1015. *
  1016. * Process "completed" transmit buffers on the specified DMA channel.
  1017. * This is normally called within the interrupt service routine.
  1018. * Note that this isn't really ideal for priority channels, since
  1019. * it processes all of the packets on a given channel before
  1020. * returning.
  1021. *
  1022. * Input parameters:
  1023. * sc - softc structure
  1024. * d - DMA channel context
  1025. *
  1026. * Return value:
  1027. * nothing
  1028. ********************************************************************* */
  1029. static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
  1030. {
  1031. int curidx;
  1032. int hwidx;
  1033. sbdmadscr_t *dsc;
  1034. struct sk_buff *sb;
  1035. unsigned long flags;
  1036. spin_lock_irqsave(&(sc->sbm_lock), flags);
  1037. for (;;) {
  1038. /*
  1039. * figure out where we are (as an index) and where
  1040. * the hardware is (also as an index)
  1041. *
  1042. * This could be done faster if (for example) the
  1043. * descriptor table was page-aligned and contiguous in
  1044. * both virtual and physical memory -- you could then
  1045. * just compare the low-order bits of the virtual address
  1046. * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
  1047. */
  1048. curidx = d->sbdma_remptr - d->sbdma_dscrtable;
  1049. hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
  1050. d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
  1051. /*
  1052. * If they're the same, that means we've processed all
  1053. * of the descriptors up to (but not including) the one that
  1054. * the hardware is working on right now.
  1055. */
  1056. if (curidx == hwidx)
  1057. break;
  1058. /*
  1059. * Otherwise, get the packet's sk_buff ptr back
  1060. */
  1061. dsc = &(d->sbdma_dscrtable[curidx]);
  1062. sb = d->sbdma_ctxtable[curidx];
  1063. d->sbdma_ctxtable[curidx] = NULL;
  1064. /*
  1065. * Stats
  1066. */
  1067. sc->sbm_stats.tx_bytes += sb->len;
  1068. sc->sbm_stats.tx_packets++;
  1069. /*
  1070. * for transmits, we just free buffers.
  1071. */
  1072. dev_kfree_skb_irq(sb);
  1073. /*
  1074. * .. and advance to the next buffer.
  1075. */
  1076. d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
  1077. }
  1078. /*
  1079. * Decide if we should wake up the protocol or not.
  1080. * Other drivers seem to do this when we reach a low
  1081. * watermark on the transmit queue.
  1082. */
  1083. netif_wake_queue(d->sbdma_eth->sbm_dev);
  1084. spin_unlock_irqrestore(&(sc->sbm_lock), flags);
  1085. }
  1086. /**********************************************************************
  1087. * SBMAC_INITCTX(s)
  1088. *
  1089. * Initialize an Ethernet context structure - this is called
  1090. * once per MAC on the 1250. Memory is allocated here, so don't
  1091. * call it again from inside the ioctl routines that bring the
  1092. * interface up/down
  1093. *
  1094. * Input parameters:
  1095. * s - sbmac context structure
  1096. *
  1097. * Return value:
  1098. * 0
  1099. ********************************************************************* */
  1100. static int sbmac_initctx(struct sbmac_softc *s)
  1101. {
  1102. /*
  1103. * figure out the addresses of some ports
  1104. */
  1105. s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
  1106. s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
  1107. s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
  1108. s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG;
  1109. s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG;
  1110. s->sbm_isr = s->sbm_base + R_MAC_STATUS;
  1111. s->sbm_imr = s->sbm_base + R_MAC_INT_MASK;
  1112. s->sbm_mdio = s->sbm_base + R_MAC_MDIO;
  1113. s->sbm_phys[0] = 1;
  1114. s->sbm_phys[1] = 0;
  1115. s->sbm_phy_oldbmsr = 0;
  1116. s->sbm_phy_oldanlpar = 0;
  1117. s->sbm_phy_oldk1stsr = 0;
  1118. s->sbm_phy_oldlinkstat = 0;
  1119. /*
  1120. * Initialize the DMA channels. Right now, only one per MAC is used
  1121. * Note: Only do this _once_, as it allocates memory from the kernel!
  1122. */
  1123. sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
  1124. sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
  1125. /*
  1126. * initial state is OFF
  1127. */
  1128. s->sbm_state = sbmac_state_off;
  1129. /*
  1130. * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
  1131. */
  1132. s->sbm_speed = sbmac_speed_10;
  1133. s->sbm_duplex = sbmac_duplex_half;
  1134. s->sbm_fc = sbmac_fc_disabled;
  1135. return 0;
  1136. }
  1137. static void sbdma_uninitctx(struct sbmacdma_s *d)
  1138. {
  1139. if (d->sbdma_dscrtable) {
  1140. kfree(d->sbdma_dscrtable);
  1141. d->sbdma_dscrtable = NULL;
  1142. }
  1143. if (d->sbdma_ctxtable) {
  1144. kfree(d->sbdma_ctxtable);
  1145. d->sbdma_ctxtable = NULL;
  1146. }
  1147. }
  1148. static void sbmac_uninitctx(struct sbmac_softc *sc)
  1149. {
  1150. sbdma_uninitctx(&(sc->sbm_txdma));
  1151. sbdma_uninitctx(&(sc->sbm_rxdma));
  1152. }
  1153. /**********************************************************************
  1154. * SBMAC_CHANNEL_START(s)
  1155. *
  1156. * Start packet processing on this MAC.
  1157. *
  1158. * Input parameters:
  1159. * s - sbmac structure
  1160. *
  1161. * Return value:
  1162. * nothing
  1163. ********************************************************************* */
  1164. static void sbmac_channel_start(struct sbmac_softc *s)
  1165. {
  1166. uint64_t reg;
  1167. volatile void __iomem *port;
  1168. uint64_t cfg,fifo,framecfg;
  1169. int idx, th_value;
  1170. /*
  1171. * Don't do this if running
  1172. */
  1173. if (s->sbm_state == sbmac_state_on)
  1174. return;
  1175. /*
  1176. * Bring the controller out of reset, but leave it off.
  1177. */
  1178. __raw_writeq(0, s->sbm_macenable);
  1179. /*
  1180. * Ignore all received packets
  1181. */
  1182. __raw_writeq(0, s->sbm_rxfilter);
  1183. /*
  1184. * Calculate values for various control registers.
  1185. */
  1186. cfg = M_MAC_RETRY_EN |
  1187. M_MAC_TX_HOLD_SOP_EN |
  1188. V_MAC_TX_PAUSE_CNT_16K |
  1189. M_MAC_AP_STAT_EN |
  1190. M_MAC_FAST_SYNC |
  1191. M_MAC_SS_EN |
  1192. 0;
  1193. /*
  1194. * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
  1195. * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
  1196. * Use a larger RD_THRSH for gigabit
  1197. */
  1198. if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
  1199. th_value = 28;
  1200. else
  1201. th_value = 64;
  1202. fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
  1203. ((s->sbm_speed == sbmac_speed_1000)
  1204. ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
  1205. V_MAC_TX_RL_THRSH(4) |
  1206. V_MAC_RX_PL_THRSH(4) |
  1207. V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
  1208. V_MAC_RX_PL_THRSH(4) |
  1209. V_MAC_RX_RL_THRSH(8) |
  1210. 0;
  1211. framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
  1212. V_MAC_MAX_FRAMESZ_DEFAULT |
  1213. V_MAC_BACKOFF_SEL(1);
  1214. /*
  1215. * Clear out the hash address map
  1216. */
  1217. port = s->sbm_base + R_MAC_HASH_BASE;
  1218. for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
  1219. __raw_writeq(0, port);
  1220. port += sizeof(uint64_t);
  1221. }
  1222. /*
  1223. * Clear out the exact-match table
  1224. */
  1225. port = s->sbm_base + R_MAC_ADDR_BASE;
  1226. for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
  1227. __raw_writeq(0, port);
  1228. port += sizeof(uint64_t);
  1229. }
  1230. /*
  1231. * Clear out the DMA Channel mapping table registers
  1232. */
  1233. port = s->sbm_base + R_MAC_CHUP0_BASE;
  1234. for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
  1235. __raw_writeq(0, port);
  1236. port += sizeof(uint64_t);
  1237. }
  1238. port = s->sbm_base + R_MAC_CHLO0_BASE;
  1239. for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
  1240. __raw_writeq(0, port);
  1241. port += sizeof(uint64_t);
  1242. }
  1243. /*
  1244. * Program the hardware address. It goes into the hardware-address
  1245. * register as well as the first filter register.
  1246. */
  1247. reg = sbmac_addr2reg(s->sbm_hwaddr);
  1248. port = s->sbm_base + R_MAC_ADDR_BASE;
  1249. __raw_writeq(reg, port);
  1250. port = s->sbm_base + R_MAC_ETHERNET_ADDR;
  1251. #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
  1252. /*
  1253. * Pass1 SOCs do not receive packets addressed to the
  1254. * destination address in the R_MAC_ETHERNET_ADDR register.
  1255. * Set the value to zero.
  1256. */
  1257. __raw_writeq(0, port);
  1258. #else
  1259. __raw_writeq(reg, port);
  1260. #endif
  1261. /*
  1262. * Set the receive filter for no packets, and write values
  1263. * to the various config registers
  1264. */
  1265. __raw_writeq(0, s->sbm_rxfilter);
  1266. __raw_writeq(0, s->sbm_imr);
  1267. __raw_writeq(framecfg, s->sbm_framecfg);
  1268. __raw_writeq(fifo, s->sbm_fifocfg);
  1269. __raw_writeq(cfg, s->sbm_maccfg);
  1270. /*
  1271. * Initialize DMA channels (rings should be ok now)
  1272. */
  1273. sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
  1274. sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
  1275. /*
  1276. * Configure the speed, duplex, and flow control
  1277. */
  1278. sbmac_set_speed(s,s->sbm_speed);
  1279. sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
  1280. /*
  1281. * Fill the receive ring
  1282. */
  1283. sbdma_fillring(&(s->sbm_rxdma));
  1284. /*
  1285. * Turn on the rest of the bits in the enable register
  1286. */
  1287. #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  1288. __raw_writeq(M_MAC_RXDMA_EN0 |
  1289. M_MAC_TXDMA_EN0, s->sbm_macenable);
  1290. #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
  1291. __raw_writeq(M_MAC_RXDMA_EN0 |
  1292. M_MAC_TXDMA_EN0 |
  1293. M_MAC_RX_ENABLE |
  1294. M_MAC_TX_ENABLE, s->sbm_macenable);
  1295. #else
  1296. #error invalid SiByte MAC configuation
  1297. #endif
  1298. #ifdef CONFIG_SBMAC_COALESCE
  1299. /*
  1300. * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
  1301. */
  1302. __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
  1303. ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
  1304. #else
  1305. /*
  1306. * Accept any kind of interrupt on TX and RX DMA channel 0
  1307. */
  1308. __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
  1309. (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
  1310. #endif
  1311. /*
  1312. * Enable receiving unicasts and broadcasts
  1313. */
  1314. __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
  1315. /*
  1316. * we're running now.
  1317. */
  1318. s->sbm_state = sbmac_state_on;
  1319. /*
  1320. * Program multicast addresses
  1321. */
  1322. sbmac_setmulti(s);
  1323. /*
  1324. * If channel was in promiscuous mode before, turn that on
  1325. */
  1326. if (s->sbm_devflags & IFF_PROMISC) {
  1327. sbmac_promiscuous_mode(s,1);
  1328. }
  1329. }
  1330. /**********************************************************************
  1331. * SBMAC_CHANNEL_STOP(s)
  1332. *
  1333. * Stop packet processing on this MAC.
  1334. *
  1335. * Input parameters:
  1336. * s - sbmac structure
  1337. *
  1338. * Return value:
  1339. * nothing
  1340. ********************************************************************* */
  1341. static void sbmac_channel_stop(struct sbmac_softc *s)
  1342. {
  1343. /* don't do this if already stopped */
  1344. if (s->sbm_state == sbmac_state_off)
  1345. return;
  1346. /* don't accept any packets, disable all interrupts */
  1347. __raw_writeq(0, s->sbm_rxfilter);
  1348. __raw_writeq(0, s->sbm_imr);
  1349. /* Turn off ticker */
  1350. /* XXX */
  1351. /* turn off receiver and transmitter */
  1352. __raw_writeq(0, s->sbm_macenable);
  1353. /* We're stopped now. */
  1354. s->sbm_state = sbmac_state_off;
  1355. /*
  1356. * Stop DMA channels (rings should be ok now)
  1357. */
  1358. sbdma_channel_stop(&(s->sbm_rxdma));
  1359. sbdma_channel_stop(&(s->sbm_txdma));
  1360. /* Empty the receive and transmit rings */
  1361. sbdma_emptyring(&(s->sbm_rxdma));
  1362. sbdma_emptyring(&(s->sbm_txdma));
  1363. }
  1364. /**********************************************************************
  1365. * SBMAC_SET_CHANNEL_STATE(state)
  1366. *
  1367. * Set the channel's state ON or OFF
  1368. *
  1369. * Input parameters:
  1370. * state - new state
  1371. *
  1372. * Return value:
  1373. * old state
  1374. ********************************************************************* */
  1375. static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
  1376. sbmac_state_t state)
  1377. {
  1378. sbmac_state_t oldstate = sc->sbm_state;
  1379. /*
  1380. * If same as previous state, return
  1381. */
  1382. if (state == oldstate) {
  1383. return oldstate;
  1384. }
  1385. /*
  1386. * If new state is ON, turn channel on
  1387. */
  1388. if (state == sbmac_state_on) {
  1389. sbmac_channel_start(sc);
  1390. }
  1391. else {
  1392. sbmac_channel_stop(sc);
  1393. }
  1394. /*
  1395. * Return previous state
  1396. */
  1397. return oldstate;
  1398. }
  1399. /**********************************************************************
  1400. * SBMAC_PROMISCUOUS_MODE(sc,onoff)
  1401. *
  1402. * Turn on or off promiscuous mode
  1403. *
  1404. * Input parameters:
  1405. * sc - softc
  1406. * onoff - 1 to turn on, 0 to turn off
  1407. *
  1408. * Return value:
  1409. * nothing
  1410. ********************************************************************* */
  1411. static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
  1412. {
  1413. uint64_t reg;
  1414. if (sc->sbm_state != sbmac_state_on)
  1415. return;
  1416. if (onoff) {
  1417. reg = __raw_readq(sc->sbm_rxfilter);
  1418. reg |= M_MAC_ALLPKT_EN;
  1419. __raw_writeq(reg, sc->sbm_rxfilter);
  1420. }
  1421. else {
  1422. reg = __raw_readq(sc->sbm_rxfilter);
  1423. reg &= ~M_MAC_ALLPKT_EN;
  1424. __raw_writeq(reg, sc->sbm_rxfilter);
  1425. }
  1426. }
  1427. /**********************************************************************
  1428. * SBMAC_SETIPHDR_OFFSET(sc,onoff)
  1429. *
  1430. * Set the iphdr offset as 15 assuming ethernet encapsulation
  1431. *
  1432. * Input parameters:
  1433. * sc - softc
  1434. *
  1435. * Return value:
  1436. * nothing
  1437. ********************************************************************* */
  1438. static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
  1439. {
  1440. uint64_t reg;
  1441. /* Hard code the off set to 15 for now */
  1442. reg = __raw_readq(sc->sbm_rxfilter);
  1443. reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
  1444. __raw_writeq(reg, sc->sbm_rxfilter);
  1445. /* BCM1250 pass1 didn't have hardware checksum. Everything
  1446. later does. */
  1447. if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
  1448. sc->rx_hw_checksum = DISABLE;
  1449. } else {
  1450. sc->rx_hw_checksum = ENABLE;
  1451. }
  1452. }
  1453. /**********************************************************************
  1454. * SBMAC_ADDR2REG(ptr)
  1455. *
  1456. * Convert six bytes into the 64-bit register value that
  1457. * we typically write into the SBMAC's address/mcast registers
  1458. *
  1459. * Input parameters:
  1460. * ptr - pointer to 6 bytes
  1461. *
  1462. * Return value:
  1463. * register value
  1464. ********************************************************************* */
  1465. static uint64_t sbmac_addr2reg(unsigned char *ptr)
  1466. {
  1467. uint64_t reg = 0;
  1468. ptr += 6;
  1469. reg |= (uint64_t) *(--ptr);
  1470. reg <<= 8;
  1471. reg |= (uint64_t) *(--ptr);
  1472. reg <<= 8;
  1473. reg |= (uint64_t) *(--ptr);
  1474. reg <<= 8;
  1475. reg |= (uint64_t) *(--ptr);
  1476. reg <<= 8;
  1477. reg |= (uint64_t) *(--ptr);
  1478. reg <<= 8;
  1479. reg |= (uint64_t) *(--ptr);
  1480. return reg;
  1481. }
  1482. /**********************************************************************
  1483. * SBMAC_SET_SPEED(s,speed)
  1484. *
  1485. * Configure LAN speed for the specified MAC.
  1486. * Warning: must be called when MAC is off!
  1487. *
  1488. * Input parameters:
  1489. * s - sbmac structure
  1490. * speed - speed to set MAC to (see sbmac_speed_t enum)
  1491. *
  1492. * Return value:
  1493. * 1 if successful
  1494. * 0 indicates invalid parameters
  1495. ********************************************************************* */
  1496. static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
  1497. {
  1498. uint64_t cfg;
  1499. uint64_t framecfg;
  1500. /*
  1501. * Save new current values
  1502. */
  1503. s->sbm_speed = speed;
  1504. if (s->sbm_state == sbmac_state_on)
  1505. return 0; /* save for next restart */
  1506. /*
  1507. * Read current register values
  1508. */
  1509. cfg = __raw_readq(s->sbm_maccfg);
  1510. framecfg = __raw_readq(s->sbm_framecfg);
  1511. /*
  1512. * Mask out the stuff we want to change
  1513. */
  1514. cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
  1515. framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
  1516. M_MAC_SLOT_SIZE);
  1517. /*
  1518. * Now add in the new bits
  1519. */
  1520. switch (speed) {
  1521. case sbmac_speed_10:
  1522. framecfg |= V_MAC_IFG_RX_10 |
  1523. V_MAC_IFG_TX_10 |
  1524. K_MAC_IFG_THRSH_10 |
  1525. V_MAC_SLOT_SIZE_10;
  1526. cfg |= V_MAC_SPEED_SEL_10MBPS;
  1527. break;
  1528. case sbmac_speed_100:
  1529. framecfg |= V_MAC_IFG_RX_100 |
  1530. V_MAC_IFG_TX_100 |
  1531. V_MAC_IFG_THRSH_100 |
  1532. V_MAC_SLOT_SIZE_100;
  1533. cfg |= V_MAC_SPEED_SEL_100MBPS ;
  1534. break;
  1535. case sbmac_speed_1000:
  1536. framecfg |= V_MAC_IFG_RX_1000 |
  1537. V_MAC_IFG_TX_1000 |
  1538. V_MAC_IFG_THRSH_1000 |
  1539. V_MAC_SLOT_SIZE_1000;
  1540. cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
  1541. break;
  1542. case sbmac_speed_auto: /* XXX not implemented */
  1543. /* fall through */
  1544. default:
  1545. return 0;
  1546. }
  1547. /*
  1548. * Send the bits back to the hardware
  1549. */
  1550. __raw_writeq(framecfg, s->sbm_framecfg);
  1551. __raw_writeq(cfg, s->sbm_maccfg);
  1552. return 1;
  1553. }
  1554. /**********************************************************************
  1555. * SBMAC_SET_DUPLEX(s,duplex,fc)
  1556. *
  1557. * Set Ethernet duplex and flow control options for this MAC
  1558. * Warning: must be called when MAC is off!
  1559. *
  1560. * Input parameters:
  1561. * s - sbmac structure
  1562. * duplex - duplex setting (see sbmac_duplex_t)
  1563. * fc - flow control setting (see sbmac_fc_t)
  1564. *
  1565. * Return value:
  1566. * 1 if ok
  1567. * 0 if an invalid parameter combination was specified
  1568. ********************************************************************* */
  1569. static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
  1570. {
  1571. uint64_t cfg;
  1572. /*
  1573. * Save new current values
  1574. */
  1575. s->sbm_duplex = duplex;
  1576. s->sbm_fc = fc;
  1577. if (s->sbm_state == sbmac_state_on)
  1578. return 0; /* save for next restart */
  1579. /*
  1580. * Read current register values
  1581. */
  1582. cfg = __raw_readq(s->sbm_maccfg);
  1583. /*
  1584. * Mask off the stuff we're about to change
  1585. */
  1586. cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
  1587. switch (duplex) {
  1588. case sbmac_duplex_half:
  1589. switch (fc) {
  1590. case sbmac_fc_disabled:
  1591. cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
  1592. break;
  1593. case sbmac_fc_collision:
  1594. cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
  1595. break;
  1596. case sbmac_fc_carrier:
  1597. cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
  1598. break;
  1599. case sbmac_fc_auto: /* XXX not implemented */
  1600. /* fall through */
  1601. case sbmac_fc_frame: /* not valid in half duplex */
  1602. default: /* invalid selection */
  1603. return 0;
  1604. }
  1605. break;
  1606. case sbmac_duplex_full:
  1607. switch (fc) {
  1608. case sbmac_fc_disabled:
  1609. cfg |= V_MAC_FC_CMD_DISABLED;
  1610. break;
  1611. case sbmac_fc_frame:
  1612. cfg |= V_MAC_FC_CMD_ENABLED;
  1613. break;
  1614. case sbmac_fc_collision: /* not valid in full duplex */
  1615. case sbmac_fc_carrier: /* not valid in full duplex */
  1616. case sbmac_fc_auto: /* XXX not implemented */
  1617. /* fall through */
  1618. default:
  1619. return 0;
  1620. }
  1621. break;
  1622. case sbmac_duplex_auto:
  1623. /* XXX not implemented */
  1624. break;
  1625. }
  1626. /*
  1627. * Send the bits back to the hardware
  1628. */
  1629. __raw_writeq(cfg, s->sbm_maccfg);
  1630. return 1;
  1631. }
  1632. /**********************************************************************
  1633. * SBMAC_INTR()
  1634. *
  1635. * Interrupt handler for MAC interrupts
  1636. *
  1637. * Input parameters:
  1638. * MAC structure
  1639. *
  1640. * Return value:
  1641. * nothing
  1642. ********************************************************************* */
  1643. static irqreturn_t sbmac_intr(int irq,void *dev_instance)
  1644. {
  1645. struct net_device *dev = (struct net_device *) dev_instance;
  1646. struct sbmac_softc *sc = netdev_priv(dev);
  1647. uint64_t isr;
  1648. int handled = 0;
  1649. for (;;) {
  1650. /*
  1651. * Read the ISR (this clears the bits in the real
  1652. * register, except for counter addr)
  1653. */
  1654. isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
  1655. if (isr == 0)
  1656. break;
  1657. handled = 1;
  1658. /*
  1659. * Transmits on channel 0
  1660. */
  1661. if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
  1662. sbdma_tx_process(sc,&(sc->sbm_txdma));
  1663. }
  1664. /*
  1665. * Receives on channel 0
  1666. */
  1667. /*
  1668. * It's important to test all the bits (or at least the
  1669. * EOP_SEEN bit) when deciding to do the RX process
  1670. * particularly when coalescing, to make sure we
  1671. * take care of the following:
  1672. *
  1673. * If you have some packets waiting (have been received
  1674. * but no interrupt) and get a TX interrupt before
  1675. * the RX timer or counter expires, reading the ISR
  1676. * above will clear the timer and counter, and you
  1677. * won't get another interrupt until a packet shows
  1678. * up to start the timer again. Testing
  1679. * EOP_SEEN here takes care of this case.
  1680. * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
  1681. */
  1682. if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
  1683. sbdma_rx_process(sc,&(sc->sbm_rxdma));
  1684. }
  1685. }
  1686. return IRQ_RETVAL(handled);
  1687. }
  1688. /**********************************************************************
  1689. * SBMAC_START_TX(skb,dev)
  1690. *
  1691. * Start output on the specified interface. Basically, we
  1692. * queue as many buffers as we can until the ring fills up, or
  1693. * we run off the end of the queue, whichever comes first.
  1694. *
  1695. * Input parameters:
  1696. *
  1697. *
  1698. * Return value:
  1699. * nothing
  1700. ********************************************************************* */
  1701. static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
  1702. {
  1703. struct sbmac_softc *sc = netdev_priv(dev);
  1704. /* lock eth irq */
  1705. spin_lock_irq (&sc->sbm_lock);
  1706. /*
  1707. * Put the buffer on the transmit ring. If we
  1708. * don't have room, stop the queue.
  1709. */
  1710. if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
  1711. /* XXX save skb that we could not send */
  1712. netif_stop_queue(dev);
  1713. spin_unlock_irq(&sc->sbm_lock);
  1714. return 1;
  1715. }
  1716. dev->trans_start = jiffies;
  1717. spin_unlock_irq (&sc->sbm_lock);
  1718. return 0;
  1719. }
  1720. /**********************************************************************
  1721. * SBMAC_SETMULTI(sc)
  1722. *
  1723. * Reprogram the multicast table into the hardware, given
  1724. * the list of multicasts associated with the interface
  1725. * structure.
  1726. *
  1727. * Input parameters:
  1728. * sc - softc
  1729. *
  1730. * Return value:
  1731. * nothing
  1732. ********************************************************************* */
  1733. static void sbmac_setmulti(struct sbmac_softc *sc)
  1734. {
  1735. uint64_t reg;
  1736. volatile void __iomem *port;
  1737. int idx;
  1738. struct dev_mc_list *mclist;
  1739. struct net_device *dev = sc->sbm_dev;
  1740. /*
  1741. * Clear out entire multicast table. We do this by nuking
  1742. * the entire hash table and all the direct matches except
  1743. * the first one, which is used for our station address
  1744. */
  1745. for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
  1746. port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
  1747. __raw_writeq(0, port);
  1748. }
  1749. for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
  1750. port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
  1751. __raw_writeq(0, port);
  1752. }
  1753. /*
  1754. * Clear the filter to say we don't want any multicasts.
  1755. */
  1756. reg = __raw_readq(sc->sbm_rxfilter);
  1757. reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
  1758. __raw_writeq(reg, sc->sbm_rxfilter);
  1759. if (dev->flags & IFF_ALLMULTI) {
  1760. /*
  1761. * Enable ALL multicasts. Do this by inverting the
  1762. * multicast enable bit.
  1763. */
  1764. reg = __raw_readq(sc->sbm_rxfilter);
  1765. reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
  1766. __raw_writeq(reg, sc->sbm_rxfilter);
  1767. return;
  1768. }
  1769. /*
  1770. * Progam new multicast entries. For now, only use the
  1771. * perfect filter. In the future we'll need to use the
  1772. * hash filter if the perfect filter overflows
  1773. */
  1774. /* XXX only using perfect filter for now, need to use hash
  1775. * XXX if the table overflows */
  1776. idx = 1; /* skip station address */
  1777. mclist = dev->mc_list;
  1778. while (mclist && (idx < MAC_ADDR_COUNT)) {
  1779. reg = sbmac_addr2reg(mclist->dmi_addr);
  1780. port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
  1781. __raw_writeq(reg, port);
  1782. idx++;
  1783. mclist = mclist->next;
  1784. }
  1785. /*
  1786. * Enable the "accept multicast bits" if we programmed at least one
  1787. * multicast.
  1788. */
  1789. if (idx > 1) {
  1790. reg = __raw_readq(sc->sbm_rxfilter);
  1791. reg |= M_MAC_MCAST_EN;
  1792. __raw_writeq(reg, sc->sbm_rxfilter);
  1793. }
  1794. }
  1795. #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
  1796. /**********************************************************************
  1797. * SBMAC_PARSE_XDIGIT(str)
  1798. *
  1799. * Parse a hex digit, returning its value
  1800. *
  1801. * Input parameters:
  1802. * str - character
  1803. *
  1804. * Return value:
  1805. * hex value, or -1 if invalid
  1806. ********************************************************************* */
  1807. static int sbmac_parse_xdigit(char str)
  1808. {
  1809. int digit;
  1810. if ((str >= '0') && (str <= '9'))
  1811. digit = str - '0';
  1812. else if ((str >= 'a') && (str <= 'f'))
  1813. digit = str - 'a' + 10;
  1814. else if ((str >= 'A') && (str <= 'F'))
  1815. digit = str - 'A' + 10;
  1816. else
  1817. return -1;
  1818. return digit;
  1819. }
  1820. /**********************************************************************
  1821. * SBMAC_PARSE_HWADDR(str,hwaddr)
  1822. *
  1823. * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
  1824. * Ethernet address.
  1825. *
  1826. * Input parameters:
  1827. * str - string
  1828. * hwaddr - pointer to hardware address
  1829. *
  1830. * Return value:
  1831. * 0 if ok, else -1
  1832. ********************************************************************* */
  1833. static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
  1834. {
  1835. int digit1,digit2;
  1836. int idx = 6;
  1837. while (*str && (idx > 0)) {
  1838. digit1 = sbmac_parse_xdigit(*str);
  1839. if (digit1 < 0)
  1840. return -1;
  1841. str++;
  1842. if (!*str)
  1843. return -1;
  1844. if ((*str == ':') || (*str == '-')) {
  1845. digit2 = digit1;
  1846. digit1 = 0;
  1847. }
  1848. else {
  1849. digit2 = sbmac_parse_xdigit(*str);
  1850. if (digit2 < 0)
  1851. return -1;
  1852. str++;
  1853. }
  1854. *hwaddr++ = (digit1 << 4) | digit2;
  1855. idx--;
  1856. if (*str == '-')
  1857. str++;
  1858. if (*str == ':')
  1859. str++;
  1860. }
  1861. return 0;
  1862. }
  1863. #endif
  1864. static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
  1865. {
  1866. if (new_mtu > ENET_PACKET_SIZE)
  1867. return -EINVAL;
  1868. _dev->mtu = new_mtu;
  1869. printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
  1870. return 0;
  1871. }
  1872. /**********************************************************************
  1873. * SBMAC_INIT(dev)
  1874. *
  1875. * Attach routine - init hardware and hook ourselves into linux
  1876. *
  1877. * Input parameters:
  1878. * dev - net_device structure
  1879. *
  1880. * Return value:
  1881. * status
  1882. ********************************************************************* */
  1883. static int sbmac_init(struct net_device *dev, int idx)
  1884. {
  1885. struct sbmac_softc *sc;
  1886. unsigned char *eaddr;
  1887. uint64_t ea_reg;
  1888. int i;
  1889. int err;
  1890. sc = netdev_priv(dev);
  1891. /* Determine controller base address */
  1892. sc->sbm_base = IOADDR(dev->base_addr);
  1893. sc->sbm_dev = dev;
  1894. sc->sbe_idx = idx;
  1895. eaddr = sc->sbm_hwaddr;
  1896. /*
  1897. * Read the ethernet address. The firwmare left this programmed
  1898. * for us in the ethernet address register for each mac.
  1899. */
  1900. ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
  1901. __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
  1902. for (i = 0; i < 6; i++) {
  1903. eaddr[i] = (uint8_t) (ea_reg & 0xFF);
  1904. ea_reg >>= 8;
  1905. }
  1906. for (i = 0; i < 6; i++) {
  1907. dev->dev_addr[i] = eaddr[i];
  1908. }
  1909. /*
  1910. * Init packet size
  1911. */
  1912. sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
  1913. /*
  1914. * Initialize context (get pointers to registers and stuff), then
  1915. * allocate the memory for the descriptor tables.
  1916. */
  1917. sbmac_initctx(sc);
  1918. /*
  1919. * Set up Linux device callins
  1920. */
  1921. spin_lock_init(&(sc->sbm_lock));
  1922. dev->open = sbmac_open;
  1923. dev->hard_start_xmit = sbmac_start_tx;
  1924. dev->stop = sbmac_close;
  1925. dev->get_stats = sbmac_get_stats;
  1926. dev->set_multicast_list = sbmac_set_rx_mode;
  1927. dev->do_ioctl = sbmac_mii_ioctl;
  1928. dev->tx_timeout = sbmac_tx_timeout;
  1929. dev->watchdog_timeo = TX_TIMEOUT;
  1930. dev->change_mtu = sb1250_change_mtu;
  1931. /* This is needed for PASS2 for Rx H/W checksum feature */
  1932. sbmac_set_iphdr_offset(sc);
  1933. err = register_netdev(dev);
  1934. if (err)
  1935. goto out_uninit;
  1936. if (sc->rx_hw_checksum == ENABLE) {
  1937. printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
  1938. sc->sbm_dev->name);
  1939. }
  1940. /*
  1941. * Display Ethernet address (this is called during the config
  1942. * process so we need to finish off the config message that
  1943. * was being displayed)
  1944. */
  1945. printk(KERN_INFO
  1946. "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
  1947. dev->name, dev->base_addr,
  1948. eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
  1949. return 0;
  1950. out_uninit:
  1951. sbmac_uninitctx(sc);
  1952. return err;
  1953. }
  1954. static int sbmac_open(struct net_device *dev)
  1955. {
  1956. struct sbmac_softc *sc = netdev_priv(dev);
  1957. if (debug > 1) {
  1958. printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
  1959. }
  1960. /*
  1961. * map/route interrupt (clear status first, in case something
  1962. * weird is pending; we haven't initialized the mac registers
  1963. * yet)
  1964. */
  1965. __raw_readq(sc->sbm_isr);
  1966. if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev))
  1967. return -EBUSY;
  1968. /*
  1969. * Probe phy address
  1970. */
  1971. if(sbmac_mii_probe(dev) == -1) {
  1972. printk("%s: failed to probe PHY.\n", dev->name);
  1973. return -EINVAL;
  1974. }
  1975. /*
  1976. * Configure default speed
  1977. */
  1978. sbmac_mii_poll(sc,noisy_mii);
  1979. /*
  1980. * Turn on the channel
  1981. */
  1982. sbmac_set_channel_state(sc,sbmac_state_on);
  1983. /*
  1984. * XXX Station address is in dev->dev_addr
  1985. */
  1986. if (dev->if_port == 0)
  1987. dev->if_port = 0;
  1988. netif_start_queue(dev);
  1989. sbmac_set_rx_mode(dev);
  1990. /* Set the timer to check for link beat. */
  1991. init_timer(&sc->sbm_timer);
  1992. sc->sbm_timer.expires = jiffies + 2 * HZ/100;
  1993. sc->sbm_timer.data = (unsigned long)dev;
  1994. sc->sbm_timer.function = &sbmac_timer;
  1995. add_timer(&sc->sbm_timer);
  1996. return 0;
  1997. }
  1998. static int sbmac_mii_probe(struct net_device *dev)
  1999. {
  2000. int i;
  2001. struct sbmac_softc *s = netdev_priv(dev);
  2002. u16 bmsr, id1, id2;
  2003. u32 vendor, device;
  2004. for (i=1; i<31; i++) {
  2005. bmsr = sbmac_mii_read(s, i, MII_BMSR);
  2006. if (bmsr != 0) {
  2007. s->sbm_phys[0] = i;
  2008. id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
  2009. id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
  2010. vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
  2011. device = (id2 >> 4) & 0x3f;
  2012. printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
  2013. dev->name, i, vendor, device);
  2014. return i;
  2015. }
  2016. }
  2017. return -1;
  2018. }
  2019. static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
  2020. {
  2021. int bmsr,bmcr,k1stsr,anlpar;
  2022. int chg;
  2023. char buffer[100];
  2024. char *p = buffer;
  2025. /* Read the mode status and mode control registers. */
  2026. bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
  2027. bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
  2028. /* get the link partner status */
  2029. anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
  2030. /* if supported, read the 1000baseT register */
  2031. if (bmsr & BMSR_1000BT_XSR) {
  2032. k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
  2033. }
  2034. else {
  2035. k1stsr = 0;
  2036. }
  2037. chg = 0;
  2038. if ((bmsr & BMSR_LINKSTAT) == 0) {
  2039. /*
  2040. * If link status is down, clear out old info so that when
  2041. * it comes back up it will force us to reconfigure speed
  2042. */
  2043. s->sbm_phy_oldbmsr = 0;
  2044. s->sbm_phy_oldanlpar = 0;
  2045. s->sbm_phy_oldk1stsr = 0;
  2046. return 0;
  2047. }
  2048. if ((s->sbm_phy_oldbmsr != bmsr) ||
  2049. (s->sbm_phy_oldanlpar != anlpar) ||
  2050. (s->sbm_phy_oldk1stsr != k1stsr)) {
  2051. if (debug > 1) {
  2052. printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n",
  2053. s->sbm_dev->name,
  2054. s->sbm_phy_oldbmsr,bmsr,
  2055. s->sbm_phy_oldanlpar,anlpar,
  2056. s->sbm_phy_oldk1stsr,k1stsr);
  2057. }
  2058. s->sbm_phy_oldbmsr = bmsr;
  2059. s->sbm_phy_oldanlpar = anlpar;
  2060. s->sbm_phy_oldk1stsr = k1stsr;
  2061. chg = 1;
  2062. }
  2063. if (chg == 0)
  2064. return 0;
  2065. p += sprintf(p,"Link speed: ");
  2066. if (k1stsr & K1STSR_LP1KFD) {
  2067. s->sbm_speed = sbmac_speed_1000;
  2068. s->sbm_duplex = sbmac_duplex_full;
  2069. s->sbm_fc = sbmac_fc_frame;
  2070. p += sprintf(p,"1000BaseT FDX");
  2071. }
  2072. else if (k1stsr & K1STSR_LP1KHD) {
  2073. s->sbm_speed = sbmac_speed_1000;
  2074. s->sbm_duplex = sbmac_duplex_half;
  2075. s->sbm_fc = sbmac_fc_disabled;
  2076. p += sprintf(p,"1000BaseT HDX");
  2077. }
  2078. else if (anlpar & ANLPAR_TXFD) {
  2079. s->sbm_speed = sbmac_speed_100;
  2080. s->sbm_duplex = sbmac_duplex_full;
  2081. s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
  2082. p += sprintf(p,"100BaseT FDX");
  2083. }
  2084. else if (anlpar & ANLPAR_TXHD) {
  2085. s->sbm_speed = sbmac_speed_100;
  2086. s->sbm_duplex = sbmac_duplex_half;
  2087. s->sbm_fc = sbmac_fc_disabled;
  2088. p += sprintf(p,"100BaseT HDX");
  2089. }
  2090. else if (anlpar & ANLPAR_10FD) {
  2091. s->sbm_speed = sbmac_speed_10;
  2092. s->sbm_duplex = sbmac_duplex_full;
  2093. s->sbm_fc = sbmac_fc_frame;
  2094. p += sprintf(p,"10BaseT FDX");
  2095. }
  2096. else if (anlpar & ANLPAR_10HD) {
  2097. s->sbm_speed = sbmac_speed_10;
  2098. s->sbm_duplex = sbmac_duplex_half;
  2099. s->sbm_fc = sbmac_fc_collision;
  2100. p += sprintf(p,"10BaseT HDX");
  2101. }
  2102. else {
  2103. p += sprintf(p,"Unknown");
  2104. }
  2105. if (noisy) {
  2106. printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
  2107. }
  2108. return 1;
  2109. }
  2110. static void sbmac_timer(unsigned long data)
  2111. {
  2112. struct net_device *dev = (struct net_device *)data;
  2113. struct sbmac_softc *sc = netdev_priv(dev);
  2114. int next_tick = HZ;
  2115. int mii_status;
  2116. spin_lock_irq (&sc->sbm_lock);
  2117. /* make IFF_RUNNING follow the MII status bit "Link established" */
  2118. mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
  2119. if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
  2120. sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
  2121. if (mii_status & BMSR_LINKSTAT) {
  2122. netif_carrier_on(dev);
  2123. }
  2124. else {
  2125. netif_carrier_off(dev);
  2126. }
  2127. }
  2128. /*
  2129. * Poll the PHY to see what speed we should be running at
  2130. */
  2131. if (sbmac_mii_poll(sc,noisy_mii)) {
  2132. if (sc->sbm_state != sbmac_state_off) {
  2133. /*
  2134. * something changed, restart the channel
  2135. */
  2136. if (debug > 1) {
  2137. printk("%s: restarting channel because speed changed\n",
  2138. sc->sbm_dev->name);
  2139. }
  2140. sbmac_channel_stop(sc);
  2141. sbmac_channel_start(sc);
  2142. }
  2143. }
  2144. spin_unlock_irq (&sc->sbm_lock);
  2145. sc->sbm_timer.expires = jiffies + next_tick;
  2146. add_timer(&sc->sbm_timer);
  2147. }
  2148. static void sbmac_tx_timeout (struct net_device *dev)
  2149. {
  2150. struct sbmac_softc *sc = netdev_priv(dev);
  2151. spin_lock_irq (&sc->sbm_lock);
  2152. dev->trans_start = jiffies;
  2153. sc->sbm_stats.tx_errors++;
  2154. spin_unlock_irq (&sc->sbm_lock);
  2155. printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
  2156. }
  2157. static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
  2158. {
  2159. struct sbmac_softc *sc = netdev_priv(dev);
  2160. unsigned long flags;
  2161. spin_lock_irqsave(&sc->sbm_lock, flags);
  2162. /* XXX update other stats here */
  2163. spin_unlock_irqrestore(&sc->sbm_lock, flags);
  2164. return &sc->sbm_stats;
  2165. }
  2166. static void sbmac_set_rx_mode(struct net_device *dev)
  2167. {
  2168. unsigned long flags;
  2169. struct sbmac_softc *sc = netdev_priv(dev);
  2170. spin_lock_irqsave(&sc->sbm_lock, flags);
  2171. if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
  2172. /*
  2173. * Promiscuous changed.
  2174. */
  2175. if (dev->flags & IFF_PROMISC) {
  2176. sbmac_promiscuous_mode(sc,1);
  2177. }
  2178. else {
  2179. sbmac_promiscuous_mode(sc,0);
  2180. }
  2181. }
  2182. spin_unlock_irqrestore(&sc->sbm_lock, flags);
  2183. /*
  2184. * Program the multicasts. Do this every time.
  2185. */
  2186. sbmac_setmulti(sc);
  2187. }
  2188. static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  2189. {
  2190. struct sbmac_softc *sc = netdev_priv(dev);
  2191. u16 *data = (u16 *)&rq->ifr_ifru;
  2192. unsigned long flags;
  2193. int retval;
  2194. spin_lock_irqsave(&sc->sbm_lock, flags);
  2195. retval = 0;
  2196. switch(cmd) {
  2197. case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
  2198. data[0] = sc->sbm_phys[0] & 0x1f;
  2199. /* Fall Through */
  2200. case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
  2201. data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
  2202. break;
  2203. case SIOCDEVPRIVATE+2: /* Write the specified MII register */
  2204. if (!capable(CAP_NET_ADMIN)) {
  2205. retval = -EPERM;
  2206. break;
  2207. }
  2208. if (debug > 1) {
  2209. printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
  2210. data[0],data[1],data[2]);
  2211. }
  2212. sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
  2213. break;
  2214. default:
  2215. retval = -EOPNOTSUPP;
  2216. }
  2217. spin_unlock_irqrestore(&sc->sbm_lock, flags);
  2218. return retval;
  2219. }
  2220. static int sbmac_close(struct net_device *dev)
  2221. {
  2222. struct sbmac_softc *sc = netdev_priv(dev);
  2223. unsigned long flags;
  2224. int irq;
  2225. sbmac_set_channel_state(sc,sbmac_state_off);
  2226. del_timer_sync(&sc->sbm_timer);
  2227. spin_lock_irqsave(&sc->sbm_lock, flags);
  2228. netif_stop_queue(dev);
  2229. if (debug > 1) {
  2230. printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
  2231. }
  2232. spin_unlock_irqrestore(&sc->sbm_lock, flags);
  2233. irq = dev->irq;
  2234. synchronize_irq(irq);
  2235. free_irq(irq, dev);
  2236. sbdma_emptyring(&(sc->sbm_txdma));
  2237. sbdma_emptyring(&(sc->sbm_rxdma));
  2238. return 0;
  2239. }
  2240. #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
  2241. static void
  2242. sbmac_setup_hwaddr(int chan,char *addr)
  2243. {
  2244. uint8_t eaddr[6];
  2245. uint64_t val;
  2246. unsigned long port;
  2247. port = A_MAC_CHANNEL_BASE(chan);
  2248. sbmac_parse_hwaddr(addr,eaddr);
  2249. val = sbmac_addr2reg(eaddr);
  2250. __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR));
  2251. val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
  2252. }
  2253. #endif
  2254. static struct net_device *dev_sbmac[MAX_UNITS];
  2255. static int __init
  2256. sbmac_init_module(void)
  2257. {
  2258. int idx;
  2259. struct net_device *dev;
  2260. unsigned long port;
  2261. int chip_max_units;
  2262. /* Set the number of available units based on the SOC type. */
  2263. switch (soc_type) {
  2264. case K_SYS_SOC_TYPE_BCM1250:
  2265. case K_SYS_SOC_TYPE_BCM1250_ALT:
  2266. chip_max_units = 3;
  2267. break;
  2268. case K_SYS_SOC_TYPE_BCM1120:
  2269. case K_SYS_SOC_TYPE_BCM1125:
  2270. case K_SYS_SOC_TYPE_BCM1125H:
  2271. case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
  2272. chip_max_units = 2;
  2273. break;
  2274. case K_SYS_SOC_TYPE_BCM1x55:
  2275. case K_SYS_SOC_TYPE_BCM1x80:
  2276. chip_max_units = 4;
  2277. break;
  2278. default:
  2279. chip_max_units = 0;
  2280. break;
  2281. }
  2282. if (chip_max_units > MAX_UNITS)
  2283. chip_max_units = MAX_UNITS;
  2284. /*
  2285. * For bringup when not using the firmware, we can pre-fill
  2286. * the MAC addresses using the environment variables
  2287. * specified in this file (or maybe from the config file?)
  2288. */
  2289. #ifdef SBMAC_ETH0_HWADDR
  2290. if (chip_max_units > 0)
  2291. sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
  2292. #endif
  2293. #ifdef SBMAC_ETH1_HWADDR
  2294. if (chip_max_units > 1)
  2295. sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
  2296. #endif
  2297. #ifdef SBMAC_ETH2_HWADDR
  2298. if (chip_max_units > 2)
  2299. sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
  2300. #endif
  2301. #ifdef SBMAC_ETH3_HWADDR
  2302. if (chip_max_units > 3)
  2303. sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR);
  2304. #endif
  2305. /*
  2306. * Walk through the Ethernet controllers and find
  2307. * those who have their MAC addresses set.
  2308. */
  2309. for (idx = 0; idx < chip_max_units; idx++) {
  2310. /*
  2311. * This is the base address of the MAC.
  2312. */
  2313. port = A_MAC_CHANNEL_BASE(idx);
  2314. /*
  2315. * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
  2316. * value for us by the firmware if we're going to use this MAC.
  2317. * If we find a zero, skip this MAC.
  2318. */
  2319. sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
  2320. if (sbmac_orig_hwaddr[idx] == 0) {
  2321. printk(KERN_DEBUG "sbmac: not configuring MAC at "
  2322. "%lx\n", port);
  2323. continue;
  2324. }
  2325. /*
  2326. * Okay, cool. Initialize this MAC.
  2327. */
  2328. dev = alloc_etherdev(sizeof(struct sbmac_softc));
  2329. if (!dev)
  2330. return -ENOMEM;
  2331. printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
  2332. dev->irq = UNIT_INT(idx);
  2333. dev->base_addr = port;
  2334. dev->mem_end = 0;
  2335. if (sbmac_init(dev, idx)) {
  2336. port = A_MAC_CHANNEL_BASE(idx);
  2337. __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
  2338. free_netdev(dev);
  2339. continue;
  2340. }
  2341. dev_sbmac[idx] = dev;
  2342. }
  2343. return 0;
  2344. }
  2345. static void __exit
  2346. sbmac_cleanup_module(void)
  2347. {
  2348. struct net_device *dev;
  2349. int idx;
  2350. for (idx = 0; idx < MAX_UNITS; idx++) {
  2351. struct sbmac_softc *sc;
  2352. dev = dev_sbmac[idx];
  2353. if (!dev)
  2354. continue;
  2355. sc = netdev_priv(dev);
  2356. unregister_netdev(dev);
  2357. sbmac_uninitctx(sc);
  2358. free_netdev(dev);
  2359. }
  2360. }
  2361. module_init(sbmac_init_module);
  2362. module_exit(sbmac_cleanup_module);