saa9730.h 15 KB

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  1. /*
  2. * Copyright (C) 2000, 2005 MIPS Technologies, Inc. All rights reserved.
  3. * Authors: Carsten Langgaard <carstenl@mips.com>
  4. * Maciej W. Rozycki <macro@mips.com>
  5. *
  6. * ########################################################################
  7. *
  8. * This program is free software; you can distribute it and/or modify it
  9. * under the terms of the GNU General Public License (Version 2) as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15. * for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, write to the Free Software Foundation, Inc.,
  19. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  20. *
  21. * ########################################################################
  22. *
  23. * SAA9730 ethernet driver description.
  24. *
  25. */
  26. #ifndef _SAA9730_H
  27. #define _SAA9730_H
  28. /* Number of 6-byte entries in the CAM. */
  29. #define LAN_SAA9730_CAM_ENTRIES 10
  30. #define LAN_SAA9730_CAM_DWORDS ((LAN_SAA9730_CAM_ENTRIES*6)/4)
  31. /* TX and RX packet size: fixed to 2048 bytes, according to HW requirements. */
  32. #define LAN_SAA9730_PACKET_SIZE 2048
  33. /*
  34. * Number of TX buffers = number of RX buffers = 2, which is fixed according
  35. * to HW requirements.
  36. */
  37. #define LAN_SAA9730_BUFFERS 2
  38. /* Number of RX packets per RX buffer. */
  39. #define LAN_SAA9730_RCV_Q_SIZE 15
  40. /* Number of TX packets per TX buffer. */
  41. #define LAN_SAA9730_TXM_Q_SIZE 15
  42. /*
  43. * We get an interrupt for each LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
  44. * packets received.
  45. * If however we receive less than LAN_SAA9730_DEFAULT_RCV_Q_INT_THRESHOLD
  46. * packets, the hardware can timeout after a certain time and still tell
  47. * us packets have arrived.
  48. * The timeout value in unit of 32 PCI clocks (33Mhz).
  49. * The value 200 approximates 0.0002 seconds.
  50. */
  51. #define LAN_SAA9730_RCV_Q_INT_THRESHOLD 1
  52. #define LAN_SAA9730_DEFAULT_TIME_OUT_CNT 10
  53. #define RXSF_NDIS 0
  54. #define RXSF_READY 2
  55. #define RXSF_HWDONE 3
  56. #define TXSF_EMPTY 0
  57. #define TXSF_READY 2
  58. #define TXSF_HWDONE 3
  59. #define LANEND_LITTLE 0
  60. #define LANEND_BIG_2143 1
  61. #define LANEND_BIG_4321 2
  62. #define LANMB_ANY 0
  63. #define LANMB_8 1
  64. #define LANMB_32 2
  65. #define LANMB_64 3
  66. #define MACCM_AUTOMATIC 0
  67. #define MACCM_10MB 1
  68. #define MACCM_MII 2
  69. /*
  70. * PHY definitions for Basic registers of QS6612 (used on MIPS ATLAS board)
  71. */
  72. #define PHY_CONTROL 0x0
  73. #define PHY_STATUS 0x1
  74. #define PHY_STATUS_LINK_UP 0x4
  75. #define PHY_CONTROL_RESET 0x8000
  76. #define PHY_CONTROL_AUTO_NEG 0x1000
  77. #define PHY_CONTROL_RESTART_AUTO_NEG 0x0200
  78. #define PHY_ADDRESS 0x0
  79. /* PK_COUNT register. */
  80. #define PK_COUNT_TX_A_SHF 24
  81. #define PK_COUNT_TX_A_MSK (0xff << PK_COUNT_TX_A_SHF)
  82. #define PK_COUNT_TX_B_SHF 16
  83. #define PK_COUNT_TX_B_MSK (0xff << PK_COUNT_TX_B_SHF)
  84. #define PK_COUNT_RX_A_SHF 8
  85. #define PK_COUNT_RX_A_MSK (0xff << PK_COUNT_RX_A_SHF)
  86. #define PK_COUNT_RX_B_SHF 0
  87. #define PK_COUNT_RX_B_MSK (0xff << PK_COUNT_RX_B_SHF)
  88. /* OK2USE register. */
  89. #define OK2USE_TX_A 0x8
  90. #define OK2USE_TX_B 0x4
  91. #define OK2USE_RX_A 0x2
  92. #define OK2USE_RX_B 0x1
  93. /* LAN DMA CONTROL register. */
  94. #define DMA_CTL_BLK_INT 0x80000000
  95. #define DMA_CTL_MAX_XFER_SHF 18
  96. #define DMA_CTL_MAX_XFER_MSK (0x3 << LAN_DMA_CTL_MAX_XFER_SHF)
  97. #define DMA_CTL_ENDIAN_SHF 16
  98. #define DMA_CTL_ENDIAN_MSK (0x3 << LAN_DMA_CTL_ENDIAN_SHF)
  99. #define DMA_CTL_RX_INT_COUNT_SHF 8
  100. #define DMA_CTL_RX_INT_COUNT_MSK (0xff << LAN_DMA_CTL_RX_INT_COUNT_SHF)
  101. #define DMA_CTL_EN_TX_DMA 0x00000080
  102. #define DMA_CTL_EN_RX_DMA 0x00000040
  103. #define DMA_CTL_RX_INT_BUFFUL_EN 0x00000020
  104. #define DMA_CTL_RX_INT_TO_EN 0x00000010
  105. #define DMA_CTL_RX_INT_EN 0x00000008
  106. #define DMA_CTL_TX_INT_EN 0x00000004
  107. #define DMA_CTL_MAC_TX_INT_EN 0x00000002
  108. #define DMA_CTL_MAC_RX_INT_EN 0x00000001
  109. /* DMA STATUS register. */
  110. #define DMA_STATUS_BAD_ADDR_SHF 16
  111. #define DMA_STATUS_BAD_ADDR_MSK (0xf << DMA_STATUS_BAD_ADDR_SHF)
  112. #define DMA_STATUS_RX_PKTS_RECEIVED_SHF 8
  113. #define DMA_STATUS_RX_PKTS_RECEIVED_MSK (0xff << DMA_STATUS_RX_PKTS_RECEIVED_SHF)
  114. #define DMA_STATUS_TX_EN_SYNC 0x00000080
  115. #define DMA_STATUS_RX_BUF_A_FUL 0x00000040
  116. #define DMA_STATUS_RX_BUF_B_FUL 0x00000020
  117. #define DMA_STATUS_RX_TO_INT 0x00000010
  118. #define DMA_STATUS_RX_INT 0x00000008
  119. #define DMA_STATUS_TX_INT 0x00000004
  120. #define DMA_STATUS_MAC_TX_INT 0x00000002
  121. #define DMA_STATUS_MAC_RX_INT 0x00000001
  122. /* DMA TEST/PANIC SWITHES register. */
  123. #define DMA_TEST_LOOPBACK 0x01000000
  124. #define DMA_TEST_SW_RESET 0x00000001
  125. /* MAC CONTROL register. */
  126. #define MAC_CONTROL_EN_MISS_ROLL 0x00002000
  127. #define MAC_CONTROL_MISS_ROLL 0x00000400
  128. #define MAC_CONTROL_LOOP10 0x00000080
  129. #define MAC_CONTROL_CONN_SHF 5
  130. #define MAC_CONTROL_CONN_MSK (0x3 << MAC_CONTROL_CONN_SHF)
  131. #define MAC_CONTROL_MAC_LOOP 0x00000010
  132. #define MAC_CONTROL_FULL_DUP 0x00000008
  133. #define MAC_CONTROL_RESET 0x00000004
  134. #define MAC_CONTROL_HALT_IMM 0x00000002
  135. #define MAC_CONTROL_HALT_REQ 0x00000001
  136. /* CAM CONTROL register. */
  137. #define CAM_CONTROL_COMP_EN 0x00000010
  138. #define CAM_CONTROL_NEG_CAM 0x00000008
  139. #define CAM_CONTROL_BROAD_ACC 0x00000004
  140. #define CAM_CONTROL_GROUP_ACC 0x00000002
  141. #define CAM_CONTROL_STATION_ACC 0x00000001
  142. /* TRANSMIT CONTROL register. */
  143. #define TX_CTL_EN_COMP 0x00004000
  144. #define TX_CTL_EN_TX_PAR 0x00002000
  145. #define TX_CTL_EN_LATE_COLL 0x00001000
  146. #define TX_CTL_EN_EX_COLL 0x00000800
  147. #define TX_CTL_EN_L_CARR 0x00000400
  148. #define TX_CTL_EN_EX_DEFER 0x00000200
  149. #define TX_CTL_EN_UNDER 0x00000100
  150. #define TX_CTL_MII10 0x00000080
  151. #define TX_CTL_SD_PAUSE 0x00000040
  152. #define TX_CTL_NO_EX_DEF0 0x00000020
  153. #define TX_CTL_F_BACK 0x00000010
  154. #define TX_CTL_NO_CRC 0x00000008
  155. #define TX_CTL_NO_PAD 0x00000004
  156. #define TX_CTL_TX_HALT 0x00000002
  157. #define TX_CTL_TX_EN 0x00000001
  158. /* TRANSMIT STATUS register. */
  159. #define TX_STATUS_SQ_ERR 0x00010000
  160. #define TX_STATUS_TX_HALTED 0x00008000
  161. #define TX_STATUS_COMP 0x00004000
  162. #define TX_STATUS_TX_PAR 0x00002000
  163. #define TX_STATUS_LATE_COLL 0x00001000
  164. #define TX_STATUS_TX10_STAT 0x00000800
  165. #define TX_STATUS_L_CARR 0x00000400
  166. #define TX_STATUS_EX_DEFER 0x00000200
  167. #define TX_STATUS_UNDER 0x00000100
  168. #define TX_STATUS_IN_TX 0x00000080
  169. #define TX_STATUS_PAUSED 0x00000040
  170. #define TX_STATUS_TX_DEFERRED 0x00000020
  171. #define TX_STATUS_EX_COLL 0x00000010
  172. #define TX_STATUS_TX_COLL_SHF 0
  173. #define TX_STATUS_TX_COLL_MSK (0xf << TX_STATUS_TX_COLL_SHF)
  174. /* RECEIVE CONTROL register. */
  175. #define RX_CTL_EN_GOOD 0x00004000
  176. #define RX_CTL_EN_RX_PAR 0x00002000
  177. #define RX_CTL_EN_LONG_ERR 0x00000800
  178. #define RX_CTL_EN_OVER 0x00000400
  179. #define RX_CTL_EN_CRC_ERR 0x00000200
  180. #define RX_CTL_EN_ALIGN 0x00000100
  181. #define RX_CTL_IGNORE_CRC 0x00000040
  182. #define RX_CTL_PASS_CTL 0x00000020
  183. #define RX_CTL_STRIP_CRC 0x00000010
  184. #define RX_CTL_SHORT_EN 0x00000008
  185. #define RX_CTL_LONG_EN 0x00000004
  186. #define RX_CTL_RX_HALT 0x00000002
  187. #define RX_CTL_RX_EN 0x00000001
  188. /* RECEIVE STATUS register. */
  189. #define RX_STATUS_RX_HALTED 0x00008000
  190. #define RX_STATUS_GOOD 0x00004000
  191. #define RX_STATUS_RX_PAR 0x00002000
  192. #define RX_STATUS_LONG_ERR 0x00000800
  193. #define RX_STATUS_OVERFLOW 0x00000400
  194. #define RX_STATUS_CRC_ERR 0x00000200
  195. #define RX_STATUS_ALIGN_ERR 0x00000100
  196. #define RX_STATUS_RX10_STAT 0x00000080
  197. #define RX_STATUS_INT_RX 0x00000040
  198. #define RX_STATUS_CTL_RECD 0x00000020
  199. /* MD_CA register. */
  200. #define MD_CA_PRE_SUP 0x00001000
  201. #define MD_CA_BUSY 0x00000800
  202. #define MD_CA_WR 0x00000400
  203. #define MD_CA_PHY_SHF 5
  204. #define MD_CA_PHY_MSK (0x1f << MD_CA_PHY_SHF)
  205. #define MD_CA_ADDR_SHF 0
  206. #define MD_CA_ADDR_MSK (0x1f << MD_CA_ADDR_SHF)
  207. /* Tx Status/Control. */
  208. #define TX_STAT_CTL_OWNER_SHF 30
  209. #define TX_STAT_CTL_OWNER_MSK (0x3 << TX_STAT_CTL_OWNER_SHF)
  210. #define TX_STAT_CTL_FRAME_SHF 27
  211. #define TX_STAT_CTL_FRAME_MSK (0x7 << TX_STAT_CTL_FRAME_SHF)
  212. #define TX_STAT_CTL_STATUS_SHF 11
  213. #define TX_STAT_CTL_STATUS_MSK (0x1ffff << TX_STAT_CTL_STATUS_SHF)
  214. #define TX_STAT_CTL_LENGTH_SHF 0
  215. #define TX_STAT_CTL_LENGTH_MSK (0x7ff << TX_STAT_CTL_LENGTH_SHF)
  216. #define TX_STAT_CTL_ERROR_MSK ((TX_STATUS_SQ_ERR | \
  217. TX_STATUS_TX_HALTED | \
  218. TX_STATUS_TX_PAR | \
  219. TX_STATUS_LATE_COLL | \
  220. TX_STATUS_L_CARR | \
  221. TX_STATUS_EX_DEFER | \
  222. TX_STATUS_UNDER | \
  223. TX_STATUS_PAUSED | \
  224. TX_STATUS_TX_DEFERRED | \
  225. TX_STATUS_EX_COLL | \
  226. TX_STATUS_TX_COLL_MSK) \
  227. << TX_STAT_CTL_STATUS_SHF)
  228. #define TX_STAT_CTL_INT_AFTER_TX 0x4
  229. /* Rx Status/Control. */
  230. #define RX_STAT_CTL_OWNER_SHF 30
  231. #define RX_STAT_CTL_OWNER_MSK (0x3 << RX_STAT_CTL_OWNER_SHF)
  232. #define RX_STAT_CTL_STATUS_SHF 11
  233. #define RX_STAT_CTL_STATUS_MSK (0xffff << RX_STAT_CTL_STATUS_SHF)
  234. #define RX_STAT_CTL_LENGTH_SHF 0
  235. #define RX_STAT_CTL_LENGTH_MSK (0x7ff << RX_STAT_CTL_LENGTH_SHF)
  236. /* The SAA9730 (LAN) controller register map, as seen via the PCI-bus. */
  237. #define SAA9730_LAN_REGS_ADDR 0x20400
  238. #define SAA9730_LAN_REGS_SIZE 0x00400
  239. struct lan_saa9730_regmap {
  240. volatile unsigned int TxBuffA; /* 0x20400 */
  241. volatile unsigned int TxBuffB; /* 0x20404 */
  242. volatile unsigned int RxBuffA; /* 0x20408 */
  243. volatile unsigned int RxBuffB; /* 0x2040c */
  244. volatile unsigned int PacketCount; /* 0x20410 */
  245. volatile unsigned int Ok2Use; /* 0x20414 */
  246. volatile unsigned int LanDmaCtl; /* 0x20418 */
  247. volatile unsigned int Timeout; /* 0x2041c */
  248. volatile unsigned int DmaStatus; /* 0x20420 */
  249. volatile unsigned int DmaTest; /* 0x20424 */
  250. volatile unsigned char filler20428[0x20430 - 0x20428];
  251. volatile unsigned int PauseCount; /* 0x20430 */
  252. volatile unsigned int RemotePauseCount; /* 0x20434 */
  253. volatile unsigned char filler20438[0x20440 - 0x20438];
  254. volatile unsigned int MacCtl; /* 0x20440 */
  255. volatile unsigned int CamCtl; /* 0x20444 */
  256. volatile unsigned int TxCtl; /* 0x20448 */
  257. volatile unsigned int TxStatus; /* 0x2044c */
  258. volatile unsigned int RxCtl; /* 0x20450 */
  259. volatile unsigned int RxStatus; /* 0x20454 */
  260. volatile unsigned int StationMgmtData; /* 0x20458 */
  261. volatile unsigned int StationMgmtCtl; /* 0x2045c */
  262. volatile unsigned int CamAddress; /* 0x20460 */
  263. volatile unsigned int CamData; /* 0x20464 */
  264. volatile unsigned int CamEnable; /* 0x20468 */
  265. volatile unsigned char filler2046c[0x20500 - 0x2046c];
  266. volatile unsigned int DebugPCIMasterAddr; /* 0x20500 */
  267. volatile unsigned int DebugLanTxStateMachine; /* 0x20504 */
  268. volatile unsigned int DebugLanRxStateMachine; /* 0x20508 */
  269. volatile unsigned int DebugLanTxFifoPointers; /* 0x2050c */
  270. volatile unsigned int DebugLanRxFifoPointers; /* 0x20510 */
  271. volatile unsigned int DebugLanCtlStateMachine; /* 0x20514 */
  272. };
  273. typedef volatile struct lan_saa9730_regmap t_lan_saa9730_regmap;
  274. /* EVM interrupt control registers. */
  275. #define EVM_LAN_INT 0x00010000
  276. #define EVM_MASTER_EN 0x00000001
  277. /* The SAA9730 (EVM) controller register map, as seen via the PCI-bus. */
  278. #define SAA9730_EVM_REGS_ADDR 0x02000
  279. #define SAA9730_EVM_REGS_SIZE 0x00400
  280. struct evm_saa9730_regmap {
  281. volatile unsigned int InterruptStatus1; /* 0x2000 */
  282. volatile unsigned int InterruptEnable1; /* 0x2004 */
  283. volatile unsigned int InterruptMonitor1; /* 0x2008 */
  284. volatile unsigned int Counter; /* 0x200c */
  285. volatile unsigned int CounterThreshold; /* 0x2010 */
  286. volatile unsigned int CounterControl; /* 0x2014 */
  287. volatile unsigned int GpioControl1; /* 0x2018 */
  288. volatile unsigned int InterruptStatus2; /* 0x201c */
  289. volatile unsigned int InterruptEnable2; /* 0x2020 */
  290. volatile unsigned int InterruptMonitor2; /* 0x2024 */
  291. volatile unsigned int GpioControl2; /* 0x2028 */
  292. volatile unsigned int InterruptBlock1; /* 0x202c */
  293. volatile unsigned int InterruptBlock2; /* 0x2030 */
  294. };
  295. typedef volatile struct evm_saa9730_regmap t_evm_saa9730_regmap;
  296. struct lan_saa9730_private {
  297. /*
  298. * Rx/Tx packet buffers.
  299. * The Rx and Tx packets must be PACKET_SIZE aligned.
  300. */
  301. void *buffer_start;
  302. unsigned int buffer_size;
  303. /*
  304. * DMA address of beginning of this object, returned
  305. * by pci_alloc_consistent().
  306. */
  307. dma_addr_t dma_addr;
  308. /* Pointer to the associated pci device structure */
  309. struct pci_dev *pci_dev;
  310. /* Pointer for the SAA9730 LAN controller register set. */
  311. t_lan_saa9730_regmap *lan_saa9730_regs;
  312. /* Pointer to the SAA9730 EVM register. */
  313. t_evm_saa9730_regmap *evm_saa9730_regs;
  314. /* Rcv buffer Index. */
  315. unsigned char NextRcvPacketIndex;
  316. /* Next buffer index. */
  317. unsigned char NextRcvBufferIndex;
  318. /* Index of next packet to use in that buffer. */
  319. unsigned char NextTxmPacketIndex;
  320. /* Next buffer index. */
  321. unsigned char NextTxmBufferIndex;
  322. /* Index of first pending packet ready to send. */
  323. unsigned char PendingTxmPacketIndex;
  324. /* Pending buffer index. */
  325. unsigned char PendingTxmBufferIndex;
  326. unsigned char DmaRcvPackets;
  327. unsigned char DmaTxmPackets;
  328. void *TxmBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_TXM_Q_SIZE];
  329. void *RcvBuffer[LAN_SAA9730_BUFFERS][LAN_SAA9730_RCV_Q_SIZE];
  330. unsigned int TxBufferFree[LAN_SAA9730_BUFFERS];
  331. unsigned char PhysicalAddress[LAN_SAA9730_CAM_ENTRIES][6];
  332. struct net_device_stats stats;
  333. spinlock_t lock;
  334. };
  335. #endif /* _SAA9730_H */