s2io.h 28 KB

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  1. /************************************************************************
  2. * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
  3. * Copyright(c) 2002-2005 Neterion Inc.
  4. * This software may be used and distributed according to the terms of
  5. * the GNU General Public License (GPL), incorporated herein by reference.
  6. * Drivers based on or derived from this code fall under the GPL and must
  7. * retain the authorship, copyright and license notice. This file is not
  8. * a complete program and may only be used when the entire operating
  9. * system is licensed under the GPL.
  10. * See the file COPYING in this distribution for more information.
  11. ************************************************************************/
  12. #ifndef _S2IO_H
  13. #define _S2IO_H
  14. #define TBD 0
  15. #define BIT(loc) (0x8000000000000000ULL >> (loc))
  16. #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
  17. #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
  18. #ifndef BOOL
  19. #define BOOL int
  20. #endif
  21. #ifndef TRUE
  22. #define TRUE 1
  23. #define FALSE 0
  24. #endif
  25. #undef SUCCESS
  26. #define SUCCESS 0
  27. #define FAILURE -1
  28. #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL
  29. #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100
  30. #define S2IO_BIT_RESET 1
  31. #define S2IO_BIT_SET 2
  32. #define CHECKBIT(value, nbit) (value & (1 << nbit))
  33. /* Maximum time to flicker LED when asked to identify NIC using ethtool */
  34. #define MAX_FLICKER_TIME 60000 /* 60 Secs */
  35. /* Maximum outstanding splits to be configured into xena. */
  36. enum {
  37. XENA_ONE_SPLIT_TRANSACTION = 0,
  38. XENA_TWO_SPLIT_TRANSACTION = 1,
  39. XENA_THREE_SPLIT_TRANSACTION = 2,
  40. XENA_FOUR_SPLIT_TRANSACTION = 3,
  41. XENA_EIGHT_SPLIT_TRANSACTION = 4,
  42. XENA_TWELVE_SPLIT_TRANSACTION = 5,
  43. XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
  44. XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
  45. };
  46. #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
  47. /* OS concerned variables and constants */
  48. #define WATCH_DOG_TIMEOUT 15*HZ
  49. #define EFILL 0x1234
  50. #define ALIGN_SIZE 127
  51. #define PCIX_COMMAND_REGISTER 0x62
  52. /*
  53. * Debug related variables.
  54. */
  55. /* different debug levels. */
  56. #define ERR_DBG 0
  57. #define INIT_DBG 1
  58. #define INFO_DBG 2
  59. #define TX_DBG 3
  60. #define INTR_DBG 4
  61. /* Global variable that defines the present debug level of the driver. */
  62. static int debug_level = ERR_DBG;
  63. /* DEBUG message print. */
  64. #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
  65. /* Protocol assist features of the NIC */
  66. #define L3_CKSUM_OK 0xFFFF
  67. #define L4_CKSUM_OK 0xFFFF
  68. #define S2IO_JUMBO_SIZE 9600
  69. /* Driver statistics maintained by driver */
  70. struct swStat {
  71. unsigned long long single_ecc_errs;
  72. unsigned long long double_ecc_errs;
  73. unsigned long long parity_err_cnt;
  74. unsigned long long serious_err_cnt;
  75. unsigned long long soft_reset_cnt;
  76. unsigned long long fifo_full_cnt;
  77. unsigned long long ring_full_cnt;
  78. /* LRO statistics */
  79. unsigned long long clubbed_frms_cnt;
  80. unsigned long long sending_both;
  81. unsigned long long outof_sequence_pkts;
  82. unsigned long long flush_max_pkts;
  83. unsigned long long sum_avg_pkts_aggregated;
  84. unsigned long long num_aggregations;
  85. };
  86. /* Xpak releated alarm and warnings */
  87. struct xpakStat {
  88. u64 alarm_transceiver_temp_high;
  89. u64 alarm_transceiver_temp_low;
  90. u64 alarm_laser_bias_current_high;
  91. u64 alarm_laser_bias_current_low;
  92. u64 alarm_laser_output_power_high;
  93. u64 alarm_laser_output_power_low;
  94. u64 warn_transceiver_temp_high;
  95. u64 warn_transceiver_temp_low;
  96. u64 warn_laser_bias_current_high;
  97. u64 warn_laser_bias_current_low;
  98. u64 warn_laser_output_power_high;
  99. u64 warn_laser_output_power_low;
  100. u64 xpak_regs_stat;
  101. u32 xpak_timer_count;
  102. };
  103. /* The statistics block of Xena */
  104. struct stat_block {
  105. /* Tx MAC statistics counters. */
  106. __le32 tmac_data_octets;
  107. __le32 tmac_frms;
  108. __le64 tmac_drop_frms;
  109. __le32 tmac_bcst_frms;
  110. __le32 tmac_mcst_frms;
  111. __le64 tmac_pause_ctrl_frms;
  112. __le32 tmac_ucst_frms;
  113. __le32 tmac_ttl_octets;
  114. __le32 tmac_any_err_frms;
  115. __le32 tmac_nucst_frms;
  116. __le64 tmac_ttl_less_fb_octets;
  117. __le64 tmac_vld_ip_octets;
  118. __le32 tmac_drop_ip;
  119. __le32 tmac_vld_ip;
  120. __le32 tmac_rst_tcp;
  121. __le32 tmac_icmp;
  122. __le64 tmac_tcp;
  123. __le32 reserved_0;
  124. __le32 tmac_udp;
  125. /* Rx MAC Statistics counters. */
  126. __le32 rmac_data_octets;
  127. __le32 rmac_vld_frms;
  128. __le64 rmac_fcs_err_frms;
  129. __le64 rmac_drop_frms;
  130. __le32 rmac_vld_bcst_frms;
  131. __le32 rmac_vld_mcst_frms;
  132. __le32 rmac_out_rng_len_err_frms;
  133. __le32 rmac_in_rng_len_err_frms;
  134. __le64 rmac_long_frms;
  135. __le64 rmac_pause_ctrl_frms;
  136. __le64 rmac_unsup_ctrl_frms;
  137. __le32 rmac_accepted_ucst_frms;
  138. __le32 rmac_ttl_octets;
  139. __le32 rmac_discarded_frms;
  140. __le32 rmac_accepted_nucst_frms;
  141. __le32 reserved_1;
  142. __le32 rmac_drop_events;
  143. __le64 rmac_ttl_less_fb_octets;
  144. __le64 rmac_ttl_frms;
  145. __le64 reserved_2;
  146. __le32 rmac_usized_frms;
  147. __le32 reserved_3;
  148. __le32 rmac_frag_frms;
  149. __le32 rmac_osized_frms;
  150. __le32 reserved_4;
  151. __le32 rmac_jabber_frms;
  152. __le64 rmac_ttl_64_frms;
  153. __le64 rmac_ttl_65_127_frms;
  154. __le64 reserved_5;
  155. __le64 rmac_ttl_128_255_frms;
  156. __le64 rmac_ttl_256_511_frms;
  157. __le64 reserved_6;
  158. __le64 rmac_ttl_512_1023_frms;
  159. __le64 rmac_ttl_1024_1518_frms;
  160. __le32 rmac_ip;
  161. __le32 reserved_7;
  162. __le64 rmac_ip_octets;
  163. __le32 rmac_drop_ip;
  164. __le32 rmac_hdr_err_ip;
  165. __le32 reserved_8;
  166. __le32 rmac_icmp;
  167. __le64 rmac_tcp;
  168. __le32 rmac_err_drp_udp;
  169. __le32 rmac_udp;
  170. __le64 rmac_xgmii_err_sym;
  171. __le64 rmac_frms_q0;
  172. __le64 rmac_frms_q1;
  173. __le64 rmac_frms_q2;
  174. __le64 rmac_frms_q3;
  175. __le64 rmac_frms_q4;
  176. __le64 rmac_frms_q5;
  177. __le64 rmac_frms_q6;
  178. __le64 rmac_frms_q7;
  179. __le16 rmac_full_q3;
  180. __le16 rmac_full_q2;
  181. __le16 rmac_full_q1;
  182. __le16 rmac_full_q0;
  183. __le16 rmac_full_q7;
  184. __le16 rmac_full_q6;
  185. __le16 rmac_full_q5;
  186. __le16 rmac_full_q4;
  187. __le32 reserved_9;
  188. __le32 rmac_pause_cnt;
  189. __le64 rmac_xgmii_data_err_cnt;
  190. __le64 rmac_xgmii_ctrl_err_cnt;
  191. __le32 rmac_err_tcp;
  192. __le32 rmac_accepted_ip;
  193. /* PCI/PCI-X Read transaction statistics. */
  194. __le32 new_rd_req_cnt;
  195. __le32 rd_req_cnt;
  196. __le32 rd_rtry_cnt;
  197. __le32 new_rd_req_rtry_cnt;
  198. /* PCI/PCI-X Write/Read transaction statistics. */
  199. __le32 wr_req_cnt;
  200. __le32 wr_rtry_rd_ack_cnt;
  201. __le32 new_wr_req_rtry_cnt;
  202. __le32 new_wr_req_cnt;
  203. __le32 wr_disc_cnt;
  204. __le32 wr_rtry_cnt;
  205. /* PCI/PCI-X Write / DMA Transaction statistics. */
  206. __le32 txp_wr_cnt;
  207. __le32 rd_rtry_wr_ack_cnt;
  208. __le32 txd_wr_cnt;
  209. __le32 txd_rd_cnt;
  210. __le32 rxd_wr_cnt;
  211. __le32 rxd_rd_cnt;
  212. __le32 rxf_wr_cnt;
  213. __le32 txf_rd_cnt;
  214. /* Tx MAC statistics overflow counters. */
  215. __le32 tmac_data_octets_oflow;
  216. __le32 tmac_frms_oflow;
  217. __le32 tmac_bcst_frms_oflow;
  218. __le32 tmac_mcst_frms_oflow;
  219. __le32 tmac_ucst_frms_oflow;
  220. __le32 tmac_ttl_octets_oflow;
  221. __le32 tmac_any_err_frms_oflow;
  222. __le32 tmac_nucst_frms_oflow;
  223. __le64 tmac_vlan_frms;
  224. __le32 tmac_drop_ip_oflow;
  225. __le32 tmac_vld_ip_oflow;
  226. __le32 tmac_rst_tcp_oflow;
  227. __le32 tmac_icmp_oflow;
  228. __le32 tpa_unknown_protocol;
  229. __le32 tmac_udp_oflow;
  230. __le32 reserved_10;
  231. __le32 tpa_parse_failure;
  232. /* Rx MAC Statistics overflow counters. */
  233. __le32 rmac_data_octets_oflow;
  234. __le32 rmac_vld_frms_oflow;
  235. __le32 rmac_vld_bcst_frms_oflow;
  236. __le32 rmac_vld_mcst_frms_oflow;
  237. __le32 rmac_accepted_ucst_frms_oflow;
  238. __le32 rmac_ttl_octets_oflow;
  239. __le32 rmac_discarded_frms_oflow;
  240. __le32 rmac_accepted_nucst_frms_oflow;
  241. __le32 rmac_usized_frms_oflow;
  242. __le32 rmac_drop_events_oflow;
  243. __le32 rmac_frag_frms_oflow;
  244. __le32 rmac_osized_frms_oflow;
  245. __le32 rmac_ip_oflow;
  246. __le32 rmac_jabber_frms_oflow;
  247. __le32 rmac_icmp_oflow;
  248. __le32 rmac_drop_ip_oflow;
  249. __le32 rmac_err_drp_udp_oflow;
  250. __le32 rmac_udp_oflow;
  251. __le32 reserved_11;
  252. __le32 rmac_pause_cnt_oflow;
  253. __le64 rmac_ttl_1519_4095_frms;
  254. __le64 rmac_ttl_4096_8191_frms;
  255. __le64 rmac_ttl_8192_max_frms;
  256. __le64 rmac_ttl_gt_max_frms;
  257. __le64 rmac_osized_alt_frms;
  258. __le64 rmac_jabber_alt_frms;
  259. __le64 rmac_gt_max_alt_frms;
  260. __le64 rmac_vlan_frms;
  261. __le32 rmac_len_discard;
  262. __le32 rmac_fcs_discard;
  263. __le32 rmac_pf_discard;
  264. __le32 rmac_da_discard;
  265. __le32 rmac_red_discard;
  266. __le32 rmac_rts_discard;
  267. __le32 reserved_12;
  268. __le32 rmac_ingm_full_discard;
  269. __le32 reserved_13;
  270. __le32 rmac_accepted_ip_oflow;
  271. __le32 reserved_14;
  272. __le32 link_fault_cnt;
  273. u8 buffer[20];
  274. struct swStat sw_stat;
  275. struct xpakStat xpak_stat;
  276. };
  277. /* Default value for 'vlan_strip_tag' configuration parameter */
  278. #define NO_STRIP_IN_PROMISC 2
  279. /*
  280. * Structures representing different init time configuration
  281. * parameters of the NIC.
  282. */
  283. #define MAX_TX_FIFOS 8
  284. #define MAX_RX_RINGS 8
  285. /* FIFO mappings for all possible number of fifos configured */
  286. static int fifo_map[][MAX_TX_FIFOS] = {
  287. {0, 0, 0, 0, 0, 0, 0, 0},
  288. {0, 0, 0, 0, 1, 1, 1, 1},
  289. {0, 0, 0, 1, 1, 1, 2, 2},
  290. {0, 0, 1, 1, 2, 2, 3, 3},
  291. {0, 0, 1, 1, 2, 2, 3, 4},
  292. {0, 0, 1, 1, 2, 3, 4, 5},
  293. {0, 0, 1, 2, 3, 4, 5, 6},
  294. {0, 1, 2, 3, 4, 5, 6, 7},
  295. };
  296. /* Maintains Per FIFO related information. */
  297. struct tx_fifo_config {
  298. #define MAX_AVAILABLE_TXDS 8192
  299. u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
  300. /* Priority definition */
  301. #define TX_FIFO_PRI_0 0 /*Highest */
  302. #define TX_FIFO_PRI_1 1
  303. #define TX_FIFO_PRI_2 2
  304. #define TX_FIFO_PRI_3 3
  305. #define TX_FIFO_PRI_4 4
  306. #define TX_FIFO_PRI_5 5
  307. #define TX_FIFO_PRI_6 6
  308. #define TX_FIFO_PRI_7 7 /*lowest */
  309. u8 fifo_priority; /* specifies pointer level for FIFO */
  310. /* user should not set twos fifos with same pri */
  311. u8 f_no_snoop;
  312. #define NO_SNOOP_TXD 0x01
  313. #define NO_SNOOP_TXD_BUFFER 0x02
  314. };
  315. /* Maintains per Ring related information */
  316. struct rx_ring_config {
  317. u32 num_rxd; /*No of RxDs per Rx Ring */
  318. #define RX_RING_PRI_0 0 /* highest */
  319. #define RX_RING_PRI_1 1
  320. #define RX_RING_PRI_2 2
  321. #define RX_RING_PRI_3 3
  322. #define RX_RING_PRI_4 4
  323. #define RX_RING_PRI_5 5
  324. #define RX_RING_PRI_6 6
  325. #define RX_RING_PRI_7 7 /* lowest */
  326. u8 ring_priority; /*Specifies service priority of ring */
  327. /* OSM should not set any two rings with same priority */
  328. u8 ring_org; /*Organization of ring */
  329. #define RING_ORG_BUFF1 0x01
  330. #define RX_RING_ORG_BUFF3 0x03
  331. #define RX_RING_ORG_BUFF5 0x05
  332. u8 f_no_snoop;
  333. #define NO_SNOOP_RXD 0x01
  334. #define NO_SNOOP_RXD_BUFFER 0x02
  335. };
  336. /* This structure provides contains values of the tunable parameters
  337. * of the H/W
  338. */
  339. struct config_param {
  340. /* Tx Side */
  341. u32 tx_fifo_num; /*Number of Tx FIFOs */
  342. u8 fifo_mapping[MAX_TX_FIFOS];
  343. struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
  344. u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
  345. u64 tx_intr_type;
  346. /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
  347. /* Rx Side */
  348. u32 rx_ring_num; /*Number of receive rings */
  349. #define MAX_RX_BLOCKS_PER_RING 150
  350. struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
  351. u8 bimodal; /*Flag for setting bimodal interrupts*/
  352. #define HEADER_ETHERNET_II_802_3_SIZE 14
  353. #define HEADER_802_2_SIZE 3
  354. #define HEADER_SNAP_SIZE 5
  355. #define HEADER_VLAN_SIZE 4
  356. #define MIN_MTU 46
  357. #define MAX_PYLD 1500
  358. #define MAX_MTU (MAX_PYLD+18)
  359. #define MAX_MTU_VLAN (MAX_PYLD+22)
  360. #define MAX_PYLD_JUMBO 9600
  361. #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
  362. #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
  363. u16 bus_speed;
  364. };
  365. /* Structure representing MAC Addrs */
  366. struct mac_addr {
  367. u8 mac_addr[ETH_ALEN];
  368. };
  369. /* Structure that represent every FIFO element in the BAR1
  370. * Address location.
  371. */
  372. struct TxFIFO_element {
  373. u64 TxDL_Pointer;
  374. u64 List_Control;
  375. #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
  376. #define TX_FIFO_FIRST_LIST BIT(14)
  377. #define TX_FIFO_LAST_LIST BIT(15)
  378. #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
  379. #define TX_FIFO_SPECIAL_FUNC BIT(23)
  380. #define TX_FIFO_DS_NO_SNOOP BIT(31)
  381. #define TX_FIFO_BUFF_NO_SNOOP BIT(30)
  382. };
  383. /* Tx descriptor structure */
  384. struct TxD {
  385. u64 Control_1;
  386. /* bit mask */
  387. #define TXD_LIST_OWN_XENA BIT(7)
  388. #define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
  389. #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
  390. #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
  391. #define TXD_GATHER_CODE (BIT(22) | BIT(23))
  392. #define TXD_GATHER_CODE_FIRST BIT(22)
  393. #define TXD_GATHER_CODE_LAST BIT(23)
  394. #define TXD_TCP_LSO_EN BIT(30)
  395. #define TXD_UDP_COF_EN BIT(31)
  396. #define TXD_UFO_EN BIT(31) | BIT(30)
  397. #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
  398. #define TXD_UFO_MSS(val) vBIT(val,34,14)
  399. #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
  400. u64 Control_2;
  401. #define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
  402. #define TXD_TX_CKO_IPV4_EN BIT(5)
  403. #define TXD_TX_CKO_TCP_EN BIT(6)
  404. #define TXD_TX_CKO_UDP_EN BIT(7)
  405. #define TXD_VLAN_ENABLE BIT(15)
  406. #define TXD_VLAN_TAG(val) vBIT(val,16,16)
  407. #define TXD_INT_NUMBER(val) vBIT(val,34,6)
  408. #define TXD_INT_TYPE_PER_LIST BIT(47)
  409. #define TXD_INT_TYPE_UTILZ BIT(46)
  410. #define TXD_SET_MARKER vBIT(0x6,0,4)
  411. u64 Buffer_Pointer;
  412. u64 Host_Control; /* reserved for host */
  413. };
  414. /* Structure to hold the phy and virt addr of every TxDL. */
  415. struct list_info_hold {
  416. dma_addr_t list_phy_addr;
  417. void *list_virt_addr;
  418. };
  419. /* Rx descriptor structure for 1 buffer mode */
  420. struct RxD_t {
  421. u64 Host_Control; /* reserved for host */
  422. u64 Control_1;
  423. #define RXD_OWN_XENA BIT(7)
  424. #define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
  425. #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
  426. #define RXD_FRAME_PROTO_IPV4 BIT(27)
  427. #define RXD_FRAME_PROTO_IPV6 BIT(28)
  428. #define RXD_FRAME_IP_FRAG BIT(29)
  429. #define RXD_FRAME_PROTO_TCP BIT(30)
  430. #define RXD_FRAME_PROTO_UDP BIT(31)
  431. #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
  432. #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
  433. #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
  434. u64 Control_2;
  435. #define THE_RXD_MARK 0x3
  436. #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
  437. #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
  438. #define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
  439. #define SET_VLAN_TAG(val) vBIT(val,48,16)
  440. #define SET_NUM_TAG(val) vBIT(val,16,32)
  441. };
  442. /* Rx descriptor structure for 1 buffer mode */
  443. struct RxD1 {
  444. struct RxD_t h;
  445. #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
  446. #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
  447. #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
  448. (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
  449. u64 Buffer0_ptr;
  450. };
  451. /* Rx descriptor structure for 3 or 2 buffer mode */
  452. struct RxD3 {
  453. struct RxD_t h;
  454. #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
  455. #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
  456. #define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
  457. #define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
  458. #define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
  459. #define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
  460. #define RXD_GET_BUFFER0_SIZE_3(Control_2) \
  461. (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
  462. #define RXD_GET_BUFFER1_SIZE_3(Control_2) \
  463. (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
  464. #define RXD_GET_BUFFER2_SIZE_3(Control_2) \
  465. (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
  466. #define BUF0_LEN 40
  467. #define BUF1_LEN 1
  468. u64 Buffer0_ptr;
  469. u64 Buffer1_ptr;
  470. u64 Buffer2_ptr;
  471. };
  472. /* Structure that represents the Rx descriptor block which contains
  473. * 128 Rx descriptors.
  474. */
  475. struct RxD_block {
  476. #define MAX_RXDS_PER_BLOCK_1 127
  477. struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1];
  478. u64 reserved_0;
  479. #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
  480. u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
  481. * Rxd in this blk */
  482. u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
  483. u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
  484. * the upper 32 bits should
  485. * be 0 */
  486. };
  487. #define SIZE_OF_BLOCK 4096
  488. #define RXD_MODE_1 0 /* One Buffer mode */
  489. #define RXD_MODE_3A 1 /* Three Buffer mode */
  490. #define RXD_MODE_3B 2 /* Two Buffer mode */
  491. /* Structure to hold virtual addresses of Buf0 and Buf1 in
  492. * 2buf mode. */
  493. struct buffAdd {
  494. void *ba_0_org;
  495. void *ba_1_org;
  496. void *ba_0;
  497. void *ba_1;
  498. };
  499. /* Structure which stores all the MAC control parameters */
  500. /* This structure stores the offset of the RxD in the ring
  501. * from which the Rx Interrupt processor can start picking
  502. * up the RxDs for processing.
  503. */
  504. struct rx_curr_get_info {
  505. u32 block_index;
  506. u32 offset;
  507. u32 ring_len;
  508. };
  509. struct rx_curr_put_info {
  510. u32 block_index;
  511. u32 offset;
  512. u32 ring_len;
  513. };
  514. /* This structure stores the offset of the TxDl in the FIFO
  515. * from which the Tx Interrupt processor can start picking
  516. * up the TxDLs for send complete interrupt processing.
  517. */
  518. struct tx_curr_get_info {
  519. u32 offset;
  520. u32 fifo_len;
  521. };
  522. struct tx_curr_put_info {
  523. u32 offset;
  524. u32 fifo_len;
  525. };
  526. struct rxd_info {
  527. void *virt_addr;
  528. dma_addr_t dma_addr;
  529. };
  530. /* Structure that holds the Phy and virt addresses of the Blocks */
  531. struct rx_block_info {
  532. void *block_virt_addr;
  533. dma_addr_t block_dma_addr;
  534. struct rxd_info *rxds;
  535. };
  536. /* Ring specific structure */
  537. struct ring_info {
  538. /* The ring number */
  539. int ring_no;
  540. /*
  541. * Place holders for the virtual and physical addresses of
  542. * all the Rx Blocks
  543. */
  544. struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING];
  545. int block_count;
  546. int pkt_cnt;
  547. /*
  548. * Put pointer info which indictes which RxD has to be replenished
  549. * with a new buffer.
  550. */
  551. struct rx_curr_put_info rx_curr_put_info;
  552. /*
  553. * Get pointer info which indictes which is the last RxD that was
  554. * processed by the driver.
  555. */
  556. struct rx_curr_get_info rx_curr_get_info;
  557. /* Index to the absolute position of the put pointer of Rx ring */
  558. int put_pos;
  559. /* Buffer Address store. */
  560. struct buffAdd **ba;
  561. struct s2io_nic *nic;
  562. };
  563. /* Fifo specific structure */
  564. struct fifo_info {
  565. /* FIFO number */
  566. int fifo_no;
  567. /* Maximum TxDs per TxDL */
  568. int max_txds;
  569. /* Place holder of all the TX List's Phy and Virt addresses. */
  570. struct list_info_hold *list_info;
  571. /*
  572. * Current offset within the tx FIFO where driver would write
  573. * new Tx frame
  574. */
  575. struct tx_curr_put_info tx_curr_put_info;
  576. /*
  577. * Current offset within tx FIFO from where the driver would start freeing
  578. * the buffers
  579. */
  580. struct tx_curr_get_info tx_curr_get_info;
  581. struct s2io_nic *nic;
  582. };
  583. /* Information related to the Tx and Rx FIFOs and Rings of Xena
  584. * is maintained in this structure.
  585. */
  586. struct mac_info {
  587. /* tx side stuff */
  588. /* logical pointer of start of each Tx FIFO */
  589. struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS];
  590. /* Fifo specific structure */
  591. struct fifo_info fifos[MAX_TX_FIFOS];
  592. /* Save virtual address of TxD page with zero DMA addr(if any) */
  593. void *zerodma_virt_addr;
  594. /* rx side stuff */
  595. /* Ring specific structure */
  596. struct ring_info rings[MAX_RX_RINGS];
  597. u16 rmac_pause_time;
  598. u16 mc_pause_threshold_q0q3;
  599. u16 mc_pause_threshold_q4q7;
  600. void *stats_mem; /* orignal pointer to allocated mem */
  601. dma_addr_t stats_mem_phy; /* Physical address of the stat block */
  602. u32 stats_mem_sz;
  603. struct stat_block *stats_info; /* Logical address of the stat block */
  604. };
  605. /* structure representing the user defined MAC addresses */
  606. struct usr_addr {
  607. char addr[ETH_ALEN];
  608. int usage_cnt;
  609. };
  610. /* Default Tunable parameters of the NIC. */
  611. #define DEFAULT_FIFO_0_LEN 4096
  612. #define DEFAULT_FIFO_1_7_LEN 512
  613. #define SMALL_BLK_CNT 30
  614. #define LARGE_BLK_CNT 100
  615. /*
  616. * Structure to keep track of the MSI-X vectors and the corresponding
  617. * argument registered against each vector
  618. */
  619. #define MAX_REQUESTED_MSI_X 17
  620. struct s2io_msix_entry
  621. {
  622. u16 vector;
  623. u16 entry;
  624. void *arg;
  625. u8 type;
  626. #define MSIX_FIFO_TYPE 1
  627. #define MSIX_RING_TYPE 2
  628. u8 in_use;
  629. #define MSIX_REGISTERED_SUCCESS 0xAA
  630. };
  631. struct msix_info_st {
  632. u64 addr;
  633. u64 data;
  634. };
  635. /* Data structure to represent a LRO session */
  636. struct lro {
  637. struct sk_buff *parent;
  638. struct sk_buff *last_frag;
  639. u8 *l2h;
  640. struct iphdr *iph;
  641. struct tcphdr *tcph;
  642. u32 tcp_next_seq;
  643. __be32 tcp_ack;
  644. int total_len;
  645. int frags_len;
  646. int sg_num;
  647. int in_use;
  648. __be16 window;
  649. u32 cur_tsval;
  650. u32 cur_tsecr;
  651. u8 saw_ts;
  652. };
  653. /* Structure representing one instance of the NIC */
  654. struct s2io_nic {
  655. int rxd_mode;
  656. /*
  657. * Count of packets to be processed in a given iteration, it will be indicated
  658. * by the quota field of the device structure when NAPI is enabled.
  659. */
  660. int pkts_to_process;
  661. struct net_device *dev;
  662. struct mac_info mac_control;
  663. struct config_param config;
  664. struct pci_dev *pdev;
  665. void __iomem *bar0;
  666. void __iomem *bar1;
  667. #define MAX_MAC_SUPPORTED 16
  668. #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
  669. struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED];
  670. struct mac_addr pre_mac_addr[MAX_MAC_SUPPORTED];
  671. struct net_device_stats stats;
  672. int high_dma_flag;
  673. int device_close_flag;
  674. int device_enabled_once;
  675. char name[60];
  676. struct tasklet_struct task;
  677. volatile unsigned long tasklet_status;
  678. /* Timer that handles I/O errors/exceptions */
  679. struct timer_list alarm_timer;
  680. /* Space to back up the PCI config space */
  681. u32 config_space[256 / sizeof(u32)];
  682. atomic_t rx_bufs_left[MAX_RX_RINGS];
  683. spinlock_t tx_lock;
  684. spinlock_t put_lock;
  685. #define PROMISC 1
  686. #define ALL_MULTI 2
  687. #define MAX_ADDRS_SUPPORTED 64
  688. u16 usr_addr_count;
  689. u16 mc_addr_count;
  690. struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED];
  691. u16 m_cast_flg;
  692. u16 all_multi_pos;
  693. u16 promisc_flg;
  694. u16 tx_pkt_count;
  695. u16 rx_pkt_count;
  696. u16 tx_err_count;
  697. u16 rx_err_count;
  698. /* Id timer, used to blink NIC to physically identify NIC. */
  699. struct timer_list id_timer;
  700. /* Restart timer, used to restart NIC if the device is stuck and
  701. * a schedule task that will set the correct Link state once the
  702. * NIC's PHY has stabilized after a state change.
  703. */
  704. struct work_struct rst_timer_task;
  705. struct work_struct set_link_task;
  706. /* Flag that can be used to turn on or turn off the Rx checksum
  707. * offload feature.
  708. */
  709. int rx_csum;
  710. /* after blink, the adapter must be restored with original
  711. * values.
  712. */
  713. u64 adapt_ctrl_org;
  714. /* Last known link state. */
  715. u16 last_link_state;
  716. #define LINK_DOWN 1
  717. #define LINK_UP 2
  718. int task_flag;
  719. #define CARD_DOWN 1
  720. #define CARD_UP 2
  721. atomic_t card_state;
  722. volatile unsigned long link_state;
  723. struct vlan_group *vlgrp;
  724. #define MSIX_FLG 0xA5
  725. struct msix_entry *entries;
  726. struct s2io_msix_entry *s2io_entries;
  727. char desc[MAX_REQUESTED_MSI_X][25];
  728. int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
  729. struct msix_info_st msix_info[0x3f];
  730. #define XFRAME_I_DEVICE 1
  731. #define XFRAME_II_DEVICE 2
  732. u8 device_type;
  733. #define MAX_LRO_SESSIONS 32
  734. struct lro lro0_n[MAX_LRO_SESSIONS];
  735. unsigned long clubbed_frms_cnt;
  736. unsigned long sending_both;
  737. u8 lro;
  738. u16 lro_max_aggr_per_sess;
  739. #define INTA 0
  740. #define MSI 1
  741. #define MSI_X 2
  742. u8 intr_type;
  743. spinlock_t rx_lock;
  744. atomic_t isr_cnt;
  745. u64 *ufo_in_band_v;
  746. #define VPD_STRING_LEN 80
  747. u8 product_name[VPD_STRING_LEN];
  748. u8 serial_num[VPD_STRING_LEN];
  749. };
  750. #define RESET_ERROR 1;
  751. #define CMD_ERROR 2;
  752. /* OS related system calls */
  753. #ifndef readq
  754. static inline u64 readq(void __iomem *addr)
  755. {
  756. u64 ret = 0;
  757. ret = readl(addr + 4);
  758. ret <<= 32;
  759. ret |= readl(addr);
  760. return ret;
  761. }
  762. #endif
  763. #ifndef writeq
  764. static inline void writeq(u64 val, void __iomem *addr)
  765. {
  766. writel((u32) (val), addr);
  767. writel((u32) (val >> 32), (addr + 4));
  768. }
  769. #endif
  770. /*
  771. * Some registers have to be written in a particular order to
  772. * expect correct hardware operation. The macro SPECIAL_REG_WRITE
  773. * is used to perform such ordered writes. Defines UF (Upper First)
  774. * and LF (Lower First) will be used to specify the required write order.
  775. */
  776. #define UF 1
  777. #define LF 2
  778. static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
  779. {
  780. u32 ret;
  781. if (order == LF) {
  782. writel((u32) (val), addr);
  783. ret = readl(addr);
  784. writel((u32) (val >> 32), (addr + 4));
  785. ret = readl(addr + 4);
  786. } else {
  787. writel((u32) (val >> 32), (addr + 4));
  788. ret = readl(addr + 4);
  789. writel((u32) (val), addr);
  790. ret = readl(addr);
  791. }
  792. }
  793. /* Interrupt related values of Xena */
  794. #define ENABLE_INTRS 1
  795. #define DISABLE_INTRS 2
  796. /* Highest level interrupt blocks */
  797. #define TX_PIC_INTR (0x0001<<0)
  798. #define TX_DMA_INTR (0x0001<<1)
  799. #define TX_MAC_INTR (0x0001<<2)
  800. #define TX_XGXS_INTR (0x0001<<3)
  801. #define TX_TRAFFIC_INTR (0x0001<<4)
  802. #define RX_PIC_INTR (0x0001<<5)
  803. #define RX_DMA_INTR (0x0001<<6)
  804. #define RX_MAC_INTR (0x0001<<7)
  805. #define RX_XGXS_INTR (0x0001<<8)
  806. #define RX_TRAFFIC_INTR (0x0001<<9)
  807. #define MC_INTR (0x0001<<10)
  808. #define ENA_ALL_INTRS ( TX_PIC_INTR | \
  809. TX_DMA_INTR | \
  810. TX_MAC_INTR | \
  811. TX_XGXS_INTR | \
  812. TX_TRAFFIC_INTR | \
  813. RX_PIC_INTR | \
  814. RX_DMA_INTR | \
  815. RX_MAC_INTR | \
  816. RX_XGXS_INTR | \
  817. RX_TRAFFIC_INTR | \
  818. MC_INTR )
  819. /* Interrupt masks for the general interrupt mask register */
  820. #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
  821. #define TXPIC_INT_M BIT(0)
  822. #define TXDMA_INT_M BIT(1)
  823. #define TXMAC_INT_M BIT(2)
  824. #define TXXGXS_INT_M BIT(3)
  825. #define TXTRAFFIC_INT_M BIT(8)
  826. #define PIC_RX_INT_M BIT(32)
  827. #define RXDMA_INT_M BIT(33)
  828. #define RXMAC_INT_M BIT(34)
  829. #define MC_INT_M BIT(35)
  830. #define RXXGXS_INT_M BIT(36)
  831. #define RXTRAFFIC_INT_M BIT(40)
  832. /* PIC level Interrupts TODO*/
  833. /* DMA level Inressupts */
  834. #define TXDMA_PFC_INT_M BIT(0)
  835. #define TXDMA_PCC_INT_M BIT(2)
  836. /* PFC block interrupts */
  837. #define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
  838. /* PCC block interrupts. */
  839. #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
  840. PCC_FB_ECC Error. */
  841. #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
  842. /*
  843. * Prototype declaration.
  844. */
  845. static int __devinit s2io_init_nic(struct pci_dev *pdev,
  846. const struct pci_device_id *pre);
  847. static void __devexit s2io_rem_nic(struct pci_dev *pdev);
  848. static int init_shared_mem(struct s2io_nic *sp);
  849. static void free_shared_mem(struct s2io_nic *sp);
  850. static int init_nic(struct s2io_nic *nic);
  851. static void rx_intr_handler(struct ring_info *ring_data);
  852. static void tx_intr_handler(struct fifo_info *fifo_data);
  853. static void alarm_intr_handler(struct s2io_nic *sp);
  854. static int s2io_starter(void);
  855. static void s2io_closer(void);
  856. static void s2io_tx_watchdog(struct net_device *dev);
  857. static void s2io_tasklet(unsigned long dev_addr);
  858. static void s2io_set_multicast(struct net_device *dev);
  859. static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp);
  860. static void s2io_link(struct s2io_nic * sp, int link);
  861. static void s2io_reset(struct s2io_nic * sp);
  862. static int s2io_poll(struct net_device *dev, int *budget);
  863. static void s2io_init_pci(struct s2io_nic * sp);
  864. static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
  865. static void s2io_alarm_handle(unsigned long data);
  866. static int s2io_enable_msi(struct s2io_nic *nic);
  867. static irqreturn_t s2io_msi_handle(int irq, void *dev_id);
  868. static irqreturn_t
  869. s2io_msix_ring_handle(int irq, void *dev_id);
  870. static irqreturn_t
  871. s2io_msix_fifo_handle(int irq, void *dev_id);
  872. static irqreturn_t s2io_isr(int irq, void *dev_id);
  873. static int verify_xena_quiescence(struct s2io_nic *sp);
  874. static const struct ethtool_ops netdev_ethtool_ops;
  875. static void s2io_set_link(struct work_struct *work);
  876. static int s2io_set_swapper(struct s2io_nic * sp);
  877. static void s2io_card_down(struct s2io_nic *nic);
  878. static int s2io_card_up(struct s2io_nic *nic);
  879. static int get_xena_rev_id(struct pci_dev *pdev);
  880. static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
  881. int bit_state);
  882. static int s2io_add_isr(struct s2io_nic * sp);
  883. static void s2io_rem_isr(struct s2io_nic * sp);
  884. static void restore_xmsi_data(struct s2io_nic *nic);
  885. static int
  886. s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
  887. struct RxD_t *rxdp, struct s2io_nic *sp);
  888. static void clear_lro_session(struct lro *lro);
  889. static void queue_rx_frame(struct sk_buff *skb);
  890. static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro);
  891. static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
  892. struct sk_buff *skb, u32 tcp_len);
  893. static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring);
  894. #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size
  895. #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size
  896. #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type
  897. #define S2IO_PARM_INT(X, def_val) \
  898. static unsigned int X = def_val;\
  899. module_param(X , uint, 0);
  900. #endif /* _S2IO_H */