s2io-regs.h 28 KB

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  1. /************************************************************************
  2. * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
  3. * Copyright(c) 2002-2005 Neterion Inc.
  4. * This software may be used and distributed according to the terms of
  5. * the GNU General Public License (GPL), incorporated herein by reference.
  6. * Drivers based on or derived from this code fall under the GPL and must
  7. * retain the authorship, copyright and license notice. This file is not
  8. * a complete program and may only be used when the entire operating
  9. * system is licensed under the GPL.
  10. * See the file COPYING in this distribution for more information.
  11. ************************************************************************/
  12. #ifndef _REGS_H
  13. #define _REGS_H
  14. #define TBD 0
  15. struct XENA_dev_config {
  16. /* Convention: mHAL_XXX is mask, vHAL_XXX is value */
  17. /* General Control-Status Registers */
  18. u64 general_int_status;
  19. #define GEN_INTR_TXPIC BIT(0)
  20. #define GEN_INTR_TXDMA BIT(1)
  21. #define GEN_INTR_TXMAC BIT(2)
  22. #define GEN_INTR_TXXGXS BIT(3)
  23. #define GEN_INTR_TXTRAFFIC BIT(8)
  24. #define GEN_INTR_RXPIC BIT(32)
  25. #define GEN_INTR_RXDMA BIT(33)
  26. #define GEN_INTR_RXMAC BIT(34)
  27. #define GEN_INTR_MC BIT(35)
  28. #define GEN_INTR_RXXGXS BIT(36)
  29. #define GEN_INTR_RXTRAFFIC BIT(40)
  30. #define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
  31. GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
  32. GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
  33. GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
  34. GEN_INTR_MC
  35. u64 general_int_mask;
  36. u8 unused0[0x100 - 0x10];
  37. u64 sw_reset;
  38. /* XGXS must be removed from reset only once. */
  39. #define SW_RESET_XENA vBIT(0xA5,0,8)
  40. #define SW_RESET_FLASH vBIT(0xA5,8,8)
  41. #define SW_RESET_EOI vBIT(0xA5,16,8)
  42. #define SW_RESET_ALL (SW_RESET_XENA | \
  43. SW_RESET_FLASH | \
  44. SW_RESET_EOI)
  45. /* The SW_RESET register must read this value after a successful reset. */
  46. #define SW_RESET_RAW_VAL 0xA5000000
  47. u64 adapter_status;
  48. #define ADAPTER_STATUS_TDMA_READY BIT(0)
  49. #define ADAPTER_STATUS_RDMA_READY BIT(1)
  50. #define ADAPTER_STATUS_PFC_READY BIT(2)
  51. #define ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3)
  52. #define ADAPTER_STATUS_PIC_QUIESCENT BIT(5)
  53. #define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)
  54. #define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)
  55. #define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
  56. #define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)
  57. #define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
  58. #define ADAPTER_STATUS_MC_DRAM_READY BIT(24)
  59. #define ADAPTER_STATUS_MC_QUEUES_READY BIT(25)
  60. #define ADAPTER_STATUS_M_PLL_LOCK BIT(30)
  61. #define ADAPTER_STATUS_P_PLL_LOCK BIT(31)
  62. u64 adapter_control;
  63. #define ADAPTER_CNTL_EN BIT(7)
  64. #define ADAPTER_EOI_TX_ON BIT(15)
  65. #define ADAPTER_LED_ON BIT(23)
  66. #define ADAPTER_UDPI(val) vBIT(val,36,4)
  67. #define ADAPTER_WAIT_INT BIT(48)
  68. #define ADAPTER_ECC_EN BIT(55)
  69. u64 serr_source;
  70. #define SERR_SOURCE_PIC BIT(0)
  71. #define SERR_SOURCE_TXDMA BIT(1)
  72. #define SERR_SOURCE_RXDMA BIT(2)
  73. #define SERR_SOURCE_MAC BIT(3)
  74. #define SERR_SOURCE_MC BIT(4)
  75. #define SERR_SOURCE_XGXS BIT(5)
  76. #define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
  77. SERR_SOURCE_TXDMA | \
  78. SERR_SOURCE_RXDMA | \
  79. SERR_SOURCE_MAC | \
  80. SERR_SOURCE_MC | \
  81. SERR_SOURCE_XGXS)
  82. u64 pci_mode;
  83. #define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)
  84. #define PCI_MODE_PCI_33 0
  85. #define PCI_MODE_PCI_66 0x1
  86. #define PCI_MODE_PCIX_M1_66 0x2
  87. #define PCI_MODE_PCIX_M1_100 0x3
  88. #define PCI_MODE_PCIX_M1_133 0x4
  89. #define PCI_MODE_PCIX_M2_66 0x5
  90. #define PCI_MODE_PCIX_M2_100 0x6
  91. #define PCI_MODE_PCIX_M2_133 0x7
  92. #define PCI_MODE_UNSUPPORTED BIT(0)
  93. #define PCI_MODE_32_BITS BIT(8)
  94. #define PCI_MODE_UNKNOWN_MODE BIT(9)
  95. u8 unused_0[0x800 - 0x128];
  96. /* PCI-X Controller registers */
  97. u64 pic_int_status;
  98. u64 pic_int_mask;
  99. #define PIC_INT_TX BIT(0)
  100. #define PIC_INT_FLSH BIT(1)
  101. #define PIC_INT_MDIO BIT(2)
  102. #define PIC_INT_IIC BIT(3)
  103. #define PIC_INT_GPIO BIT(4)
  104. #define PIC_INT_RX BIT(32)
  105. u64 txpic_int_reg;
  106. u64 txpic_int_mask;
  107. #define PCIX_INT_REG_ECC_SG_ERR BIT(0)
  108. #define PCIX_INT_REG_ECC_DB_ERR BIT(1)
  109. #define PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8)
  110. #define PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9)
  111. #define PCIX_INT_REG_INI_TX_FSM_SERR BIT(10)
  112. #define PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11)
  113. #define PCIX_INT_REG_TRT_FSM_SERR BIT(13)
  114. #define PCIX_INT_REG_SRT_FSM_SERR BIT(14)
  115. #define PCIX_INT_REG_PIFR_FSM_SERR BIT(15)
  116. #define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21)
  117. #define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23)
  118. #define PCIX_INT_REG_INI_RX_FSM_SERR BIT(48)
  119. #define PCIX_INT_REG_RA_RX_FSM_SERR BIT(50)
  120. /*
  121. #define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
  122. #define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
  123. #define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
  124. */
  125. u64 txpic_alarms;
  126. u64 rxpic_int_reg;
  127. u64 rxpic_int_mask;
  128. u64 rxpic_alarms;
  129. u64 flsh_int_reg;
  130. u64 flsh_int_mask;
  131. #define PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63)
  132. #define PIC_FLSH_INT_REG_ERR BIT(62)
  133. u64 flash_alarms;
  134. u64 mdio_int_reg;
  135. u64 mdio_int_mask;
  136. #define MDIO_INT_REG_MDIO_BUS_ERR BIT(0)
  137. #define MDIO_INT_REG_DTX_BUS_ERR BIT(8)
  138. #define MDIO_INT_REG_LASI BIT(39)
  139. u64 mdio_alarms;
  140. u64 iic_int_reg;
  141. u64 iic_int_mask;
  142. #define IIC_INT_REG_BUS_FSM_ERR BIT(4)
  143. #define IIC_INT_REG_BIT_FSM_ERR BIT(5)
  144. #define IIC_INT_REG_CYCLE_FSM_ERR BIT(6)
  145. #define IIC_INT_REG_REQ_FSM_ERR BIT(7)
  146. #define IIC_INT_REG_ACK_ERR BIT(8)
  147. u64 iic_alarms;
  148. u8 unused4[0x08];
  149. u64 gpio_int_reg;
  150. #define GPIO_INT_REG_DP_ERR_INT BIT(0)
  151. #define GPIO_INT_REG_LINK_DOWN BIT(1)
  152. #define GPIO_INT_REG_LINK_UP BIT(2)
  153. u64 gpio_int_mask;
  154. #define GPIO_INT_MASK_LINK_DOWN BIT(1)
  155. #define GPIO_INT_MASK_LINK_UP BIT(2)
  156. u64 gpio_alarms;
  157. u8 unused5[0x38];
  158. u64 tx_traffic_int;
  159. #define TX_TRAFFIC_INT_n(n) BIT(n)
  160. u64 tx_traffic_mask;
  161. u64 rx_traffic_int;
  162. #define RX_TRAFFIC_INT_n(n) BIT(n)
  163. u64 rx_traffic_mask;
  164. /* PIC Control registers */
  165. u64 pic_control;
  166. #define PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
  167. #define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5)
  168. u64 swapper_ctrl;
  169. #define SWAPPER_CTRL_PIF_R_FE BIT(0)
  170. #define SWAPPER_CTRL_PIF_R_SE BIT(1)
  171. #define SWAPPER_CTRL_PIF_W_FE BIT(8)
  172. #define SWAPPER_CTRL_PIF_W_SE BIT(9)
  173. #define SWAPPER_CTRL_TXP_FE BIT(16)
  174. #define SWAPPER_CTRL_TXP_SE BIT(17)
  175. #define SWAPPER_CTRL_TXD_R_FE BIT(18)
  176. #define SWAPPER_CTRL_TXD_R_SE BIT(19)
  177. #define SWAPPER_CTRL_TXD_W_FE BIT(20)
  178. #define SWAPPER_CTRL_TXD_W_SE BIT(21)
  179. #define SWAPPER_CTRL_TXF_R_FE BIT(22)
  180. #define SWAPPER_CTRL_TXF_R_SE BIT(23)
  181. #define SWAPPER_CTRL_RXD_R_FE BIT(32)
  182. #define SWAPPER_CTRL_RXD_R_SE BIT(33)
  183. #define SWAPPER_CTRL_RXD_W_FE BIT(34)
  184. #define SWAPPER_CTRL_RXD_W_SE BIT(35)
  185. #define SWAPPER_CTRL_RXF_W_FE BIT(36)
  186. #define SWAPPER_CTRL_RXF_W_SE BIT(37)
  187. #define SWAPPER_CTRL_XMSI_FE BIT(40)
  188. #define SWAPPER_CTRL_XMSI_SE BIT(41)
  189. #define SWAPPER_CTRL_STATS_FE BIT(48)
  190. #define SWAPPER_CTRL_STATS_SE BIT(49)
  191. u64 pif_rd_swapper_fb;
  192. #define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
  193. u64 scheduled_int_ctrl;
  194. #define SCHED_INT_CTRL_TIMER_EN BIT(0)
  195. #define SCHED_INT_CTRL_ONE_SHOT BIT(1)
  196. #define SCHED_INT_CTRL_INT2MSI TBD
  197. #define SCHED_INT_PERIOD TBD
  198. u64 txreqtimeout;
  199. #define TXREQTO_VAL(val) vBIT(val,0,32)
  200. #define TXREQTO_EN BIT(63)
  201. u64 statsreqtimeout;
  202. #define STATREQTO_VAL(n) TBD
  203. #define STATREQTO_EN BIT(63)
  204. u64 read_retry_delay;
  205. u64 read_retry_acceleration;
  206. u64 write_retry_delay;
  207. u64 write_retry_acceleration;
  208. u64 xmsi_control;
  209. u64 xmsi_access;
  210. u64 xmsi_address;
  211. u64 xmsi_data;
  212. u64 rx_mat;
  213. #define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8)
  214. u8 unused6[0x8];
  215. u64 tx_mat0_n[0x8];
  216. #define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
  217. u8 unused_1[0x8];
  218. u64 stat_byte_cnt;
  219. #define STAT_BC(n) vBIT(n,4,12)
  220. /* Automated statistics collection */
  221. u64 stat_cfg;
  222. #define STAT_CFG_STAT_EN BIT(0)
  223. #define STAT_CFG_ONE_SHOT_EN BIT(1)
  224. #define STAT_CFG_STAT_NS_EN BIT(8)
  225. #define STAT_CFG_STAT_RO BIT(9)
  226. #define STAT_TRSF_PER(n) TBD
  227. #define PER_SEC 0x208d5
  228. #define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
  229. #define SET_UPDT_CLICKS(val) vBIT(val, 32, 32)
  230. u64 stat_addr;
  231. /* General Configuration */
  232. u64 mdio_control;
  233. #define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16)
  234. #define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5)
  235. #define MDIO_MMD_PMA_DEV_ADDR 0x1
  236. #define MDIO_MMD_PMD_DEV_ADDR 0x1
  237. #define MDIO_MMD_WIS_DEV_ADDR 0x2
  238. #define MDIO_MMD_PCS_DEV_ADDR 0x3
  239. #define MDIO_MMD_PHYXS_DEV_ADDR 0x4
  240. #define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5)
  241. #define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4)
  242. #define MDIO_OP(val) vBIT(val, 60, 2)
  243. #define MDIO_OP_ADDR_TRANS 0x0
  244. #define MDIO_OP_WRITE_TRANS 0x1
  245. #define MDIO_OP_READ_POST_INC_TRANS 0x2
  246. #define MDIO_OP_READ_TRANS 0x3
  247. #define MDIO_MDIO_DATA(val) vBIT(val, 32, 16)
  248. u64 dtx_control;
  249. u64 i2c_control;
  250. #define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
  251. #define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
  252. #define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
  253. #define I2C_CONTROL_READ BIT(24)
  254. #define I2C_CONTROL_NACK BIT(25)
  255. #define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
  256. #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
  257. #define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
  258. #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
  259. u64 gpio_control;
  260. #define GPIO_CTRL_GPIO_0 BIT(8)
  261. u64 misc_control;
  262. #define FAULT_BEHAVIOUR BIT(0)
  263. #define EXT_REQ_EN BIT(1)
  264. #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
  265. u8 unused7_1[0x230 - 0x208];
  266. u64 pic_control2;
  267. u64 ini_dperr_ctrl;
  268. u64 wreq_split_mask;
  269. #define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
  270. u8 unused7_2[0x800 - 0x248];
  271. /* TxDMA registers */
  272. u64 txdma_int_status;
  273. u64 txdma_int_mask;
  274. #define TXDMA_PFC_INT BIT(0)
  275. #define TXDMA_TDA_INT BIT(1)
  276. #define TXDMA_PCC_INT BIT(2)
  277. #define TXDMA_TTI_INT BIT(3)
  278. #define TXDMA_LSO_INT BIT(4)
  279. #define TXDMA_TPA_INT BIT(5)
  280. #define TXDMA_SM_INT BIT(6)
  281. u64 pfc_err_reg;
  282. u64 pfc_err_mask;
  283. u64 pfc_err_alarm;
  284. u64 tda_err_reg;
  285. u64 tda_err_mask;
  286. u64 tda_err_alarm;
  287. u64 pcc_err_reg;
  288. #define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8)
  289. #define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
  290. u64 pcc_err_mask;
  291. u64 pcc_err_alarm;
  292. u64 tti_err_reg;
  293. u64 tti_err_mask;
  294. u64 tti_err_alarm;
  295. u64 lso_err_reg;
  296. u64 lso_err_mask;
  297. u64 lso_err_alarm;
  298. u64 tpa_err_reg;
  299. u64 tpa_err_mask;
  300. u64 tpa_err_alarm;
  301. u64 sm_err_reg;
  302. u64 sm_err_mask;
  303. u64 sm_err_alarm;
  304. u8 unused8[0x100 - 0xB8];
  305. /* TxDMA arbiter */
  306. u64 tx_dma_wrap_stat;
  307. /* Tx FIFO controller */
  308. #define X_MAX_FIFOS 8
  309. #define X_FIFO_MAX_LEN 0x1FFF /*8191 */
  310. u64 tx_fifo_partition_0;
  311. #define TX_FIFO_PARTITION_EN BIT(0)
  312. #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
  313. #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
  314. #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
  315. #define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
  316. u64 tx_fifo_partition_1;
  317. #define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
  318. #define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
  319. #define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
  320. #define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
  321. u64 tx_fifo_partition_2;
  322. #define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
  323. #define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
  324. #define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
  325. #define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
  326. u64 tx_fifo_partition_3;
  327. #define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
  328. #define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
  329. #define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
  330. #define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
  331. #define TX_FIFO_PARTITION_PRI_0 0 /* highest */
  332. #define TX_FIFO_PARTITION_PRI_1 1
  333. #define TX_FIFO_PARTITION_PRI_2 2
  334. #define TX_FIFO_PARTITION_PRI_3 3
  335. #define TX_FIFO_PARTITION_PRI_4 4
  336. #define TX_FIFO_PARTITION_PRI_5 5
  337. #define TX_FIFO_PARTITION_PRI_6 6
  338. #define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
  339. u64 tx_w_round_robin_0;
  340. u64 tx_w_round_robin_1;
  341. u64 tx_w_round_robin_2;
  342. u64 tx_w_round_robin_3;
  343. u64 tx_w_round_robin_4;
  344. u64 tti_command_mem;
  345. #define TTI_CMD_MEM_WE BIT(7)
  346. #define TTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
  347. #define TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15)
  348. #define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
  349. u64 tti_data1_mem;
  350. #define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
  351. #define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
  352. #define TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38)
  353. #define TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39)
  354. #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
  355. #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
  356. #define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
  357. u64 tti_data2_mem;
  358. #define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
  359. #define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
  360. #define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
  361. #define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
  362. /* Tx Protocol assist */
  363. u64 tx_pa_cfg;
  364. #define TX_PA_CFG_IGNORE_FRM_ERR BIT(1)
  365. #define TX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
  366. #define TX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
  367. #define TX_PA_CFG_IGNORE_L2_ERR BIT(6)
  368. #define RX_PA_CFG_STRIP_VLAN_TAG BIT(15)
  369. /* Recent add, used only debug purposes. */
  370. u64 pcc_enable;
  371. u8 unused9[0x700 - 0x178];
  372. u64 txdma_debug_ctrl;
  373. u8 unused10[0x1800 - 0x1708];
  374. /* RxDMA Registers */
  375. u64 rxdma_int_status;
  376. u64 rxdma_int_mask;
  377. #define RXDMA_INT_RC_INT_M BIT(0)
  378. #define RXDMA_INT_RPA_INT_M BIT(1)
  379. #define RXDMA_INT_RDA_INT_M BIT(2)
  380. #define RXDMA_INT_RTI_INT_M BIT(3)
  381. u64 rda_err_reg;
  382. u64 rda_err_mask;
  383. u64 rda_err_alarm;
  384. u64 rc_err_reg;
  385. u64 rc_err_mask;
  386. u64 rc_err_alarm;
  387. u64 prc_pcix_err_reg;
  388. u64 prc_pcix_err_mask;
  389. u64 prc_pcix_err_alarm;
  390. u64 rpa_err_reg;
  391. u64 rpa_err_mask;
  392. u64 rpa_err_alarm;
  393. u64 rti_err_reg;
  394. u64 rti_err_mask;
  395. u64 rti_err_alarm;
  396. u8 unused11[0x100 - 0x88];
  397. /* DMA arbiter */
  398. u64 rx_queue_priority;
  399. #define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
  400. #define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
  401. #define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
  402. #define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
  403. #define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
  404. #define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
  405. #define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
  406. #define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
  407. #define RX_QUEUE_PRI_0 0 /* highest */
  408. #define RX_QUEUE_PRI_1 1
  409. #define RX_QUEUE_PRI_2 2
  410. #define RX_QUEUE_PRI_3 3
  411. #define RX_QUEUE_PRI_4 4
  412. #define RX_QUEUE_PRI_5 5
  413. #define RX_QUEUE_PRI_6 6
  414. #define RX_QUEUE_PRI_7 7 /* lowest */
  415. u64 rx_w_round_robin_0;
  416. u64 rx_w_round_robin_1;
  417. u64 rx_w_round_robin_2;
  418. u64 rx_w_round_robin_3;
  419. u64 rx_w_round_robin_4;
  420. /* Per-ring controller regs */
  421. #define RX_MAX_RINGS 8
  422. #if 0
  423. #define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */
  424. #define RX_MIN_RINGS_SZ 0x3F /* 63 */
  425. #endif
  426. u64 prc_rxd0_n[RX_MAX_RINGS];
  427. u64 prc_ctrl_n[RX_MAX_RINGS];
  428. #define PRC_CTRL_RC_ENABLED BIT(7)
  429. #define PRC_CTRL_RING_MODE (BIT(14)|BIT(15))
  430. #define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
  431. #define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
  432. #define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
  433. #define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
  434. #define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23))
  435. #define PRC_CTRL_NO_SNOOP_DESC BIT(22)
  436. #define PRC_CTRL_NO_SNOOP_BUFF BIT(23)
  437. #define PRC_CTRL_BIMODAL_INTERRUPT BIT(37)
  438. #define PRC_CTRL_GROUP_READS BIT(38)
  439. #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
  440. u64 prc_alarm_action;
  441. #define PRC_ALARM_ACTION_RR_R0_STOP BIT(3)
  442. #define PRC_ALARM_ACTION_RW_R0_STOP BIT(7)
  443. #define PRC_ALARM_ACTION_RR_R1_STOP BIT(11)
  444. #define PRC_ALARM_ACTION_RW_R1_STOP BIT(15)
  445. #define PRC_ALARM_ACTION_RR_R2_STOP BIT(19)
  446. #define PRC_ALARM_ACTION_RW_R2_STOP BIT(23)
  447. #define PRC_ALARM_ACTION_RR_R3_STOP BIT(27)
  448. #define PRC_ALARM_ACTION_RW_R3_STOP BIT(31)
  449. #define PRC_ALARM_ACTION_RR_R4_STOP BIT(35)
  450. #define PRC_ALARM_ACTION_RW_R4_STOP BIT(39)
  451. #define PRC_ALARM_ACTION_RR_R5_STOP BIT(43)
  452. #define PRC_ALARM_ACTION_RW_R5_STOP BIT(47)
  453. #define PRC_ALARM_ACTION_RR_R6_STOP BIT(51)
  454. #define PRC_ALARM_ACTION_RW_R6_STOP BIT(55)
  455. #define PRC_ALARM_ACTION_RR_R7_STOP BIT(59)
  456. #define PRC_ALARM_ACTION_RW_R7_STOP BIT(63)
  457. /* Receive traffic interrupts */
  458. u64 rti_command_mem;
  459. #define RTI_CMD_MEM_WE BIT(7)
  460. #define RTI_CMD_MEM_STROBE BIT(15)
  461. #define RTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
  462. #define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)
  463. #define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
  464. u64 rti_data1_mem;
  465. #define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
  466. #define RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38)
  467. #define RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39)
  468. #define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
  469. #define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
  470. #define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
  471. u64 rti_data2_mem;
  472. #define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
  473. #define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
  474. #define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
  475. #define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
  476. u64 rx_pa_cfg;
  477. #define RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
  478. #define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
  479. #define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
  480. #define RX_PA_CFG_IGNORE_L2_ERR BIT(6)
  481. u64 unused_11_1;
  482. u64 ring_bump_counter1;
  483. u64 ring_bump_counter2;
  484. u8 unused12[0x700 - 0x1F0];
  485. u64 rxdma_debug_ctrl;
  486. u8 unused13[0x2000 - 0x1f08];
  487. /* Media Access Controller Register */
  488. u64 mac_int_status;
  489. u64 mac_int_mask;
  490. #define MAC_INT_STATUS_TMAC_INT BIT(0)
  491. #define MAC_INT_STATUS_RMAC_INT BIT(1)
  492. u64 mac_tmac_err_reg;
  493. #define TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15)
  494. #define TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23)
  495. #define TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31)
  496. u64 mac_tmac_err_mask;
  497. u64 mac_tmac_err_alarm;
  498. u64 mac_rmac_err_reg;
  499. #define RMAC_ERR_REG_RX_BUFF_OVRN BIT(0)
  500. #define RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14)
  501. #define RMAC_ERR_REG_ECC_DB_ERR BIT(15)
  502. #define RMAC_LINK_STATE_CHANGE_INT BIT(31)
  503. u64 mac_rmac_err_mask;
  504. u64 mac_rmac_err_alarm;
  505. u8 unused14[0x100 - 0x40];
  506. u64 mac_cfg;
  507. #define MAC_CFG_TMAC_ENABLE BIT(0)
  508. #define MAC_CFG_RMAC_ENABLE BIT(1)
  509. #define MAC_CFG_LAN_NOT_WAN BIT(2)
  510. #define MAC_CFG_TMAC_LOOPBACK BIT(3)
  511. #define MAC_CFG_TMAC_APPEND_PAD BIT(4)
  512. #define MAC_CFG_RMAC_STRIP_FCS BIT(5)
  513. #define MAC_CFG_RMAC_STRIP_PAD BIT(6)
  514. #define MAC_CFG_RMAC_PROM_ENABLE BIT(7)
  515. #define MAC_RMAC_DISCARD_PFRM BIT(8)
  516. #define MAC_RMAC_BCAST_ENABLE BIT(9)
  517. #define MAC_RMAC_ALL_ADDR_ENABLE BIT(10)
  518. #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
  519. u64 tmac_avg_ipg;
  520. #define TMAC_AVG_IPG(val) vBIT(val,0,8)
  521. u64 rmac_max_pyld_len;
  522. #define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
  523. #define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
  524. #define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
  525. u64 rmac_err_cfg;
  526. #define RMAC_ERR_FCS BIT(0)
  527. #define RMAC_ERR_FCS_ACCEPT BIT(1)
  528. #define RMAC_ERR_TOO_LONG BIT(1)
  529. #define RMAC_ERR_TOO_LONG_ACCEPT BIT(1)
  530. #define RMAC_ERR_RUNT BIT(2)
  531. #define RMAC_ERR_RUNT_ACCEPT BIT(2)
  532. #define RMAC_ERR_LEN_MISMATCH BIT(3)
  533. #define RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3)
  534. u64 rmac_cfg_key;
  535. #define RMAC_CFG_KEY(val) vBIT(val,0,16)
  536. #define MAX_MAC_ADDRESSES 16
  537. #define MAX_MC_ADDRESSES 32 /* Multicast addresses */
  538. #define MAC_MAC_ADDR_START_OFFSET 0
  539. #define MAC_MC_ADDR_START_OFFSET 16
  540. #define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */
  541. u64 rmac_addr_cmd_mem;
  542. #define RMAC_ADDR_CMD_MEM_WE BIT(7)
  543. #define RMAC_ADDR_CMD_MEM_RD 0
  544. #define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15)
  545. #define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15)
  546. #define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
  547. u64 rmac_addr_data0_mem;
  548. #define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
  549. #define RMAC_ADDR_DATA0_MEM_USER BIT(48)
  550. u64 rmac_addr_data1_mem;
  551. #define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
  552. u8 unused15[0x8];
  553. /*
  554. u64 rmac_addr_cfg;
  555. #define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
  556. #define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
  557. #define RMAC_ADDR_BCAST_EN vBIT(0)_48
  558. #define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
  559. */
  560. u64 tmac_ipg_cfg;
  561. u64 rmac_pause_cfg;
  562. #define RMAC_PAUSE_GEN BIT(0)
  563. #define RMAC_PAUSE_GEN_ENABLE BIT(0)
  564. #define RMAC_PAUSE_RX BIT(1)
  565. #define RMAC_PAUSE_RX_ENABLE BIT(1)
  566. #define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
  567. #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
  568. u64 rmac_red_cfg;
  569. u64 rmac_red_rate_q0q3;
  570. u64 rmac_red_rate_q4q7;
  571. u64 mac_link_util;
  572. #define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
  573. #define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
  574. #define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
  575. #define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
  576. #define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
  577. #define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
  578. #define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
  579. MAC_RX_LINK_UTIL_DISABLE
  580. u64 rmac_invalid_ipg;
  581. /* rx traffic steering */
  582. #define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
  583. u64 rts_frm_len_n[8];
  584. u64 rts_qos_steering;
  585. #define MAX_DIX_MAP 4
  586. u64 rts_dix_map_n[MAX_DIX_MAP];
  587. #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
  588. #define RTS_DIX_MAP_SCW(val) BIT(val,21)
  589. u64 rts_q_alternates;
  590. u64 rts_default_q;
  591. u64 rts_ctrl;
  592. #define RTS_CTRL_IGNORE_SNAP_OUI BIT(2)
  593. #define RTS_CTRL_IGNORE_LLC_CTRL BIT(3)
  594. u64 rts_pn_cam_ctrl;
  595. #define RTS_PN_CAM_CTRL_WE BIT(7)
  596. #define RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15)
  597. #define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15)
  598. #define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
  599. u64 rts_pn_cam_data;
  600. #define RTS_PN_CAM_DATA_TCP_SELECT BIT(7)
  601. #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
  602. #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
  603. u64 rts_ds_mem_ctrl;
  604. #define RTS_DS_MEM_CTRL_WE BIT(7)
  605. #define RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15)
  606. #define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15)
  607. #define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
  608. u64 rts_ds_mem_data;
  609. #define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
  610. u8 unused16[0x700 - 0x220];
  611. u64 mac_debug_ctrl;
  612. #define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
  613. u8 unused17[0x2800 - 0x2708];
  614. /* memory controller registers */
  615. u64 mc_int_status;
  616. #define MC_INT_STATUS_MC_INT BIT(0)
  617. u64 mc_int_mask;
  618. #define MC_INT_MASK_MC_INT BIT(0)
  619. u64 mc_err_reg;
  620. #define MC_ERR_REG_ECC_DB_ERR_L BIT(14)
  621. #define MC_ERR_REG_ECC_DB_ERR_U BIT(15)
  622. #define MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18)
  623. #define MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20)
  624. #define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)
  625. #define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)
  626. #define MC_ERR_REG_SM_ERR BIT(31)
  627. #define MC_ERR_REG_ECC_ALL_SNG (BIT(2) | BIT(3) | BIT(4) | BIT(5) |\
  628. BIT(6) | BIT(7) | BIT(17) | BIT(19))
  629. #define MC_ERR_REG_ECC_ALL_DBL (BIT(10) | BIT(11) | BIT(12) |\
  630. BIT(13) | BIT(14) | BIT(15) |\
  631. BIT(18) | BIT(20))
  632. u64 mc_err_mask;
  633. u64 mc_err_alarm;
  634. u8 unused18[0x100 - 0x28];
  635. /* MC configuration */
  636. u64 rx_queue_cfg;
  637. #define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
  638. #define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
  639. #define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
  640. #define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
  641. #define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
  642. #define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
  643. #define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
  644. #define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
  645. u64 mc_rldram_mrs;
  646. #define MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39)
  647. #define MC_RLDRAM_MRS_ENABLE BIT(47)
  648. u64 mc_rldram_interleave;
  649. u64 mc_pause_thresh_q0q3;
  650. u64 mc_pause_thresh_q4q7;
  651. u64 mc_red_thresh_q[8];
  652. u8 unused19[0x200 - 0x168];
  653. u64 mc_rldram_ref_per;
  654. u8 unused20[0x220 - 0x208];
  655. u64 mc_rldram_test_ctrl;
  656. #define MC_RLDRAM_TEST_MODE BIT(47)
  657. #define MC_RLDRAM_TEST_WRITE BIT(7)
  658. #define MC_RLDRAM_TEST_GO BIT(15)
  659. #define MC_RLDRAM_TEST_DONE BIT(23)
  660. #define MC_RLDRAM_TEST_PASS BIT(31)
  661. u8 unused21[0x240 - 0x228];
  662. u64 mc_rldram_test_add;
  663. u8 unused22[0x260 - 0x248];
  664. u64 mc_rldram_test_d0;
  665. u8 unused23[0x280 - 0x268];
  666. u64 mc_rldram_test_d1;
  667. u8 unused24[0x300 - 0x288];
  668. u64 mc_rldram_test_d2;
  669. u8 unused24_1[0x360 - 0x308];
  670. u64 mc_rldram_ctrl;
  671. #define MC_RLDRAM_ENABLE_ODT BIT(7)
  672. u8 unused24_2[0x640 - 0x368];
  673. u64 mc_rldram_ref_per_herc;
  674. #define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16)
  675. u8 unused24_3[0x660 - 0x648];
  676. u64 mc_rldram_mrs_herc;
  677. u8 unused25[0x700 - 0x668];
  678. u64 mc_debug_ctrl;
  679. u8 unused26[0x3000 - 0x2f08];
  680. /* XGXG */
  681. /* XGXS control registers */
  682. u64 xgxs_int_status;
  683. #define XGXS_INT_STATUS_TXGXS BIT(0)
  684. #define XGXS_INT_STATUS_RXGXS BIT(1)
  685. u64 xgxs_int_mask;
  686. #define XGXS_INT_MASK_TXGXS BIT(0)
  687. #define XGXS_INT_MASK_RXGXS BIT(1)
  688. u64 xgxs_txgxs_err_reg;
  689. #define TXGXS_ECC_DB_ERR BIT(15)
  690. u64 xgxs_txgxs_err_mask;
  691. u64 xgxs_txgxs_err_alarm;
  692. u64 xgxs_rxgxs_err_reg;
  693. u64 xgxs_rxgxs_err_mask;
  694. u64 xgxs_rxgxs_err_alarm;
  695. u8 unused27[0x100 - 0x40];
  696. u64 xgxs_cfg;
  697. u64 xgxs_status;
  698. u64 xgxs_cfg_key;
  699. u64 xgxs_efifo_cfg; /* CHANGED */
  700. u64 rxgxs_ber_0; /* CHANGED */
  701. u64 rxgxs_ber_1; /* CHANGED */
  702. u64 spi_control;
  703. #define SPI_CONTROL_KEY(key) vBIT(key,0,4)
  704. #define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3)
  705. #define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)
  706. #define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24)
  707. #define SPI_CONTROL_SEL1 BIT(4)
  708. #define SPI_CONTROL_REQ BIT(7)
  709. #define SPI_CONTROL_NACK BIT(5)
  710. #define SPI_CONTROL_DONE BIT(6)
  711. u64 spi_data;
  712. #define SPI_DATA_WRITE(data,len) vBIT(data,0,len)
  713. };
  714. #define XENA_REG_SPACE sizeof(struct XENA_dev_config)
  715. #define XENA_EEPROM_SPACE (0x01 << 11)
  716. #endif /* _REGS_H */