rrunner.h 15 KB

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  1. #ifndef _RRUNNER_H_
  2. #define _RRUNNER_H_
  3. #include <linux/interrupt.h>
  4. #if ((BITS_PER_LONG != 32) && (BITS_PER_LONG != 64))
  5. #error "BITS_PER_LONG not defined or not valid"
  6. #endif
  7. struct rr_regs {
  8. u32 pad0[16];
  9. u32 HostCtrl;
  10. u32 LocalCtrl;
  11. u32 Pc;
  12. u32 BrkPt;
  13. /* Timer increments every 0.97 micro-seconds (unsigned int) */
  14. u32 Timer_Hi;
  15. u32 Timer;
  16. u32 TimerRef;
  17. u32 PciState;
  18. u32 Event;
  19. u32 MbEvent;
  20. u32 WinBase;
  21. u32 WinData;
  22. u32 RX_state;
  23. u32 TX_state;
  24. u32 Overhead;
  25. u32 ExtIo;
  26. u32 DmaWriteHostHi;
  27. u32 DmaWriteHostLo;
  28. u32 pad1[2];
  29. u32 DmaReadHostHi;
  30. u32 DmaReadHostLo;
  31. u32 pad2;
  32. u32 DmaReadLen;
  33. u32 DmaWriteState;
  34. u32 DmaWriteLcl;
  35. u32 DmaWriteIPchecksum;
  36. u32 DmaWriteLen;
  37. u32 DmaReadState;
  38. u32 DmaReadLcl;
  39. u32 DmaReadIPchecksum;
  40. u32 pad3;
  41. u32 RxBase;
  42. u32 RxPrd;
  43. u32 RxCon;
  44. u32 pad4;
  45. u32 TxBase;
  46. u32 TxPrd;
  47. u32 TxCon;
  48. u32 pad5;
  49. u32 RxIndPro;
  50. u32 RxIndCon;
  51. u32 RxIndRef;
  52. u32 pad6;
  53. u32 TxIndPro;
  54. u32 TxIndCon;
  55. u32 TxIndRef;
  56. u32 pad7[17];
  57. u32 DrCmndPro;
  58. u32 DrCmndCon;
  59. u32 DrCmndRef;
  60. u32 pad8;
  61. u32 DwCmndPro;
  62. u32 DwCmndCon;
  63. u32 DwCmndRef;
  64. u32 AssistState;
  65. u32 DrDataPro;
  66. u32 DrDataCon;
  67. u32 DrDataRef;
  68. u32 pad9;
  69. u32 DwDataPro;
  70. u32 DwDataCon;
  71. u32 DwDataRef;
  72. u32 pad10[33];
  73. u32 EvtCon;
  74. u32 pad11[5];
  75. u32 TxPi;
  76. u32 IpRxPi;
  77. u32 pad11a[8];
  78. u32 CmdRing[16];
  79. /* The ULA is in two registers the high order two bytes of the first
  80. * word contain the RunCode features.
  81. * ula0 res res byte0 byte1
  82. * ula1 byte2 byte3 byte4 byte5
  83. */
  84. u32 Ula0;
  85. u32 Ula1;
  86. u32 RxRingHi;
  87. u32 RxRingLo;
  88. u32 InfoPtrHi;
  89. u32 InfoPtrLo;
  90. u32 Mode;
  91. u32 ConRetry;
  92. u32 ConRetryTmr;
  93. u32 ConTmout;
  94. u32 CtatTmr;
  95. u32 MaxRxRng;
  96. u32 IntrTmr;
  97. u32 TxDataMvTimeout;
  98. u32 RxDataMvTimeout;
  99. u32 EvtPrd;
  100. u32 TraceIdx;
  101. u32 Fail1;
  102. u32 Fail2;
  103. u32 DrvPrm;
  104. u32 FilterLA;
  105. u32 FwRev;
  106. u32 FwRes1;
  107. u32 FwRes2;
  108. u32 FwRes3;
  109. u32 WriteDmaThresh;
  110. u32 ReadDmaThresh;
  111. u32 pad12[325];
  112. u32 Window[512];
  113. };
  114. /*
  115. * Host control register bits.
  116. */
  117. #define RR_INT 0x01
  118. #define RR_CLEAR_INT 0x02
  119. #define NO_SWAP 0x04000004
  120. #define NO_SWAP1 0x00000004
  121. #define PCI_RESET_NIC 0x08
  122. #define HALT_NIC 0x10
  123. #define SSTEP_NIC 0x20
  124. #define MEM_READ_MULTI 0x40
  125. #define NIC_HALTED 0x100
  126. #define HALT_INST 0x200
  127. #define PARITY_ERR 0x400
  128. #define INVALID_INST_B 0x800
  129. #define RR_REV_2 0x20000000
  130. #define RR_REV_MASK 0xf0000000
  131. /*
  132. * Local control register bits.
  133. */
  134. #define INTA_STATE 0x01
  135. #define CLEAR_INTA 0x02
  136. #define FAST_EEPROM_ACCESS 0x08
  137. #define ENABLE_EXTRA_SRAM 0x100
  138. #define ENABLE_EXTRA_DESC 0x200
  139. #define ENABLE_PARITY 0x400
  140. #define FORCE_DMA_PARITY_ERROR 0x800
  141. #define ENABLE_EEPROM_WRITE 0x1000
  142. #define ENABLE_DATA_CACHE 0x2000
  143. #define SRAM_LO_PARITY_ERR 0x4000
  144. #define SRAM_HI_PARITY_ERR 0x8000
  145. /*
  146. * PCI state bits.
  147. */
  148. #define FORCE_PCI_RESET 0x01
  149. #define PROVIDE_LENGTH 0x02
  150. #define MASK_DMA_READ_MAX 0x1C
  151. #define RBURST_DISABLE 0x00
  152. #define RBURST_4 0x04
  153. #define RBURST_16 0x08
  154. #define RBURST_32 0x0C
  155. #define RBURST_64 0x10
  156. #define RBURST_128 0x14
  157. #define RBURST_256 0x18
  158. #define RBURST_1024 0x1C
  159. #define MASK_DMA_WRITE_MAX 0xE0
  160. #define WBURST_DISABLE 0x00
  161. #define WBURST_4 0x20
  162. #define WBURST_16 0x40
  163. #define WBURST_32 0x60
  164. #define WBURST_64 0x80
  165. #define WBURST_128 0xa0
  166. #define WBURST_256 0xc0
  167. #define WBURST_1024 0xe0
  168. #define MASK_MIN_DMA 0xFF00
  169. #define FIFO_RETRY_ENABLE 0x10000
  170. /*
  171. * Event register
  172. */
  173. #define DMA_WRITE_DONE 0x10000
  174. #define DMA_READ_DONE 0x20000
  175. #define DMA_WRITE_ERR 0x40000
  176. #define DMA_READ_ERR 0x80000
  177. /*
  178. * Receive state
  179. *
  180. * RoadRunner HIPPI Receive State Register controls and monitors the
  181. * HIPPI receive interface in the NIC. Look at err bits when a HIPPI
  182. * receive Error Event occurs.
  183. */
  184. #define ENABLE_NEW_CON 0x01
  185. #define RESET_RECV 0x02
  186. #define RECV_ALL 0x00
  187. #define RECV_1K 0x20
  188. #define RECV_2K 0x40
  189. #define RECV_4K 0x60
  190. #define RECV_8K 0x80
  191. #define RECV_16K 0xa0
  192. #define RECV_32K 0xc0
  193. #define RECV_64K 0xe0
  194. /*
  195. * Transmit status.
  196. */
  197. #define ENA_XMIT 0x01
  198. #define PERM_CON 0x02
  199. /*
  200. * DMA write state
  201. */
  202. #define RESET_DMA 0x01
  203. #define NO_SWAP_DMA 0x02
  204. #define DMA_ACTIVE 0x04
  205. #define THRESH_MASK 0x1F
  206. #define DMA_ERROR_MASK 0xff000000
  207. /*
  208. * Gooddies stored in the ULA registers.
  209. */
  210. #define TRACE_ON_WHAT_BIT 0x00020000 /* Traces on */
  211. #define ONEM_BUF_WHAT_BIT 0x00040000 /* 1Meg vs 256K */
  212. #define CHAR_API_WHAT_BIT 0x00080000 /* Char API vs network only */
  213. #define CMD_EVT_WHAT_BIT 0x00200000 /* Command event */
  214. #define LONG_TX_WHAT_BIT 0x00400000
  215. #define LONG_RX_WHAT_BIT 0x00800000
  216. #define WHAT_BIT_MASK 0xFFFD0000 /* Feature bit mask */
  217. /*
  218. * Mode status
  219. */
  220. #define EVENT_OVFL 0x80000000
  221. #define FATAL_ERR 0x40000000
  222. #define LOOP_BACK 0x01
  223. #define MODE_PH 0x02
  224. #define MODE_FP 0x00
  225. #define PTR64BIT 0x04
  226. #define PTR32BIT 0x00
  227. #define PTR_WD_SWAP 0x08
  228. #define PTR_WD_NOSWAP 0x00
  229. #define POST_WARN_EVENT 0x10
  230. #define ERR_TERM 0x20
  231. #define DIRECT_CONN 0x40
  232. #define NO_NIC_WATCHDOG 0x80
  233. #define SWAP_DATA 0x100
  234. #define SWAP_CONTROL 0x200
  235. #define NIC_HALT_ON_ERR 0x400
  236. #define NIC_NO_RESTART 0x800
  237. #define HALF_DUP_TX 0x1000
  238. #define HALF_DUP_RX 0x2000
  239. /*
  240. * Error codes
  241. */
  242. /* Host Error Codes - values of fail1 */
  243. #define ERR_UNKNOWN_MBOX 0x1001
  244. #define ERR_UNKNOWN_CMD 0x1002
  245. #define ERR_MAX_RING 0x1003
  246. #define ERR_RING_CLOSED 0x1004
  247. #define ERR_RING_OPEN 0x1005
  248. /* Firmware internal errors */
  249. #define ERR_EVENT_RING_FULL 0x01
  250. #define ERR_DW_PEND_CMND_FULL 0x02
  251. #define ERR_DR_PEND_CMND_FULL 0x03
  252. #define ERR_DW_PEND_DATA_FULL 0x04
  253. #define ERR_DR_PEND_DATA_FULL 0x05
  254. #define ERR_ILLEGAL_JUMP 0x06
  255. #define ERR_UNIMPLEMENTED 0x07
  256. #define ERR_TX_INFO_FULL 0x08
  257. #define ERR_RX_INFO_FULL 0x09
  258. #define ERR_ILLEGAL_MODE 0x0A
  259. #define ERR_MAIN_TIMEOUT 0x0B
  260. #define ERR_EVENT_BITS 0x0C
  261. #define ERR_UNPEND_FULL 0x0D
  262. #define ERR_TIMER_QUEUE_FULL 0x0E
  263. #define ERR_TIMER_QUEUE_EMPTY 0x0F
  264. #define ERR_TIMER_NO_FREE 0x10
  265. #define ERR_INTR_START 0x11
  266. #define ERR_BAD_STARTUP 0x12
  267. #define ERR_NO_PKT_END 0x13
  268. #define ERR_HALTED_ON_ERR 0x14
  269. /* Hardware NIC Errors */
  270. #define ERR_WRITE_DMA 0x0101
  271. #define ERR_READ_DMA 0x0102
  272. #define ERR_EXT_SERIAL 0x0103
  273. #define ERR_TX_INT_PARITY 0x0104
  274. /*
  275. * Event definitions
  276. */
  277. #define EVT_RING_ENTRIES 64
  278. #define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event))
  279. struct event {
  280. #ifdef __LITTLE_ENDIAN
  281. u16 index;
  282. u8 ring;
  283. u8 code;
  284. #else
  285. u8 code;
  286. u8 ring;
  287. u16 index;
  288. #endif
  289. u32 timestamp;
  290. };
  291. /*
  292. * General Events
  293. */
  294. #define E_NIC_UP 0x01
  295. #define E_WATCHDOG 0x02
  296. #define E_STAT_UPD 0x04
  297. #define E_INVAL_CMD 0x05
  298. #define E_SET_CMD_CONS 0x06
  299. #define E_LINK_ON 0x07
  300. #define E_LINK_OFF 0x08
  301. #define E_INTERN_ERR 0x09
  302. #define E_HOST_ERR 0x0A
  303. #define E_STATS_UPDATE 0x0B
  304. #define E_REJECTING 0x0C
  305. /*
  306. * Send Events
  307. */
  308. #define E_CON_REJ 0x13
  309. #define E_CON_TMOUT 0x14
  310. #define E_CON_NC_TMOUT 0x15 /* I , Connection No Campon Timeout */
  311. #define E_DISC_ERR 0x16
  312. #define E_INT_PRTY 0x17
  313. #define E_TX_IDLE 0x18
  314. #define E_TX_LINK_DROP 0x19
  315. #define E_TX_INV_RNG 0x1A
  316. #define E_TX_INV_BUF 0x1B
  317. #define E_TX_INV_DSC 0x1C
  318. /*
  319. * Destination Events
  320. */
  321. /*
  322. * General Receive events
  323. */
  324. #define E_VAL_RNG 0x20
  325. #define E_RX_RNG_ENER 0x21
  326. #define E_INV_RNG 0x22
  327. #define E_RX_RNG_SPC 0x23
  328. #define E_RX_RNG_OUT 0x24
  329. #define E_PKT_DISCARD 0x25
  330. #define E_INFO_EVT 0x27
  331. /*
  332. * Data corrupted events
  333. */
  334. #define E_RX_PAR_ERR 0x2B
  335. #define E_RX_LLRC_ERR 0x2C
  336. #define E_IP_CKSM_ERR 0x2D
  337. #define E_DTA_CKSM_ERR 0x2E
  338. #define E_SHT_BST 0x2F
  339. /*
  340. * Data lost events
  341. */
  342. #define E_LST_LNK_ERR 0x30
  343. #define E_FLG_SYN_ERR 0x31
  344. #define E_FRM_ERR 0x32
  345. #define E_RX_IDLE 0x33
  346. #define E_PKT_LN_ERR 0x34
  347. #define E_STATE_ERR 0x35
  348. #define E_UNEXP_DATA 0x3C
  349. /*
  350. * Fatal events
  351. */
  352. #define E_RX_INV_BUF 0x36
  353. #define E_RX_INV_DSC 0x37
  354. #define E_RNG_BLK 0x38
  355. /*
  356. * Warning events
  357. */
  358. #define E_RX_TO 0x39
  359. #define E_BFR_SPC 0x3A
  360. #define E_INV_ULP 0x3B
  361. #define E_NOT_IMPLEMENTED 0x40
  362. /*
  363. * Commands
  364. */
  365. #define CMD_RING_ENTRIES 16
  366. struct cmd {
  367. #ifdef __LITTLE_ENDIAN
  368. u16 index;
  369. u8 ring;
  370. u8 code;
  371. #else
  372. u8 code;
  373. u8 ring;
  374. u16 index;
  375. #endif
  376. };
  377. #define C_START_FW 0x01
  378. #define C_UPD_STAT 0x02
  379. #define C_WATCHDOG 0x05
  380. #define C_DEL_RNG 0x09
  381. #define C_NEW_RNG 0x0A
  382. #define C_CONN 0x0D
  383. /*
  384. * Mode bits
  385. */
  386. #define PACKET_BAD 0x01 /* Packet had link-layer error */
  387. #define INTERRUPT 0x02
  388. #define TX_IP_CKSUM 0x04
  389. #define PACKET_END 0x08
  390. #define PACKET_START 0x10
  391. #define SAME_IFIELD 0x80
  392. typedef struct {
  393. #if (BITS_PER_LONG == 64)
  394. u64 addrlo;
  395. #else
  396. u32 addrhi;
  397. u32 addrlo;
  398. #endif
  399. } rraddr;
  400. static inline void set_rraddr(rraddr *ra, dma_addr_t addr)
  401. {
  402. unsigned long baddr = addr;
  403. #if (BITS_PER_LONG == 64)
  404. ra->addrlo = baddr;
  405. #else
  406. /* Don't bother setting zero every time */
  407. ra->addrlo = baddr;
  408. #endif
  409. mb();
  410. }
  411. static inline void set_rxaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr)
  412. {
  413. unsigned long baddr = addr;
  414. #if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN)
  415. writel(baddr & 0xffffffff, &regs->RxRingHi);
  416. writel(baddr >> 32, &regs->RxRingLo);
  417. #elif (BITS_PER_LONG == 64)
  418. writel(baddr >> 32, &regs->RxRingHi);
  419. writel(baddr & 0xffffffff, &regs->RxRingLo);
  420. #else
  421. writel(0, &regs->RxRingHi);
  422. writel(baddr, &regs->RxRingLo);
  423. #endif
  424. mb();
  425. }
  426. static inline void set_infoaddr(struct rr_regs __iomem *regs, volatile dma_addr_t addr)
  427. {
  428. unsigned long baddr = addr;
  429. #if (BITS_PER_LONG == 64) && defined(__LITTLE_ENDIAN)
  430. writel(baddr & 0xffffffff, &regs->InfoPtrHi);
  431. writel(baddr >> 32, &regs->InfoPtrLo);
  432. #elif (BITS_PER_LONG == 64)
  433. writel(baddr >> 32, &regs->InfoPtrHi);
  434. writel(baddr & 0xffffffff, &regs->InfoPtrLo);
  435. #else
  436. writel(0, &regs->InfoPtrHi);
  437. writel(baddr, &regs->InfoPtrLo);
  438. #endif
  439. mb();
  440. }
  441. /*
  442. * TX ring
  443. */
  444. #ifdef CONFIG_ROADRUNNER_LARGE_RINGS
  445. #define TX_RING_ENTRIES 32
  446. #else
  447. #define TX_RING_ENTRIES 16
  448. #endif
  449. #define TX_TOTAL_SIZE (TX_RING_ENTRIES * sizeof(struct tx_desc))
  450. struct tx_desc{
  451. rraddr addr;
  452. u32 res;
  453. #ifdef __LITTLE_ENDIAN
  454. u16 size;
  455. u8 pad;
  456. u8 mode;
  457. #else
  458. u8 mode;
  459. u8 pad;
  460. u16 size;
  461. #endif
  462. };
  463. #ifdef CONFIG_ROADRUNNER_LARGE_RINGS
  464. #define RX_RING_ENTRIES 32
  465. #else
  466. #define RX_RING_ENTRIES 16
  467. #endif
  468. #define RX_TOTAL_SIZE (RX_RING_ENTRIES * sizeof(struct rx_desc))
  469. struct rx_desc{
  470. rraddr addr;
  471. u32 res;
  472. #ifdef __LITTLE_ENDIAN
  473. u16 size;
  474. u8 pad;
  475. u8 mode;
  476. #else
  477. u8 mode;
  478. u8 pad;
  479. u16 size;
  480. #endif
  481. };
  482. /*
  483. * ioctl's
  484. */
  485. #define SIOCRRPFW SIOCDEVPRIVATE /* put firmware */
  486. #define SIOCRRGFW SIOCDEVPRIVATE+1 /* get firmware */
  487. #define SIOCRRID SIOCDEVPRIVATE+2 /* identify */
  488. struct seg_hdr {
  489. u32 seg_start;
  490. u32 seg_len;
  491. u32 seg_eestart;
  492. };
  493. #define EEPROM_BASE 0x80000000
  494. #define EEPROM_WORDS 8192
  495. #define EEPROM_BYTES (EEPROM_WORDS * sizeof(u32))
  496. struct eeprom_boot {
  497. u32 key1;
  498. u32 key2;
  499. u32 sram_size;
  500. struct seg_hdr loader;
  501. u32 init_chksum;
  502. u32 reserved1;
  503. };
  504. struct eeprom_manf {
  505. u32 HeaderFmt;
  506. u32 Firmware;
  507. u32 BoardRevision;
  508. u32 RoadrunnerRev;
  509. char OpticsPart[8];
  510. u32 OpticsRev;
  511. u32 pad1;
  512. char SramPart[8];
  513. u32 SramRev;
  514. u32 pad2;
  515. char EepromPart[8];
  516. u32 EepromRev;
  517. u32 EepromSize;
  518. char PalPart[8];
  519. u32 PalRev;
  520. u32 pad3;
  521. char PalCodeFile[12];
  522. u32 PalCodeRev;
  523. char BoardULA[8];
  524. char SerialNo[8];
  525. char MfgDate[8];
  526. char MfgTime[8];
  527. char ModifyDate[8];
  528. u32 ModCount;
  529. u32 pad4[13];
  530. };
  531. struct eeprom_phase_info {
  532. char phase1File[12];
  533. u32 phase1Rev;
  534. char phase1Date[8];
  535. char phase2File[12];
  536. u32 phase2Rev;
  537. char phase2Date[8];
  538. u32 reserved7[4];
  539. };
  540. struct eeprom_rncd_info {
  541. u32 FwStart;
  542. u32 FwRev;
  543. char FwDate[8];
  544. u32 AddrRunCodeSegs;
  545. u32 FileNames;
  546. char File[13][8];
  547. };
  548. /* Phase 1 region (starts are word offset 0x80) */
  549. struct phase1_hdr{
  550. u32 jump;
  551. u32 noop;
  552. struct seg_hdr phase2Seg;
  553. };
  554. struct eeprom {
  555. struct eeprom_boot boot;
  556. u32 pad1[8];
  557. struct eeprom_manf manf;
  558. struct eeprom_phase_info phase_info;
  559. struct eeprom_rncd_info rncd_info;
  560. u32 pad2[15];
  561. u32 hdr_checksum;
  562. struct phase1_hdr phase1;
  563. };
  564. struct rr_stats {
  565. u32 NicTimeStamp;
  566. u32 RngCreated;
  567. u32 RngDeleted;
  568. u32 IntrGen;
  569. u32 NEvtOvfl;
  570. u32 InvCmd;
  571. u32 DmaReadErrs;
  572. u32 DmaWriteErrs;
  573. u32 StatUpdtT;
  574. u32 StatUpdtC;
  575. u32 WatchDog;
  576. u32 Trace;
  577. /* Serial HIPPI */
  578. u32 LnkRdyEst;
  579. u32 GLinkErr;
  580. u32 AltFlgErr;
  581. u32 OvhdBit8Sync;
  582. u32 RmtSerPrtyErr;
  583. u32 RmtParPrtyErr;
  584. u32 RmtLoopBk;
  585. u32 pad1;
  586. /* HIPPI tx */
  587. u32 ConEst;
  588. u32 ConRejS;
  589. u32 ConRetry;
  590. u32 ConTmOut;
  591. u32 SndConDiscon;
  592. u32 SndParErr;
  593. u32 PktSnt;
  594. u32 pad2[2];
  595. u32 ShFBstSnt;
  596. u64 BytSent;
  597. u32 TxTimeout;
  598. u32 pad3[3];
  599. /* HIPPI rx */
  600. u32 ConAcc;
  601. u32 ConRejdiPrty;
  602. u32 ConRejd64b;
  603. u32 ConRejdBuf;
  604. u32 RxConDiscon;
  605. u32 RxConNoData;
  606. u32 PktRx;
  607. u32 pad4[2];
  608. u32 ShFBstRx;
  609. u64 BytRx;
  610. u32 RxParErr;
  611. u32 RxLLRCerr;
  612. u32 RxBstSZerr;
  613. u32 RxStateErr;
  614. u32 RxRdyErr;
  615. u32 RxInvULP;
  616. u32 RxSpcBuf;
  617. u32 RxSpcDesc;
  618. u32 RxRngSpc;
  619. u32 RxRngFull;
  620. u32 RxPktLenErr;
  621. u32 RxCksmErr;
  622. u32 RxPktDrp;
  623. u32 RngLowSpc;
  624. u32 RngDataClose;
  625. u32 RxTimeout;
  626. u32 RxIdle;
  627. };
  628. /*
  629. * This struct is shared with the NIC firmware.
  630. */
  631. struct ring_ctrl {
  632. rraddr rngptr;
  633. #ifdef __LITTLE_ENDIAN
  634. u16 entries;
  635. u8 pad;
  636. u8 entry_size;
  637. u16 pi;
  638. u16 mode;
  639. #else
  640. u8 entry_size;
  641. u8 pad;
  642. u16 entries;
  643. u16 mode;
  644. u16 pi;
  645. #endif
  646. };
  647. struct rr_info {
  648. union {
  649. struct rr_stats stats;
  650. u32 stati[128];
  651. } s;
  652. struct ring_ctrl evt_ctrl;
  653. struct ring_ctrl cmd_ctrl;
  654. struct ring_ctrl tx_ctrl;
  655. u8 pad[464];
  656. u8 trace[3072];
  657. };
  658. /*
  659. * The linux structure for the RoadRunner.
  660. *
  661. * RX/TX descriptors are put first to make sure they are properly
  662. * aligned and do not cross cache-line boundaries.
  663. */
  664. struct rr_private
  665. {
  666. struct rx_desc *rx_ring;
  667. struct tx_desc *tx_ring;
  668. struct event *evt_ring;
  669. dma_addr_t tx_ring_dma;
  670. dma_addr_t rx_ring_dma;
  671. dma_addr_t evt_ring_dma;
  672. /* Alignment ok ? */
  673. struct sk_buff *rx_skbuff[RX_RING_ENTRIES];
  674. struct sk_buff *tx_skbuff[TX_RING_ENTRIES];
  675. struct rr_regs __iomem *regs; /* Register base */
  676. struct ring_ctrl *rx_ctrl; /* Receive ring control */
  677. struct rr_info *info; /* Shared info page */
  678. dma_addr_t rx_ctrl_dma;
  679. dma_addr_t info_dma;
  680. spinlock_t lock;
  681. struct timer_list timer;
  682. u32 cur_rx, cur_cmd, cur_evt;
  683. u32 dirty_rx, dirty_tx;
  684. u32 tx_full;
  685. u32 fw_rev;
  686. volatile short fw_running;
  687. struct net_device_stats stats;
  688. struct pci_dev *pci_dev;
  689. };
  690. /*
  691. * Prototypes
  692. */
  693. static int rr_init(struct net_device *dev);
  694. static int rr_init1(struct net_device *dev);
  695. static irqreturn_t rr_interrupt(int irq, void *dev_id);
  696. static int rr_open(struct net_device *dev);
  697. static int rr_start_xmit(struct sk_buff *skb, struct net_device *dev);
  698. static int rr_close(struct net_device *dev);
  699. static struct net_device_stats *rr_get_stats(struct net_device *dev);
  700. static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  701. static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
  702. unsigned long offset,
  703. unsigned char *buf,
  704. unsigned long length);
  705. static u32 rr_read_eeprom_word(struct rr_private *rrpriv, void * offset);
  706. static int rr_load_firmware(struct net_device *dev);
  707. static inline void rr_raz_tx(struct rr_private *, struct net_device *);
  708. static inline void rr_raz_rx(struct rr_private *, struct net_device *);
  709. #endif /* _RRUNNER_H_ */