r8169.c 74 KB

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  1. /*
  2. =========================================================================
  3. r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
  4. --------------------------------------------------------------------
  5. History:
  6. Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
  7. May 20 2002 - Add link status force-mode and TBI mode support.
  8. 2004 - Massive updates. See kernel SCM system for details.
  9. =========================================================================
  10. 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
  11. Command: 'insmod r8169 media = SET_MEDIA'
  12. Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
  13. SET_MEDIA can be:
  14. _10_Half = 0x01
  15. _10_Full = 0x02
  16. _100_Half = 0x04
  17. _100_Full = 0x08
  18. _1000_Full = 0x10
  19. 2. Support TBI mode.
  20. =========================================================================
  21. VERSION 1.1 <2002/10/4>
  22. The bit4:0 of MII register 4 is called "selector field", and have to be
  23. 00001b to indicate support of IEEE std 802.3 during NWay process of
  24. exchanging Link Code Word (FLP).
  25. VERSION 1.2 <2002/11/30>
  26. - Large style cleanup
  27. - Use ether_crc in stock kernel (linux/crc32.h)
  28. - Copy mc_filter setup code from 8139cp
  29. (includes an optimization, and avoids set_bit use)
  30. VERSION 1.6LK <2004/04/14>
  31. - Merge of Realtek's version 1.6
  32. - Conversion to DMA API
  33. - Suspend/resume
  34. - Endianness
  35. - Misc Rx/Tx bugs
  36. VERSION 2.2LK <2005/01/25>
  37. - RX csum, TX csum/SG, TSO
  38. - VLAN
  39. - baby (< 7200) Jumbo frames support
  40. - Merge of Realtek's version 2.2 (new phy)
  41. */
  42. #include <linux/module.h>
  43. #include <linux/moduleparam.h>
  44. #include <linux/pci.h>
  45. #include <linux/netdevice.h>
  46. #include <linux/etherdevice.h>
  47. #include <linux/delay.h>
  48. #include <linux/ethtool.h>
  49. #include <linux/mii.h>
  50. #include <linux/if_vlan.h>
  51. #include <linux/crc32.h>
  52. #include <linux/in.h>
  53. #include <linux/ip.h>
  54. #include <linux/tcp.h>
  55. #include <linux/init.h>
  56. #include <linux/dma-mapping.h>
  57. #include <asm/system.h>
  58. #include <asm/io.h>
  59. #include <asm/irq.h>
  60. #ifdef CONFIG_R8169_NAPI
  61. #define NAPI_SUFFIX "-NAPI"
  62. #else
  63. #define NAPI_SUFFIX ""
  64. #endif
  65. #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  66. #define MODULENAME "r8169"
  67. #define PFX MODULENAME ": "
  68. #ifdef RTL8169_DEBUG
  69. #define assert(expr) \
  70. if (!(expr)) { \
  71. printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  72. #expr,__FILE__,__FUNCTION__,__LINE__); \
  73. }
  74. #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
  75. #else
  76. #define assert(expr) do {} while (0)
  77. #define dprintk(fmt, args...) do {} while (0)
  78. #endif /* RTL8169_DEBUG */
  79. #define R8169_MSG_DEFAULT \
  80. (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  81. #define TX_BUFFS_AVAIL(tp) \
  82. (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  83. #ifdef CONFIG_R8169_NAPI
  84. #define rtl8169_rx_skb netif_receive_skb
  85. #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
  86. #define rtl8169_rx_quota(count, quota) min(count, quota)
  87. #else
  88. #define rtl8169_rx_skb netif_rx
  89. #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
  90. #define rtl8169_rx_quota(count, quota) count
  91. #endif
  92. /* media options */
  93. #define MAX_UNITS 8
  94. static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
  95. static int num_media = 0;
  96. /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  97. static const int max_interrupt_work = 20;
  98. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  99. The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  100. static const int multicast_filter_limit = 32;
  101. /* MAC address length */
  102. #define MAC_ADDR_LEN 6
  103. #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  104. #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  105. #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  106. #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
  107. #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  108. #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
  109. #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
  110. #define R8169_REGS_SIZE 256
  111. #define R8169_NAPI_WEIGHT 64
  112. #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
  113. #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
  114. #define RX_BUF_SIZE 1536 /* Rx Buffer size */
  115. #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
  116. #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
  117. #define RTL8169_TX_TIMEOUT (6*HZ)
  118. #define RTL8169_PHY_TIMEOUT (10*HZ)
  119. /* write/read MMIO register */
  120. #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
  121. #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
  122. #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
  123. #define RTL_R8(reg) readb (ioaddr + (reg))
  124. #define RTL_R16(reg) readw (ioaddr + (reg))
  125. #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
  126. enum mac_version {
  127. RTL_GIGA_MAC_VER_01 = 0x00,
  128. RTL_GIGA_MAC_VER_02 = 0x01,
  129. RTL_GIGA_MAC_VER_03 = 0x02,
  130. RTL_GIGA_MAC_VER_04 = 0x03,
  131. RTL_GIGA_MAC_VER_05 = 0x04,
  132. RTL_GIGA_MAC_VER_11 = 0x0b,
  133. RTL_GIGA_MAC_VER_12 = 0x0c,
  134. RTL_GIGA_MAC_VER_13 = 0x0d,
  135. RTL_GIGA_MAC_VER_14 = 0x0e,
  136. RTL_GIGA_MAC_VER_15 = 0x0f
  137. };
  138. enum phy_version {
  139. RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
  140. RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
  141. RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
  142. RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
  143. RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
  144. RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
  145. };
  146. #define _R(NAME,MAC,MASK) \
  147. { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
  148. static const struct {
  149. const char *name;
  150. u8 mac_version;
  151. u32 RxConfigMask; /* Clears the bits supported by this chip */
  152. } rtl_chip_info[] = {
  153. _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
  154. _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
  155. _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
  156. _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
  157. _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
  158. _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
  159. _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
  160. _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
  161. _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
  162. _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
  163. };
  164. #undef _R
  165. enum cfg_version {
  166. RTL_CFG_0 = 0x00,
  167. RTL_CFG_1,
  168. RTL_CFG_2
  169. };
  170. static const struct {
  171. unsigned int region;
  172. unsigned int align;
  173. } rtl_cfg_info[] = {
  174. [RTL_CFG_0] = { 1, NET_IP_ALIGN },
  175. [RTL_CFG_1] = { 2, NET_IP_ALIGN },
  176. [RTL_CFG_2] = { 2, 8 }
  177. };
  178. static struct pci_device_id rtl8169_pci_tbl[] = {
  179. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
  180. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
  181. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
  182. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
  183. { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
  184. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
  185. { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
  186. { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
  187. { PCI_VENDOR_ID_LINKSYS, 0x1032,
  188. PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
  189. {0,},
  190. };
  191. MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
  192. static int rx_copybreak = 200;
  193. static int use_dac;
  194. static struct {
  195. u32 msg_enable;
  196. } debug = { -1 };
  197. enum RTL8169_registers {
  198. MAC0 = 0, /* Ethernet hardware address. */
  199. MAR0 = 8, /* Multicast filter. */
  200. CounterAddrLow = 0x10,
  201. CounterAddrHigh = 0x14,
  202. TxDescStartAddrLow = 0x20,
  203. TxDescStartAddrHigh = 0x24,
  204. TxHDescStartAddrLow = 0x28,
  205. TxHDescStartAddrHigh = 0x2c,
  206. FLASH = 0x30,
  207. ERSR = 0x36,
  208. ChipCmd = 0x37,
  209. TxPoll = 0x38,
  210. IntrMask = 0x3C,
  211. IntrStatus = 0x3E,
  212. TxConfig = 0x40,
  213. RxConfig = 0x44,
  214. RxMissed = 0x4C,
  215. Cfg9346 = 0x50,
  216. Config0 = 0x51,
  217. Config1 = 0x52,
  218. Config2 = 0x53,
  219. Config3 = 0x54,
  220. Config4 = 0x55,
  221. Config5 = 0x56,
  222. MultiIntr = 0x5C,
  223. PHYAR = 0x60,
  224. TBICSR = 0x64,
  225. TBI_ANAR = 0x68,
  226. TBI_LPAR = 0x6A,
  227. PHYstatus = 0x6C,
  228. RxMaxSize = 0xDA,
  229. CPlusCmd = 0xE0,
  230. IntrMitigate = 0xE2,
  231. RxDescAddrLow = 0xE4,
  232. RxDescAddrHigh = 0xE8,
  233. EarlyTxThres = 0xEC,
  234. FuncEvent = 0xF0,
  235. FuncEventMask = 0xF4,
  236. FuncPresetState = 0xF8,
  237. FuncForceEvent = 0xFC,
  238. };
  239. enum RTL8169_register_content {
  240. /* InterruptStatusBits */
  241. SYSErr = 0x8000,
  242. PCSTimeout = 0x4000,
  243. SWInt = 0x0100,
  244. TxDescUnavail = 0x80,
  245. RxFIFOOver = 0x40,
  246. LinkChg = 0x20,
  247. RxOverflow = 0x10,
  248. TxErr = 0x08,
  249. TxOK = 0x04,
  250. RxErr = 0x02,
  251. RxOK = 0x01,
  252. /* RxStatusDesc */
  253. RxFOVF = (1 << 23),
  254. RxRWT = (1 << 22),
  255. RxRES = (1 << 21),
  256. RxRUNT = (1 << 20),
  257. RxCRC = (1 << 19),
  258. /* ChipCmdBits */
  259. CmdReset = 0x10,
  260. CmdRxEnb = 0x08,
  261. CmdTxEnb = 0x04,
  262. RxBufEmpty = 0x01,
  263. /* Cfg9346Bits */
  264. Cfg9346_Lock = 0x00,
  265. Cfg9346_Unlock = 0xC0,
  266. /* rx_mode_bits */
  267. AcceptErr = 0x20,
  268. AcceptRunt = 0x10,
  269. AcceptBroadcast = 0x08,
  270. AcceptMulticast = 0x04,
  271. AcceptMyPhys = 0x02,
  272. AcceptAllPhys = 0x01,
  273. /* RxConfigBits */
  274. RxCfgFIFOShift = 13,
  275. RxCfgDMAShift = 8,
  276. /* TxConfigBits */
  277. TxInterFrameGapShift = 24,
  278. TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
  279. /* Config1 register p.24 */
  280. PMEnable = (1 << 0), /* Power Management Enable */
  281. /* Config3 register p.25 */
  282. MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
  283. LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
  284. /* Config5 register p.27 */
  285. BWF = (1 << 6), /* Accept Broadcast wakeup frame */
  286. MWF = (1 << 5), /* Accept Multicast wakeup frame */
  287. UWF = (1 << 4), /* Accept Unicast wakeup frame */
  288. LanWake = (1 << 1), /* LanWake enable/disable */
  289. PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
  290. /* TBICSR p.28 */
  291. TBIReset = 0x80000000,
  292. TBILoopback = 0x40000000,
  293. TBINwEnable = 0x20000000,
  294. TBINwRestart = 0x10000000,
  295. TBILinkOk = 0x02000000,
  296. TBINwComplete = 0x01000000,
  297. /* CPlusCmd p.31 */
  298. RxVlan = (1 << 6),
  299. RxChkSum = (1 << 5),
  300. PCIDAC = (1 << 4),
  301. PCIMulRW = (1 << 3),
  302. /* rtl8169_PHYstatus */
  303. TBI_Enable = 0x80,
  304. TxFlowCtrl = 0x40,
  305. RxFlowCtrl = 0x20,
  306. _1000bpsF = 0x10,
  307. _100bps = 0x08,
  308. _10bps = 0x04,
  309. LinkStatus = 0x02,
  310. FullDup = 0x01,
  311. /* _MediaType */
  312. _10_Half = 0x01,
  313. _10_Full = 0x02,
  314. _100_Half = 0x04,
  315. _100_Full = 0x08,
  316. _1000_Full = 0x10,
  317. /* _TBICSRBit */
  318. TBILinkOK = 0x02000000,
  319. /* DumpCounterCommand */
  320. CounterDump = 0x8,
  321. };
  322. enum _DescStatusBit {
  323. DescOwn = (1 << 31), /* Descriptor is owned by NIC */
  324. RingEnd = (1 << 30), /* End of descriptor ring */
  325. FirstFrag = (1 << 29), /* First segment of a packet */
  326. LastFrag = (1 << 28), /* Final segment of a packet */
  327. /* Tx private */
  328. LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
  329. MSSShift = 16, /* MSS value position */
  330. MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
  331. IPCS = (1 << 18), /* Calculate IP checksum */
  332. UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
  333. TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
  334. TxVlanTag = (1 << 17), /* Add VLAN tag */
  335. /* Rx private */
  336. PID1 = (1 << 18), /* Protocol ID bit 1/2 */
  337. PID0 = (1 << 17), /* Protocol ID bit 2/2 */
  338. #define RxProtoUDP (PID1)
  339. #define RxProtoTCP (PID0)
  340. #define RxProtoIP (PID1 | PID0)
  341. #define RxProtoMask RxProtoIP
  342. IPFail = (1 << 16), /* IP checksum failed */
  343. UDPFail = (1 << 15), /* UDP/IP checksum failed */
  344. TCPFail = (1 << 14), /* TCP/IP checksum failed */
  345. RxVlanTag = (1 << 16), /* VLAN tag available */
  346. };
  347. #define RsvdMask 0x3fffc000
  348. struct TxDesc {
  349. u32 opts1;
  350. u32 opts2;
  351. u64 addr;
  352. };
  353. struct RxDesc {
  354. u32 opts1;
  355. u32 opts2;
  356. u64 addr;
  357. };
  358. struct ring_info {
  359. struct sk_buff *skb;
  360. u32 len;
  361. u8 __pad[sizeof(void *) - sizeof(u32)];
  362. };
  363. struct rtl8169_private {
  364. void __iomem *mmio_addr; /* memory map physical address */
  365. struct pci_dev *pci_dev; /* Index of PCI device */
  366. struct net_device *dev;
  367. struct net_device_stats stats; /* statistics of net device */
  368. spinlock_t lock; /* spin lock flag */
  369. u32 msg_enable;
  370. int chipset;
  371. int mac_version;
  372. int phy_version;
  373. u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
  374. u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
  375. u32 dirty_rx;
  376. u32 dirty_tx;
  377. struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
  378. struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
  379. dma_addr_t TxPhyAddr;
  380. dma_addr_t RxPhyAddr;
  381. struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
  382. struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
  383. unsigned align;
  384. unsigned rx_buf_sz;
  385. struct timer_list timer;
  386. u16 cp_cmd;
  387. u16 intr_mask;
  388. int phy_auto_nego_reg;
  389. int phy_1000_ctrl_reg;
  390. #ifdef CONFIG_R8169_VLAN
  391. struct vlan_group *vlgrp;
  392. #endif
  393. int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
  394. void (*get_settings)(struct net_device *, struct ethtool_cmd *);
  395. void (*phy_reset_enable)(void __iomem *);
  396. unsigned int (*phy_reset_pending)(void __iomem *);
  397. unsigned int (*link_ok)(void __iomem *);
  398. struct delayed_work task;
  399. unsigned wol_enabled : 1;
  400. };
  401. MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
  402. MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
  403. module_param_array(media, int, &num_media, 0);
  404. MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
  405. module_param(rx_copybreak, int, 0);
  406. MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
  407. module_param(use_dac, int, 0);
  408. MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
  409. module_param_named(debug, debug.msg_enable, int, 0);
  410. MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
  411. MODULE_LICENSE("GPL");
  412. MODULE_VERSION(RTL8169_VERSION);
  413. static int rtl8169_open(struct net_device *dev);
  414. static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
  415. static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
  416. static int rtl8169_init_ring(struct net_device *dev);
  417. static void rtl8169_hw_start(struct net_device *dev);
  418. static int rtl8169_close(struct net_device *dev);
  419. static void rtl8169_set_rx_mode(struct net_device *dev);
  420. static void rtl8169_tx_timeout(struct net_device *dev);
  421. static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
  422. static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
  423. void __iomem *);
  424. static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
  425. static void rtl8169_down(struct net_device *dev);
  426. static void rtl8169_rx_clear(struct rtl8169_private *tp);
  427. #ifdef CONFIG_R8169_NAPI
  428. static int rtl8169_poll(struct net_device *dev, int *budget);
  429. #endif
  430. static const u16 rtl8169_intr_mask =
  431. SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
  432. static const u16 rtl8169_napi_event =
  433. RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
  434. static const unsigned int rtl8169_rx_config =
  435. (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
  436. static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
  437. {
  438. int i;
  439. RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
  440. for (i = 20; i > 0; i--) {
  441. /* Check if the RTL8169 has completed writing to the specified MII register */
  442. if (!(RTL_R32(PHYAR) & 0x80000000))
  443. break;
  444. udelay(25);
  445. }
  446. }
  447. static int mdio_read(void __iomem *ioaddr, int RegAddr)
  448. {
  449. int i, value = -1;
  450. RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
  451. for (i = 20; i > 0; i--) {
  452. /* Check if the RTL8169 has completed retrieving data from the specified MII register */
  453. if (RTL_R32(PHYAR) & 0x80000000) {
  454. value = (int) (RTL_R32(PHYAR) & 0xFFFF);
  455. break;
  456. }
  457. udelay(25);
  458. }
  459. return value;
  460. }
  461. static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
  462. {
  463. RTL_W16(IntrMask, 0x0000);
  464. RTL_W16(IntrStatus, 0xffff);
  465. }
  466. static void rtl8169_asic_down(void __iomem *ioaddr)
  467. {
  468. RTL_W8(ChipCmd, 0x00);
  469. rtl8169_irq_mask_and_ack(ioaddr);
  470. RTL_R16(CPlusCmd);
  471. }
  472. static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
  473. {
  474. return RTL_R32(TBICSR) & TBIReset;
  475. }
  476. static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
  477. {
  478. return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
  479. }
  480. static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
  481. {
  482. return RTL_R32(TBICSR) & TBILinkOk;
  483. }
  484. static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
  485. {
  486. return RTL_R8(PHYstatus) & LinkStatus;
  487. }
  488. static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
  489. {
  490. RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
  491. }
  492. static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
  493. {
  494. unsigned int val;
  495. val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
  496. mdio_write(ioaddr, MII_BMCR, val & 0xffff);
  497. }
  498. static void rtl8169_check_link_status(struct net_device *dev,
  499. struct rtl8169_private *tp, void __iomem *ioaddr)
  500. {
  501. unsigned long flags;
  502. spin_lock_irqsave(&tp->lock, flags);
  503. if (tp->link_ok(ioaddr)) {
  504. netif_carrier_on(dev);
  505. if (netif_msg_ifup(tp))
  506. printk(KERN_INFO PFX "%s: link up\n", dev->name);
  507. } else {
  508. if (netif_msg_ifdown(tp))
  509. printk(KERN_INFO PFX "%s: link down\n", dev->name);
  510. netif_carrier_off(dev);
  511. }
  512. spin_unlock_irqrestore(&tp->lock, flags);
  513. }
  514. static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
  515. {
  516. struct {
  517. u16 speed;
  518. u8 duplex;
  519. u8 autoneg;
  520. u8 media;
  521. } link_settings[] = {
  522. { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
  523. { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
  524. { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
  525. { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
  526. { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
  527. /* Make TBI happy */
  528. { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
  529. }, *p;
  530. unsigned char option;
  531. option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
  532. if ((option != 0xff) && !idx && netif_msg_drv(&debug))
  533. printk(KERN_WARNING PFX "media option is deprecated.\n");
  534. for (p = link_settings; p->media != 0xff; p++) {
  535. if (p->media == option)
  536. break;
  537. }
  538. *autoneg = p->autoneg;
  539. *speed = p->speed;
  540. *duplex = p->duplex;
  541. }
  542. static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  543. {
  544. struct rtl8169_private *tp = netdev_priv(dev);
  545. void __iomem *ioaddr = tp->mmio_addr;
  546. u8 options;
  547. wol->wolopts = 0;
  548. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  549. wol->supported = WAKE_ANY;
  550. spin_lock_irq(&tp->lock);
  551. options = RTL_R8(Config1);
  552. if (!(options & PMEnable))
  553. goto out_unlock;
  554. options = RTL_R8(Config3);
  555. if (options & LinkUp)
  556. wol->wolopts |= WAKE_PHY;
  557. if (options & MagicPacket)
  558. wol->wolopts |= WAKE_MAGIC;
  559. options = RTL_R8(Config5);
  560. if (options & UWF)
  561. wol->wolopts |= WAKE_UCAST;
  562. if (options & BWF)
  563. wol->wolopts |= WAKE_BCAST;
  564. if (options & MWF)
  565. wol->wolopts |= WAKE_MCAST;
  566. out_unlock:
  567. spin_unlock_irq(&tp->lock);
  568. }
  569. static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  570. {
  571. struct rtl8169_private *tp = netdev_priv(dev);
  572. void __iomem *ioaddr = tp->mmio_addr;
  573. int i;
  574. static struct {
  575. u32 opt;
  576. u16 reg;
  577. u8 mask;
  578. } cfg[] = {
  579. { WAKE_ANY, Config1, PMEnable },
  580. { WAKE_PHY, Config3, LinkUp },
  581. { WAKE_MAGIC, Config3, MagicPacket },
  582. { WAKE_UCAST, Config5, UWF },
  583. { WAKE_BCAST, Config5, BWF },
  584. { WAKE_MCAST, Config5, MWF },
  585. { WAKE_ANY, Config5, LanWake }
  586. };
  587. spin_lock_irq(&tp->lock);
  588. RTL_W8(Cfg9346, Cfg9346_Unlock);
  589. for (i = 0; i < ARRAY_SIZE(cfg); i++) {
  590. u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
  591. if (wol->wolopts & cfg[i].opt)
  592. options |= cfg[i].mask;
  593. RTL_W8(cfg[i].reg, options);
  594. }
  595. RTL_W8(Cfg9346, Cfg9346_Lock);
  596. tp->wol_enabled = (wol->wolopts) ? 1 : 0;
  597. spin_unlock_irq(&tp->lock);
  598. return 0;
  599. }
  600. static void rtl8169_get_drvinfo(struct net_device *dev,
  601. struct ethtool_drvinfo *info)
  602. {
  603. struct rtl8169_private *tp = netdev_priv(dev);
  604. strcpy(info->driver, MODULENAME);
  605. strcpy(info->version, RTL8169_VERSION);
  606. strcpy(info->bus_info, pci_name(tp->pci_dev));
  607. }
  608. static int rtl8169_get_regs_len(struct net_device *dev)
  609. {
  610. return R8169_REGS_SIZE;
  611. }
  612. static int rtl8169_set_speed_tbi(struct net_device *dev,
  613. u8 autoneg, u16 speed, u8 duplex)
  614. {
  615. struct rtl8169_private *tp = netdev_priv(dev);
  616. void __iomem *ioaddr = tp->mmio_addr;
  617. int ret = 0;
  618. u32 reg;
  619. reg = RTL_R32(TBICSR);
  620. if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
  621. (duplex == DUPLEX_FULL)) {
  622. RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
  623. } else if (autoneg == AUTONEG_ENABLE)
  624. RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
  625. else {
  626. if (netif_msg_link(tp)) {
  627. printk(KERN_WARNING "%s: "
  628. "incorrect speed setting refused in TBI mode\n",
  629. dev->name);
  630. }
  631. ret = -EOPNOTSUPP;
  632. }
  633. return ret;
  634. }
  635. static int rtl8169_set_speed_xmii(struct net_device *dev,
  636. u8 autoneg, u16 speed, u8 duplex)
  637. {
  638. struct rtl8169_private *tp = netdev_priv(dev);
  639. void __iomem *ioaddr = tp->mmio_addr;
  640. int auto_nego, giga_ctrl;
  641. auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
  642. auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  643. ADVERTISE_100HALF | ADVERTISE_100FULL);
  644. giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
  645. giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  646. if (autoneg == AUTONEG_ENABLE) {
  647. auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
  648. ADVERTISE_100HALF | ADVERTISE_100FULL);
  649. giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  650. } else {
  651. if (speed == SPEED_10)
  652. auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  653. else if (speed == SPEED_100)
  654. auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  655. else if (speed == SPEED_1000)
  656. giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  657. if (duplex == DUPLEX_HALF)
  658. auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
  659. if (duplex == DUPLEX_FULL)
  660. auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
  661. /* This tweak comes straight from Realtek's driver. */
  662. if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
  663. (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
  664. auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
  665. }
  666. }
  667. /* The 8100e/8101e do Fast Ethernet only. */
  668. if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
  669. (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
  670. (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
  671. if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
  672. netif_msg_link(tp)) {
  673. printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
  674. dev->name);
  675. }
  676. giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  677. }
  678. auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  679. tp->phy_auto_nego_reg = auto_nego;
  680. tp->phy_1000_ctrl_reg = giga_ctrl;
  681. mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
  682. mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
  683. mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
  684. return 0;
  685. }
  686. static int rtl8169_set_speed(struct net_device *dev,
  687. u8 autoneg, u16 speed, u8 duplex)
  688. {
  689. struct rtl8169_private *tp = netdev_priv(dev);
  690. int ret;
  691. ret = tp->set_speed(dev, autoneg, speed, duplex);
  692. if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
  693. mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
  694. return ret;
  695. }
  696. static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  697. {
  698. struct rtl8169_private *tp = netdev_priv(dev);
  699. unsigned long flags;
  700. int ret;
  701. spin_lock_irqsave(&tp->lock, flags);
  702. ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
  703. spin_unlock_irqrestore(&tp->lock, flags);
  704. return ret;
  705. }
  706. static u32 rtl8169_get_rx_csum(struct net_device *dev)
  707. {
  708. struct rtl8169_private *tp = netdev_priv(dev);
  709. return tp->cp_cmd & RxChkSum;
  710. }
  711. static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
  712. {
  713. struct rtl8169_private *tp = netdev_priv(dev);
  714. void __iomem *ioaddr = tp->mmio_addr;
  715. unsigned long flags;
  716. spin_lock_irqsave(&tp->lock, flags);
  717. if (data)
  718. tp->cp_cmd |= RxChkSum;
  719. else
  720. tp->cp_cmd &= ~RxChkSum;
  721. RTL_W16(CPlusCmd, tp->cp_cmd);
  722. RTL_R16(CPlusCmd);
  723. spin_unlock_irqrestore(&tp->lock, flags);
  724. return 0;
  725. }
  726. #ifdef CONFIG_R8169_VLAN
  727. static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
  728. struct sk_buff *skb)
  729. {
  730. return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
  731. TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
  732. }
  733. static void rtl8169_vlan_rx_register(struct net_device *dev,
  734. struct vlan_group *grp)
  735. {
  736. struct rtl8169_private *tp = netdev_priv(dev);
  737. void __iomem *ioaddr = tp->mmio_addr;
  738. unsigned long flags;
  739. spin_lock_irqsave(&tp->lock, flags);
  740. tp->vlgrp = grp;
  741. if (tp->vlgrp)
  742. tp->cp_cmd |= RxVlan;
  743. else
  744. tp->cp_cmd &= ~RxVlan;
  745. RTL_W16(CPlusCmd, tp->cp_cmd);
  746. RTL_R16(CPlusCmd);
  747. spin_unlock_irqrestore(&tp->lock, flags);
  748. }
  749. static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
  750. {
  751. struct rtl8169_private *tp = netdev_priv(dev);
  752. unsigned long flags;
  753. spin_lock_irqsave(&tp->lock, flags);
  754. vlan_group_set_device(tp->vlgrp, vid, NULL);
  755. spin_unlock_irqrestore(&tp->lock, flags);
  756. }
  757. static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
  758. struct sk_buff *skb)
  759. {
  760. u32 opts2 = le32_to_cpu(desc->opts2);
  761. int ret;
  762. if (tp->vlgrp && (opts2 & RxVlanTag)) {
  763. rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
  764. swab16(opts2 & 0xffff));
  765. ret = 0;
  766. } else
  767. ret = -1;
  768. desc->opts2 = 0;
  769. return ret;
  770. }
  771. #else /* !CONFIG_R8169_VLAN */
  772. static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
  773. struct sk_buff *skb)
  774. {
  775. return 0;
  776. }
  777. static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
  778. struct sk_buff *skb)
  779. {
  780. return -1;
  781. }
  782. #endif
  783. static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
  784. {
  785. struct rtl8169_private *tp = netdev_priv(dev);
  786. void __iomem *ioaddr = tp->mmio_addr;
  787. u32 status;
  788. cmd->supported =
  789. SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  790. cmd->port = PORT_FIBRE;
  791. cmd->transceiver = XCVR_INTERNAL;
  792. status = RTL_R32(TBICSR);
  793. cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
  794. cmd->autoneg = !!(status & TBINwEnable);
  795. cmd->speed = SPEED_1000;
  796. cmd->duplex = DUPLEX_FULL; /* Always set */
  797. }
  798. static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
  799. {
  800. struct rtl8169_private *tp = netdev_priv(dev);
  801. void __iomem *ioaddr = tp->mmio_addr;
  802. u8 status;
  803. cmd->supported = SUPPORTED_10baseT_Half |
  804. SUPPORTED_10baseT_Full |
  805. SUPPORTED_100baseT_Half |
  806. SUPPORTED_100baseT_Full |
  807. SUPPORTED_1000baseT_Full |
  808. SUPPORTED_Autoneg |
  809. SUPPORTED_TP;
  810. cmd->autoneg = 1;
  811. cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
  812. if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
  813. cmd->advertising |= ADVERTISED_10baseT_Half;
  814. if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
  815. cmd->advertising |= ADVERTISED_10baseT_Full;
  816. if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
  817. cmd->advertising |= ADVERTISED_100baseT_Half;
  818. if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
  819. cmd->advertising |= ADVERTISED_100baseT_Full;
  820. if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
  821. cmd->advertising |= ADVERTISED_1000baseT_Full;
  822. status = RTL_R8(PHYstatus);
  823. if (status & _1000bpsF)
  824. cmd->speed = SPEED_1000;
  825. else if (status & _100bps)
  826. cmd->speed = SPEED_100;
  827. else if (status & _10bps)
  828. cmd->speed = SPEED_10;
  829. if (status & TxFlowCtrl)
  830. cmd->advertising |= ADVERTISED_Asym_Pause;
  831. if (status & RxFlowCtrl)
  832. cmd->advertising |= ADVERTISED_Pause;
  833. cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
  834. DUPLEX_FULL : DUPLEX_HALF;
  835. }
  836. static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  837. {
  838. struct rtl8169_private *tp = netdev_priv(dev);
  839. unsigned long flags;
  840. spin_lock_irqsave(&tp->lock, flags);
  841. tp->get_settings(dev, cmd);
  842. spin_unlock_irqrestore(&tp->lock, flags);
  843. return 0;
  844. }
  845. static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  846. void *p)
  847. {
  848. struct rtl8169_private *tp = netdev_priv(dev);
  849. unsigned long flags;
  850. if (regs->len > R8169_REGS_SIZE)
  851. regs->len = R8169_REGS_SIZE;
  852. spin_lock_irqsave(&tp->lock, flags);
  853. memcpy_fromio(p, tp->mmio_addr, regs->len);
  854. spin_unlock_irqrestore(&tp->lock, flags);
  855. }
  856. static u32 rtl8169_get_msglevel(struct net_device *dev)
  857. {
  858. struct rtl8169_private *tp = netdev_priv(dev);
  859. return tp->msg_enable;
  860. }
  861. static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
  862. {
  863. struct rtl8169_private *tp = netdev_priv(dev);
  864. tp->msg_enable = value;
  865. }
  866. static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
  867. "tx_packets",
  868. "rx_packets",
  869. "tx_errors",
  870. "rx_errors",
  871. "rx_missed",
  872. "align_errors",
  873. "tx_single_collisions",
  874. "tx_multi_collisions",
  875. "unicast",
  876. "broadcast",
  877. "multicast",
  878. "tx_aborted",
  879. "tx_underrun",
  880. };
  881. struct rtl8169_counters {
  882. u64 tx_packets;
  883. u64 rx_packets;
  884. u64 tx_errors;
  885. u32 rx_errors;
  886. u16 rx_missed;
  887. u16 align_errors;
  888. u32 tx_one_collision;
  889. u32 tx_multi_collision;
  890. u64 rx_unicast;
  891. u64 rx_broadcast;
  892. u32 rx_multicast;
  893. u16 tx_aborted;
  894. u16 tx_underun;
  895. };
  896. static int rtl8169_get_stats_count(struct net_device *dev)
  897. {
  898. return ARRAY_SIZE(rtl8169_gstrings);
  899. }
  900. static void rtl8169_get_ethtool_stats(struct net_device *dev,
  901. struct ethtool_stats *stats, u64 *data)
  902. {
  903. struct rtl8169_private *tp = netdev_priv(dev);
  904. void __iomem *ioaddr = tp->mmio_addr;
  905. struct rtl8169_counters *counters;
  906. dma_addr_t paddr;
  907. u32 cmd;
  908. ASSERT_RTNL();
  909. counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
  910. if (!counters)
  911. return;
  912. RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
  913. cmd = (u64)paddr & DMA_32BIT_MASK;
  914. RTL_W32(CounterAddrLow, cmd);
  915. RTL_W32(CounterAddrLow, cmd | CounterDump);
  916. while (RTL_R32(CounterAddrLow) & CounterDump) {
  917. if (msleep_interruptible(1))
  918. break;
  919. }
  920. RTL_W32(CounterAddrLow, 0);
  921. RTL_W32(CounterAddrHigh, 0);
  922. data[0] = le64_to_cpu(counters->tx_packets);
  923. data[1] = le64_to_cpu(counters->rx_packets);
  924. data[2] = le64_to_cpu(counters->tx_errors);
  925. data[3] = le32_to_cpu(counters->rx_errors);
  926. data[4] = le16_to_cpu(counters->rx_missed);
  927. data[5] = le16_to_cpu(counters->align_errors);
  928. data[6] = le32_to_cpu(counters->tx_one_collision);
  929. data[7] = le32_to_cpu(counters->tx_multi_collision);
  930. data[8] = le64_to_cpu(counters->rx_unicast);
  931. data[9] = le64_to_cpu(counters->rx_broadcast);
  932. data[10] = le32_to_cpu(counters->rx_multicast);
  933. data[11] = le16_to_cpu(counters->tx_aborted);
  934. data[12] = le16_to_cpu(counters->tx_underun);
  935. pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
  936. }
  937. static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  938. {
  939. switch(stringset) {
  940. case ETH_SS_STATS:
  941. memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
  942. break;
  943. }
  944. }
  945. static const struct ethtool_ops rtl8169_ethtool_ops = {
  946. .get_drvinfo = rtl8169_get_drvinfo,
  947. .get_regs_len = rtl8169_get_regs_len,
  948. .get_link = ethtool_op_get_link,
  949. .get_settings = rtl8169_get_settings,
  950. .set_settings = rtl8169_set_settings,
  951. .get_msglevel = rtl8169_get_msglevel,
  952. .set_msglevel = rtl8169_set_msglevel,
  953. .get_rx_csum = rtl8169_get_rx_csum,
  954. .set_rx_csum = rtl8169_set_rx_csum,
  955. .get_tx_csum = ethtool_op_get_tx_csum,
  956. .set_tx_csum = ethtool_op_set_tx_csum,
  957. .get_sg = ethtool_op_get_sg,
  958. .set_sg = ethtool_op_set_sg,
  959. .get_tso = ethtool_op_get_tso,
  960. .set_tso = ethtool_op_set_tso,
  961. .get_regs = rtl8169_get_regs,
  962. .get_wol = rtl8169_get_wol,
  963. .set_wol = rtl8169_set_wol,
  964. .get_strings = rtl8169_get_strings,
  965. .get_stats_count = rtl8169_get_stats_count,
  966. .get_ethtool_stats = rtl8169_get_ethtool_stats,
  967. .get_perm_addr = ethtool_op_get_perm_addr,
  968. };
  969. static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
  970. int bitval)
  971. {
  972. int val;
  973. val = mdio_read(ioaddr, reg);
  974. val = (bitval == 1) ?
  975. val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
  976. mdio_write(ioaddr, reg, val & 0xffff);
  977. }
  978. static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
  979. {
  980. const struct {
  981. u32 mask;
  982. int mac_version;
  983. } mac_info[] = {
  984. { 0x38800000, RTL_GIGA_MAC_VER_15 },
  985. { 0x38000000, RTL_GIGA_MAC_VER_12 },
  986. { 0x34000000, RTL_GIGA_MAC_VER_13 },
  987. { 0x30800000, RTL_GIGA_MAC_VER_14 },
  988. { 0x30000000, RTL_GIGA_MAC_VER_11 },
  989. { 0x18000000, RTL_GIGA_MAC_VER_05 },
  990. { 0x10000000, RTL_GIGA_MAC_VER_04 },
  991. { 0x04000000, RTL_GIGA_MAC_VER_03 },
  992. { 0x00800000, RTL_GIGA_MAC_VER_02 },
  993. { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
  994. }, *p = mac_info;
  995. u32 reg;
  996. reg = RTL_R32(TxConfig) & 0x7c800000;
  997. while ((reg & p->mask) != p->mask)
  998. p++;
  999. tp->mac_version = p->mac_version;
  1000. }
  1001. static void rtl8169_print_mac_version(struct rtl8169_private *tp)
  1002. {
  1003. dprintk("mac_version = 0x%02x\n", tp->mac_version);
  1004. }
  1005. static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
  1006. {
  1007. const struct {
  1008. u16 mask;
  1009. u16 set;
  1010. int phy_version;
  1011. } phy_info[] = {
  1012. { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
  1013. { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
  1014. { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
  1015. { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
  1016. }, *p = phy_info;
  1017. u16 reg;
  1018. reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
  1019. while ((reg & p->mask) != p->set)
  1020. p++;
  1021. tp->phy_version = p->phy_version;
  1022. }
  1023. static void rtl8169_print_phy_version(struct rtl8169_private *tp)
  1024. {
  1025. struct {
  1026. int version;
  1027. char *msg;
  1028. u32 reg;
  1029. } phy_print[] = {
  1030. { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
  1031. { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
  1032. { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
  1033. { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
  1034. { 0, NULL, 0x0000 }
  1035. }, *p;
  1036. for (p = phy_print; p->msg; p++) {
  1037. if (tp->phy_version == p->version) {
  1038. dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
  1039. return;
  1040. }
  1041. }
  1042. dprintk("phy_version == Unknown\n");
  1043. }
  1044. static void rtl8169_hw_phy_config(struct net_device *dev)
  1045. {
  1046. struct rtl8169_private *tp = netdev_priv(dev);
  1047. void __iomem *ioaddr = tp->mmio_addr;
  1048. struct {
  1049. u16 regs[5]; /* Beware of bit-sign propagation */
  1050. } phy_magic[5] = { {
  1051. { 0x0000, //w 4 15 12 0
  1052. 0x00a1, //w 3 15 0 00a1
  1053. 0x0008, //w 2 15 0 0008
  1054. 0x1020, //w 1 15 0 1020
  1055. 0x1000 } },{ //w 0 15 0 1000
  1056. { 0x7000, //w 4 15 12 7
  1057. 0xff41, //w 3 15 0 ff41
  1058. 0xde60, //w 2 15 0 de60
  1059. 0x0140, //w 1 15 0 0140
  1060. 0x0077 } },{ //w 0 15 0 0077
  1061. { 0xa000, //w 4 15 12 a
  1062. 0xdf01, //w 3 15 0 df01
  1063. 0xdf20, //w 2 15 0 df20
  1064. 0xff95, //w 1 15 0 ff95
  1065. 0xfa00 } },{ //w 0 15 0 fa00
  1066. { 0xb000, //w 4 15 12 b
  1067. 0xff41, //w 3 15 0 ff41
  1068. 0xde20, //w 2 15 0 de20
  1069. 0x0140, //w 1 15 0 0140
  1070. 0x00bb } },{ //w 0 15 0 00bb
  1071. { 0xf000, //w 4 15 12 f
  1072. 0xdf01, //w 3 15 0 df01
  1073. 0xdf20, //w 2 15 0 df20
  1074. 0xff95, //w 1 15 0 ff95
  1075. 0xbf00 } //w 0 15 0 bf00
  1076. }
  1077. }, *p = phy_magic;
  1078. int i;
  1079. rtl8169_print_mac_version(tp);
  1080. rtl8169_print_phy_version(tp);
  1081. if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
  1082. return;
  1083. if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
  1084. return;
  1085. dprintk("MAC version != 0 && PHY version == 0 or 1\n");
  1086. dprintk("Do final_reg2.cfg\n");
  1087. /* Shazam ! */
  1088. if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
  1089. mdio_write(ioaddr, 31, 0x0002);
  1090. mdio_write(ioaddr, 1, 0x90d0);
  1091. mdio_write(ioaddr, 31, 0x0000);
  1092. return;
  1093. }
  1094. /* phy config for RTL8169s mac_version C chip */
  1095. mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
  1096. mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
  1097. mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
  1098. rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
  1099. for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
  1100. int val, pos = 4;
  1101. val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
  1102. mdio_write(ioaddr, pos, val);
  1103. while (--pos >= 0)
  1104. mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
  1105. rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
  1106. rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
  1107. }
  1108. mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
  1109. }
  1110. static void rtl8169_phy_timer(unsigned long __opaque)
  1111. {
  1112. struct net_device *dev = (struct net_device *)__opaque;
  1113. struct rtl8169_private *tp = netdev_priv(dev);
  1114. struct timer_list *timer = &tp->timer;
  1115. void __iomem *ioaddr = tp->mmio_addr;
  1116. unsigned long timeout = RTL8169_PHY_TIMEOUT;
  1117. assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
  1118. assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
  1119. if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
  1120. return;
  1121. spin_lock_irq(&tp->lock);
  1122. if (tp->phy_reset_pending(ioaddr)) {
  1123. /*
  1124. * A busy loop could burn quite a few cycles on nowadays CPU.
  1125. * Let's delay the execution of the timer for a few ticks.
  1126. */
  1127. timeout = HZ/10;
  1128. goto out_mod_timer;
  1129. }
  1130. if (tp->link_ok(ioaddr))
  1131. goto out_unlock;
  1132. if (netif_msg_link(tp))
  1133. printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
  1134. tp->phy_reset_enable(ioaddr);
  1135. out_mod_timer:
  1136. mod_timer(timer, jiffies + timeout);
  1137. out_unlock:
  1138. spin_unlock_irq(&tp->lock);
  1139. }
  1140. static inline void rtl8169_delete_timer(struct net_device *dev)
  1141. {
  1142. struct rtl8169_private *tp = netdev_priv(dev);
  1143. struct timer_list *timer = &tp->timer;
  1144. if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
  1145. (tp->phy_version >= RTL_GIGA_PHY_VER_H))
  1146. return;
  1147. del_timer_sync(timer);
  1148. }
  1149. static inline void rtl8169_request_timer(struct net_device *dev)
  1150. {
  1151. struct rtl8169_private *tp = netdev_priv(dev);
  1152. struct timer_list *timer = &tp->timer;
  1153. if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
  1154. (tp->phy_version >= RTL_GIGA_PHY_VER_H))
  1155. return;
  1156. mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
  1157. }
  1158. #ifdef CONFIG_NET_POLL_CONTROLLER
  1159. /*
  1160. * Polling 'interrupt' - used by things like netconsole to send skbs
  1161. * without having to re-enable interrupts. It's not called while
  1162. * the interrupt routine is executing.
  1163. */
  1164. static void rtl8169_netpoll(struct net_device *dev)
  1165. {
  1166. struct rtl8169_private *tp = netdev_priv(dev);
  1167. struct pci_dev *pdev = tp->pci_dev;
  1168. disable_irq(pdev->irq);
  1169. rtl8169_interrupt(pdev->irq, dev);
  1170. enable_irq(pdev->irq);
  1171. }
  1172. #endif
  1173. static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
  1174. void __iomem *ioaddr)
  1175. {
  1176. iounmap(ioaddr);
  1177. pci_release_regions(pdev);
  1178. pci_disable_device(pdev);
  1179. free_netdev(dev);
  1180. }
  1181. static void rtl8169_phy_reset(struct net_device *dev,
  1182. struct rtl8169_private *tp)
  1183. {
  1184. void __iomem *ioaddr = tp->mmio_addr;
  1185. int i;
  1186. tp->phy_reset_enable(ioaddr);
  1187. for (i = 0; i < 100; i++) {
  1188. if (!tp->phy_reset_pending(ioaddr))
  1189. return;
  1190. msleep(1);
  1191. }
  1192. if (netif_msg_link(tp))
  1193. printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
  1194. }
  1195. static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
  1196. {
  1197. void __iomem *ioaddr = tp->mmio_addr;
  1198. static int board_idx = -1;
  1199. u8 autoneg, duplex;
  1200. u16 speed;
  1201. board_idx++;
  1202. rtl8169_hw_phy_config(dev);
  1203. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  1204. RTL_W8(0x82, 0x01);
  1205. if (tp->mac_version < RTL_GIGA_MAC_VER_03) {
  1206. dprintk("Set PCI Latency=0x40\n");
  1207. pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
  1208. }
  1209. if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
  1210. dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
  1211. RTL_W8(0x82, 0x01);
  1212. dprintk("Set PHY Reg 0x0bh = 0x00h\n");
  1213. mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
  1214. }
  1215. rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
  1216. rtl8169_phy_reset(dev, tp);
  1217. rtl8169_set_speed(dev, autoneg, speed, duplex);
  1218. if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
  1219. printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
  1220. }
  1221. static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1222. {
  1223. struct rtl8169_private *tp = netdev_priv(dev);
  1224. struct mii_ioctl_data *data = if_mii(ifr);
  1225. if (!netif_running(dev))
  1226. return -ENODEV;
  1227. switch (cmd) {
  1228. case SIOCGMIIPHY:
  1229. data->phy_id = 32; /* Internal PHY */
  1230. return 0;
  1231. case SIOCGMIIREG:
  1232. data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
  1233. return 0;
  1234. case SIOCSMIIREG:
  1235. if (!capable(CAP_NET_ADMIN))
  1236. return -EPERM;
  1237. mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
  1238. return 0;
  1239. }
  1240. return -EOPNOTSUPP;
  1241. }
  1242. static int __devinit
  1243. rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  1244. {
  1245. const unsigned int region = rtl_cfg_info[ent->driver_data].region;
  1246. struct rtl8169_private *tp;
  1247. struct net_device *dev;
  1248. void __iomem *ioaddr;
  1249. unsigned int pm_cap;
  1250. int i, rc;
  1251. if (netif_msg_drv(&debug)) {
  1252. printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
  1253. MODULENAME, RTL8169_VERSION);
  1254. }
  1255. dev = alloc_etherdev(sizeof (*tp));
  1256. if (!dev) {
  1257. if (netif_msg_drv(&debug))
  1258. dev_err(&pdev->dev, "unable to alloc new ethernet\n");
  1259. rc = -ENOMEM;
  1260. goto out;
  1261. }
  1262. SET_MODULE_OWNER(dev);
  1263. SET_NETDEV_DEV(dev, &pdev->dev);
  1264. tp = netdev_priv(dev);
  1265. tp->dev = dev;
  1266. tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
  1267. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  1268. rc = pci_enable_device(pdev);
  1269. if (rc < 0) {
  1270. if (netif_msg_probe(tp))
  1271. dev_err(&pdev->dev, "enable failure\n");
  1272. goto err_out_free_dev_1;
  1273. }
  1274. rc = pci_set_mwi(pdev);
  1275. if (rc < 0)
  1276. goto err_out_disable_2;
  1277. /* save power state before pci_enable_device overwrites it */
  1278. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  1279. if (pm_cap) {
  1280. u16 pwr_command, acpi_idle_state;
  1281. pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
  1282. acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
  1283. } else {
  1284. if (netif_msg_probe(tp)) {
  1285. dev_err(&pdev->dev,
  1286. "PowerManagement capability not found.\n");
  1287. }
  1288. }
  1289. /* make sure PCI base addr 1 is MMIO */
  1290. if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
  1291. if (netif_msg_probe(tp)) {
  1292. dev_err(&pdev->dev,
  1293. "region #%d not an MMIO resource, aborting\n",
  1294. region);
  1295. }
  1296. rc = -ENODEV;
  1297. goto err_out_mwi_3;
  1298. }
  1299. /* check for weird/broken PCI region reporting */
  1300. if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
  1301. if (netif_msg_probe(tp)) {
  1302. dev_err(&pdev->dev,
  1303. "Invalid PCI region size(s), aborting\n");
  1304. }
  1305. rc = -ENODEV;
  1306. goto err_out_mwi_3;
  1307. }
  1308. rc = pci_request_regions(pdev, MODULENAME);
  1309. if (rc < 0) {
  1310. if (netif_msg_probe(tp))
  1311. dev_err(&pdev->dev, "could not request regions.\n");
  1312. goto err_out_mwi_3;
  1313. }
  1314. tp->cp_cmd = PCIMulRW | RxChkSum;
  1315. if ((sizeof(dma_addr_t) > 4) &&
  1316. !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
  1317. tp->cp_cmd |= PCIDAC;
  1318. dev->features |= NETIF_F_HIGHDMA;
  1319. } else {
  1320. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  1321. if (rc < 0) {
  1322. if (netif_msg_probe(tp)) {
  1323. dev_err(&pdev->dev,
  1324. "DMA configuration failed.\n");
  1325. }
  1326. goto err_out_free_res_4;
  1327. }
  1328. }
  1329. pci_set_master(pdev);
  1330. /* ioremap MMIO region */
  1331. ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
  1332. if (!ioaddr) {
  1333. if (netif_msg_probe(tp))
  1334. dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
  1335. rc = -EIO;
  1336. goto err_out_free_res_4;
  1337. }
  1338. /* Unneeded ? Don't mess with Mrs. Murphy. */
  1339. rtl8169_irq_mask_and_ack(ioaddr);
  1340. /* Soft reset the chip. */
  1341. RTL_W8(ChipCmd, CmdReset);
  1342. /* Check that the chip has finished the reset. */
  1343. for (i = 100; i > 0; i--) {
  1344. if ((RTL_R8(ChipCmd) & CmdReset) == 0)
  1345. break;
  1346. msleep_interruptible(1);
  1347. }
  1348. /* Identify chip attached to board */
  1349. rtl8169_get_mac_version(tp, ioaddr);
  1350. rtl8169_get_phy_version(tp, ioaddr);
  1351. rtl8169_print_mac_version(tp);
  1352. rtl8169_print_phy_version(tp);
  1353. for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
  1354. if (tp->mac_version == rtl_chip_info[i].mac_version)
  1355. break;
  1356. }
  1357. if (i < 0) {
  1358. /* Unknown chip: assume array element #0, original RTL-8169 */
  1359. if (netif_msg_probe(tp)) {
  1360. dev_printk(KERN_DEBUG, &pdev->dev,
  1361. "unknown chip version, assuming %s\n",
  1362. rtl_chip_info[0].name);
  1363. }
  1364. i++;
  1365. }
  1366. tp->chipset = i;
  1367. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1368. RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
  1369. RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
  1370. RTL_W8(Cfg9346, Cfg9346_Lock);
  1371. if (RTL_R8(PHYstatus) & TBI_Enable) {
  1372. tp->set_speed = rtl8169_set_speed_tbi;
  1373. tp->get_settings = rtl8169_gset_tbi;
  1374. tp->phy_reset_enable = rtl8169_tbi_reset_enable;
  1375. tp->phy_reset_pending = rtl8169_tbi_reset_pending;
  1376. tp->link_ok = rtl8169_tbi_link_ok;
  1377. tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
  1378. } else {
  1379. tp->set_speed = rtl8169_set_speed_xmii;
  1380. tp->get_settings = rtl8169_gset_xmii;
  1381. tp->phy_reset_enable = rtl8169_xmii_reset_enable;
  1382. tp->phy_reset_pending = rtl8169_xmii_reset_pending;
  1383. tp->link_ok = rtl8169_xmii_link_ok;
  1384. dev->do_ioctl = rtl8169_ioctl;
  1385. }
  1386. /* Get MAC address. FIXME: read EEPROM */
  1387. for (i = 0; i < MAC_ADDR_LEN; i++)
  1388. dev->dev_addr[i] = RTL_R8(MAC0 + i);
  1389. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  1390. dev->open = rtl8169_open;
  1391. dev->hard_start_xmit = rtl8169_start_xmit;
  1392. dev->get_stats = rtl8169_get_stats;
  1393. SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
  1394. dev->stop = rtl8169_close;
  1395. dev->tx_timeout = rtl8169_tx_timeout;
  1396. dev->set_multicast_list = rtl8169_set_rx_mode;
  1397. dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
  1398. dev->irq = pdev->irq;
  1399. dev->base_addr = (unsigned long) ioaddr;
  1400. dev->change_mtu = rtl8169_change_mtu;
  1401. #ifdef CONFIG_R8169_NAPI
  1402. dev->poll = rtl8169_poll;
  1403. dev->weight = R8169_NAPI_WEIGHT;
  1404. #endif
  1405. #ifdef CONFIG_R8169_VLAN
  1406. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  1407. dev->vlan_rx_register = rtl8169_vlan_rx_register;
  1408. dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
  1409. #endif
  1410. #ifdef CONFIG_NET_POLL_CONTROLLER
  1411. dev->poll_controller = rtl8169_netpoll;
  1412. #endif
  1413. tp->intr_mask = 0xffff;
  1414. tp->pci_dev = pdev;
  1415. tp->mmio_addr = ioaddr;
  1416. tp->align = rtl_cfg_info[ent->driver_data].align;
  1417. init_timer(&tp->timer);
  1418. tp->timer.data = (unsigned long) dev;
  1419. tp->timer.function = rtl8169_phy_timer;
  1420. spin_lock_init(&tp->lock);
  1421. rc = register_netdev(dev);
  1422. if (rc < 0)
  1423. goto err_out_unmap_5;
  1424. pci_set_drvdata(pdev, dev);
  1425. if (netif_msg_probe(tp)) {
  1426. printk(KERN_INFO "%s: %s at 0x%lx, "
  1427. "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
  1428. "IRQ %d\n",
  1429. dev->name,
  1430. rtl_chip_info[tp->chipset].name,
  1431. dev->base_addr,
  1432. dev->dev_addr[0], dev->dev_addr[1],
  1433. dev->dev_addr[2], dev->dev_addr[3],
  1434. dev->dev_addr[4], dev->dev_addr[5], dev->irq);
  1435. }
  1436. rtl8169_init_phy(dev, tp);
  1437. out:
  1438. return rc;
  1439. err_out_unmap_5:
  1440. iounmap(ioaddr);
  1441. err_out_free_res_4:
  1442. pci_release_regions(pdev);
  1443. err_out_mwi_3:
  1444. pci_clear_mwi(pdev);
  1445. err_out_disable_2:
  1446. pci_disable_device(pdev);
  1447. err_out_free_dev_1:
  1448. free_netdev(dev);
  1449. goto out;
  1450. }
  1451. static void __devexit
  1452. rtl8169_remove_one(struct pci_dev *pdev)
  1453. {
  1454. struct net_device *dev = pci_get_drvdata(pdev);
  1455. struct rtl8169_private *tp = netdev_priv(dev);
  1456. assert(dev != NULL);
  1457. assert(tp != NULL);
  1458. flush_scheduled_work();
  1459. unregister_netdev(dev);
  1460. rtl8169_release_board(pdev, dev, tp->mmio_addr);
  1461. pci_set_drvdata(pdev, NULL);
  1462. }
  1463. static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
  1464. struct net_device *dev)
  1465. {
  1466. unsigned int mtu = dev->mtu;
  1467. tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
  1468. }
  1469. static int rtl8169_open(struct net_device *dev)
  1470. {
  1471. struct rtl8169_private *tp = netdev_priv(dev);
  1472. struct pci_dev *pdev = tp->pci_dev;
  1473. int retval = -ENOMEM;
  1474. rtl8169_set_rxbufsize(tp, dev);
  1475. /*
  1476. * Rx and Tx desscriptors needs 256 bytes alignment.
  1477. * pci_alloc_consistent provides more.
  1478. */
  1479. tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
  1480. &tp->TxPhyAddr);
  1481. if (!tp->TxDescArray)
  1482. goto out;
  1483. tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
  1484. &tp->RxPhyAddr);
  1485. if (!tp->RxDescArray)
  1486. goto err_free_tx_0;
  1487. retval = rtl8169_init_ring(dev);
  1488. if (retval < 0)
  1489. goto err_free_rx_1;
  1490. INIT_DELAYED_WORK(&tp->task, NULL);
  1491. smp_mb();
  1492. retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
  1493. dev->name, dev);
  1494. if (retval < 0)
  1495. goto err_release_ring_2;
  1496. rtl8169_hw_start(dev);
  1497. rtl8169_request_timer(dev);
  1498. rtl8169_check_link_status(dev, tp, tp->mmio_addr);
  1499. out:
  1500. return retval;
  1501. err_release_ring_2:
  1502. rtl8169_rx_clear(tp);
  1503. err_free_rx_1:
  1504. pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
  1505. tp->RxPhyAddr);
  1506. err_free_tx_0:
  1507. pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
  1508. tp->TxPhyAddr);
  1509. goto out;
  1510. }
  1511. static void rtl8169_hw_reset(void __iomem *ioaddr)
  1512. {
  1513. /* Disable interrupts */
  1514. rtl8169_irq_mask_and_ack(ioaddr);
  1515. /* Reset the chipset */
  1516. RTL_W8(ChipCmd, CmdReset);
  1517. /* PCI commit */
  1518. RTL_R8(ChipCmd);
  1519. }
  1520. static void rtl8169_set_rx_tx_config_registers(struct rtl8169_private *tp)
  1521. {
  1522. void __iomem *ioaddr = tp->mmio_addr;
  1523. u32 cfg = rtl8169_rx_config;
  1524. cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
  1525. RTL_W32(RxConfig, cfg);
  1526. /* Set DMA burst size and Interframe Gap Time */
  1527. RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
  1528. (InterFrameGap << TxInterFrameGapShift));
  1529. }
  1530. static void rtl8169_hw_start(struct net_device *dev)
  1531. {
  1532. struct rtl8169_private *tp = netdev_priv(dev);
  1533. void __iomem *ioaddr = tp->mmio_addr;
  1534. struct pci_dev *pdev = tp->pci_dev;
  1535. u16 cmd;
  1536. u32 i;
  1537. /* Soft reset the chip. */
  1538. RTL_W8(ChipCmd, CmdReset);
  1539. /* Check that the chip has finished the reset. */
  1540. for (i = 100; i > 0; i--) {
  1541. if ((RTL_R8(ChipCmd) & CmdReset) == 0)
  1542. break;
  1543. msleep_interruptible(1);
  1544. }
  1545. if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
  1546. RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
  1547. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
  1548. }
  1549. if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
  1550. pci_write_config_word(pdev, 0x68, 0x00);
  1551. pci_write_config_word(pdev, 0x69, 0x08);
  1552. }
  1553. /* Undocumented stuff. */
  1554. if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
  1555. /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
  1556. if ((RTL_R8(Config2) & 0x07) & 0x01)
  1557. RTL_W32(0x7c, 0x0007ffff);
  1558. RTL_W32(0x7c, 0x0007ff00);
  1559. pci_read_config_word(pdev, PCI_COMMAND, &cmd);
  1560. cmd = cmd & 0xef;
  1561. pci_write_config_word(pdev, PCI_COMMAND, cmd);
  1562. }
  1563. RTL_W8(Cfg9346, Cfg9346_Unlock);
  1564. if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
  1565. (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
  1566. (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
  1567. (tp->mac_version == RTL_GIGA_MAC_VER_04))
  1568. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  1569. RTL_W8(EarlyTxThres, EarlyTxThld);
  1570. /* Low hurts. Let's disable the filtering. */
  1571. RTL_W16(RxMaxSize, 16383);
  1572. if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
  1573. (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
  1574. (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
  1575. (tp->mac_version == RTL_GIGA_MAC_VER_04))
  1576. rtl8169_set_rx_tx_config_registers(tp);
  1577. cmd = RTL_R16(CPlusCmd);
  1578. RTL_W16(CPlusCmd, cmd);
  1579. tp->cp_cmd |= cmd | PCIMulRW;
  1580. if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
  1581. (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
  1582. dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
  1583. "Bit-3 and bit-14 MUST be 1\n");
  1584. tp->cp_cmd |= (1 << 14);
  1585. }
  1586. RTL_W16(CPlusCmd, tp->cp_cmd);
  1587. /*
  1588. * Undocumented corner. Supposedly:
  1589. * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
  1590. */
  1591. RTL_W16(IntrMitigate, 0x0000);
  1592. /*
  1593. * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
  1594. * register to be written before TxDescAddrLow to work.
  1595. * Switching from MMIO to I/O access fixes the issue as well.
  1596. */
  1597. RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
  1598. RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
  1599. RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
  1600. RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
  1601. if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
  1602. (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
  1603. (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
  1604. (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
  1605. RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
  1606. rtl8169_set_rx_tx_config_registers(tp);
  1607. }
  1608. RTL_W8(Cfg9346, Cfg9346_Lock);
  1609. /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
  1610. RTL_R8(IntrMask);
  1611. RTL_W32(RxMissed, 0);
  1612. rtl8169_set_rx_mode(dev);
  1613. /* no early-rx interrupts */
  1614. RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
  1615. /* Enable all known interrupts by setting the interrupt mask. */
  1616. RTL_W16(IntrMask, rtl8169_intr_mask);
  1617. netif_start_queue(dev);
  1618. }
  1619. static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
  1620. {
  1621. struct rtl8169_private *tp = netdev_priv(dev);
  1622. int ret = 0;
  1623. if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
  1624. return -EINVAL;
  1625. dev->mtu = new_mtu;
  1626. if (!netif_running(dev))
  1627. goto out;
  1628. rtl8169_down(dev);
  1629. rtl8169_set_rxbufsize(tp, dev);
  1630. ret = rtl8169_init_ring(dev);
  1631. if (ret < 0)
  1632. goto out;
  1633. netif_poll_enable(dev);
  1634. rtl8169_hw_start(dev);
  1635. rtl8169_request_timer(dev);
  1636. out:
  1637. return ret;
  1638. }
  1639. static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
  1640. {
  1641. desc->addr = 0x0badbadbadbadbadull;
  1642. desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
  1643. }
  1644. static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
  1645. struct sk_buff **sk_buff, struct RxDesc *desc)
  1646. {
  1647. struct pci_dev *pdev = tp->pci_dev;
  1648. pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
  1649. PCI_DMA_FROMDEVICE);
  1650. dev_kfree_skb(*sk_buff);
  1651. *sk_buff = NULL;
  1652. rtl8169_make_unusable_by_asic(desc);
  1653. }
  1654. static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
  1655. {
  1656. u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
  1657. desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
  1658. }
  1659. static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
  1660. u32 rx_buf_sz)
  1661. {
  1662. desc->addr = cpu_to_le64(mapping);
  1663. wmb();
  1664. rtl8169_mark_to_asic(desc, rx_buf_sz);
  1665. }
  1666. static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
  1667. struct RxDesc *desc, int rx_buf_sz,
  1668. unsigned int align)
  1669. {
  1670. struct sk_buff *skb;
  1671. dma_addr_t mapping;
  1672. int ret = 0;
  1673. skb = dev_alloc_skb(rx_buf_sz + align);
  1674. if (!skb)
  1675. goto err_out;
  1676. skb_reserve(skb, (align - 1) & (unsigned long)skb->data);
  1677. *sk_buff = skb;
  1678. mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
  1679. PCI_DMA_FROMDEVICE);
  1680. rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
  1681. out:
  1682. return ret;
  1683. err_out:
  1684. ret = -ENOMEM;
  1685. rtl8169_make_unusable_by_asic(desc);
  1686. goto out;
  1687. }
  1688. static void rtl8169_rx_clear(struct rtl8169_private *tp)
  1689. {
  1690. int i;
  1691. for (i = 0; i < NUM_RX_DESC; i++) {
  1692. if (tp->Rx_skbuff[i]) {
  1693. rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
  1694. tp->RxDescArray + i);
  1695. }
  1696. }
  1697. }
  1698. static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
  1699. u32 start, u32 end)
  1700. {
  1701. u32 cur;
  1702. for (cur = start; end - cur > 0; cur++) {
  1703. int ret, i = cur % NUM_RX_DESC;
  1704. if (tp->Rx_skbuff[i])
  1705. continue;
  1706. ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
  1707. tp->RxDescArray + i, tp->rx_buf_sz, tp->align);
  1708. if (ret < 0)
  1709. break;
  1710. }
  1711. return cur - start;
  1712. }
  1713. static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
  1714. {
  1715. desc->opts1 |= cpu_to_le32(RingEnd);
  1716. }
  1717. static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
  1718. {
  1719. tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
  1720. }
  1721. static int rtl8169_init_ring(struct net_device *dev)
  1722. {
  1723. struct rtl8169_private *tp = netdev_priv(dev);
  1724. rtl8169_init_ring_indexes(tp);
  1725. memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
  1726. memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
  1727. if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
  1728. goto err_out;
  1729. rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
  1730. return 0;
  1731. err_out:
  1732. rtl8169_rx_clear(tp);
  1733. return -ENOMEM;
  1734. }
  1735. static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
  1736. struct TxDesc *desc)
  1737. {
  1738. unsigned int len = tx_skb->len;
  1739. pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
  1740. desc->opts1 = 0x00;
  1741. desc->opts2 = 0x00;
  1742. desc->addr = 0x00;
  1743. tx_skb->len = 0;
  1744. }
  1745. static void rtl8169_tx_clear(struct rtl8169_private *tp)
  1746. {
  1747. unsigned int i;
  1748. for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
  1749. unsigned int entry = i % NUM_TX_DESC;
  1750. struct ring_info *tx_skb = tp->tx_skb + entry;
  1751. unsigned int len = tx_skb->len;
  1752. if (len) {
  1753. struct sk_buff *skb = tx_skb->skb;
  1754. rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
  1755. tp->TxDescArray + entry);
  1756. if (skb) {
  1757. dev_kfree_skb(skb);
  1758. tx_skb->skb = NULL;
  1759. }
  1760. tp->stats.tx_dropped++;
  1761. }
  1762. }
  1763. tp->cur_tx = tp->dirty_tx = 0;
  1764. }
  1765. static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
  1766. {
  1767. struct rtl8169_private *tp = netdev_priv(dev);
  1768. PREPARE_DELAYED_WORK(&tp->task, task);
  1769. schedule_delayed_work(&tp->task, 4);
  1770. }
  1771. static void rtl8169_wait_for_quiescence(struct net_device *dev)
  1772. {
  1773. struct rtl8169_private *tp = netdev_priv(dev);
  1774. void __iomem *ioaddr = tp->mmio_addr;
  1775. synchronize_irq(dev->irq);
  1776. /* Wait for any pending NAPI task to complete */
  1777. netif_poll_disable(dev);
  1778. rtl8169_irq_mask_and_ack(ioaddr);
  1779. netif_poll_enable(dev);
  1780. }
  1781. static void rtl8169_reinit_task(struct work_struct *work)
  1782. {
  1783. struct rtl8169_private *tp =
  1784. container_of(work, struct rtl8169_private, task.work);
  1785. struct net_device *dev = tp->dev;
  1786. int ret;
  1787. rtnl_lock();
  1788. if (!netif_running(dev))
  1789. goto out_unlock;
  1790. rtl8169_wait_for_quiescence(dev);
  1791. rtl8169_close(dev);
  1792. ret = rtl8169_open(dev);
  1793. if (unlikely(ret < 0)) {
  1794. if (net_ratelimit()) {
  1795. struct rtl8169_private *tp = netdev_priv(dev);
  1796. if (netif_msg_drv(tp)) {
  1797. printk(PFX KERN_ERR
  1798. "%s: reinit failure (status = %d)."
  1799. " Rescheduling.\n", dev->name, ret);
  1800. }
  1801. }
  1802. rtl8169_schedule_work(dev, rtl8169_reinit_task);
  1803. }
  1804. out_unlock:
  1805. rtnl_unlock();
  1806. }
  1807. static void rtl8169_reset_task(struct work_struct *work)
  1808. {
  1809. struct rtl8169_private *tp =
  1810. container_of(work, struct rtl8169_private, task.work);
  1811. struct net_device *dev = tp->dev;
  1812. rtnl_lock();
  1813. if (!netif_running(dev))
  1814. goto out_unlock;
  1815. rtl8169_wait_for_quiescence(dev);
  1816. rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
  1817. rtl8169_tx_clear(tp);
  1818. if (tp->dirty_rx == tp->cur_rx) {
  1819. rtl8169_init_ring_indexes(tp);
  1820. rtl8169_hw_start(dev);
  1821. netif_wake_queue(dev);
  1822. } else {
  1823. if (net_ratelimit()) {
  1824. struct rtl8169_private *tp = netdev_priv(dev);
  1825. if (netif_msg_intr(tp)) {
  1826. printk(PFX KERN_EMERG
  1827. "%s: Rx buffers shortage\n", dev->name);
  1828. }
  1829. }
  1830. rtl8169_schedule_work(dev, rtl8169_reset_task);
  1831. }
  1832. out_unlock:
  1833. rtnl_unlock();
  1834. }
  1835. static void rtl8169_tx_timeout(struct net_device *dev)
  1836. {
  1837. struct rtl8169_private *tp = netdev_priv(dev);
  1838. rtl8169_hw_reset(tp->mmio_addr);
  1839. /* Let's wait a bit while any (async) irq lands on */
  1840. rtl8169_schedule_work(dev, rtl8169_reset_task);
  1841. }
  1842. static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
  1843. u32 opts1)
  1844. {
  1845. struct skb_shared_info *info = skb_shinfo(skb);
  1846. unsigned int cur_frag, entry;
  1847. struct TxDesc *txd;
  1848. entry = tp->cur_tx;
  1849. for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
  1850. skb_frag_t *frag = info->frags + cur_frag;
  1851. dma_addr_t mapping;
  1852. u32 status, len;
  1853. void *addr;
  1854. entry = (entry + 1) % NUM_TX_DESC;
  1855. txd = tp->TxDescArray + entry;
  1856. len = frag->size;
  1857. addr = ((void *) page_address(frag->page)) + frag->page_offset;
  1858. mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
  1859. /* anti gcc 2.95.3 bugware (sic) */
  1860. status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
  1861. txd->opts1 = cpu_to_le32(status);
  1862. txd->addr = cpu_to_le64(mapping);
  1863. tp->tx_skb[entry].len = len;
  1864. }
  1865. if (cur_frag) {
  1866. tp->tx_skb[entry].skb = skb;
  1867. txd->opts1 |= cpu_to_le32(LastFrag);
  1868. }
  1869. return cur_frag;
  1870. }
  1871. static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
  1872. {
  1873. if (dev->features & NETIF_F_TSO) {
  1874. u32 mss = skb_shinfo(skb)->gso_size;
  1875. if (mss)
  1876. return LargeSend | ((mss & MSSMask) << MSSShift);
  1877. }
  1878. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1879. const struct iphdr *ip = skb->nh.iph;
  1880. if (ip->protocol == IPPROTO_TCP)
  1881. return IPCS | TCPCS;
  1882. else if (ip->protocol == IPPROTO_UDP)
  1883. return IPCS | UDPCS;
  1884. WARN_ON(1); /* we need a WARN() */
  1885. }
  1886. return 0;
  1887. }
  1888. static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1889. {
  1890. struct rtl8169_private *tp = netdev_priv(dev);
  1891. unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
  1892. struct TxDesc *txd = tp->TxDescArray + entry;
  1893. void __iomem *ioaddr = tp->mmio_addr;
  1894. dma_addr_t mapping;
  1895. u32 status, len;
  1896. u32 opts1;
  1897. int ret = NETDEV_TX_OK;
  1898. if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
  1899. if (netif_msg_drv(tp)) {
  1900. printk(KERN_ERR
  1901. "%s: BUG! Tx Ring full when queue awake!\n",
  1902. dev->name);
  1903. }
  1904. goto err_stop;
  1905. }
  1906. if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
  1907. goto err_stop;
  1908. opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
  1909. frags = rtl8169_xmit_frags(tp, skb, opts1);
  1910. if (frags) {
  1911. len = skb_headlen(skb);
  1912. opts1 |= FirstFrag;
  1913. } else {
  1914. len = skb->len;
  1915. if (unlikely(len < ETH_ZLEN)) {
  1916. if (skb_padto(skb, ETH_ZLEN))
  1917. goto err_update_stats;
  1918. len = ETH_ZLEN;
  1919. }
  1920. opts1 |= FirstFrag | LastFrag;
  1921. tp->tx_skb[entry].skb = skb;
  1922. }
  1923. mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  1924. tp->tx_skb[entry].len = len;
  1925. txd->addr = cpu_to_le64(mapping);
  1926. txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
  1927. wmb();
  1928. /* anti gcc 2.95.3 bugware (sic) */
  1929. status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
  1930. txd->opts1 = cpu_to_le32(status);
  1931. dev->trans_start = jiffies;
  1932. tp->cur_tx += frags + 1;
  1933. smp_wmb();
  1934. RTL_W8(TxPoll, 0x40); /* set polling bit */
  1935. if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
  1936. netif_stop_queue(dev);
  1937. smp_rmb();
  1938. if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
  1939. netif_wake_queue(dev);
  1940. }
  1941. out:
  1942. return ret;
  1943. err_stop:
  1944. netif_stop_queue(dev);
  1945. ret = NETDEV_TX_BUSY;
  1946. err_update_stats:
  1947. tp->stats.tx_dropped++;
  1948. goto out;
  1949. }
  1950. static void rtl8169_pcierr_interrupt(struct net_device *dev)
  1951. {
  1952. struct rtl8169_private *tp = netdev_priv(dev);
  1953. struct pci_dev *pdev = tp->pci_dev;
  1954. void __iomem *ioaddr = tp->mmio_addr;
  1955. u16 pci_status, pci_cmd;
  1956. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  1957. pci_read_config_word(pdev, PCI_STATUS, &pci_status);
  1958. if (netif_msg_intr(tp)) {
  1959. printk(KERN_ERR
  1960. "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
  1961. dev->name, pci_cmd, pci_status);
  1962. }
  1963. /*
  1964. * The recovery sequence below admits a very elaborated explanation:
  1965. * - it seems to work;
  1966. * - I did not see what else could be done;
  1967. * - it makes iop3xx happy.
  1968. *
  1969. * Feel free to adjust to your needs.
  1970. */
  1971. if (pdev->broken_parity_status)
  1972. pci_cmd &= ~PCI_COMMAND_PARITY;
  1973. else
  1974. pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
  1975. pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
  1976. pci_write_config_word(pdev, PCI_STATUS,
  1977. pci_status & (PCI_STATUS_DETECTED_PARITY |
  1978. PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
  1979. PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
  1980. /* The infamous DAC f*ckup only happens at boot time */
  1981. if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
  1982. if (netif_msg_intr(tp))
  1983. printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
  1984. tp->cp_cmd &= ~PCIDAC;
  1985. RTL_W16(CPlusCmd, tp->cp_cmd);
  1986. dev->features &= ~NETIF_F_HIGHDMA;
  1987. }
  1988. rtl8169_hw_reset(ioaddr);
  1989. rtl8169_schedule_work(dev, rtl8169_reinit_task);
  1990. }
  1991. static void
  1992. rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
  1993. void __iomem *ioaddr)
  1994. {
  1995. unsigned int dirty_tx, tx_left;
  1996. assert(dev != NULL);
  1997. assert(tp != NULL);
  1998. assert(ioaddr != NULL);
  1999. dirty_tx = tp->dirty_tx;
  2000. smp_rmb();
  2001. tx_left = tp->cur_tx - dirty_tx;
  2002. while (tx_left > 0) {
  2003. unsigned int entry = dirty_tx % NUM_TX_DESC;
  2004. struct ring_info *tx_skb = tp->tx_skb + entry;
  2005. u32 len = tx_skb->len;
  2006. u32 status;
  2007. rmb();
  2008. status = le32_to_cpu(tp->TxDescArray[entry].opts1);
  2009. if (status & DescOwn)
  2010. break;
  2011. tp->stats.tx_bytes += len;
  2012. tp->stats.tx_packets++;
  2013. rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
  2014. if (status & LastFrag) {
  2015. dev_kfree_skb_irq(tx_skb->skb);
  2016. tx_skb->skb = NULL;
  2017. }
  2018. dirty_tx++;
  2019. tx_left--;
  2020. }
  2021. if (tp->dirty_tx != dirty_tx) {
  2022. tp->dirty_tx = dirty_tx;
  2023. smp_wmb();
  2024. if (netif_queue_stopped(dev) &&
  2025. (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
  2026. netif_wake_queue(dev);
  2027. }
  2028. }
  2029. }
  2030. static inline int rtl8169_fragmented_frame(u32 status)
  2031. {
  2032. return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
  2033. }
  2034. static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
  2035. {
  2036. u32 opts1 = le32_to_cpu(desc->opts1);
  2037. u32 status = opts1 & RxProtoMask;
  2038. if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
  2039. ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
  2040. ((status == RxProtoIP) && !(opts1 & IPFail)))
  2041. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2042. else
  2043. skb->ip_summed = CHECKSUM_NONE;
  2044. }
  2045. static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
  2046. struct RxDesc *desc, int rx_buf_sz,
  2047. unsigned int align)
  2048. {
  2049. int ret = -1;
  2050. if (pkt_size < rx_copybreak) {
  2051. struct sk_buff *skb;
  2052. skb = dev_alloc_skb(pkt_size + align);
  2053. if (skb) {
  2054. skb_reserve(skb, (align - 1) & (unsigned long)skb->data);
  2055. eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
  2056. *sk_buff = skb;
  2057. rtl8169_mark_to_asic(desc, rx_buf_sz);
  2058. ret = 0;
  2059. }
  2060. }
  2061. return ret;
  2062. }
  2063. static int
  2064. rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
  2065. void __iomem *ioaddr)
  2066. {
  2067. unsigned int cur_rx, rx_left;
  2068. unsigned int delta, count;
  2069. assert(dev != NULL);
  2070. assert(tp != NULL);
  2071. assert(ioaddr != NULL);
  2072. cur_rx = tp->cur_rx;
  2073. rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
  2074. rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
  2075. for (; rx_left > 0; rx_left--, cur_rx++) {
  2076. unsigned int entry = cur_rx % NUM_RX_DESC;
  2077. struct RxDesc *desc = tp->RxDescArray + entry;
  2078. u32 status;
  2079. rmb();
  2080. status = le32_to_cpu(desc->opts1);
  2081. if (status & DescOwn)
  2082. break;
  2083. if (unlikely(status & RxRES)) {
  2084. if (netif_msg_rx_err(tp)) {
  2085. printk(KERN_INFO
  2086. "%s: Rx ERROR. status = %08x\n",
  2087. dev->name, status);
  2088. }
  2089. tp->stats.rx_errors++;
  2090. if (status & (RxRWT | RxRUNT))
  2091. tp->stats.rx_length_errors++;
  2092. if (status & RxCRC)
  2093. tp->stats.rx_crc_errors++;
  2094. if (status & RxFOVF) {
  2095. rtl8169_schedule_work(dev, rtl8169_reset_task);
  2096. tp->stats.rx_fifo_errors++;
  2097. }
  2098. rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
  2099. } else {
  2100. struct sk_buff *skb = tp->Rx_skbuff[entry];
  2101. int pkt_size = (status & 0x00001FFF) - 4;
  2102. void (*pci_action)(struct pci_dev *, dma_addr_t,
  2103. size_t, int) = pci_dma_sync_single_for_device;
  2104. /*
  2105. * The driver does not support incoming fragmented
  2106. * frames. They are seen as a symptom of over-mtu
  2107. * sized frames.
  2108. */
  2109. if (unlikely(rtl8169_fragmented_frame(status))) {
  2110. tp->stats.rx_dropped++;
  2111. tp->stats.rx_length_errors++;
  2112. rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
  2113. continue;
  2114. }
  2115. rtl8169_rx_csum(skb, desc);
  2116. pci_dma_sync_single_for_cpu(tp->pci_dev,
  2117. le64_to_cpu(desc->addr), tp->rx_buf_sz,
  2118. PCI_DMA_FROMDEVICE);
  2119. if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
  2120. tp->rx_buf_sz, tp->align)) {
  2121. pci_action = pci_unmap_single;
  2122. tp->Rx_skbuff[entry] = NULL;
  2123. }
  2124. pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
  2125. tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
  2126. skb->dev = dev;
  2127. skb_put(skb, pkt_size);
  2128. skb->protocol = eth_type_trans(skb, dev);
  2129. if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
  2130. rtl8169_rx_skb(skb);
  2131. dev->last_rx = jiffies;
  2132. tp->stats.rx_bytes += pkt_size;
  2133. tp->stats.rx_packets++;
  2134. }
  2135. }
  2136. count = cur_rx - tp->cur_rx;
  2137. tp->cur_rx = cur_rx;
  2138. delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
  2139. if (!delta && count && netif_msg_intr(tp))
  2140. printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
  2141. tp->dirty_rx += delta;
  2142. /*
  2143. * FIXME: until there is periodic timer to try and refill the ring,
  2144. * a temporary shortage may definitely kill the Rx process.
  2145. * - disable the asic to try and avoid an overflow and kick it again
  2146. * after refill ?
  2147. * - how do others driver handle this condition (Uh oh...).
  2148. */
  2149. if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
  2150. printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
  2151. return count;
  2152. }
  2153. /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
  2154. static irqreturn_t
  2155. rtl8169_interrupt(int irq, void *dev_instance)
  2156. {
  2157. struct net_device *dev = (struct net_device *) dev_instance;
  2158. struct rtl8169_private *tp = netdev_priv(dev);
  2159. int boguscnt = max_interrupt_work;
  2160. void __iomem *ioaddr = tp->mmio_addr;
  2161. int status;
  2162. int handled = 0;
  2163. do {
  2164. status = RTL_R16(IntrStatus);
  2165. /* hotplug/major error/no more work/shared irq */
  2166. if ((status == 0xFFFF) || !status)
  2167. break;
  2168. handled = 1;
  2169. if (unlikely(!netif_running(dev))) {
  2170. rtl8169_asic_down(ioaddr);
  2171. goto out;
  2172. }
  2173. status &= tp->intr_mask;
  2174. RTL_W16(IntrStatus,
  2175. (status & RxFIFOOver) ? (status | RxOverflow) : status);
  2176. if (!(status & rtl8169_intr_mask))
  2177. break;
  2178. if (unlikely(status & SYSErr)) {
  2179. rtl8169_pcierr_interrupt(dev);
  2180. break;
  2181. }
  2182. if (status & LinkChg)
  2183. rtl8169_check_link_status(dev, tp, ioaddr);
  2184. #ifdef CONFIG_R8169_NAPI
  2185. RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
  2186. tp->intr_mask = ~rtl8169_napi_event;
  2187. if (likely(netif_rx_schedule_prep(dev)))
  2188. __netif_rx_schedule(dev);
  2189. else if (netif_msg_intr(tp)) {
  2190. printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
  2191. dev->name, status);
  2192. }
  2193. break;
  2194. #else
  2195. /* Rx interrupt */
  2196. if (status & (RxOK | RxOverflow | RxFIFOOver)) {
  2197. rtl8169_rx_interrupt(dev, tp, ioaddr);
  2198. }
  2199. /* Tx interrupt */
  2200. if (status & (TxOK | TxErr))
  2201. rtl8169_tx_interrupt(dev, tp, ioaddr);
  2202. #endif
  2203. boguscnt--;
  2204. } while (boguscnt > 0);
  2205. if (boguscnt <= 0) {
  2206. if (netif_msg_intr(tp) && net_ratelimit() ) {
  2207. printk(KERN_WARNING
  2208. "%s: Too much work at interrupt!\n", dev->name);
  2209. }
  2210. /* Clear all interrupt sources. */
  2211. RTL_W16(IntrStatus, 0xffff);
  2212. }
  2213. out:
  2214. return IRQ_RETVAL(handled);
  2215. }
  2216. #ifdef CONFIG_R8169_NAPI
  2217. static int rtl8169_poll(struct net_device *dev, int *budget)
  2218. {
  2219. unsigned int work_done, work_to_do = min(*budget, dev->quota);
  2220. struct rtl8169_private *tp = netdev_priv(dev);
  2221. void __iomem *ioaddr = tp->mmio_addr;
  2222. work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
  2223. rtl8169_tx_interrupt(dev, tp, ioaddr);
  2224. *budget -= work_done;
  2225. dev->quota -= work_done;
  2226. if (work_done < work_to_do) {
  2227. netif_rx_complete(dev);
  2228. tp->intr_mask = 0xffff;
  2229. /*
  2230. * 20040426: the barrier is not strictly required but the
  2231. * behavior of the irq handler could be less predictable
  2232. * without it. Btw, the lack of flush for the posted pci
  2233. * write is safe - FR
  2234. */
  2235. smp_wmb();
  2236. RTL_W16(IntrMask, rtl8169_intr_mask);
  2237. }
  2238. return (work_done >= work_to_do);
  2239. }
  2240. #endif
  2241. static void rtl8169_down(struct net_device *dev)
  2242. {
  2243. struct rtl8169_private *tp = netdev_priv(dev);
  2244. void __iomem *ioaddr = tp->mmio_addr;
  2245. unsigned int poll_locked = 0;
  2246. unsigned int intrmask;
  2247. rtl8169_delete_timer(dev);
  2248. netif_stop_queue(dev);
  2249. core_down:
  2250. spin_lock_irq(&tp->lock);
  2251. rtl8169_asic_down(ioaddr);
  2252. /* Update the error counts. */
  2253. tp->stats.rx_missed_errors += RTL_R32(RxMissed);
  2254. RTL_W32(RxMissed, 0);
  2255. spin_unlock_irq(&tp->lock);
  2256. synchronize_irq(dev->irq);
  2257. if (!poll_locked) {
  2258. netif_poll_disable(dev);
  2259. poll_locked++;
  2260. }
  2261. /* Give a racing hard_start_xmit a few cycles to complete. */
  2262. synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
  2263. /*
  2264. * And now for the 50k$ question: are IRQ disabled or not ?
  2265. *
  2266. * Two paths lead here:
  2267. * 1) dev->close
  2268. * -> netif_running() is available to sync the current code and the
  2269. * IRQ handler. See rtl8169_interrupt for details.
  2270. * 2) dev->change_mtu
  2271. * -> rtl8169_poll can not be issued again and re-enable the
  2272. * interruptions. Let's simply issue the IRQ down sequence again.
  2273. *
  2274. * No loop if hotpluged or major error (0xffff).
  2275. */
  2276. intrmask = RTL_R16(IntrMask);
  2277. if (intrmask && (intrmask != 0xffff))
  2278. goto core_down;
  2279. rtl8169_tx_clear(tp);
  2280. rtl8169_rx_clear(tp);
  2281. }
  2282. static int rtl8169_close(struct net_device *dev)
  2283. {
  2284. struct rtl8169_private *tp = netdev_priv(dev);
  2285. struct pci_dev *pdev = tp->pci_dev;
  2286. rtl8169_down(dev);
  2287. free_irq(dev->irq, dev);
  2288. netif_poll_enable(dev);
  2289. pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
  2290. tp->RxPhyAddr);
  2291. pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
  2292. tp->TxPhyAddr);
  2293. tp->TxDescArray = NULL;
  2294. tp->RxDescArray = NULL;
  2295. return 0;
  2296. }
  2297. static void
  2298. rtl8169_set_rx_mode(struct net_device *dev)
  2299. {
  2300. struct rtl8169_private *tp = netdev_priv(dev);
  2301. void __iomem *ioaddr = tp->mmio_addr;
  2302. unsigned long flags;
  2303. u32 mc_filter[2]; /* Multicast hash filter */
  2304. int i, rx_mode;
  2305. u32 tmp = 0;
  2306. if (dev->flags & IFF_PROMISC) {
  2307. /* Unconditionally log net taps. */
  2308. if (netif_msg_link(tp)) {
  2309. printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
  2310. dev->name);
  2311. }
  2312. rx_mode =
  2313. AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
  2314. AcceptAllPhys;
  2315. mc_filter[1] = mc_filter[0] = 0xffffffff;
  2316. } else if ((dev->mc_count > multicast_filter_limit)
  2317. || (dev->flags & IFF_ALLMULTI)) {
  2318. /* Too many to filter perfectly -- accept all multicasts. */
  2319. rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  2320. mc_filter[1] = mc_filter[0] = 0xffffffff;
  2321. } else {
  2322. struct dev_mc_list *mclist;
  2323. rx_mode = AcceptBroadcast | AcceptMyPhys;
  2324. mc_filter[1] = mc_filter[0] = 0;
  2325. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  2326. i++, mclist = mclist->next) {
  2327. int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
  2328. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  2329. rx_mode |= AcceptMulticast;
  2330. }
  2331. }
  2332. spin_lock_irqsave(&tp->lock, flags);
  2333. tmp = rtl8169_rx_config | rx_mode |
  2334. (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
  2335. if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
  2336. (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
  2337. (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
  2338. (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
  2339. (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
  2340. mc_filter[0] = 0xffffffff;
  2341. mc_filter[1] = 0xffffffff;
  2342. }
  2343. RTL_W32(RxConfig, tmp);
  2344. RTL_W32(MAR0 + 0, mc_filter[0]);
  2345. RTL_W32(MAR0 + 4, mc_filter[1]);
  2346. spin_unlock_irqrestore(&tp->lock, flags);
  2347. }
  2348. /**
  2349. * rtl8169_get_stats - Get rtl8169 read/write statistics
  2350. * @dev: The Ethernet Device to get statistics for
  2351. *
  2352. * Get TX/RX statistics for rtl8169
  2353. */
  2354. static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
  2355. {
  2356. struct rtl8169_private *tp = netdev_priv(dev);
  2357. void __iomem *ioaddr = tp->mmio_addr;
  2358. unsigned long flags;
  2359. if (netif_running(dev)) {
  2360. spin_lock_irqsave(&tp->lock, flags);
  2361. tp->stats.rx_missed_errors += RTL_R32(RxMissed);
  2362. RTL_W32(RxMissed, 0);
  2363. spin_unlock_irqrestore(&tp->lock, flags);
  2364. }
  2365. return &tp->stats;
  2366. }
  2367. #ifdef CONFIG_PM
  2368. static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
  2369. {
  2370. struct net_device *dev = pci_get_drvdata(pdev);
  2371. struct rtl8169_private *tp = netdev_priv(dev);
  2372. void __iomem *ioaddr = tp->mmio_addr;
  2373. if (!netif_running(dev))
  2374. goto out_pci_suspend;
  2375. netif_device_detach(dev);
  2376. netif_stop_queue(dev);
  2377. spin_lock_irq(&tp->lock);
  2378. rtl8169_asic_down(ioaddr);
  2379. tp->stats.rx_missed_errors += RTL_R32(RxMissed);
  2380. RTL_W32(RxMissed, 0);
  2381. spin_unlock_irq(&tp->lock);
  2382. out_pci_suspend:
  2383. pci_save_state(pdev);
  2384. pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
  2385. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2386. return 0;
  2387. }
  2388. static int rtl8169_resume(struct pci_dev *pdev)
  2389. {
  2390. struct net_device *dev = pci_get_drvdata(pdev);
  2391. pci_set_power_state(pdev, PCI_D0);
  2392. pci_restore_state(pdev);
  2393. pci_enable_wake(pdev, PCI_D0, 0);
  2394. if (!netif_running(dev))
  2395. goto out;
  2396. netif_device_attach(dev);
  2397. rtl8169_schedule_work(dev, rtl8169_reset_task);
  2398. out:
  2399. return 0;
  2400. }
  2401. #endif /* CONFIG_PM */
  2402. static struct pci_driver rtl8169_pci_driver = {
  2403. .name = MODULENAME,
  2404. .id_table = rtl8169_pci_tbl,
  2405. .probe = rtl8169_init_one,
  2406. .remove = __devexit_p(rtl8169_remove_one),
  2407. #ifdef CONFIG_PM
  2408. .suspend = rtl8169_suspend,
  2409. .resume = rtl8169_resume,
  2410. #endif
  2411. };
  2412. static int __init
  2413. rtl8169_init_module(void)
  2414. {
  2415. return pci_register_driver(&rtl8169_pci_driver);
  2416. }
  2417. static void __exit
  2418. rtl8169_cleanup_module(void)
  2419. {
  2420. pci_unregister_driver(&rtl8169_pci_driver);
  2421. }
  2422. module_init(rtl8169_init_module);
  2423. module_exit(rtl8169_cleanup_module);