qla3xxx.h 32 KB

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  1. /*
  2. * QLogic QLA3xxx NIC HBA Driver
  3. * Copyright (c) 2003-2006 QLogic Corporation
  4. *
  5. * See LICENSE.qla3xxx for copyright and licensing details.
  6. */
  7. #ifndef _QLA3XXX_H_
  8. #define _QLA3XXX_H_
  9. /*
  10. * IOCB Definitions...
  11. */
  12. #pragma pack(1)
  13. #define OPCODE_OB_MAC_IOCB_FN0 0x01
  14. #define OPCODE_OB_MAC_IOCB_FN2 0x21
  15. #define OPCODE_OB_TCP_IOCB_FN0 0x03
  16. #define OPCODE_OB_TCP_IOCB_FN2 0x23
  17. #define OPCODE_UPDATE_NCB_IOCB_FN0 0x00
  18. #define OPCODE_UPDATE_NCB_IOCB_FN2 0x20
  19. #define OPCODE_UPDATE_NCB_IOCB 0xF0
  20. #define OPCODE_IB_MAC_IOCB 0xF9
  21. #define OPCODE_IB_3032_MAC_IOCB 0x09
  22. #define OPCODE_IB_IP_IOCB 0xFA
  23. #define OPCODE_IB_3032_IP_IOCB 0x0A
  24. #define OPCODE_IB_TCP_IOCB 0xFB
  25. #define OPCODE_DUMP_PROTO_IOCB 0xFE
  26. #define OPCODE_BUFFER_ALERT_IOCB 0xFB
  27. #define OPCODE_FUNC_ID_MASK 0x30
  28. #define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */
  29. #define OUTBOUND_TCP_IOCB 0x03 /* plus function bits */
  30. #define UPDATE_NCB_IOCB 0x00 /* plus function bits */
  31. #define FN0_MA_BITS_MASK 0x00
  32. #define FN1_MA_BITS_MASK 0x80
  33. struct ob_mac_iocb_req {
  34. u8 opcode;
  35. u8 flags;
  36. #define OB_MAC_IOCB_REQ_MA 0xe0
  37. #define OB_MAC_IOCB_REQ_F 0x10
  38. #define OB_MAC_IOCB_REQ_X 0x08
  39. #define OB_MAC_IOCB_REQ_D 0x02
  40. #define OB_MAC_IOCB_REQ_I 0x01
  41. u8 flags1;
  42. #define OB_3032MAC_IOCB_REQ_IC 0x04
  43. #define OB_3032MAC_IOCB_REQ_TC 0x02
  44. #define OB_3032MAC_IOCB_REQ_UC 0x01
  45. u8 reserved0;
  46. __le32 transaction_id;
  47. __le16 data_len;
  48. u8 ip_hdr_off;
  49. u8 ip_hdr_len;
  50. __le32 reserved1;
  51. __le32 reserved2;
  52. __le32 buf_addr0_low;
  53. __le32 buf_addr0_high;
  54. __le32 buf_0_len;
  55. __le32 buf_addr1_low;
  56. __le32 buf_addr1_high;
  57. __le32 buf_1_len;
  58. __le32 buf_addr2_low;
  59. __le32 buf_addr2_high;
  60. __le32 buf_2_len;
  61. __le32 reserved3;
  62. __le32 reserved4;
  63. };
  64. /*
  65. * The following constants define control bits for buffer
  66. * length fields for all IOCB's.
  67. */
  68. #define OB_MAC_IOCB_REQ_E 0x80000000 /* Last valid buffer in list. */
  69. #define OB_MAC_IOCB_REQ_C 0x40000000 /* points to an OAL. (continuation) */
  70. #define OB_MAC_IOCB_REQ_L 0x20000000 /* Auburn local address pointer. */
  71. #define OB_MAC_IOCB_REQ_R 0x10000000 /* 32-bit address pointer. */
  72. struct ob_mac_iocb_rsp {
  73. u8 opcode;
  74. u8 flags;
  75. #define OB_MAC_IOCB_RSP_P 0x08
  76. #define OB_MAC_IOCB_RSP_L 0x04
  77. #define OB_MAC_IOCB_RSP_S 0x02
  78. #define OB_MAC_IOCB_RSP_I 0x01
  79. __le16 reserved0;
  80. __le32 transaction_id;
  81. __le32 reserved1;
  82. __le32 reserved2;
  83. };
  84. struct ib_mac_iocb_rsp {
  85. u8 opcode;
  86. #define IB_MAC_IOCB_RSP_V 0x80
  87. u8 flags;
  88. #define IB_MAC_IOCB_RSP_S 0x80
  89. #define IB_MAC_IOCB_RSP_H1 0x40
  90. #define IB_MAC_IOCB_RSP_H0 0x20
  91. #define IB_MAC_IOCB_RSP_B 0x10
  92. #define IB_MAC_IOCB_RSP_M 0x08
  93. #define IB_MAC_IOCB_RSP_MA 0x07
  94. __le16 length;
  95. __le32 reserved;
  96. __le32 ial_low;
  97. __le32 ial_high;
  98. };
  99. struct ob_ip_iocb_req {
  100. u8 opcode;
  101. __le16 flags;
  102. #define OB_IP_IOCB_REQ_O 0x100
  103. #define OB_IP_IOCB_REQ_H 0x008
  104. #define OB_IP_IOCB_REQ_U 0x004
  105. #define OB_IP_IOCB_REQ_D 0x002
  106. #define OB_IP_IOCB_REQ_I 0x001
  107. u8 reserved0;
  108. __le32 transaction_id;
  109. __le16 data_len;
  110. __le16 reserved1;
  111. __le32 hncb_ptr_low;
  112. __le32 hncb_ptr_high;
  113. __le32 buf_addr0_low;
  114. __le32 buf_addr0_high;
  115. __le32 buf_0_len;
  116. __le32 buf_addr1_low;
  117. __le32 buf_addr1_high;
  118. __le32 buf_1_len;
  119. __le32 buf_addr2_low;
  120. __le32 buf_addr2_high;
  121. __le32 buf_2_len;
  122. __le32 reserved2;
  123. __le32 reserved3;
  124. };
  125. /* defines for BufferLength fields above */
  126. #define OB_IP_IOCB_REQ_E 0x80000000
  127. #define OB_IP_IOCB_REQ_C 0x40000000
  128. #define OB_IP_IOCB_REQ_L 0x20000000
  129. #define OB_IP_IOCB_REQ_R 0x10000000
  130. struct ob_ip_iocb_rsp {
  131. u8 opcode;
  132. u8 flags;
  133. #define OB_MAC_IOCB_RSP_H 0x10
  134. #define OB_MAC_IOCB_RSP_E 0x08
  135. #define OB_MAC_IOCB_RSP_L 0x04
  136. #define OB_MAC_IOCB_RSP_S 0x02
  137. #define OB_MAC_IOCB_RSP_I 0x01
  138. __le16 reserved0;
  139. __le32 transaction_id;
  140. __le32 reserved1;
  141. __le32 reserved2;
  142. };
  143. struct ob_tcp_iocb_req {
  144. u8 opcode;
  145. u8 flags0;
  146. #define OB_TCP_IOCB_REQ_P 0x80
  147. #define OB_TCP_IOCB_REQ_CI 0x20
  148. #define OB_TCP_IOCB_REQ_H 0x10
  149. #define OB_TCP_IOCB_REQ_LN 0x08
  150. #define OB_TCP_IOCB_REQ_K 0x04
  151. #define OB_TCP_IOCB_REQ_D 0x02
  152. #define OB_TCP_IOCB_REQ_I 0x01
  153. u8 flags1;
  154. #define OB_TCP_IOCB_REQ_OSM 0x40
  155. #define OB_TCP_IOCB_REQ_URG 0x20
  156. #define OB_TCP_IOCB_REQ_ACK 0x10
  157. #define OB_TCP_IOCB_REQ_PSH 0x08
  158. #define OB_TCP_IOCB_REQ_RST 0x04
  159. #define OB_TCP_IOCB_REQ_SYN 0x02
  160. #define OB_TCP_IOCB_REQ_FIN 0x01
  161. u8 options_len;
  162. #define OB_TCP_IOCB_REQ_OMASK 0xF0
  163. #define OB_TCP_IOCB_REQ_SHIFT 4
  164. __le32 transaction_id;
  165. __le32 data_len;
  166. __le32 hncb_ptr_low;
  167. __le32 hncb_ptr_high;
  168. __le32 buf_addr0_low;
  169. __le32 buf_addr0_high;
  170. __le32 buf_0_len;
  171. __le32 buf_addr1_low;
  172. __le32 buf_addr1_high;
  173. __le32 buf_1_len;
  174. __le32 buf_addr2_low;
  175. __le32 buf_addr2_high;
  176. __le32 buf_2_len;
  177. __le32 time_stamp;
  178. __le32 reserved1;
  179. };
  180. struct ob_tcp_iocb_rsp {
  181. u8 opcode;
  182. u8 flags0;
  183. #define OB_TCP_IOCB_RSP_C 0x20
  184. #define OB_TCP_IOCB_RSP_H 0x10
  185. #define OB_TCP_IOCB_RSP_LN 0x08
  186. #define OB_TCP_IOCB_RSP_K 0x04
  187. #define OB_TCP_IOCB_RSP_D 0x02
  188. #define OB_TCP_IOCB_RSP_I 0x01
  189. u8 flags1;
  190. #define OB_TCP_IOCB_RSP_E 0x10
  191. #define OB_TCP_IOCB_RSP_W 0x08
  192. #define OB_TCP_IOCB_RSP_P 0x04
  193. #define OB_TCP_IOCB_RSP_T 0x02
  194. #define OB_TCP_IOCB_RSP_F 0x01
  195. u8 state;
  196. #define OB_TCP_IOCB_RSP_SMASK 0xF0
  197. #define OB_TCP_IOCB_RSP_SHIFT 4
  198. __le32 transaction_id;
  199. __le32 local_ncb_ptr;
  200. __le32 reserved0;
  201. };
  202. struct ib_ip_iocb_rsp {
  203. u8 opcode;
  204. #define IB_IP_IOCB_RSP_3032_V 0x80
  205. #define IB_IP_IOCB_RSP_3032_O 0x40
  206. #define IB_IP_IOCB_RSP_3032_I 0x20
  207. #define IB_IP_IOCB_RSP_3032_R 0x10
  208. u8 flags;
  209. #define IB_IP_IOCB_RSP_S 0x80
  210. #define IB_IP_IOCB_RSP_H1 0x40
  211. #define IB_IP_IOCB_RSP_H0 0x20
  212. #define IB_IP_IOCB_RSP_B 0x10
  213. #define IB_IP_IOCB_RSP_M 0x08
  214. #define IB_IP_IOCB_RSP_MA 0x07
  215. __le16 length;
  216. __le16 checksum;
  217. #define IB_IP_IOCB_RSP_3032_ICE 0x01
  218. #define IB_IP_IOCB_RSP_3032_CE 0x02
  219. #define IB_IP_IOCB_RSP_3032_NUC 0x04
  220. #define IB_IP_IOCB_RSP_3032_UDP 0x08
  221. #define IB_IP_IOCB_RSP_3032_TCP 0x10
  222. #define IB_IP_IOCB_RSP_3032_IPE 0x20
  223. __le16 reserved;
  224. #define IB_IP_IOCB_RSP_R 0x01
  225. __le32 ial_low;
  226. __le32 ial_high;
  227. };
  228. struct ib_tcp_iocb_rsp {
  229. u8 opcode;
  230. u8 flags;
  231. #define IB_TCP_IOCB_RSP_P 0x80
  232. #define IB_TCP_IOCB_RSP_T 0x40
  233. #define IB_TCP_IOCB_RSP_D 0x20
  234. #define IB_TCP_IOCB_RSP_N 0x10
  235. #define IB_TCP_IOCB_RSP_IP 0x03
  236. #define IB_TCP_FLAG_MASK 0xf0
  237. #define IB_TCP_FLAG_IOCB_SYN 0x00
  238. #define TCP_IB_RSP_FLAGS(x) (x->flags & ~IB_TCP_FLAG_MASK)
  239. __le16 length;
  240. __le32 hncb_ref_num;
  241. __le32 ial_low;
  242. __le32 ial_high;
  243. };
  244. struct net_rsp_iocb {
  245. u8 opcode;
  246. u8 flags;
  247. __le16 reserved0;
  248. __le32 reserved[3];
  249. };
  250. #pragma pack()
  251. /*
  252. * Register Definitions...
  253. */
  254. #define PORT0_PHY_ADDRESS 0x1e00
  255. #define PORT1_PHY_ADDRESS 0x1f00
  256. #define ETHERNET_CRC_SIZE 4
  257. #define MII_SCAN_REGISTER 0x00000001
  258. /* 32-bit ispControlStatus */
  259. enum {
  260. ISP_CONTROL_NP_MASK = 0x0003,
  261. ISP_CONTROL_NP_PCSR = 0x0000,
  262. ISP_CONTROL_NP_HMCR = 0x0001,
  263. ISP_CONTROL_NP_LRAMCR = 0x0002,
  264. ISP_CONTROL_NP_PSR = 0x0003,
  265. ISP_CONTROL_RI = 0x0008,
  266. ISP_CONTROL_CI = 0x0010,
  267. ISP_CONTROL_PI = 0x0020,
  268. ISP_CONTROL_IN = 0x0040,
  269. ISP_CONTROL_BE = 0x0080,
  270. ISP_CONTROL_FN_MASK = 0x0700,
  271. ISP_CONTROL_FN0_NET = 0x0400,
  272. ISP_CONTROL_FN0_SCSI = 0x0500,
  273. ISP_CONTROL_FN1_NET = 0x0600,
  274. ISP_CONTROL_FN1_SCSI = 0x0700,
  275. ISP_CONTROL_LINK_DN_0 = 0x0800,
  276. ISP_CONTROL_LINK_DN_1 = 0x1000,
  277. ISP_CONTROL_FSR = 0x2000,
  278. ISP_CONTROL_FE = 0x4000,
  279. ISP_CONTROL_SR = 0x8000,
  280. };
  281. /* 32-bit ispInterruptMaskReg */
  282. enum {
  283. ISP_IMR_ENABLE_INT = 0x0004,
  284. ISP_IMR_DISABLE_RESET_INT = 0x0008,
  285. ISP_IMR_DISABLE_CMPL_INT = 0x0010,
  286. ISP_IMR_DISABLE_PROC_INT = 0x0020,
  287. };
  288. /* 32-bit serialPortInterfaceReg */
  289. enum {
  290. ISP_SERIAL_PORT_IF_CLK = 0x0001,
  291. ISP_SERIAL_PORT_IF_CS = 0x0002,
  292. ISP_SERIAL_PORT_IF_D0 = 0x0004,
  293. ISP_SERIAL_PORT_IF_DI = 0x0008,
  294. ISP_NVRAM_MASK = (0x000F << 16),
  295. ISP_SERIAL_PORT_IF_WE = 0x0010,
  296. ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
  297. ISP_SERIAL_PORT_IF_SCI = 0x0400,
  298. ISP_SERIAL_PORT_IF_SC0 = 0x0800,
  299. ISP_SERIAL_PORT_IF_SCE = 0x1000,
  300. ISP_SERIAL_PORT_IF_SDI = 0x2000,
  301. ISP_SERIAL_PORT_IF_SDO = 0x4000,
  302. ISP_SERIAL_PORT_IF_SDE = 0x8000,
  303. ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,
  304. };
  305. /* semaphoreReg */
  306. enum {
  307. QL_RESOURCE_MASK_BASE_CODE = 0x7,
  308. QL_RESOURCE_BITS_BASE_CODE = 0x4,
  309. QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),
  310. QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
  311. QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),
  312. QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),
  313. QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),
  314. QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
  315. QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),
  316. QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),
  317. QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),
  318. QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)),
  319. };
  320. /*
  321. * QL3XXX memory-mapped registers
  322. * QL3XXX has 4 "pages" of registers, each page occupying
  323. * 256 bytes. Each page has a "common" area at the start and then
  324. * page-specific registers after that.
  325. */
  326. struct ql3xxx_common_registers {
  327. u32 MB0; /* Offset 0x00 */
  328. u32 MB1; /* Offset 0x04 */
  329. u32 MB2; /* Offset 0x08 */
  330. u32 MB3; /* Offset 0x0c */
  331. u32 MB4; /* Offset 0x10 */
  332. u32 MB5; /* Offset 0x14 */
  333. u32 MB6; /* Offset 0x18 */
  334. u32 MB7; /* Offset 0x1c */
  335. u32 flashBiosAddr;
  336. u32 flashBiosData;
  337. u32 ispControlStatus;
  338. u32 ispInterruptMaskReg;
  339. u32 serialPortInterfaceReg;
  340. u32 semaphoreReg;
  341. u32 reqQProducerIndex;
  342. u32 rspQConsumerIndex;
  343. u32 rxLargeQProducerIndex;
  344. u32 rxSmallQProducerIndex;
  345. u32 arcMadiCommand;
  346. u32 arcMadiData;
  347. };
  348. enum {
  349. EXT_HW_CONFIG_SP_MASK = 0x0006,
  350. EXT_HW_CONFIG_SP_NONE = 0x0000,
  351. EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
  352. EXT_HW_CONFIG_SP_ECC = 0x0004,
  353. EXT_HW_CONFIG_SP_ECCx = 0x0006,
  354. EXT_HW_CONFIG_SIZE_MASK = 0x0060,
  355. EXT_HW_CONFIG_SIZE_128M = 0x0000,
  356. EXT_HW_CONFIG_SIZE_256M = 0x0020,
  357. EXT_HW_CONFIG_SIZE_512M = 0x0040,
  358. EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
  359. EXT_HW_CONFIG_PD = 0x0080,
  360. EXT_HW_CONFIG_FW = 0x0200,
  361. EXT_HW_CONFIG_US = 0x0400,
  362. EXT_HW_CONFIG_DCS_MASK = 0x1800,
  363. EXT_HW_CONFIG_DCS_9MA = 0x0000,
  364. EXT_HW_CONFIG_DCS_15MA = 0x0800,
  365. EXT_HW_CONFIG_DCS_18MA = 0x1000,
  366. EXT_HW_CONFIG_DCS_24MA = 0x1800,
  367. EXT_HW_CONFIG_DDS_MASK = 0x6000,
  368. EXT_HW_CONFIG_DDS_9MA = 0x0000,
  369. EXT_HW_CONFIG_DDS_15MA = 0x2000,
  370. EXT_HW_CONFIG_DDS_18MA = 0x4000,
  371. EXT_HW_CONFIG_DDS_24MA = 0x6000,
  372. };
  373. /* InternalChipConfig */
  374. enum {
  375. INTERNAL_CHIP_DM = 0x0001,
  376. INTERNAL_CHIP_SD = 0x0002,
  377. INTERNAL_CHIP_RAP_MASK = 0x000C,
  378. INTERNAL_CHIP_RAP_RR = 0x0000,
  379. INTERNAL_CHIP_RAP_NRM = 0x0004,
  380. INTERNAL_CHIP_RAP_ERM = 0x0008,
  381. INTERNAL_CHIP_RAP_ERMx = 0x000C,
  382. INTERNAL_CHIP_WE = 0x0010,
  383. INTERNAL_CHIP_EF = 0x0020,
  384. INTERNAL_CHIP_FR = 0x0040,
  385. INTERNAL_CHIP_FW = 0x0080,
  386. INTERNAL_CHIP_FI = 0x0100,
  387. INTERNAL_CHIP_FT = 0x0200,
  388. };
  389. /* portControl */
  390. enum {
  391. PORT_CONTROL_DS = 0x0001,
  392. PORT_CONTROL_HH = 0x0002,
  393. PORT_CONTROL_EI = 0x0004,
  394. PORT_CONTROL_ET = 0x0008,
  395. PORT_CONTROL_EF = 0x0010,
  396. PORT_CONTROL_DRM = 0x0020,
  397. PORT_CONTROL_RLB = 0x0040,
  398. PORT_CONTROL_RCB = 0x0080,
  399. PORT_CONTROL_MAC = 0x0100,
  400. PORT_CONTROL_IPV = 0x0200,
  401. PORT_CONTROL_IFP = 0x0400,
  402. PORT_CONTROL_ITP = 0x0800,
  403. PORT_CONTROL_FI = 0x1000,
  404. PORT_CONTROL_DFP = 0x2000,
  405. PORT_CONTROL_OI = 0x4000,
  406. PORT_CONTROL_CC = 0x8000,
  407. };
  408. /* portStatus */
  409. enum {
  410. PORT_STATUS_SM0 = 0x0001,
  411. PORT_STATUS_SM1 = 0x0002,
  412. PORT_STATUS_X = 0x0008,
  413. PORT_STATUS_DL = 0x0080,
  414. PORT_STATUS_IC = 0x0200,
  415. PORT_STATUS_MRC = 0x0400,
  416. PORT_STATUS_NL = 0x0800,
  417. PORT_STATUS_REV_ID_MASK = 0x7000,
  418. PORT_STATUS_REV_ID_1 = 0x1000,
  419. PORT_STATUS_REV_ID_2 = 0x2000,
  420. PORT_STATUS_REV_ID_3 = 0x3000,
  421. PORT_STATUS_64 = 0x8000,
  422. PORT_STATUS_UP0 = 0x10000,
  423. PORT_STATUS_AC0 = 0x20000,
  424. PORT_STATUS_AE0 = 0x40000,
  425. PORT_STATUS_UP1 = 0x100000,
  426. PORT_STATUS_AC1 = 0x200000,
  427. PORT_STATUS_AE1 = 0x400000,
  428. PORT_STATUS_F0_ENABLED = 0x1000000,
  429. PORT_STATUS_F1_ENABLED = 0x2000000,
  430. PORT_STATUS_F2_ENABLED = 0x4000000,
  431. PORT_STATUS_F3_ENABLED = 0x8000000,
  432. };
  433. /* macMIIMgmtControlReg */
  434. enum {
  435. MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
  436. MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
  437. MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
  438. MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
  439. MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
  440. MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
  441. MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
  442. MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
  443. MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
  444. MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,
  445. };
  446. /* macMIIMgmtControlReg */
  447. enum {
  448. MAC_MII_CONTROL_RC = 0x0001,
  449. MAC_MII_CONTROL_SC = 0x0002,
  450. MAC_MII_CONTROL_AS = 0x0004,
  451. MAC_MII_CONTROL_NP = 0x0008,
  452. MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
  453. MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
  454. MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
  455. MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
  456. MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
  457. MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
  458. MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
  459. MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
  460. MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
  461. MAC_MII_CONTROL_RM = 0x8000,
  462. };
  463. /* macMIIStatusReg */
  464. enum {
  465. MAC_MII_STATUS_BSY = 0x0001,
  466. MAC_MII_STATUS_SC = 0x0002,
  467. MAC_MII_STATUS_NV = 0x0004,
  468. };
  469. enum {
  470. MAC_CONFIG_REG_PE = 0x0001,
  471. MAC_CONFIG_REG_TF = 0x0002,
  472. MAC_CONFIG_REG_RF = 0x0004,
  473. MAC_CONFIG_REG_FD = 0x0008,
  474. MAC_CONFIG_REG_GM = 0x0010,
  475. MAC_CONFIG_REG_LB = 0x0020,
  476. MAC_CONFIG_REG_SR = 0x8000,
  477. };
  478. enum {
  479. MAC_HALF_DUPLEX_REG_ED = 0x10000,
  480. MAC_HALF_DUPLEX_REG_NB = 0x20000,
  481. MAC_HALF_DUPLEX_REG_BNB = 0x40000,
  482. MAC_HALF_DUPLEX_REG_ALT = 0x80000,
  483. };
  484. enum {
  485. IP_ADDR_INDEX_REG_MASK = 0x000f,
  486. IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
  487. IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
  488. IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
  489. IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
  490. IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
  491. IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
  492. IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
  493. IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
  494. IP_ADDR_INDEX_REG_6 = 0x0008,
  495. IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
  496. IP_ADDR_INDEX_REG_E = 0x0040,
  497. };
  498. enum {
  499. QL3032_PORT_CONTROL_DS = 0x0001,
  500. QL3032_PORT_CONTROL_HH = 0x0002,
  501. QL3032_PORT_CONTROL_EIv6 = 0x0004,
  502. QL3032_PORT_CONTROL_EIv4 = 0x0008,
  503. QL3032_PORT_CONTROL_ET = 0x0010,
  504. QL3032_PORT_CONTROL_EF = 0x0020,
  505. QL3032_PORT_CONTROL_DRM = 0x0040,
  506. QL3032_PORT_CONTROL_RLB = 0x0080,
  507. QL3032_PORT_CONTROL_RCB = 0x0100,
  508. QL3032_PORT_CONTROL_KIE = 0x0200,
  509. };
  510. enum {
  511. PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
  512. PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
  513. PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
  514. PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
  515. PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
  516. PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
  517. PROBE_MUX_ADDR_REG_UP = 0x4000,
  518. PROBE_MUX_ADDR_REG_RE = 0x8000,
  519. };
  520. enum {
  521. STATISTICS_INDEX_REG_MASK = 0x01ff,
  522. STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
  523. STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
  524. STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
  525. STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
  526. STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
  527. STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
  528. STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
  529. STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
  530. STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
  531. STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
  532. STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
  533. STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
  534. STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
  535. STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
  536. STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
  537. STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
  538. STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
  539. STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
  540. STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
  541. STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
  542. STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
  543. STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
  544. STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
  545. STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
  546. STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
  547. STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
  548. STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
  549. STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
  550. STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
  551. STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
  552. STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
  553. STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
  554. STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
  555. STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
  556. STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
  557. STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
  558. STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
  559. STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
  560. STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
  561. STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
  562. STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
  563. STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
  564. STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
  565. STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
  566. STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
  567. STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
  568. STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
  569. STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
  570. STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
  571. STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
  572. STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
  573. STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,
  574. };
  575. enum {
  576. PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
  577. PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
  578. PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
  579. PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
  580. PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
  581. PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
  582. PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
  583. PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
  584. PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
  585. PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
  586. PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
  587. PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
  588. PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
  589. PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
  590. PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
  591. PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
  592. PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
  593. PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
  594. PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
  595. PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
  596. PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
  597. PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
  598. PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
  599. PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
  600. PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,
  601. };
  602. /*
  603. * port control and status page - page 0
  604. */
  605. struct ql3xxx_port_registers {
  606. struct ql3xxx_common_registers CommonRegs;
  607. u32 ExternalHWConfig;
  608. u32 InternalChipConfig;
  609. u32 portControl;
  610. u32 portStatus;
  611. u32 macAddrIndirectPtrReg;
  612. u32 macAddrDataReg;
  613. u32 macMIIMgmtControlReg;
  614. u32 macMIIMgmtAddrReg;
  615. u32 macMIIMgmtDataReg;
  616. u32 macMIIStatusReg;
  617. u32 mac0ConfigReg;
  618. u32 mac0IpgIfgReg;
  619. u32 mac0HalfDuplexReg;
  620. u32 mac0MaxFrameLengthReg;
  621. u32 mac0PauseThresholdReg;
  622. u32 mac1ConfigReg;
  623. u32 mac1IpgIfgReg;
  624. u32 mac1HalfDuplexReg;
  625. u32 mac1MaxFrameLengthReg;
  626. u32 mac1PauseThresholdReg;
  627. u32 ipAddrIndexReg;
  628. u32 ipAddrDataReg;
  629. u32 ipReassemblyTimeout;
  630. u32 tcpMaxWindow;
  631. u32 currentTcpTimestamp[2];
  632. u32 internalRamRWAddrReg;
  633. u32 internalRamWDataReg;
  634. u32 reclaimedBufferAddrRegLow;
  635. u32 reclaimedBufferAddrRegHigh;
  636. u32 tcpConfiguration;
  637. u32 functionControl;
  638. u32 fpgaRevID;
  639. u32 localRamAddr;
  640. u32 localRamDataAutoIncr;
  641. u32 localRamDataNonIncr;
  642. u32 gpOutput;
  643. u32 gpInput;
  644. u32 probeMuxAddr;
  645. u32 probeMuxData;
  646. u32 statisticsIndexReg;
  647. u32 statisticsReadDataRegAutoIncr;
  648. u32 statisticsReadDataRegNoIncr;
  649. u32 PortFatalErrStatus;
  650. };
  651. /*
  652. * port host memory config page - page 1
  653. */
  654. struct ql3xxx_host_memory_registers {
  655. struct ql3xxx_common_registers CommonRegs;
  656. u32 reserved[12];
  657. /* Network Request Queue */
  658. u32 reqConsumerIndex;
  659. u32 reqConsumerIndexAddrLow;
  660. u32 reqConsumerIndexAddrHigh;
  661. u32 reqBaseAddrLow;
  662. u32 reqBaseAddrHigh;
  663. u32 reqLength;
  664. /* Network Completion Queue */
  665. u32 rspProducerIndex;
  666. u32 rspProducerIndexAddrLow;
  667. u32 rspProducerIndexAddrHigh;
  668. u32 rspBaseAddrLow;
  669. u32 rspBaseAddrHigh;
  670. u32 rspLength;
  671. /* RX Large Buffer Queue */
  672. u32 rxLargeQConsumerIndex;
  673. u32 rxLargeQBaseAddrLow;
  674. u32 rxLargeQBaseAddrHigh;
  675. u32 rxLargeQLength;
  676. u32 rxLargeBufferLength;
  677. /* RX Small Buffer Queue */
  678. u32 rxSmallQConsumerIndex;
  679. u32 rxSmallQBaseAddrLow;
  680. u32 rxSmallQBaseAddrHigh;
  681. u32 rxSmallQLength;
  682. u32 rxSmallBufferLength;
  683. };
  684. /*
  685. * port local RAM page - page 2
  686. */
  687. struct ql3xxx_local_ram_registers {
  688. struct ql3xxx_common_registers CommonRegs;
  689. u32 bufletSize;
  690. u32 maxBufletCount;
  691. u32 currentBufletCount;
  692. u32 reserved;
  693. u32 freeBufletThresholdLow;
  694. u32 freeBufletThresholdHigh;
  695. u32 ipHashTableBase;
  696. u32 ipHashTableCount;
  697. u32 tcpHashTableBase;
  698. u32 tcpHashTableCount;
  699. u32 ncbBase;
  700. u32 maxNcbCount;
  701. u32 currentNcbCount;
  702. u32 drbBase;
  703. u32 maxDrbCount;
  704. u32 currentDrbCount;
  705. };
  706. /*
  707. * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register
  708. */
  709. #define LS_64BITS(x) (u32)(0xffffffff & ((u64)x))
  710. #define MS_64BITS(x) (u32)(0xffffffff & (((u64)x)>>16>>16) )
  711. /*
  712. * I/O register
  713. */
  714. enum {
  715. CONTROL_REG = 0,
  716. STATUS_REG = 1,
  717. PHY_STAT_LINK_UP = 0x0004,
  718. PHY_CTRL_LOOPBACK = 0x4000,
  719. PETBI_CONTROL_REG = 0x00,
  720. PETBI_CTRL_SOFT_RESET = 0x8000,
  721. PETBI_CTRL_AUTO_NEG = 0x1000,
  722. PETBI_CTRL_RESTART_NEG = 0x0200,
  723. PETBI_CTRL_FULL_DUPLEX = 0x0100,
  724. PETBI_CTRL_SPEED_1000 = 0x0040,
  725. PETBI_STATUS_REG = 0x01,
  726. PETBI_STAT_NEG_DONE = 0x0020,
  727. PETBI_STAT_LINK_UP = 0x0004,
  728. PETBI_NEG_ADVER = 0x04,
  729. PETBI_NEG_PAUSE = 0x0080,
  730. PETBI_NEG_PAUSE_MASK = 0x0180,
  731. PETBI_NEG_DUPLEX = 0x0020,
  732. PETBI_NEG_DUPLEX_MASK = 0x0060,
  733. PETBI_NEG_PARTNER = 0x05,
  734. PETBI_NEG_ERROR_MASK = 0x3000,
  735. PETBI_EXPANSION_REG = 0x06,
  736. PETBI_EXP_PAGE_RX = 0x0002,
  737. PETBI_TBI_CTRL = 0x11,
  738. PETBI_TBI_RESET = 0x8000,
  739. PETBI_TBI_AUTO_SENSE = 0x0100,
  740. PETBI_TBI_SERDES_MODE = 0x0010,
  741. PETBI_TBI_SERDES_WRAP = 0x0002,
  742. AUX_CONTROL_STATUS = 0x1c,
  743. PHY_AUX_NEG_DONE = 0x8000,
  744. PHY_NEG_PARTNER = 5,
  745. PHY_AUX_DUPLEX_STAT = 0x0020,
  746. PHY_AUX_SPEED_STAT = 0x0018,
  747. PHY_AUX_NO_HW_STRAP = 0x0004,
  748. PHY_AUX_RESET_STICK = 0x0002,
  749. PHY_NEG_PAUSE = 0x0400,
  750. PHY_CTRL_SOFT_RESET = 0x8000,
  751. PHY_NEG_ADVER = 4,
  752. PHY_NEG_ADV_SPEED = 0x01e0,
  753. PHY_CTRL_RESTART_NEG = 0x0200,
  754. };
  755. enum {
  756. /* AM29LV Flash definitions */
  757. FM93C56A_START = 0x1,
  758. /* Commands */
  759. FM93C56A_READ = 0x2,
  760. FM93C56A_WEN = 0x0,
  761. FM93C56A_WRITE = 0x1,
  762. FM93C56A_WRITE_ALL = 0x0,
  763. FM93C56A_WDS = 0x0,
  764. FM93C56A_ERASE = 0x3,
  765. FM93C56A_ERASE_ALL = 0x0,
  766. /* Command Extentions */
  767. FM93C56A_WEN_EXT = 0x3,
  768. FM93C56A_WRITE_ALL_EXT = 0x1,
  769. FM93C56A_WDS_EXT = 0x0,
  770. FM93C56A_ERASE_ALL_EXT = 0x2,
  771. /* Special Bits */
  772. FM93C56A_READ_DUMMY_BITS = 1,
  773. FM93C56A_READY = 0,
  774. FM93C56A_BUSY = 1,
  775. FM93C56A_CMD_BITS = 2,
  776. /* AM29LV Flash definitions */
  777. FM93C56A_SIZE_8 = 0x100,
  778. FM93C56A_SIZE_16 = 0x80,
  779. FM93C66A_SIZE_8 = 0x200,
  780. FM93C66A_SIZE_16 = 0x100,
  781. FM93C86A_SIZE_16 = 0x400,
  782. /* Address Bits */
  783. FM93C56A_NO_ADDR_BITS_16 = 8,
  784. FM93C56A_NO_ADDR_BITS_8 = 9,
  785. FM93C86A_NO_ADDR_BITS_16 = 10,
  786. /* Data Bits */
  787. FM93C56A_DATA_BITS_16 = 16,
  788. FM93C56A_DATA_BITS_8 = 8,
  789. };
  790. enum {
  791. /* Auburn Bits */
  792. AUBURN_EEPROM_DI = 0x8,
  793. AUBURN_EEPROM_DI_0 = 0x0,
  794. AUBURN_EEPROM_DI_1 = 0x8,
  795. AUBURN_EEPROM_DO = 0x4,
  796. AUBURN_EEPROM_DO_0 = 0x0,
  797. AUBURN_EEPROM_DO_1 = 0x4,
  798. AUBURN_EEPROM_CS = 0x2,
  799. AUBURN_EEPROM_CS_0 = 0x0,
  800. AUBURN_EEPROM_CS_1 = 0x2,
  801. AUBURN_EEPROM_CLK_RISE = 0x1,
  802. AUBURN_EEPROM_CLK_FALL = 0x0,
  803. };
  804. enum {EEPROM_SIZE = FM93C86A_SIZE_16,
  805. EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16,
  806. EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16,
  807. };
  808. /*
  809. * MAC Config data structure
  810. */
  811. struct eeprom_port_cfg {
  812. u16 etherMtu_mac;
  813. u16 pauseThreshold_mac;
  814. u16 resumeThreshold_mac;
  815. u16 portConfiguration;
  816. #define PORT_CONFIG_AUTO_NEG_ENABLED 0x8000
  817. #define PORT_CONFIG_SYM_PAUSE_ENABLED 0x4000
  818. #define PORT_CONFIG_FULL_DUPLEX_ENABLED 0x2000
  819. #define PORT_CONFIG_HALF_DUPLEX_ENABLED 0x1000
  820. #define PORT_CONFIG_1000MB_SPEED 0x0400
  821. #define PORT_CONFIG_100MB_SPEED 0x0200
  822. #define PORT_CONFIG_10MB_SPEED 0x0100
  823. #define PORT_CONFIG_LINK_SPEED_MASK 0x0F00
  824. u16 reserved[12];
  825. };
  826. /*
  827. * BIOS data structure
  828. */
  829. struct eeprom_bios_cfg {
  830. u16 SpinDlyEn:1, disBios:1, EnMemMap:1, EnSelectBoot:1, Reserved:12;
  831. u8 bootID0:7, boodID0Valid:1;
  832. u8 bootLun0[8];
  833. u8 bootID1:7, boodID1Valid:1;
  834. u8 bootLun1[8];
  835. u16 MaxLunsTrgt;
  836. u8 reserved[10];
  837. };
  838. /*
  839. * Function Specific Data structure
  840. */
  841. struct eeprom_function_cfg {
  842. u8 reserved[30];
  843. u8 macAddress[6];
  844. u8 macAddressSecondary[6];
  845. u16 subsysVendorId;
  846. u16 subsysDeviceId;
  847. };
  848. /*
  849. * EEPROM format
  850. */
  851. struct eeprom_data {
  852. u8 asicId[4];
  853. u8 version;
  854. u8 numPorts;
  855. u16 boardId;
  856. #define EEPROM_BOARDID_STR_SIZE 16
  857. #define EEPROM_SERIAL_NUM_SIZE 16
  858. u8 boardIdStr[16];
  859. u8 serialNumber[16];
  860. u16 extHwConfig;
  861. struct eeprom_port_cfg macCfg_port0;
  862. struct eeprom_port_cfg macCfg_port1;
  863. u16 bufletSize;
  864. u16 bufletCount;
  865. u16 tcpWindowThreshold50;
  866. u16 tcpWindowThreshold25;
  867. u16 tcpWindowThreshold0;
  868. u16 ipHashTableBaseHi;
  869. u16 ipHashTableBaseLo;
  870. u16 ipHashTableSize;
  871. u16 tcpHashTableBaseHi;
  872. u16 tcpHashTableBaseLo;
  873. u16 tcpHashTableSize;
  874. u16 ncbTableBaseHi;
  875. u16 ncbTableBaseLo;
  876. u16 ncbTableSize;
  877. u16 drbTableBaseHi;
  878. u16 drbTableBaseLo;
  879. u16 drbTableSize;
  880. u16 reserved_142[4];
  881. u16 ipReassemblyTimeout;
  882. u16 tcpMaxWindowSize;
  883. u16 ipSecurity;
  884. #define IPSEC_CONFIG_PRESENT 0x0001
  885. u8 reserved_156[294];
  886. u16 qDebug[8];
  887. struct eeprom_function_cfg funcCfg_fn0;
  888. u16 reserved_510;
  889. u8 oemSpace[432];
  890. struct eeprom_bios_cfg biosCfg_fn1;
  891. struct eeprom_function_cfg funcCfg_fn1;
  892. u16 reserved_1022;
  893. u8 reserved_1024[464];
  894. struct eeprom_function_cfg funcCfg_fn2;
  895. u16 reserved_1534;
  896. u8 reserved_1536[432];
  897. struct eeprom_bios_cfg biosCfg_fn3;
  898. struct eeprom_function_cfg funcCfg_fn3;
  899. u16 checksum;
  900. };
  901. /*
  902. * General definitions...
  903. */
  904. /*
  905. * Below are a number compiler switches for controlling driver behavior.
  906. * Some are not supported under certain conditions and are notated as such.
  907. */
  908. #define QL3XXX_VENDOR_ID 0x1077
  909. #define QL3022_DEVICE_ID 0x3022
  910. #define QL3032_DEVICE_ID 0x3032
  911. /* MTU & Frame Size stuff */
  912. #define NORMAL_MTU_SIZE ETH_DATA_LEN
  913. #define JUMBO_MTU_SIZE 9000
  914. #define VLAN_ID_LEN 2
  915. /* Request Queue Related Definitions */
  916. #define NUM_REQ_Q_ENTRIES 256 /* so that 64 * 64 = 4096 (1 page) */
  917. /* Response Queue Related Definitions */
  918. #define NUM_RSP_Q_ENTRIES 256 /* so that 256 * 16 = 4096 (1 page) */
  919. /* Transmit and Receive Buffers */
  920. #define NUM_LBUFQ_ENTRIES 128
  921. #define JUMBO_NUM_LBUFQ_ENTRIES 32
  922. #define NUM_SBUFQ_ENTRIES 64
  923. #define QL_SMALL_BUFFER_SIZE 32
  924. #define QL_ADDR_ELE_PER_BUFQ_ENTRY \
  925. (sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
  926. /* Each send has at least control block. This is how many we keep. */
  927. #define NUM_SMALL_BUFFERS NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
  928. #define QL_HEADER_SPACE 32 /* make header space at top of skb. */
  929. /*
  930. * Large & Small Buffers for Receives
  931. */
  932. struct lrg_buf_q_entry {
  933. u32 addr0_lower;
  934. #define IAL_LAST_ENTRY 0x00000001
  935. #define IAL_CONT_ENTRY 0x00000002
  936. #define IAL_FLAG_MASK 0x00000003
  937. u32 addr0_upper;
  938. u32 addr1_lower;
  939. u32 addr1_upper;
  940. u32 addr2_lower;
  941. u32 addr2_upper;
  942. u32 addr3_lower;
  943. u32 addr3_upper;
  944. u32 addr4_lower;
  945. u32 addr4_upper;
  946. u32 addr5_lower;
  947. u32 addr5_upper;
  948. u32 addr6_lower;
  949. u32 addr6_upper;
  950. u32 addr7_lower;
  951. u32 addr7_upper;
  952. };
  953. struct bufq_addr_element {
  954. u32 addr_low;
  955. u32 addr_high;
  956. };
  957. #define QL_NO_RESET 0
  958. #define QL_DO_RESET 1
  959. enum link_state_t {
  960. LS_UNKNOWN = 0,
  961. LS_DOWN,
  962. LS_DEGRADE,
  963. LS_RECOVER,
  964. LS_UP,
  965. };
  966. struct ql_rcv_buf_cb {
  967. struct ql_rcv_buf_cb *next;
  968. struct sk_buff *skb;
  969. DECLARE_PCI_UNMAP_ADDR(mapaddr);
  970. DECLARE_PCI_UNMAP_LEN(maplen);
  971. __le32 buf_phy_addr_low;
  972. __le32 buf_phy_addr_high;
  973. int index;
  974. };
  975. /*
  976. * Original IOCB has 3 sg entries:
  977. * first points to skb-data area
  978. * second points to first frag
  979. * third points to next oal.
  980. * OAL has 5 entries:
  981. * 1 thru 4 point to frags
  982. * fifth points to next oal.
  983. */
  984. #define MAX_OAL_CNT ((MAX_SKB_FRAGS-1)/4 + 1)
  985. struct oal_entry {
  986. u32 dma_lo;
  987. u32 dma_hi;
  988. u32 len;
  989. #define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */
  990. #define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */
  991. };
  992. struct oal {
  993. struct oal_entry oal_entry[5];
  994. };
  995. struct map_list {
  996. DECLARE_PCI_UNMAP_ADDR(mapaddr);
  997. DECLARE_PCI_UNMAP_LEN(maplen);
  998. };
  999. struct ql_tx_buf_cb {
  1000. struct sk_buff *skb;
  1001. struct ob_mac_iocb_req *queue_entry ;
  1002. int seg_count;
  1003. struct oal *oal;
  1004. struct map_list map[MAX_SKB_FRAGS+1];
  1005. };
  1006. /* definitions for type field */
  1007. #define QL_BUF_TYPE_MACIOCB 0x01
  1008. #define QL_BUF_TYPE_IPIOCB 0x02
  1009. #define QL_BUF_TYPE_TCPIOCB 0x03
  1010. /* qdev->flags definitions. */
  1011. enum { QL_RESET_DONE = 1, /* Reset finished. */
  1012. QL_RESET_ACTIVE = 2, /* Waiting for reset to finish. */
  1013. QL_RESET_START = 3, /* Please reset the chip. */
  1014. QL_RESET_PER_SCSI = 4, /* SCSI driver requests reset. */
  1015. QL_TX_TIMEOUT = 5, /* Timeout in progress. */
  1016. QL_LINK_MASTER = 6, /* This driver controls the link. */
  1017. QL_ADAPTER_UP = 7, /* Adapter has been brought up. */
  1018. QL_THREAD_UP = 8, /* This flag is available. */
  1019. QL_LINK_UP = 9, /* Link Status. */
  1020. QL_ALLOC_REQ_RSP_Q_DONE = 10,
  1021. QL_ALLOC_BUFQS_DONE = 11,
  1022. QL_ALLOC_SMALL_BUF_DONE = 12,
  1023. QL_LINK_OPTICAL = 13,
  1024. QL_MSI_ENABLED = 14,
  1025. };
  1026. /*
  1027. * ql3_adapter - The main Adapter structure definition.
  1028. * This structure has all fields relevant to the hardware.
  1029. */
  1030. struct ql3_adapter {
  1031. u32 reserved_00;
  1032. unsigned long flags;
  1033. /* PCI Configuration information for this device */
  1034. struct pci_dev *pdev;
  1035. struct net_device *ndev; /* Parent NET device */
  1036. /* Hardware information */
  1037. u8 chip_rev_id;
  1038. u8 pci_slot;
  1039. u8 pci_width;
  1040. u8 pci_x;
  1041. u32 msi;
  1042. int index;
  1043. struct timer_list adapter_timer; /* timer used for various functions */
  1044. spinlock_t adapter_lock;
  1045. spinlock_t hw_lock;
  1046. /* PCI Bus Relative Register Addresses */
  1047. u8 __iomem *mmap_virt_base; /* stores return value from ioremap() */
  1048. struct ql3xxx_port_registers __iomem *mem_map_registers;
  1049. u32 current_page; /* tracks current register page */
  1050. u32 msg_enable;
  1051. u8 reserved_01[2];
  1052. u8 reserved_02[2];
  1053. /* Page for Shadow Registers */
  1054. void *shadow_reg_virt_addr;
  1055. dma_addr_t shadow_reg_phy_addr;
  1056. /* Net Request Queue */
  1057. u32 req_q_size;
  1058. u32 reserved_03;
  1059. struct ob_mac_iocb_req *req_q_virt_addr;
  1060. dma_addr_t req_q_phy_addr;
  1061. u16 req_producer_index;
  1062. u16 reserved_04;
  1063. u16 *preq_consumer_index;
  1064. u32 req_consumer_index_phy_addr_high;
  1065. u32 req_consumer_index_phy_addr_low;
  1066. atomic_t tx_count;
  1067. struct ql_tx_buf_cb tx_buf[NUM_REQ_Q_ENTRIES];
  1068. /* Net Response Queue */
  1069. u32 rsp_q_size;
  1070. u32 eeprom_cmd_data;
  1071. struct net_rsp_iocb *rsp_q_virt_addr;
  1072. dma_addr_t rsp_q_phy_addr;
  1073. struct net_rsp_iocb *rsp_current;
  1074. u16 rsp_consumer_index;
  1075. u16 reserved_06;
  1076. volatile u32 *prsp_producer_index;
  1077. u32 rsp_producer_index_phy_addr_high;
  1078. u32 rsp_producer_index_phy_addr_low;
  1079. /* Large Buffer Queue */
  1080. u32 lrg_buf_q_alloc_size;
  1081. u32 lrg_buf_q_size;
  1082. void *lrg_buf_q_alloc_virt_addr;
  1083. void *lrg_buf_q_virt_addr;
  1084. dma_addr_t lrg_buf_q_alloc_phy_addr;
  1085. dma_addr_t lrg_buf_q_phy_addr;
  1086. u32 lrg_buf_q_producer_index;
  1087. u32 lrg_buf_release_cnt;
  1088. struct bufq_addr_element *lrg_buf_next_free;
  1089. u32 num_large_buffers;
  1090. u32 num_lbufq_entries;
  1091. /* Large (Receive) Buffers */
  1092. struct ql_rcv_buf_cb *lrg_buf;
  1093. struct ql_rcv_buf_cb *lrg_buf_free_head;
  1094. struct ql_rcv_buf_cb *lrg_buf_free_tail;
  1095. u32 lrg_buf_free_count;
  1096. u32 lrg_buffer_len;
  1097. u32 lrg_buf_index;
  1098. u32 lrg_buf_skb_check;
  1099. /* Small Buffer Queue */
  1100. u32 small_buf_q_alloc_size;
  1101. u32 small_buf_q_size;
  1102. u32 small_buf_q_producer_index;
  1103. void *small_buf_q_alloc_virt_addr;
  1104. void *small_buf_q_virt_addr;
  1105. dma_addr_t small_buf_q_alloc_phy_addr;
  1106. dma_addr_t small_buf_q_phy_addr;
  1107. u32 small_buf_index;
  1108. /* Small (Receive) Buffers */
  1109. void *small_buf_virt_addr;
  1110. dma_addr_t small_buf_phy_addr;
  1111. u32 small_buf_phy_addr_low;
  1112. u32 small_buf_phy_addr_high;
  1113. u32 small_buf_release_cnt;
  1114. u32 small_buf_total_size;
  1115. /* ISR related, saves status for DPC. */
  1116. u32 control_status;
  1117. struct eeprom_data nvram_data;
  1118. struct timer_list ioctl_timer;
  1119. u32 port_link_state;
  1120. u32 last_rsp_offset;
  1121. /* 4022 specific */
  1122. u32 mac_index; /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
  1123. u32 PHYAddr; /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
  1124. u32 mac_ob_opcode; /* Opcode to use on mac transmission */
  1125. u32 tcp_ob_opcode; /* Opcode to use on tcp transmission */
  1126. u32 update_ob_opcode; /* Opcode to use for updating NCB */
  1127. u32 mb_bit_mask; /* MA Bits mask to use on transmission */
  1128. u32 numPorts;
  1129. struct net_device_stats stats;
  1130. struct workqueue_struct *workqueue;
  1131. struct delayed_work reset_work;
  1132. struct delayed_work tx_timeout_work;
  1133. u32 max_frame_size;
  1134. u32 device_id;
  1135. };
  1136. #endif /* _QLA3XXX_H_ */