qla3xxx.c 101 KB

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  1. /*
  2. * QLogic QLA3xxx NIC HBA Driver
  3. * Copyright (c) 2003-2006 QLogic Corporation
  4. *
  5. * See LICENSE.qla3xxx for copyright and licensing details.
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/init.h>
  9. #include <linux/types.h>
  10. #include <linux/module.h>
  11. #include <linux/list.h>
  12. #include <linux/pci.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/sched.h>
  15. #include <linux/slab.h>
  16. #include <linux/dmapool.h>
  17. #include <linux/mempool.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/kthread.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/errno.h>
  22. #include <linux/ioport.h>
  23. #include <linux/ip.h>
  24. #include <linux/in.h>
  25. #include <linux/if_arp.h>
  26. #include <linux/if_ether.h>
  27. #include <linux/netdevice.h>
  28. #include <linux/etherdevice.h>
  29. #include <linux/ethtool.h>
  30. #include <linux/skbuff.h>
  31. #include <linux/rtnetlink.h>
  32. #include <linux/if_vlan.h>
  33. #include <linux/init.h>
  34. #include <linux/delay.h>
  35. #include <linux/mm.h>
  36. #include "qla3xxx.h"
  37. #define DRV_NAME "qla3xxx"
  38. #define DRV_STRING "QLogic ISP3XXX Network Driver"
  39. #define DRV_VERSION "v2.03.00-k3"
  40. #define PFX DRV_NAME " "
  41. static const char ql3xxx_driver_name[] = DRV_NAME;
  42. static const char ql3xxx_driver_version[] = DRV_VERSION;
  43. MODULE_AUTHOR("QLogic Corporation");
  44. MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
  45. MODULE_LICENSE("GPL");
  46. MODULE_VERSION(DRV_VERSION);
  47. static const u32 default_msg
  48. = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  49. | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  50. static int debug = -1; /* defaults above */
  51. module_param(debug, int, 0);
  52. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  53. static int msi;
  54. module_param(msi, int, 0);
  55. MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
  56. static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
  57. {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
  58. {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
  59. /* required last entry */
  60. {0,}
  61. };
  62. MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
  63. /*
  64. * Caller must take hw_lock.
  65. */
  66. static int ql_sem_spinlock(struct ql3_adapter *qdev,
  67. u32 sem_mask, u32 sem_bits)
  68. {
  69. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  70. u32 value;
  71. unsigned int seconds = 3;
  72. do {
  73. writel((sem_mask | sem_bits),
  74. &port_regs->CommonRegs.semaphoreReg);
  75. value = readl(&port_regs->CommonRegs.semaphoreReg);
  76. if ((value & (sem_mask >> 16)) == sem_bits)
  77. return 0;
  78. ssleep(1);
  79. } while(--seconds);
  80. return -1;
  81. }
  82. static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
  83. {
  84. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  85. writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
  86. readl(&port_regs->CommonRegs.semaphoreReg);
  87. }
  88. static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
  89. {
  90. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  91. u32 value;
  92. writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
  93. value = readl(&port_regs->CommonRegs.semaphoreReg);
  94. return ((value & (sem_mask >> 16)) == sem_bits);
  95. }
  96. /*
  97. * Caller holds hw_lock.
  98. */
  99. static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
  100. {
  101. int i = 0;
  102. while (1) {
  103. if (!ql_sem_lock(qdev,
  104. QL_DRVR_SEM_MASK,
  105. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
  106. * 2) << 1)) {
  107. if (i < 10) {
  108. ssleep(1);
  109. i++;
  110. } else {
  111. printk(KERN_ERR PFX "%s: Timed out waiting for "
  112. "driver lock...\n",
  113. qdev->ndev->name);
  114. return 0;
  115. }
  116. } else {
  117. printk(KERN_DEBUG PFX
  118. "%s: driver lock acquired.\n",
  119. qdev->ndev->name);
  120. return 1;
  121. }
  122. }
  123. }
  124. static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
  125. {
  126. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  127. writel(((ISP_CONTROL_NP_MASK << 16) | page),
  128. &port_regs->CommonRegs.ispControlStatus);
  129. readl(&port_regs->CommonRegs.ispControlStatus);
  130. qdev->current_page = page;
  131. }
  132. static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
  133. u32 __iomem * reg)
  134. {
  135. u32 value;
  136. unsigned long hw_flags;
  137. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  138. value = readl(reg);
  139. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  140. return value;
  141. }
  142. static u32 ql_read_common_reg(struct ql3_adapter *qdev,
  143. u32 __iomem * reg)
  144. {
  145. return readl(reg);
  146. }
  147. static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
  148. {
  149. u32 value;
  150. unsigned long hw_flags;
  151. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  152. if (qdev->current_page != 0)
  153. ql_set_register_page(qdev,0);
  154. value = readl(reg);
  155. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  156. return value;
  157. }
  158. static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
  159. {
  160. if (qdev->current_page != 0)
  161. ql_set_register_page(qdev,0);
  162. return readl(reg);
  163. }
  164. static void ql_write_common_reg_l(struct ql3_adapter *qdev,
  165. u32 __iomem *reg, u32 value)
  166. {
  167. unsigned long hw_flags;
  168. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  169. writel(value, reg);
  170. readl(reg);
  171. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  172. return;
  173. }
  174. static void ql_write_common_reg(struct ql3_adapter *qdev,
  175. u32 __iomem *reg, u32 value)
  176. {
  177. writel(value, reg);
  178. readl(reg);
  179. return;
  180. }
  181. static void ql_write_nvram_reg(struct ql3_adapter *qdev,
  182. u32 __iomem *reg, u32 value)
  183. {
  184. writel(value, reg);
  185. readl(reg);
  186. udelay(1);
  187. return;
  188. }
  189. static void ql_write_page0_reg(struct ql3_adapter *qdev,
  190. u32 __iomem *reg, u32 value)
  191. {
  192. if (qdev->current_page != 0)
  193. ql_set_register_page(qdev,0);
  194. writel(value, reg);
  195. readl(reg);
  196. return;
  197. }
  198. /*
  199. * Caller holds hw_lock. Only called during init.
  200. */
  201. static void ql_write_page1_reg(struct ql3_adapter *qdev,
  202. u32 __iomem *reg, u32 value)
  203. {
  204. if (qdev->current_page != 1)
  205. ql_set_register_page(qdev,1);
  206. writel(value, reg);
  207. readl(reg);
  208. return;
  209. }
  210. /*
  211. * Caller holds hw_lock. Only called during init.
  212. */
  213. static void ql_write_page2_reg(struct ql3_adapter *qdev,
  214. u32 __iomem *reg, u32 value)
  215. {
  216. if (qdev->current_page != 2)
  217. ql_set_register_page(qdev,2);
  218. writel(value, reg);
  219. readl(reg);
  220. return;
  221. }
  222. static void ql_disable_interrupts(struct ql3_adapter *qdev)
  223. {
  224. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  225. ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
  226. (ISP_IMR_ENABLE_INT << 16));
  227. }
  228. static void ql_enable_interrupts(struct ql3_adapter *qdev)
  229. {
  230. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  231. ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
  232. ((0xff << 16) | ISP_IMR_ENABLE_INT));
  233. }
  234. static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
  235. struct ql_rcv_buf_cb *lrg_buf_cb)
  236. {
  237. dma_addr_t map;
  238. int err;
  239. lrg_buf_cb->next = NULL;
  240. if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
  241. qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
  242. } else {
  243. qdev->lrg_buf_free_tail->next = lrg_buf_cb;
  244. qdev->lrg_buf_free_tail = lrg_buf_cb;
  245. }
  246. if (!lrg_buf_cb->skb) {
  247. lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
  248. qdev->lrg_buffer_len);
  249. if (unlikely(!lrg_buf_cb->skb)) {
  250. printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
  251. qdev->ndev->name);
  252. qdev->lrg_buf_skb_check++;
  253. } else {
  254. /*
  255. * We save some space to copy the ethhdr from first
  256. * buffer
  257. */
  258. skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
  259. map = pci_map_single(qdev->pdev,
  260. lrg_buf_cb->skb->data,
  261. qdev->lrg_buffer_len -
  262. QL_HEADER_SPACE,
  263. PCI_DMA_FROMDEVICE);
  264. err = pci_dma_mapping_error(map);
  265. if(err) {
  266. printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
  267. qdev->ndev->name, err);
  268. dev_kfree_skb(lrg_buf_cb->skb);
  269. lrg_buf_cb->skb = NULL;
  270. qdev->lrg_buf_skb_check++;
  271. return;
  272. }
  273. lrg_buf_cb->buf_phy_addr_low =
  274. cpu_to_le32(LS_64BITS(map));
  275. lrg_buf_cb->buf_phy_addr_high =
  276. cpu_to_le32(MS_64BITS(map));
  277. pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
  278. pci_unmap_len_set(lrg_buf_cb, maplen,
  279. qdev->lrg_buffer_len -
  280. QL_HEADER_SPACE);
  281. }
  282. }
  283. qdev->lrg_buf_free_count++;
  284. }
  285. static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
  286. *qdev)
  287. {
  288. struct ql_rcv_buf_cb *lrg_buf_cb;
  289. if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
  290. if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
  291. qdev->lrg_buf_free_tail = NULL;
  292. qdev->lrg_buf_free_count--;
  293. }
  294. return lrg_buf_cb;
  295. }
  296. static u32 addrBits = EEPROM_NO_ADDR_BITS;
  297. static u32 dataBits = EEPROM_NO_DATA_BITS;
  298. static void fm93c56a_deselect(struct ql3_adapter *qdev);
  299. static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
  300. unsigned short *value);
  301. /*
  302. * Caller holds hw_lock.
  303. */
  304. static void fm93c56a_select(struct ql3_adapter *qdev)
  305. {
  306. struct ql3xxx_port_registers __iomem *port_regs =
  307. qdev->mem_map_registers;
  308. qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
  309. ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
  310. ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
  311. ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
  312. ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
  313. }
  314. /*
  315. * Caller holds hw_lock.
  316. */
  317. static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
  318. {
  319. int i;
  320. u32 mask;
  321. u32 dataBit;
  322. u32 previousBit;
  323. struct ql3xxx_port_registers __iomem *port_regs =
  324. qdev->mem_map_registers;
  325. /* Clock in a zero, then do the start bit */
  326. ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
  327. ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  328. AUBURN_EEPROM_DO_1);
  329. ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
  330. ISP_NVRAM_MASK | qdev->
  331. eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
  332. AUBURN_EEPROM_CLK_RISE);
  333. ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
  334. ISP_NVRAM_MASK | qdev->
  335. eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
  336. AUBURN_EEPROM_CLK_FALL);
  337. mask = 1 << (FM93C56A_CMD_BITS - 1);
  338. /* Force the previous data bit to be different */
  339. previousBit = 0xffff;
  340. for (i = 0; i < FM93C56A_CMD_BITS; i++) {
  341. dataBit =
  342. (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
  343. if (previousBit != dataBit) {
  344. /*
  345. * If the bit changed, then change the DO state to
  346. * match
  347. */
  348. ql_write_nvram_reg(qdev,
  349. &port_regs->CommonRegs.
  350. serialPortInterfaceReg,
  351. ISP_NVRAM_MASK | qdev->
  352. eeprom_cmd_data | dataBit);
  353. previousBit = dataBit;
  354. }
  355. ql_write_nvram_reg(qdev,
  356. &port_regs->CommonRegs.
  357. serialPortInterfaceReg,
  358. ISP_NVRAM_MASK | qdev->
  359. eeprom_cmd_data | dataBit |
  360. AUBURN_EEPROM_CLK_RISE);
  361. ql_write_nvram_reg(qdev,
  362. &port_regs->CommonRegs.
  363. serialPortInterfaceReg,
  364. ISP_NVRAM_MASK | qdev->
  365. eeprom_cmd_data | dataBit |
  366. AUBURN_EEPROM_CLK_FALL);
  367. cmd = cmd << 1;
  368. }
  369. mask = 1 << (addrBits - 1);
  370. /* Force the previous data bit to be different */
  371. previousBit = 0xffff;
  372. for (i = 0; i < addrBits; i++) {
  373. dataBit =
  374. (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
  375. AUBURN_EEPROM_DO_0;
  376. if (previousBit != dataBit) {
  377. /*
  378. * If the bit changed, then change the DO state to
  379. * match
  380. */
  381. ql_write_nvram_reg(qdev,
  382. &port_regs->CommonRegs.
  383. serialPortInterfaceReg,
  384. ISP_NVRAM_MASK | qdev->
  385. eeprom_cmd_data | dataBit);
  386. previousBit = dataBit;
  387. }
  388. ql_write_nvram_reg(qdev,
  389. &port_regs->CommonRegs.
  390. serialPortInterfaceReg,
  391. ISP_NVRAM_MASK | qdev->
  392. eeprom_cmd_data | dataBit |
  393. AUBURN_EEPROM_CLK_RISE);
  394. ql_write_nvram_reg(qdev,
  395. &port_regs->CommonRegs.
  396. serialPortInterfaceReg,
  397. ISP_NVRAM_MASK | qdev->
  398. eeprom_cmd_data | dataBit |
  399. AUBURN_EEPROM_CLK_FALL);
  400. eepromAddr = eepromAddr << 1;
  401. }
  402. }
  403. /*
  404. * Caller holds hw_lock.
  405. */
  406. static void fm93c56a_deselect(struct ql3_adapter *qdev)
  407. {
  408. struct ql3xxx_port_registers __iomem *port_regs =
  409. qdev->mem_map_registers;
  410. qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
  411. ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
  412. ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
  413. }
  414. /*
  415. * Caller holds hw_lock.
  416. */
  417. static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
  418. {
  419. int i;
  420. u32 data = 0;
  421. u32 dataBit;
  422. struct ql3xxx_port_registers __iomem *port_regs =
  423. qdev->mem_map_registers;
  424. /* Read the data bits */
  425. /* The first bit is a dummy. Clock right over it. */
  426. for (i = 0; i < dataBits; i++) {
  427. ql_write_nvram_reg(qdev,
  428. &port_regs->CommonRegs.
  429. serialPortInterfaceReg,
  430. ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  431. AUBURN_EEPROM_CLK_RISE);
  432. ql_write_nvram_reg(qdev,
  433. &port_regs->CommonRegs.
  434. serialPortInterfaceReg,
  435. ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
  436. AUBURN_EEPROM_CLK_FALL);
  437. dataBit =
  438. (ql_read_common_reg
  439. (qdev,
  440. &port_regs->CommonRegs.
  441. serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
  442. data = (data << 1) | dataBit;
  443. }
  444. *value = (u16) data;
  445. }
  446. /*
  447. * Caller holds hw_lock.
  448. */
  449. static void eeprom_readword(struct ql3_adapter *qdev,
  450. u32 eepromAddr, unsigned short *value)
  451. {
  452. fm93c56a_select(qdev);
  453. fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
  454. fm93c56a_datain(qdev, value);
  455. fm93c56a_deselect(qdev);
  456. }
  457. static void ql_swap_mac_addr(u8 * macAddress)
  458. {
  459. #ifdef __BIG_ENDIAN
  460. u8 temp;
  461. temp = macAddress[0];
  462. macAddress[0] = macAddress[1];
  463. macAddress[1] = temp;
  464. temp = macAddress[2];
  465. macAddress[2] = macAddress[3];
  466. macAddress[3] = temp;
  467. temp = macAddress[4];
  468. macAddress[4] = macAddress[5];
  469. macAddress[5] = temp;
  470. #endif
  471. }
  472. static int ql_get_nvram_params(struct ql3_adapter *qdev)
  473. {
  474. u16 *pEEPROMData;
  475. u16 checksum = 0;
  476. u32 index;
  477. unsigned long hw_flags;
  478. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  479. pEEPROMData = (u16 *) & qdev->nvram_data;
  480. qdev->eeprom_cmd_data = 0;
  481. if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
  482. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  483. 2) << 10)) {
  484. printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
  485. __func__);
  486. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  487. return -1;
  488. }
  489. for (index = 0; index < EEPROM_SIZE; index++) {
  490. eeprom_readword(qdev, index, pEEPROMData);
  491. checksum += *pEEPROMData;
  492. pEEPROMData++;
  493. }
  494. ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
  495. if (checksum != 0) {
  496. printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
  497. qdev->ndev->name, checksum);
  498. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  499. return -1;
  500. }
  501. /*
  502. * We have a problem with endianness for the MAC addresses
  503. * and the two 8-bit values version, and numPorts. We
  504. * have to swap them on big endian systems.
  505. */
  506. ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
  507. ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
  508. ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
  509. ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
  510. pEEPROMData = (u16 *) & qdev->nvram_data.version;
  511. *pEEPROMData = le16_to_cpu(*pEEPROMData);
  512. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  513. return checksum;
  514. }
  515. static const u32 PHYAddr[2] = {
  516. PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
  517. };
  518. static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
  519. {
  520. struct ql3xxx_port_registers __iomem *port_regs =
  521. qdev->mem_map_registers;
  522. u32 temp;
  523. int count = 1000;
  524. while (count) {
  525. temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
  526. if (!(temp & MAC_MII_STATUS_BSY))
  527. return 0;
  528. udelay(10);
  529. count--;
  530. }
  531. return -1;
  532. }
  533. static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
  534. {
  535. struct ql3xxx_port_registers __iomem *port_regs =
  536. qdev->mem_map_registers;
  537. u32 scanControl;
  538. if (qdev->numPorts > 1) {
  539. /* Auto scan will cycle through multiple ports */
  540. scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
  541. } else {
  542. scanControl = MAC_MII_CONTROL_SC;
  543. }
  544. /*
  545. * Scan register 1 of PHY/PETBI,
  546. * Set up to scan both devices
  547. * The autoscan starts from the first register, completes
  548. * the last one before rolling over to the first
  549. */
  550. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  551. PHYAddr[0] | MII_SCAN_REGISTER);
  552. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  553. (scanControl) |
  554. ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
  555. }
  556. static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
  557. {
  558. u8 ret;
  559. struct ql3xxx_port_registers __iomem *port_regs =
  560. qdev->mem_map_registers;
  561. /* See if scan mode is enabled before we turn it off */
  562. if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
  563. (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
  564. /* Scan is enabled */
  565. ret = 1;
  566. } else {
  567. /* Scan is disabled */
  568. ret = 0;
  569. }
  570. /*
  571. * When disabling scan mode you must first change the MII register
  572. * address
  573. */
  574. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  575. PHYAddr[0] | MII_SCAN_REGISTER);
  576. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  577. ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
  578. MAC_MII_CONTROL_RC) << 16));
  579. return ret;
  580. }
  581. static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
  582. u16 regAddr, u16 value, u32 mac_index)
  583. {
  584. struct ql3xxx_port_registers __iomem *port_regs =
  585. qdev->mem_map_registers;
  586. u8 scanWasEnabled;
  587. scanWasEnabled = ql_mii_disable_scan_mode(qdev);
  588. if (ql_wait_for_mii_ready(qdev)) {
  589. if (netif_msg_link(qdev))
  590. printk(KERN_WARNING PFX
  591. "%s Timed out waiting for management port to "
  592. "get free before issuing command.\n",
  593. qdev->ndev->name);
  594. return -1;
  595. }
  596. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  597. PHYAddr[mac_index] | regAddr);
  598. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
  599. /* Wait for write to complete 9/10/04 SJP */
  600. if (ql_wait_for_mii_ready(qdev)) {
  601. if (netif_msg_link(qdev))
  602. printk(KERN_WARNING PFX
  603. "%s: Timed out waiting for management port to"
  604. "get free before issuing command.\n",
  605. qdev->ndev->name);
  606. return -1;
  607. }
  608. if (scanWasEnabled)
  609. ql_mii_enable_scan_mode(qdev);
  610. return 0;
  611. }
  612. static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
  613. u16 * value, u32 mac_index)
  614. {
  615. struct ql3xxx_port_registers __iomem *port_regs =
  616. qdev->mem_map_registers;
  617. u8 scanWasEnabled;
  618. u32 temp;
  619. scanWasEnabled = ql_mii_disable_scan_mode(qdev);
  620. if (ql_wait_for_mii_ready(qdev)) {
  621. if (netif_msg_link(qdev))
  622. printk(KERN_WARNING PFX
  623. "%s: Timed out waiting for management port to "
  624. "get free before issuing command.\n",
  625. qdev->ndev->name);
  626. return -1;
  627. }
  628. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  629. PHYAddr[mac_index] | regAddr);
  630. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  631. (MAC_MII_CONTROL_RC << 16));
  632. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  633. (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
  634. /* Wait for the read to complete */
  635. if (ql_wait_for_mii_ready(qdev)) {
  636. if (netif_msg_link(qdev))
  637. printk(KERN_WARNING PFX
  638. "%s: Timed out waiting for management port to "
  639. "get free after issuing command.\n",
  640. qdev->ndev->name);
  641. return -1;
  642. }
  643. temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
  644. *value = (u16) temp;
  645. if (scanWasEnabled)
  646. ql_mii_enable_scan_mode(qdev);
  647. return 0;
  648. }
  649. static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
  650. {
  651. struct ql3xxx_port_registers __iomem *port_regs =
  652. qdev->mem_map_registers;
  653. ql_mii_disable_scan_mode(qdev);
  654. if (ql_wait_for_mii_ready(qdev)) {
  655. if (netif_msg_link(qdev))
  656. printk(KERN_WARNING PFX
  657. "%s: Timed out waiting for management port to "
  658. "get free before issuing command.\n",
  659. qdev->ndev->name);
  660. return -1;
  661. }
  662. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  663. qdev->PHYAddr | regAddr);
  664. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
  665. /* Wait for write to complete. */
  666. if (ql_wait_for_mii_ready(qdev)) {
  667. if (netif_msg_link(qdev))
  668. printk(KERN_WARNING PFX
  669. "%s: Timed out waiting for management port to "
  670. "get free before issuing command.\n",
  671. qdev->ndev->name);
  672. return -1;
  673. }
  674. ql_mii_enable_scan_mode(qdev);
  675. return 0;
  676. }
  677. static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
  678. {
  679. u32 temp;
  680. struct ql3xxx_port_registers __iomem *port_regs =
  681. qdev->mem_map_registers;
  682. ql_mii_disable_scan_mode(qdev);
  683. if (ql_wait_for_mii_ready(qdev)) {
  684. if (netif_msg_link(qdev))
  685. printk(KERN_WARNING PFX
  686. "%s: Timed out waiting for management port to "
  687. "get free before issuing command.\n",
  688. qdev->ndev->name);
  689. return -1;
  690. }
  691. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
  692. qdev->PHYAddr | regAddr);
  693. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  694. (MAC_MII_CONTROL_RC << 16));
  695. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  696. (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
  697. /* Wait for the read to complete */
  698. if (ql_wait_for_mii_ready(qdev)) {
  699. if (netif_msg_link(qdev))
  700. printk(KERN_WARNING PFX
  701. "%s: Timed out waiting for management port to "
  702. "get free before issuing command.\n",
  703. qdev->ndev->name);
  704. return -1;
  705. }
  706. temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
  707. *value = (u16) temp;
  708. ql_mii_enable_scan_mode(qdev);
  709. return 0;
  710. }
  711. static void ql_petbi_reset(struct ql3_adapter *qdev)
  712. {
  713. ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
  714. }
  715. static void ql_petbi_start_neg(struct ql3_adapter *qdev)
  716. {
  717. u16 reg;
  718. /* Enable Auto-negotiation sense */
  719. ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
  720. reg |= PETBI_TBI_AUTO_SENSE;
  721. ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
  722. ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
  723. PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
  724. ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
  725. PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
  726. PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
  727. }
  728. static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
  729. {
  730. ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
  731. mac_index);
  732. }
  733. static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
  734. {
  735. u16 reg;
  736. /* Enable Auto-negotiation sense */
  737. ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
  738. reg |= PETBI_TBI_AUTO_SENSE;
  739. ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
  740. ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
  741. PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
  742. ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
  743. PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
  744. PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
  745. mac_index);
  746. }
  747. static void ql_petbi_init(struct ql3_adapter *qdev)
  748. {
  749. ql_petbi_reset(qdev);
  750. ql_petbi_start_neg(qdev);
  751. }
  752. static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
  753. {
  754. ql_petbi_reset_ex(qdev, mac_index);
  755. ql_petbi_start_neg_ex(qdev, mac_index);
  756. }
  757. static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
  758. {
  759. u16 reg;
  760. if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
  761. return 0;
  762. return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
  763. }
  764. static int ql_phy_get_speed(struct ql3_adapter *qdev)
  765. {
  766. u16 reg;
  767. if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
  768. return 0;
  769. reg = (((reg & 0x18) >> 3) & 3);
  770. if (reg == 2)
  771. return SPEED_1000;
  772. else if (reg == 1)
  773. return SPEED_100;
  774. else if (reg == 0)
  775. return SPEED_10;
  776. else
  777. return -1;
  778. }
  779. static int ql_is_full_dup(struct ql3_adapter *qdev)
  780. {
  781. u16 reg;
  782. if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
  783. return 0;
  784. return (reg & PHY_AUX_DUPLEX_STAT) != 0;
  785. }
  786. static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
  787. {
  788. u16 reg;
  789. if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
  790. return 0;
  791. return (reg & PHY_NEG_PAUSE) != 0;
  792. }
  793. /*
  794. * Caller holds hw_lock.
  795. */
  796. static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
  797. {
  798. struct ql3xxx_port_registers __iomem *port_regs =
  799. qdev->mem_map_registers;
  800. u32 value;
  801. if (enable)
  802. value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
  803. else
  804. value = (MAC_CONFIG_REG_PE << 16);
  805. if (qdev->mac_index)
  806. ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
  807. else
  808. ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
  809. }
  810. /*
  811. * Caller holds hw_lock.
  812. */
  813. static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
  814. {
  815. struct ql3xxx_port_registers __iomem *port_regs =
  816. qdev->mem_map_registers;
  817. u32 value;
  818. if (enable)
  819. value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
  820. else
  821. value = (MAC_CONFIG_REG_SR << 16);
  822. if (qdev->mac_index)
  823. ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
  824. else
  825. ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
  826. }
  827. /*
  828. * Caller holds hw_lock.
  829. */
  830. static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
  831. {
  832. struct ql3xxx_port_registers __iomem *port_regs =
  833. qdev->mem_map_registers;
  834. u32 value;
  835. if (enable)
  836. value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
  837. else
  838. value = (MAC_CONFIG_REG_GM << 16);
  839. if (qdev->mac_index)
  840. ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
  841. else
  842. ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
  843. }
  844. /*
  845. * Caller holds hw_lock.
  846. */
  847. static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
  848. {
  849. struct ql3xxx_port_registers __iomem *port_regs =
  850. qdev->mem_map_registers;
  851. u32 value;
  852. if (enable)
  853. value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
  854. else
  855. value = (MAC_CONFIG_REG_FD << 16);
  856. if (qdev->mac_index)
  857. ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
  858. else
  859. ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
  860. }
  861. /*
  862. * Caller holds hw_lock.
  863. */
  864. static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
  865. {
  866. struct ql3xxx_port_registers __iomem *port_regs =
  867. qdev->mem_map_registers;
  868. u32 value;
  869. if (enable)
  870. value =
  871. ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
  872. ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
  873. else
  874. value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
  875. if (qdev->mac_index)
  876. ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
  877. else
  878. ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
  879. }
  880. /*
  881. * Caller holds hw_lock.
  882. */
  883. static int ql_is_fiber(struct ql3_adapter *qdev)
  884. {
  885. struct ql3xxx_port_registers __iomem *port_regs =
  886. qdev->mem_map_registers;
  887. u32 bitToCheck = 0;
  888. u32 temp;
  889. switch (qdev->mac_index) {
  890. case 0:
  891. bitToCheck = PORT_STATUS_SM0;
  892. break;
  893. case 1:
  894. bitToCheck = PORT_STATUS_SM1;
  895. break;
  896. }
  897. temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
  898. return (temp & bitToCheck) != 0;
  899. }
  900. static int ql_is_auto_cfg(struct ql3_adapter *qdev)
  901. {
  902. u16 reg;
  903. ql_mii_read_reg(qdev, 0x00, &reg);
  904. return (reg & 0x1000) != 0;
  905. }
  906. /*
  907. * Caller holds hw_lock.
  908. */
  909. static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
  910. {
  911. struct ql3xxx_port_registers __iomem *port_regs =
  912. qdev->mem_map_registers;
  913. u32 bitToCheck = 0;
  914. u32 temp;
  915. switch (qdev->mac_index) {
  916. case 0:
  917. bitToCheck = PORT_STATUS_AC0;
  918. break;
  919. case 1:
  920. bitToCheck = PORT_STATUS_AC1;
  921. break;
  922. }
  923. temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
  924. if (temp & bitToCheck) {
  925. if (netif_msg_link(qdev))
  926. printk(KERN_INFO PFX
  927. "%s: Auto-Negotiate complete.\n",
  928. qdev->ndev->name);
  929. return 1;
  930. } else {
  931. if (netif_msg_link(qdev))
  932. printk(KERN_WARNING PFX
  933. "%s: Auto-Negotiate incomplete.\n",
  934. qdev->ndev->name);
  935. return 0;
  936. }
  937. }
  938. /*
  939. * ql_is_neg_pause() returns 1 if pause was negotiated to be on
  940. */
  941. static int ql_is_neg_pause(struct ql3_adapter *qdev)
  942. {
  943. if (ql_is_fiber(qdev))
  944. return ql_is_petbi_neg_pause(qdev);
  945. else
  946. return ql_is_phy_neg_pause(qdev);
  947. }
  948. static int ql_auto_neg_error(struct ql3_adapter *qdev)
  949. {
  950. struct ql3xxx_port_registers __iomem *port_regs =
  951. qdev->mem_map_registers;
  952. u32 bitToCheck = 0;
  953. u32 temp;
  954. switch (qdev->mac_index) {
  955. case 0:
  956. bitToCheck = PORT_STATUS_AE0;
  957. break;
  958. case 1:
  959. bitToCheck = PORT_STATUS_AE1;
  960. break;
  961. }
  962. temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
  963. return (temp & bitToCheck) != 0;
  964. }
  965. static u32 ql_get_link_speed(struct ql3_adapter *qdev)
  966. {
  967. if (ql_is_fiber(qdev))
  968. return SPEED_1000;
  969. else
  970. return ql_phy_get_speed(qdev);
  971. }
  972. static int ql_is_link_full_dup(struct ql3_adapter *qdev)
  973. {
  974. if (ql_is_fiber(qdev))
  975. return 1;
  976. else
  977. return ql_is_full_dup(qdev);
  978. }
  979. /*
  980. * Caller holds hw_lock.
  981. */
  982. static int ql_link_down_detect(struct ql3_adapter *qdev)
  983. {
  984. struct ql3xxx_port_registers __iomem *port_regs =
  985. qdev->mem_map_registers;
  986. u32 bitToCheck = 0;
  987. u32 temp;
  988. switch (qdev->mac_index) {
  989. case 0:
  990. bitToCheck = ISP_CONTROL_LINK_DN_0;
  991. break;
  992. case 1:
  993. bitToCheck = ISP_CONTROL_LINK_DN_1;
  994. break;
  995. }
  996. temp =
  997. ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
  998. return (temp & bitToCheck) != 0;
  999. }
  1000. /*
  1001. * Caller holds hw_lock.
  1002. */
  1003. static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
  1004. {
  1005. struct ql3xxx_port_registers __iomem *port_regs =
  1006. qdev->mem_map_registers;
  1007. switch (qdev->mac_index) {
  1008. case 0:
  1009. ql_write_common_reg(qdev,
  1010. &port_regs->CommonRegs.ispControlStatus,
  1011. (ISP_CONTROL_LINK_DN_0) |
  1012. (ISP_CONTROL_LINK_DN_0 << 16));
  1013. break;
  1014. case 1:
  1015. ql_write_common_reg(qdev,
  1016. &port_regs->CommonRegs.ispControlStatus,
  1017. (ISP_CONTROL_LINK_DN_1) |
  1018. (ISP_CONTROL_LINK_DN_1 << 16));
  1019. break;
  1020. default:
  1021. return 1;
  1022. }
  1023. return 0;
  1024. }
  1025. /*
  1026. * Caller holds hw_lock.
  1027. */
  1028. static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
  1029. u32 mac_index)
  1030. {
  1031. struct ql3xxx_port_registers __iomem *port_regs =
  1032. qdev->mem_map_registers;
  1033. u32 bitToCheck = 0;
  1034. u32 temp;
  1035. switch (mac_index) {
  1036. case 0:
  1037. bitToCheck = PORT_STATUS_F1_ENABLED;
  1038. break;
  1039. case 1:
  1040. bitToCheck = PORT_STATUS_F3_ENABLED;
  1041. break;
  1042. default:
  1043. break;
  1044. }
  1045. temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
  1046. if (temp & bitToCheck) {
  1047. if (netif_msg_link(qdev))
  1048. printk(KERN_DEBUG PFX
  1049. "%s: is not link master.\n", qdev->ndev->name);
  1050. return 0;
  1051. } else {
  1052. if (netif_msg_link(qdev))
  1053. printk(KERN_DEBUG PFX
  1054. "%s: is link master.\n", qdev->ndev->name);
  1055. return 1;
  1056. }
  1057. }
  1058. static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
  1059. {
  1060. ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
  1061. }
  1062. static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
  1063. {
  1064. u16 reg;
  1065. ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
  1066. PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
  1067. ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
  1068. ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
  1069. mac_index);
  1070. }
  1071. static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
  1072. {
  1073. ql_phy_reset_ex(qdev, mac_index);
  1074. ql_phy_start_neg_ex(qdev, mac_index);
  1075. }
  1076. /*
  1077. * Caller holds hw_lock.
  1078. */
  1079. static u32 ql_get_link_state(struct ql3_adapter *qdev)
  1080. {
  1081. struct ql3xxx_port_registers __iomem *port_regs =
  1082. qdev->mem_map_registers;
  1083. u32 bitToCheck = 0;
  1084. u32 temp, linkState;
  1085. switch (qdev->mac_index) {
  1086. case 0:
  1087. bitToCheck = PORT_STATUS_UP0;
  1088. break;
  1089. case 1:
  1090. bitToCheck = PORT_STATUS_UP1;
  1091. break;
  1092. }
  1093. temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
  1094. if (temp & bitToCheck) {
  1095. linkState = LS_UP;
  1096. } else {
  1097. linkState = LS_DOWN;
  1098. if (netif_msg_link(qdev))
  1099. printk(KERN_WARNING PFX
  1100. "%s: Link is down.\n", qdev->ndev->name);
  1101. }
  1102. return linkState;
  1103. }
  1104. static int ql_port_start(struct ql3_adapter *qdev)
  1105. {
  1106. if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1107. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  1108. 2) << 7))
  1109. return -1;
  1110. if (ql_is_fiber(qdev)) {
  1111. ql_petbi_init(qdev);
  1112. } else {
  1113. /* Copper port */
  1114. ql_phy_init_ex(qdev, qdev->mac_index);
  1115. }
  1116. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1117. return 0;
  1118. }
  1119. static int ql_finish_auto_neg(struct ql3_adapter *qdev)
  1120. {
  1121. if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1122. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  1123. 2) << 7))
  1124. return -1;
  1125. if (!ql_auto_neg_error(qdev)) {
  1126. if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
  1127. /* configure the MAC */
  1128. if (netif_msg_link(qdev))
  1129. printk(KERN_DEBUG PFX
  1130. "%s: Configuring link.\n",
  1131. qdev->ndev->
  1132. name);
  1133. ql_mac_cfg_soft_reset(qdev, 1);
  1134. ql_mac_cfg_gig(qdev,
  1135. (ql_get_link_speed
  1136. (qdev) ==
  1137. SPEED_1000));
  1138. ql_mac_cfg_full_dup(qdev,
  1139. ql_is_link_full_dup
  1140. (qdev));
  1141. ql_mac_cfg_pause(qdev,
  1142. ql_is_neg_pause
  1143. (qdev));
  1144. ql_mac_cfg_soft_reset(qdev, 0);
  1145. /* enable the MAC */
  1146. if (netif_msg_link(qdev))
  1147. printk(KERN_DEBUG PFX
  1148. "%s: Enabling mac.\n",
  1149. qdev->ndev->
  1150. name);
  1151. ql_mac_enable(qdev, 1);
  1152. }
  1153. if (netif_msg_link(qdev))
  1154. printk(KERN_DEBUG PFX
  1155. "%s: Change port_link_state LS_DOWN to LS_UP.\n",
  1156. qdev->ndev->name);
  1157. qdev->port_link_state = LS_UP;
  1158. netif_start_queue(qdev->ndev);
  1159. netif_carrier_on(qdev->ndev);
  1160. if (netif_msg_link(qdev))
  1161. printk(KERN_INFO PFX
  1162. "%s: Link is up at %d Mbps, %s duplex.\n",
  1163. qdev->ndev->name,
  1164. ql_get_link_speed(qdev),
  1165. ql_is_link_full_dup(qdev)
  1166. ? "full" : "half");
  1167. } else { /* Remote error detected */
  1168. if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
  1169. if (netif_msg_link(qdev))
  1170. printk(KERN_DEBUG PFX
  1171. "%s: Remote error detected. "
  1172. "Calling ql_port_start().\n",
  1173. qdev->ndev->
  1174. name);
  1175. /*
  1176. * ql_port_start() is shared code and needs
  1177. * to lock the PHY on it's own.
  1178. */
  1179. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1180. if(ql_port_start(qdev)) {/* Restart port */
  1181. return -1;
  1182. } else
  1183. return 0;
  1184. }
  1185. }
  1186. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1187. return 0;
  1188. }
  1189. static void ql_link_state_machine(struct ql3_adapter *qdev)
  1190. {
  1191. u32 curr_link_state;
  1192. unsigned long hw_flags;
  1193. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  1194. curr_link_state = ql_get_link_state(qdev);
  1195. if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
  1196. if (netif_msg_link(qdev))
  1197. printk(KERN_INFO PFX
  1198. "%s: Reset in progress, skip processing link "
  1199. "state.\n", qdev->ndev->name);
  1200. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1201. return;
  1202. }
  1203. switch (qdev->port_link_state) {
  1204. default:
  1205. if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
  1206. ql_port_start(qdev);
  1207. }
  1208. qdev->port_link_state = LS_DOWN;
  1209. /* Fall Through */
  1210. case LS_DOWN:
  1211. if (netif_msg_link(qdev))
  1212. printk(KERN_DEBUG PFX
  1213. "%s: port_link_state = LS_DOWN.\n",
  1214. qdev->ndev->name);
  1215. if (curr_link_state == LS_UP) {
  1216. if (netif_msg_link(qdev))
  1217. printk(KERN_DEBUG PFX
  1218. "%s: curr_link_state = LS_UP.\n",
  1219. qdev->ndev->name);
  1220. if (ql_is_auto_neg_complete(qdev))
  1221. ql_finish_auto_neg(qdev);
  1222. if (qdev->port_link_state == LS_UP)
  1223. ql_link_down_detect_clear(qdev);
  1224. }
  1225. break;
  1226. case LS_UP:
  1227. /*
  1228. * See if the link is currently down or went down and came
  1229. * back up
  1230. */
  1231. if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
  1232. if (netif_msg_link(qdev))
  1233. printk(KERN_INFO PFX "%s: Link is down.\n",
  1234. qdev->ndev->name);
  1235. qdev->port_link_state = LS_DOWN;
  1236. }
  1237. break;
  1238. }
  1239. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1240. }
  1241. /*
  1242. * Caller must take hw_lock and QL_PHY_GIO_SEM.
  1243. */
  1244. static void ql_get_phy_owner(struct ql3_adapter *qdev)
  1245. {
  1246. if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
  1247. set_bit(QL_LINK_MASTER,&qdev->flags);
  1248. else
  1249. clear_bit(QL_LINK_MASTER,&qdev->flags);
  1250. }
  1251. /*
  1252. * Caller must take hw_lock and QL_PHY_GIO_SEM.
  1253. */
  1254. static void ql_init_scan_mode(struct ql3_adapter *qdev)
  1255. {
  1256. ql_mii_enable_scan_mode(qdev);
  1257. if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
  1258. if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
  1259. ql_petbi_init_ex(qdev, qdev->mac_index);
  1260. } else {
  1261. if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
  1262. ql_phy_init_ex(qdev, qdev->mac_index);
  1263. }
  1264. }
  1265. /*
  1266. * MII_Setup needs to be called before taking the PHY out of reset so that the
  1267. * management interface clock speed can be set properly. It would be better if
  1268. * we had a way to disable MDC until after the PHY is out of reset, but we
  1269. * don't have that capability.
  1270. */
  1271. static int ql_mii_setup(struct ql3_adapter *qdev)
  1272. {
  1273. u32 reg;
  1274. struct ql3xxx_port_registers __iomem *port_regs =
  1275. qdev->mem_map_registers;
  1276. if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1277. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  1278. 2) << 7))
  1279. return -1;
  1280. if (qdev->device_id == QL3032_DEVICE_ID)
  1281. ql_write_page0_reg(qdev,
  1282. &port_regs->macMIIMgmtControlReg, 0x0f00000);
  1283. /* Divide 125MHz clock by 28 to meet PHY timing requirements */
  1284. reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
  1285. ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
  1286. reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
  1287. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1288. return 0;
  1289. }
  1290. static u32 ql_supported_modes(struct ql3_adapter *qdev)
  1291. {
  1292. u32 supported;
  1293. if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
  1294. supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
  1295. | SUPPORTED_Autoneg;
  1296. } else {
  1297. supported = SUPPORTED_10baseT_Half
  1298. | SUPPORTED_10baseT_Full
  1299. | SUPPORTED_100baseT_Half
  1300. | SUPPORTED_100baseT_Full
  1301. | SUPPORTED_1000baseT_Half
  1302. | SUPPORTED_1000baseT_Full
  1303. | SUPPORTED_Autoneg | SUPPORTED_TP;
  1304. }
  1305. return supported;
  1306. }
  1307. static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
  1308. {
  1309. int status;
  1310. unsigned long hw_flags;
  1311. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  1312. if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1313. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  1314. 2) << 7)) {
  1315. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1316. return 0;
  1317. }
  1318. status = ql_is_auto_cfg(qdev);
  1319. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1320. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1321. return status;
  1322. }
  1323. static u32 ql_get_speed(struct ql3_adapter *qdev)
  1324. {
  1325. u32 status;
  1326. unsigned long hw_flags;
  1327. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  1328. if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1329. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  1330. 2) << 7)) {
  1331. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1332. return 0;
  1333. }
  1334. status = ql_get_link_speed(qdev);
  1335. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1336. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1337. return status;
  1338. }
  1339. static int ql_get_full_dup(struct ql3_adapter *qdev)
  1340. {
  1341. int status;
  1342. unsigned long hw_flags;
  1343. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  1344. if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  1345. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  1346. 2) << 7)) {
  1347. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1348. return 0;
  1349. }
  1350. status = ql_is_link_full_dup(qdev);
  1351. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  1352. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1353. return status;
  1354. }
  1355. static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
  1356. {
  1357. struct ql3_adapter *qdev = netdev_priv(ndev);
  1358. ecmd->transceiver = XCVR_INTERNAL;
  1359. ecmd->supported = ql_supported_modes(qdev);
  1360. if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
  1361. ecmd->port = PORT_FIBRE;
  1362. } else {
  1363. ecmd->port = PORT_TP;
  1364. ecmd->phy_address = qdev->PHYAddr;
  1365. }
  1366. ecmd->advertising = ql_supported_modes(qdev);
  1367. ecmd->autoneg = ql_get_auto_cfg_status(qdev);
  1368. ecmd->speed = ql_get_speed(qdev);
  1369. ecmd->duplex = ql_get_full_dup(qdev);
  1370. return 0;
  1371. }
  1372. static void ql_get_drvinfo(struct net_device *ndev,
  1373. struct ethtool_drvinfo *drvinfo)
  1374. {
  1375. struct ql3_adapter *qdev = netdev_priv(ndev);
  1376. strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
  1377. strncpy(drvinfo->version, ql3xxx_driver_version, 32);
  1378. strncpy(drvinfo->fw_version, "N/A", 32);
  1379. strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
  1380. drvinfo->n_stats = 0;
  1381. drvinfo->testinfo_len = 0;
  1382. drvinfo->regdump_len = 0;
  1383. drvinfo->eedump_len = 0;
  1384. }
  1385. static u32 ql_get_msglevel(struct net_device *ndev)
  1386. {
  1387. struct ql3_adapter *qdev = netdev_priv(ndev);
  1388. return qdev->msg_enable;
  1389. }
  1390. static void ql_set_msglevel(struct net_device *ndev, u32 value)
  1391. {
  1392. struct ql3_adapter *qdev = netdev_priv(ndev);
  1393. qdev->msg_enable = value;
  1394. }
  1395. static const struct ethtool_ops ql3xxx_ethtool_ops = {
  1396. .get_settings = ql_get_settings,
  1397. .get_drvinfo = ql_get_drvinfo,
  1398. .get_perm_addr = ethtool_op_get_perm_addr,
  1399. .get_link = ethtool_op_get_link,
  1400. .get_msglevel = ql_get_msglevel,
  1401. .set_msglevel = ql_set_msglevel,
  1402. };
  1403. static int ql_populate_free_queue(struct ql3_adapter *qdev)
  1404. {
  1405. struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
  1406. dma_addr_t map;
  1407. int err;
  1408. while (lrg_buf_cb) {
  1409. if (!lrg_buf_cb->skb) {
  1410. lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
  1411. qdev->lrg_buffer_len);
  1412. if (unlikely(!lrg_buf_cb->skb)) {
  1413. printk(KERN_DEBUG PFX
  1414. "%s: Failed netdev_alloc_skb().\n",
  1415. qdev->ndev->name);
  1416. break;
  1417. } else {
  1418. /*
  1419. * We save some space to copy the ethhdr from
  1420. * first buffer
  1421. */
  1422. skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
  1423. map = pci_map_single(qdev->pdev,
  1424. lrg_buf_cb->skb->data,
  1425. qdev->lrg_buffer_len -
  1426. QL_HEADER_SPACE,
  1427. PCI_DMA_FROMDEVICE);
  1428. err = pci_dma_mapping_error(map);
  1429. if(err) {
  1430. printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
  1431. qdev->ndev->name, err);
  1432. dev_kfree_skb(lrg_buf_cb->skb);
  1433. lrg_buf_cb->skb = NULL;
  1434. break;
  1435. }
  1436. lrg_buf_cb->buf_phy_addr_low =
  1437. cpu_to_le32(LS_64BITS(map));
  1438. lrg_buf_cb->buf_phy_addr_high =
  1439. cpu_to_le32(MS_64BITS(map));
  1440. pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
  1441. pci_unmap_len_set(lrg_buf_cb, maplen,
  1442. qdev->lrg_buffer_len -
  1443. QL_HEADER_SPACE);
  1444. --qdev->lrg_buf_skb_check;
  1445. if (!qdev->lrg_buf_skb_check)
  1446. return 1;
  1447. }
  1448. }
  1449. lrg_buf_cb = lrg_buf_cb->next;
  1450. }
  1451. return 0;
  1452. }
  1453. /*
  1454. * Caller holds hw_lock.
  1455. */
  1456. static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
  1457. {
  1458. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  1459. if (qdev->small_buf_release_cnt >= 16) {
  1460. while (qdev->small_buf_release_cnt >= 16) {
  1461. qdev->small_buf_q_producer_index++;
  1462. if (qdev->small_buf_q_producer_index ==
  1463. NUM_SBUFQ_ENTRIES)
  1464. qdev->small_buf_q_producer_index = 0;
  1465. qdev->small_buf_release_cnt -= 8;
  1466. }
  1467. wmb();
  1468. writel(qdev->small_buf_q_producer_index,
  1469. &port_regs->CommonRegs.rxSmallQProducerIndex);
  1470. }
  1471. }
  1472. /*
  1473. * Caller holds hw_lock.
  1474. */
  1475. static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
  1476. {
  1477. struct bufq_addr_element *lrg_buf_q_ele;
  1478. int i;
  1479. struct ql_rcv_buf_cb *lrg_buf_cb;
  1480. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  1481. if ((qdev->lrg_buf_free_count >= 8)
  1482. && (qdev->lrg_buf_release_cnt >= 16)) {
  1483. if (qdev->lrg_buf_skb_check)
  1484. if (!ql_populate_free_queue(qdev))
  1485. return;
  1486. lrg_buf_q_ele = qdev->lrg_buf_next_free;
  1487. while ((qdev->lrg_buf_release_cnt >= 16)
  1488. && (qdev->lrg_buf_free_count >= 8)) {
  1489. for (i = 0; i < 8; i++) {
  1490. lrg_buf_cb =
  1491. ql_get_from_lrg_buf_free_list(qdev);
  1492. lrg_buf_q_ele->addr_high =
  1493. lrg_buf_cb->buf_phy_addr_high;
  1494. lrg_buf_q_ele->addr_low =
  1495. lrg_buf_cb->buf_phy_addr_low;
  1496. lrg_buf_q_ele++;
  1497. qdev->lrg_buf_release_cnt--;
  1498. }
  1499. qdev->lrg_buf_q_producer_index++;
  1500. if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
  1501. qdev->lrg_buf_q_producer_index = 0;
  1502. if (qdev->lrg_buf_q_producer_index ==
  1503. (qdev->num_lbufq_entries - 1)) {
  1504. lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
  1505. }
  1506. }
  1507. wmb();
  1508. qdev->lrg_buf_next_free = lrg_buf_q_ele;
  1509. writel(qdev->lrg_buf_q_producer_index,
  1510. &port_regs->CommonRegs.rxLargeQProducerIndex);
  1511. }
  1512. }
  1513. static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
  1514. struct ob_mac_iocb_rsp *mac_rsp)
  1515. {
  1516. struct ql_tx_buf_cb *tx_cb;
  1517. int i;
  1518. int retval = 0;
  1519. if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
  1520. printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
  1521. }
  1522. tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
  1523. /* Check the transmit response flags for any errors */
  1524. if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
  1525. printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
  1526. qdev->stats.tx_errors++;
  1527. retval = -EIO;
  1528. goto frame_not_sent;
  1529. }
  1530. if(tx_cb->seg_count == 0) {
  1531. printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
  1532. qdev->stats.tx_errors++;
  1533. retval = -EIO;
  1534. goto invalid_seg_count;
  1535. }
  1536. pci_unmap_single(qdev->pdev,
  1537. pci_unmap_addr(&tx_cb->map[0], mapaddr),
  1538. pci_unmap_len(&tx_cb->map[0], maplen),
  1539. PCI_DMA_TODEVICE);
  1540. tx_cb->seg_count--;
  1541. if (tx_cb->seg_count) {
  1542. for (i = 1; i < tx_cb->seg_count; i++) {
  1543. pci_unmap_page(qdev->pdev,
  1544. pci_unmap_addr(&tx_cb->map[i],
  1545. mapaddr),
  1546. pci_unmap_len(&tx_cb->map[i], maplen),
  1547. PCI_DMA_TODEVICE);
  1548. }
  1549. }
  1550. qdev->stats.tx_packets++;
  1551. qdev->stats.tx_bytes += tx_cb->skb->len;
  1552. frame_not_sent:
  1553. dev_kfree_skb_irq(tx_cb->skb);
  1554. tx_cb->skb = NULL;
  1555. invalid_seg_count:
  1556. atomic_inc(&qdev->tx_count);
  1557. }
  1558. void ql_get_sbuf(struct ql3_adapter *qdev)
  1559. {
  1560. if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
  1561. qdev->small_buf_index = 0;
  1562. qdev->small_buf_release_cnt++;
  1563. }
  1564. struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
  1565. {
  1566. struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
  1567. lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
  1568. qdev->lrg_buf_release_cnt++;
  1569. if (++qdev->lrg_buf_index == qdev->num_large_buffers)
  1570. qdev->lrg_buf_index = 0;
  1571. return(lrg_buf_cb);
  1572. }
  1573. /*
  1574. * The difference between 3022 and 3032 for inbound completions:
  1575. * 3022 uses two buffers per completion. The first buffer contains
  1576. * (some) header info, the second the remainder of the headers plus
  1577. * the data. For this chip we reserve some space at the top of the
  1578. * receive buffer so that the header info in buffer one can be
  1579. * prepended to the buffer two. Buffer two is the sent up while
  1580. * buffer one is returned to the hardware to be reused.
  1581. * 3032 receives all of it's data and headers in one buffer for a
  1582. * simpler process. 3032 also supports checksum verification as
  1583. * can be seen in ql_process_macip_rx_intr().
  1584. */
  1585. static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
  1586. struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
  1587. {
  1588. struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
  1589. struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
  1590. struct sk_buff *skb;
  1591. u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
  1592. /*
  1593. * Get the inbound address list (small buffer).
  1594. */
  1595. ql_get_sbuf(qdev);
  1596. if (qdev->device_id == QL3022_DEVICE_ID)
  1597. lrg_buf_cb1 = ql_get_lbuf(qdev);
  1598. /* start of second buffer */
  1599. lrg_buf_cb2 = ql_get_lbuf(qdev);
  1600. skb = lrg_buf_cb2->skb;
  1601. qdev->stats.rx_packets++;
  1602. qdev->stats.rx_bytes += length;
  1603. skb_put(skb, length);
  1604. pci_unmap_single(qdev->pdev,
  1605. pci_unmap_addr(lrg_buf_cb2, mapaddr),
  1606. pci_unmap_len(lrg_buf_cb2, maplen),
  1607. PCI_DMA_FROMDEVICE);
  1608. prefetch(skb->data);
  1609. skb->dev = qdev->ndev;
  1610. skb->ip_summed = CHECKSUM_NONE;
  1611. skb->protocol = eth_type_trans(skb, qdev->ndev);
  1612. netif_receive_skb(skb);
  1613. qdev->ndev->last_rx = jiffies;
  1614. lrg_buf_cb2->skb = NULL;
  1615. if (qdev->device_id == QL3022_DEVICE_ID)
  1616. ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
  1617. ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
  1618. }
  1619. static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
  1620. struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
  1621. {
  1622. struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
  1623. struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
  1624. struct sk_buff *skb1 = NULL, *skb2;
  1625. struct net_device *ndev = qdev->ndev;
  1626. u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
  1627. u16 size = 0;
  1628. /*
  1629. * Get the inbound address list (small buffer).
  1630. */
  1631. ql_get_sbuf(qdev);
  1632. if (qdev->device_id == QL3022_DEVICE_ID) {
  1633. /* start of first buffer on 3022 */
  1634. lrg_buf_cb1 = ql_get_lbuf(qdev);
  1635. skb1 = lrg_buf_cb1->skb;
  1636. size = ETH_HLEN;
  1637. if (*((u16 *) skb1->data) != 0xFFFF)
  1638. size += VLAN_ETH_HLEN - ETH_HLEN;
  1639. }
  1640. /* start of second buffer */
  1641. lrg_buf_cb2 = ql_get_lbuf(qdev);
  1642. skb2 = lrg_buf_cb2->skb;
  1643. skb_put(skb2, length); /* Just the second buffer length here. */
  1644. pci_unmap_single(qdev->pdev,
  1645. pci_unmap_addr(lrg_buf_cb2, mapaddr),
  1646. pci_unmap_len(lrg_buf_cb2, maplen),
  1647. PCI_DMA_FROMDEVICE);
  1648. prefetch(skb2->data);
  1649. skb2->ip_summed = CHECKSUM_NONE;
  1650. if (qdev->device_id == QL3022_DEVICE_ID) {
  1651. /*
  1652. * Copy the ethhdr from first buffer to second. This
  1653. * is necessary for 3022 IP completions.
  1654. */
  1655. memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
  1656. } else {
  1657. u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
  1658. if (checksum &
  1659. (IB_IP_IOCB_RSP_3032_ICE |
  1660. IB_IP_IOCB_RSP_3032_CE)) {
  1661. printk(KERN_ERR
  1662. "%s: Bad checksum for this %s packet, checksum = %x.\n",
  1663. __func__,
  1664. ((checksum &
  1665. IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
  1666. "UDP"),checksum);
  1667. } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
  1668. (checksum & IB_IP_IOCB_RSP_3032_UDP &&
  1669. !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
  1670. skb2->ip_summed = CHECKSUM_UNNECESSARY;
  1671. }
  1672. }
  1673. skb2->dev = qdev->ndev;
  1674. skb2->protocol = eth_type_trans(skb2, qdev->ndev);
  1675. netif_receive_skb(skb2);
  1676. qdev->stats.rx_packets++;
  1677. qdev->stats.rx_bytes += length;
  1678. ndev->last_rx = jiffies;
  1679. lrg_buf_cb2->skb = NULL;
  1680. if (qdev->device_id == QL3022_DEVICE_ID)
  1681. ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
  1682. ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
  1683. }
  1684. static int ql_tx_rx_clean(struct ql3_adapter *qdev,
  1685. int *tx_cleaned, int *rx_cleaned, int work_to_do)
  1686. {
  1687. struct net_rsp_iocb *net_rsp;
  1688. struct net_device *ndev = qdev->ndev;
  1689. int work_done = 0;
  1690. /* While there are entries in the completion queue. */
  1691. while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
  1692. qdev->rsp_consumer_index) && (work_done < work_to_do)) {
  1693. net_rsp = qdev->rsp_current;
  1694. switch (net_rsp->opcode) {
  1695. case OPCODE_OB_MAC_IOCB_FN0:
  1696. case OPCODE_OB_MAC_IOCB_FN2:
  1697. ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
  1698. net_rsp);
  1699. (*tx_cleaned)++;
  1700. break;
  1701. case OPCODE_IB_MAC_IOCB:
  1702. case OPCODE_IB_3032_MAC_IOCB:
  1703. ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
  1704. net_rsp);
  1705. (*rx_cleaned)++;
  1706. break;
  1707. case OPCODE_IB_IP_IOCB:
  1708. case OPCODE_IB_3032_IP_IOCB:
  1709. ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
  1710. net_rsp);
  1711. (*rx_cleaned)++;
  1712. break;
  1713. default:
  1714. {
  1715. u32 *tmp = (u32 *) net_rsp;
  1716. printk(KERN_ERR PFX
  1717. "%s: Hit default case, not "
  1718. "handled!\n"
  1719. " dropping the packet, opcode = "
  1720. "%x.\n",
  1721. ndev->name, net_rsp->opcode);
  1722. printk(KERN_ERR PFX
  1723. "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
  1724. (unsigned long int)tmp[0],
  1725. (unsigned long int)tmp[1],
  1726. (unsigned long int)tmp[2],
  1727. (unsigned long int)tmp[3]);
  1728. }
  1729. }
  1730. qdev->rsp_consumer_index++;
  1731. if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
  1732. qdev->rsp_consumer_index = 0;
  1733. qdev->rsp_current = qdev->rsp_q_virt_addr;
  1734. } else {
  1735. qdev->rsp_current++;
  1736. }
  1737. work_done = *tx_cleaned + *rx_cleaned;
  1738. }
  1739. return work_done;
  1740. }
  1741. static int ql_poll(struct net_device *ndev, int *budget)
  1742. {
  1743. struct ql3_adapter *qdev = netdev_priv(ndev);
  1744. int work_to_do = min(*budget, ndev->quota);
  1745. int rx_cleaned = 0, tx_cleaned = 0;
  1746. unsigned long hw_flags;
  1747. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  1748. if (!netif_carrier_ok(ndev))
  1749. goto quit_polling;
  1750. ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
  1751. *budget -= rx_cleaned;
  1752. ndev->quota -= rx_cleaned;
  1753. if( tx_cleaned + rx_cleaned != work_to_do ||
  1754. !netif_running(ndev)) {
  1755. quit_polling:
  1756. netif_rx_complete(ndev);
  1757. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  1758. ql_update_small_bufq_prod_index(qdev);
  1759. ql_update_lrg_bufq_prod_index(qdev);
  1760. writel(qdev->rsp_consumer_index,
  1761. &port_regs->CommonRegs.rspQConsumerIndex);
  1762. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  1763. ql_enable_interrupts(qdev);
  1764. return 0;
  1765. }
  1766. return 1;
  1767. }
  1768. static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
  1769. {
  1770. struct net_device *ndev = dev_id;
  1771. struct ql3_adapter *qdev = netdev_priv(ndev);
  1772. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  1773. u32 value;
  1774. int handled = 1;
  1775. u32 var;
  1776. port_regs = qdev->mem_map_registers;
  1777. value =
  1778. ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
  1779. if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
  1780. spin_lock(&qdev->adapter_lock);
  1781. netif_stop_queue(qdev->ndev);
  1782. netif_carrier_off(qdev->ndev);
  1783. ql_disable_interrupts(qdev);
  1784. qdev->port_link_state = LS_DOWN;
  1785. set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
  1786. if (value & ISP_CONTROL_FE) {
  1787. /*
  1788. * Chip Fatal Error.
  1789. */
  1790. var =
  1791. ql_read_page0_reg_l(qdev,
  1792. &port_regs->PortFatalErrStatus);
  1793. printk(KERN_WARNING PFX
  1794. "%s: Resetting chip. PortFatalErrStatus "
  1795. "register = 0x%x\n", ndev->name, var);
  1796. set_bit(QL_RESET_START,&qdev->flags) ;
  1797. } else {
  1798. /*
  1799. * Soft Reset Requested.
  1800. */
  1801. set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
  1802. printk(KERN_ERR PFX
  1803. "%s: Another function issued a reset to the "
  1804. "chip. ISR value = %x.\n", ndev->name, value);
  1805. }
  1806. queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
  1807. spin_unlock(&qdev->adapter_lock);
  1808. } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
  1809. ql_disable_interrupts(qdev);
  1810. if (likely(netif_rx_schedule_prep(ndev))) {
  1811. __netif_rx_schedule(ndev);
  1812. }
  1813. } else {
  1814. return IRQ_NONE;
  1815. }
  1816. return IRQ_RETVAL(handled);
  1817. }
  1818. /*
  1819. * Get the total number of segments needed for the
  1820. * given number of fragments. This is necessary because
  1821. * outbound address lists (OAL) will be used when more than
  1822. * two frags are given. Each address list has 5 addr/len
  1823. * pairs. The 5th pair in each AOL is used to point to
  1824. * the next AOL if more frags are coming.
  1825. * That is why the frags:segment count ratio is not linear.
  1826. */
  1827. static int ql_get_seg_count(struct ql3_adapter *qdev,
  1828. unsigned short frags)
  1829. {
  1830. if (qdev->device_id == QL3022_DEVICE_ID)
  1831. return 1;
  1832. switch(frags) {
  1833. case 0: return 1; /* just the skb->data seg */
  1834. case 1: return 2; /* skb->data + 1 frag */
  1835. case 2: return 3; /* skb->data + 2 frags */
  1836. case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */
  1837. case 4: return 6;
  1838. case 5: return 7;
  1839. case 6: return 8;
  1840. case 7: return 10;
  1841. case 8: return 11;
  1842. case 9: return 12;
  1843. case 10: return 13;
  1844. case 11: return 15;
  1845. case 12: return 16;
  1846. case 13: return 17;
  1847. case 14: return 18;
  1848. case 15: return 20;
  1849. case 16: return 21;
  1850. case 17: return 22;
  1851. case 18: return 23;
  1852. }
  1853. return -1;
  1854. }
  1855. static void ql_hw_csum_setup(struct sk_buff *skb,
  1856. struct ob_mac_iocb_req *mac_iocb_ptr)
  1857. {
  1858. struct ethhdr *eth;
  1859. struct iphdr *ip = NULL;
  1860. u8 offset = ETH_HLEN;
  1861. eth = (struct ethhdr *)(skb->data);
  1862. if (eth->h_proto == __constant_htons(ETH_P_IP)) {
  1863. ip = (struct iphdr *)&skb->data[ETH_HLEN];
  1864. } else if (eth->h_proto == htons(ETH_P_8021Q) &&
  1865. ((struct vlan_ethhdr *)skb->data)->
  1866. h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
  1867. ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
  1868. offset = VLAN_ETH_HLEN;
  1869. }
  1870. if (ip) {
  1871. if (ip->protocol == IPPROTO_TCP) {
  1872. mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
  1873. OB_3032MAC_IOCB_REQ_IC;
  1874. mac_iocb_ptr->ip_hdr_off = offset;
  1875. mac_iocb_ptr->ip_hdr_len = ip->ihl;
  1876. } else if (ip->protocol == IPPROTO_UDP) {
  1877. mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
  1878. OB_3032MAC_IOCB_REQ_IC;
  1879. mac_iocb_ptr->ip_hdr_off = offset;
  1880. mac_iocb_ptr->ip_hdr_len = ip->ihl;
  1881. }
  1882. }
  1883. }
  1884. /*
  1885. * Map the buffers for this transmit. This will return
  1886. * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
  1887. */
  1888. static int ql_send_map(struct ql3_adapter *qdev,
  1889. struct ob_mac_iocb_req *mac_iocb_ptr,
  1890. struct ql_tx_buf_cb *tx_cb,
  1891. struct sk_buff *skb)
  1892. {
  1893. struct oal *oal;
  1894. struct oal_entry *oal_entry;
  1895. int len = skb_headlen(skb);
  1896. dma_addr_t map;
  1897. int err;
  1898. int completed_segs, i;
  1899. int seg_cnt, seg = 0;
  1900. int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
  1901. seg_cnt = tx_cb->seg_count;
  1902. /*
  1903. * Map the skb buffer first.
  1904. */
  1905. map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
  1906. err = pci_dma_mapping_error(map);
  1907. if(err) {
  1908. printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
  1909. qdev->ndev->name, err);
  1910. return NETDEV_TX_BUSY;
  1911. }
  1912. oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
  1913. oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
  1914. oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
  1915. oal_entry->len = cpu_to_le32(len);
  1916. pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
  1917. pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
  1918. seg++;
  1919. if (seg_cnt == 1) {
  1920. /* Terminate the last segment. */
  1921. oal_entry->len =
  1922. cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
  1923. } else {
  1924. oal = tx_cb->oal;
  1925. for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
  1926. skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
  1927. oal_entry++;
  1928. if ((seg == 2 && seg_cnt > 3) || /* Check for continuation */
  1929. (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
  1930. (seg == 12 && seg_cnt > 13) || /* but necessary. */
  1931. (seg == 17 && seg_cnt > 18)) {
  1932. /* Continuation entry points to outbound address list. */
  1933. map = pci_map_single(qdev->pdev, oal,
  1934. sizeof(struct oal),
  1935. PCI_DMA_TODEVICE);
  1936. err = pci_dma_mapping_error(map);
  1937. if(err) {
  1938. printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
  1939. qdev->ndev->name, err);
  1940. goto map_error;
  1941. }
  1942. oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
  1943. oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
  1944. oal_entry->len =
  1945. cpu_to_le32(sizeof(struct oal) |
  1946. OAL_CONT_ENTRY);
  1947. pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
  1948. map);
  1949. pci_unmap_len_set(&tx_cb->map[seg], maplen,
  1950. sizeof(struct oal));
  1951. oal_entry = (struct oal_entry *)oal;
  1952. oal++;
  1953. seg++;
  1954. }
  1955. map =
  1956. pci_map_page(qdev->pdev, frag->page,
  1957. frag->page_offset, frag->size,
  1958. PCI_DMA_TODEVICE);
  1959. err = pci_dma_mapping_error(map);
  1960. if(err) {
  1961. printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
  1962. qdev->ndev->name, err);
  1963. goto map_error;
  1964. }
  1965. oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
  1966. oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
  1967. oal_entry->len = cpu_to_le32(frag->size);
  1968. pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
  1969. pci_unmap_len_set(&tx_cb->map[seg], maplen,
  1970. frag->size);
  1971. }
  1972. /* Terminate the last segment. */
  1973. oal_entry->len =
  1974. cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
  1975. }
  1976. return NETDEV_TX_OK;
  1977. map_error:
  1978. /* A PCI mapping failed and now we will need to back out
  1979. * We need to traverse through the oal's and associated pages which
  1980. * have been mapped and now we must unmap them to clean up properly
  1981. */
  1982. seg = 1;
  1983. oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
  1984. oal = tx_cb->oal;
  1985. for (i=0; i<completed_segs; i++,seg++) {
  1986. oal_entry++;
  1987. if((seg == 2 && seg_cnt > 3) || /* Check for continuation */
  1988. (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
  1989. (seg == 12 && seg_cnt > 13) || /* but necessary. */
  1990. (seg == 17 && seg_cnt > 18)) {
  1991. pci_unmap_single(qdev->pdev,
  1992. pci_unmap_addr(&tx_cb->map[seg], mapaddr),
  1993. pci_unmap_len(&tx_cb->map[seg], maplen),
  1994. PCI_DMA_TODEVICE);
  1995. oal++;
  1996. seg++;
  1997. }
  1998. pci_unmap_page(qdev->pdev,
  1999. pci_unmap_addr(&tx_cb->map[seg], mapaddr),
  2000. pci_unmap_len(&tx_cb->map[seg], maplen),
  2001. PCI_DMA_TODEVICE);
  2002. }
  2003. pci_unmap_single(qdev->pdev,
  2004. pci_unmap_addr(&tx_cb->map[0], mapaddr),
  2005. pci_unmap_addr(&tx_cb->map[0], maplen),
  2006. PCI_DMA_TODEVICE);
  2007. return NETDEV_TX_BUSY;
  2008. }
  2009. /*
  2010. * The difference between 3022 and 3032 sends:
  2011. * 3022 only supports a simple single segment transmission.
  2012. * 3032 supports checksumming and scatter/gather lists (fragments).
  2013. * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
  2014. * in the IOCB plus a chain of outbound address lists (OAL) that
  2015. * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
  2016. * will used to point to an OAL when more ALP entries are required.
  2017. * The IOCB is always the top of the chain followed by one or more
  2018. * OALs (when necessary).
  2019. */
  2020. static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
  2021. {
  2022. struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
  2023. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  2024. struct ql_tx_buf_cb *tx_cb;
  2025. u32 tot_len = skb->len;
  2026. struct ob_mac_iocb_req *mac_iocb_ptr;
  2027. if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
  2028. return NETDEV_TX_BUSY;
  2029. }
  2030. tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
  2031. if((tx_cb->seg_count = ql_get_seg_count(qdev,
  2032. (skb_shinfo(skb)->nr_frags))) == -1) {
  2033. printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
  2034. return NETDEV_TX_OK;
  2035. }
  2036. mac_iocb_ptr = tx_cb->queue_entry;
  2037. memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
  2038. mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
  2039. mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
  2040. mac_iocb_ptr->flags |= qdev->mb_bit_mask;
  2041. mac_iocb_ptr->transaction_id = qdev->req_producer_index;
  2042. mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
  2043. tx_cb->skb = skb;
  2044. if (qdev->device_id == QL3032_DEVICE_ID &&
  2045. skb->ip_summed == CHECKSUM_PARTIAL)
  2046. ql_hw_csum_setup(skb, mac_iocb_ptr);
  2047. if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
  2048. printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
  2049. return NETDEV_TX_BUSY;
  2050. }
  2051. wmb();
  2052. qdev->req_producer_index++;
  2053. if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
  2054. qdev->req_producer_index = 0;
  2055. wmb();
  2056. ql_write_common_reg_l(qdev,
  2057. &port_regs->CommonRegs.reqQProducerIndex,
  2058. qdev->req_producer_index);
  2059. ndev->trans_start = jiffies;
  2060. if (netif_msg_tx_queued(qdev))
  2061. printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
  2062. ndev->name, qdev->req_producer_index, skb->len);
  2063. atomic_dec(&qdev->tx_count);
  2064. return NETDEV_TX_OK;
  2065. }
  2066. static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
  2067. {
  2068. qdev->req_q_size =
  2069. (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
  2070. qdev->req_q_virt_addr =
  2071. pci_alloc_consistent(qdev->pdev,
  2072. (size_t) qdev->req_q_size,
  2073. &qdev->req_q_phy_addr);
  2074. if ((qdev->req_q_virt_addr == NULL) ||
  2075. LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
  2076. printk(KERN_ERR PFX "%s: reqQ failed.\n",
  2077. qdev->ndev->name);
  2078. return -ENOMEM;
  2079. }
  2080. qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
  2081. qdev->rsp_q_virt_addr =
  2082. pci_alloc_consistent(qdev->pdev,
  2083. (size_t) qdev->rsp_q_size,
  2084. &qdev->rsp_q_phy_addr);
  2085. if ((qdev->rsp_q_virt_addr == NULL) ||
  2086. LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
  2087. printk(KERN_ERR PFX
  2088. "%s: rspQ allocation failed\n",
  2089. qdev->ndev->name);
  2090. pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
  2091. qdev->req_q_virt_addr,
  2092. qdev->req_q_phy_addr);
  2093. return -ENOMEM;
  2094. }
  2095. set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
  2096. return 0;
  2097. }
  2098. static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
  2099. {
  2100. if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
  2101. printk(KERN_INFO PFX
  2102. "%s: Already done.\n", qdev->ndev->name);
  2103. return;
  2104. }
  2105. pci_free_consistent(qdev->pdev,
  2106. qdev->req_q_size,
  2107. qdev->req_q_virt_addr, qdev->req_q_phy_addr);
  2108. qdev->req_q_virt_addr = NULL;
  2109. pci_free_consistent(qdev->pdev,
  2110. qdev->rsp_q_size,
  2111. qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
  2112. qdev->rsp_q_virt_addr = NULL;
  2113. clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
  2114. }
  2115. static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
  2116. {
  2117. /* Create Large Buffer Queue */
  2118. qdev->lrg_buf_q_size =
  2119. qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
  2120. if (qdev->lrg_buf_q_size < PAGE_SIZE)
  2121. qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
  2122. else
  2123. qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
  2124. qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
  2125. if (qdev->lrg_buf == NULL) {
  2126. printk(KERN_ERR PFX
  2127. "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
  2128. return -ENOMEM;
  2129. }
  2130. qdev->lrg_buf_q_alloc_virt_addr =
  2131. pci_alloc_consistent(qdev->pdev,
  2132. qdev->lrg_buf_q_alloc_size,
  2133. &qdev->lrg_buf_q_alloc_phy_addr);
  2134. if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
  2135. printk(KERN_ERR PFX
  2136. "%s: lBufQ failed\n", qdev->ndev->name);
  2137. return -ENOMEM;
  2138. }
  2139. qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
  2140. qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
  2141. /* Create Small Buffer Queue */
  2142. qdev->small_buf_q_size =
  2143. NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
  2144. if (qdev->small_buf_q_size < PAGE_SIZE)
  2145. qdev->small_buf_q_alloc_size = PAGE_SIZE;
  2146. else
  2147. qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
  2148. qdev->small_buf_q_alloc_virt_addr =
  2149. pci_alloc_consistent(qdev->pdev,
  2150. qdev->small_buf_q_alloc_size,
  2151. &qdev->small_buf_q_alloc_phy_addr);
  2152. if (qdev->small_buf_q_alloc_virt_addr == NULL) {
  2153. printk(KERN_ERR PFX
  2154. "%s: Small Buffer Queue allocation failed.\n",
  2155. qdev->ndev->name);
  2156. pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
  2157. qdev->lrg_buf_q_alloc_virt_addr,
  2158. qdev->lrg_buf_q_alloc_phy_addr);
  2159. return -ENOMEM;
  2160. }
  2161. qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
  2162. qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
  2163. set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
  2164. return 0;
  2165. }
  2166. static void ql_free_buffer_queues(struct ql3_adapter *qdev)
  2167. {
  2168. if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
  2169. printk(KERN_INFO PFX
  2170. "%s: Already done.\n", qdev->ndev->name);
  2171. return;
  2172. }
  2173. if(qdev->lrg_buf) kfree(qdev->lrg_buf);
  2174. pci_free_consistent(qdev->pdev,
  2175. qdev->lrg_buf_q_alloc_size,
  2176. qdev->lrg_buf_q_alloc_virt_addr,
  2177. qdev->lrg_buf_q_alloc_phy_addr);
  2178. qdev->lrg_buf_q_virt_addr = NULL;
  2179. pci_free_consistent(qdev->pdev,
  2180. qdev->small_buf_q_alloc_size,
  2181. qdev->small_buf_q_alloc_virt_addr,
  2182. qdev->small_buf_q_alloc_phy_addr);
  2183. qdev->small_buf_q_virt_addr = NULL;
  2184. clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
  2185. }
  2186. static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
  2187. {
  2188. int i;
  2189. struct bufq_addr_element *small_buf_q_entry;
  2190. /* Currently we allocate on one of memory and use it for smallbuffers */
  2191. qdev->small_buf_total_size =
  2192. (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
  2193. QL_SMALL_BUFFER_SIZE);
  2194. qdev->small_buf_virt_addr =
  2195. pci_alloc_consistent(qdev->pdev,
  2196. qdev->small_buf_total_size,
  2197. &qdev->small_buf_phy_addr);
  2198. if (qdev->small_buf_virt_addr == NULL) {
  2199. printk(KERN_ERR PFX
  2200. "%s: Failed to get small buffer memory.\n",
  2201. qdev->ndev->name);
  2202. return -ENOMEM;
  2203. }
  2204. qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
  2205. qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
  2206. small_buf_q_entry = qdev->small_buf_q_virt_addr;
  2207. /* Initialize the small buffer queue. */
  2208. for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
  2209. small_buf_q_entry->addr_high =
  2210. cpu_to_le32(qdev->small_buf_phy_addr_high);
  2211. small_buf_q_entry->addr_low =
  2212. cpu_to_le32(qdev->small_buf_phy_addr_low +
  2213. (i * QL_SMALL_BUFFER_SIZE));
  2214. small_buf_q_entry++;
  2215. }
  2216. qdev->small_buf_index = 0;
  2217. set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
  2218. return 0;
  2219. }
  2220. static void ql_free_small_buffers(struct ql3_adapter *qdev)
  2221. {
  2222. if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
  2223. printk(KERN_INFO PFX
  2224. "%s: Already done.\n", qdev->ndev->name);
  2225. return;
  2226. }
  2227. if (qdev->small_buf_virt_addr != NULL) {
  2228. pci_free_consistent(qdev->pdev,
  2229. qdev->small_buf_total_size,
  2230. qdev->small_buf_virt_addr,
  2231. qdev->small_buf_phy_addr);
  2232. qdev->small_buf_virt_addr = NULL;
  2233. }
  2234. }
  2235. static void ql_free_large_buffers(struct ql3_adapter *qdev)
  2236. {
  2237. int i = 0;
  2238. struct ql_rcv_buf_cb *lrg_buf_cb;
  2239. for (i = 0; i < qdev->num_large_buffers; i++) {
  2240. lrg_buf_cb = &qdev->lrg_buf[i];
  2241. if (lrg_buf_cb->skb) {
  2242. dev_kfree_skb(lrg_buf_cb->skb);
  2243. pci_unmap_single(qdev->pdev,
  2244. pci_unmap_addr(lrg_buf_cb, mapaddr),
  2245. pci_unmap_len(lrg_buf_cb, maplen),
  2246. PCI_DMA_FROMDEVICE);
  2247. memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
  2248. } else {
  2249. break;
  2250. }
  2251. }
  2252. }
  2253. static void ql_init_large_buffers(struct ql3_adapter *qdev)
  2254. {
  2255. int i;
  2256. struct ql_rcv_buf_cb *lrg_buf_cb;
  2257. struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
  2258. for (i = 0; i < qdev->num_large_buffers; i++) {
  2259. lrg_buf_cb = &qdev->lrg_buf[i];
  2260. buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
  2261. buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
  2262. buf_addr_ele++;
  2263. }
  2264. qdev->lrg_buf_index = 0;
  2265. qdev->lrg_buf_skb_check = 0;
  2266. }
  2267. static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
  2268. {
  2269. int i;
  2270. struct ql_rcv_buf_cb *lrg_buf_cb;
  2271. struct sk_buff *skb;
  2272. dma_addr_t map;
  2273. int err;
  2274. for (i = 0; i < qdev->num_large_buffers; i++) {
  2275. skb = netdev_alloc_skb(qdev->ndev,
  2276. qdev->lrg_buffer_len);
  2277. if (unlikely(!skb)) {
  2278. /* Better luck next round */
  2279. printk(KERN_ERR PFX
  2280. "%s: large buff alloc failed, "
  2281. "for %d bytes at index %d.\n",
  2282. qdev->ndev->name,
  2283. qdev->lrg_buffer_len * 2, i);
  2284. ql_free_large_buffers(qdev);
  2285. return -ENOMEM;
  2286. } else {
  2287. lrg_buf_cb = &qdev->lrg_buf[i];
  2288. memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
  2289. lrg_buf_cb->index = i;
  2290. lrg_buf_cb->skb = skb;
  2291. /*
  2292. * We save some space to copy the ethhdr from first
  2293. * buffer
  2294. */
  2295. skb_reserve(skb, QL_HEADER_SPACE);
  2296. map = pci_map_single(qdev->pdev,
  2297. skb->data,
  2298. qdev->lrg_buffer_len -
  2299. QL_HEADER_SPACE,
  2300. PCI_DMA_FROMDEVICE);
  2301. err = pci_dma_mapping_error(map);
  2302. if(err) {
  2303. printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
  2304. qdev->ndev->name, err);
  2305. ql_free_large_buffers(qdev);
  2306. return -ENOMEM;
  2307. }
  2308. pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
  2309. pci_unmap_len_set(lrg_buf_cb, maplen,
  2310. qdev->lrg_buffer_len -
  2311. QL_HEADER_SPACE);
  2312. lrg_buf_cb->buf_phy_addr_low =
  2313. cpu_to_le32(LS_64BITS(map));
  2314. lrg_buf_cb->buf_phy_addr_high =
  2315. cpu_to_le32(MS_64BITS(map));
  2316. }
  2317. }
  2318. return 0;
  2319. }
  2320. static void ql_free_send_free_list(struct ql3_adapter *qdev)
  2321. {
  2322. struct ql_tx_buf_cb *tx_cb;
  2323. int i;
  2324. tx_cb = &qdev->tx_buf[0];
  2325. for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
  2326. if (tx_cb->oal) {
  2327. kfree(tx_cb->oal);
  2328. tx_cb->oal = NULL;
  2329. }
  2330. tx_cb++;
  2331. }
  2332. }
  2333. static int ql_create_send_free_list(struct ql3_adapter *qdev)
  2334. {
  2335. struct ql_tx_buf_cb *tx_cb;
  2336. int i;
  2337. struct ob_mac_iocb_req *req_q_curr =
  2338. qdev->req_q_virt_addr;
  2339. /* Create free list of transmit buffers */
  2340. for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
  2341. tx_cb = &qdev->tx_buf[i];
  2342. tx_cb->skb = NULL;
  2343. tx_cb->queue_entry = req_q_curr;
  2344. req_q_curr++;
  2345. tx_cb->oal = kmalloc(512, GFP_KERNEL);
  2346. if (tx_cb->oal == NULL)
  2347. return -1;
  2348. }
  2349. return 0;
  2350. }
  2351. static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
  2352. {
  2353. if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
  2354. qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
  2355. qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
  2356. }
  2357. else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
  2358. /*
  2359. * Bigger buffers, so less of them.
  2360. */
  2361. qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
  2362. qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
  2363. } else {
  2364. printk(KERN_ERR PFX
  2365. "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
  2366. qdev->ndev->name);
  2367. return -ENOMEM;
  2368. }
  2369. qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
  2370. qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
  2371. qdev->max_frame_size =
  2372. (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
  2373. /*
  2374. * First allocate a page of shared memory and use it for shadow
  2375. * locations of Network Request Queue Consumer Address Register and
  2376. * Network Completion Queue Producer Index Register
  2377. */
  2378. qdev->shadow_reg_virt_addr =
  2379. pci_alloc_consistent(qdev->pdev,
  2380. PAGE_SIZE, &qdev->shadow_reg_phy_addr);
  2381. if (qdev->shadow_reg_virt_addr != NULL) {
  2382. qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
  2383. qdev->req_consumer_index_phy_addr_high =
  2384. MS_64BITS(qdev->shadow_reg_phy_addr);
  2385. qdev->req_consumer_index_phy_addr_low =
  2386. LS_64BITS(qdev->shadow_reg_phy_addr);
  2387. qdev->prsp_producer_index =
  2388. (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
  2389. qdev->rsp_producer_index_phy_addr_high =
  2390. qdev->req_consumer_index_phy_addr_high;
  2391. qdev->rsp_producer_index_phy_addr_low =
  2392. qdev->req_consumer_index_phy_addr_low + 8;
  2393. } else {
  2394. printk(KERN_ERR PFX
  2395. "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
  2396. return -ENOMEM;
  2397. }
  2398. if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
  2399. printk(KERN_ERR PFX
  2400. "%s: ql_alloc_net_req_rsp_queues failed.\n",
  2401. qdev->ndev->name);
  2402. goto err_req_rsp;
  2403. }
  2404. if (ql_alloc_buffer_queues(qdev) != 0) {
  2405. printk(KERN_ERR PFX
  2406. "%s: ql_alloc_buffer_queues failed.\n",
  2407. qdev->ndev->name);
  2408. goto err_buffer_queues;
  2409. }
  2410. if (ql_alloc_small_buffers(qdev) != 0) {
  2411. printk(KERN_ERR PFX
  2412. "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
  2413. goto err_small_buffers;
  2414. }
  2415. if (ql_alloc_large_buffers(qdev) != 0) {
  2416. printk(KERN_ERR PFX
  2417. "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
  2418. goto err_small_buffers;
  2419. }
  2420. /* Initialize the large buffer queue. */
  2421. ql_init_large_buffers(qdev);
  2422. if (ql_create_send_free_list(qdev))
  2423. goto err_free_list;
  2424. qdev->rsp_current = qdev->rsp_q_virt_addr;
  2425. return 0;
  2426. err_free_list:
  2427. ql_free_send_free_list(qdev);
  2428. err_small_buffers:
  2429. ql_free_buffer_queues(qdev);
  2430. err_buffer_queues:
  2431. ql_free_net_req_rsp_queues(qdev);
  2432. err_req_rsp:
  2433. pci_free_consistent(qdev->pdev,
  2434. PAGE_SIZE,
  2435. qdev->shadow_reg_virt_addr,
  2436. qdev->shadow_reg_phy_addr);
  2437. return -ENOMEM;
  2438. }
  2439. static void ql_free_mem_resources(struct ql3_adapter *qdev)
  2440. {
  2441. ql_free_send_free_list(qdev);
  2442. ql_free_large_buffers(qdev);
  2443. ql_free_small_buffers(qdev);
  2444. ql_free_buffer_queues(qdev);
  2445. ql_free_net_req_rsp_queues(qdev);
  2446. if (qdev->shadow_reg_virt_addr != NULL) {
  2447. pci_free_consistent(qdev->pdev,
  2448. PAGE_SIZE,
  2449. qdev->shadow_reg_virt_addr,
  2450. qdev->shadow_reg_phy_addr);
  2451. qdev->shadow_reg_virt_addr = NULL;
  2452. }
  2453. }
  2454. static int ql_init_misc_registers(struct ql3_adapter *qdev)
  2455. {
  2456. struct ql3xxx_local_ram_registers __iomem *local_ram =
  2457. (void __iomem *)qdev->mem_map_registers;
  2458. if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
  2459. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  2460. 2) << 4))
  2461. return -1;
  2462. ql_write_page2_reg(qdev,
  2463. &local_ram->bufletSize, qdev->nvram_data.bufletSize);
  2464. ql_write_page2_reg(qdev,
  2465. &local_ram->maxBufletCount,
  2466. qdev->nvram_data.bufletCount);
  2467. ql_write_page2_reg(qdev,
  2468. &local_ram->freeBufletThresholdLow,
  2469. (qdev->nvram_data.tcpWindowThreshold25 << 16) |
  2470. (qdev->nvram_data.tcpWindowThreshold0));
  2471. ql_write_page2_reg(qdev,
  2472. &local_ram->freeBufletThresholdHigh,
  2473. qdev->nvram_data.tcpWindowThreshold50);
  2474. ql_write_page2_reg(qdev,
  2475. &local_ram->ipHashTableBase,
  2476. (qdev->nvram_data.ipHashTableBaseHi << 16) |
  2477. qdev->nvram_data.ipHashTableBaseLo);
  2478. ql_write_page2_reg(qdev,
  2479. &local_ram->ipHashTableCount,
  2480. qdev->nvram_data.ipHashTableSize);
  2481. ql_write_page2_reg(qdev,
  2482. &local_ram->tcpHashTableBase,
  2483. (qdev->nvram_data.tcpHashTableBaseHi << 16) |
  2484. qdev->nvram_data.tcpHashTableBaseLo);
  2485. ql_write_page2_reg(qdev,
  2486. &local_ram->tcpHashTableCount,
  2487. qdev->nvram_data.tcpHashTableSize);
  2488. ql_write_page2_reg(qdev,
  2489. &local_ram->ncbBase,
  2490. (qdev->nvram_data.ncbTableBaseHi << 16) |
  2491. qdev->nvram_data.ncbTableBaseLo);
  2492. ql_write_page2_reg(qdev,
  2493. &local_ram->maxNcbCount,
  2494. qdev->nvram_data.ncbTableSize);
  2495. ql_write_page2_reg(qdev,
  2496. &local_ram->drbBase,
  2497. (qdev->nvram_data.drbTableBaseHi << 16) |
  2498. qdev->nvram_data.drbTableBaseLo);
  2499. ql_write_page2_reg(qdev,
  2500. &local_ram->maxDrbCount,
  2501. qdev->nvram_data.drbTableSize);
  2502. ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
  2503. return 0;
  2504. }
  2505. static int ql_adapter_initialize(struct ql3_adapter *qdev)
  2506. {
  2507. u32 value;
  2508. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  2509. struct ql3xxx_host_memory_registers __iomem *hmem_regs =
  2510. (void __iomem *)port_regs;
  2511. u32 delay = 10;
  2512. int status = 0;
  2513. if(ql_mii_setup(qdev))
  2514. return -1;
  2515. /* Bring out PHY out of reset */
  2516. ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
  2517. (ISP_SERIAL_PORT_IF_WE |
  2518. (ISP_SERIAL_PORT_IF_WE << 16)));
  2519. qdev->port_link_state = LS_DOWN;
  2520. netif_carrier_off(qdev->ndev);
  2521. /* V2 chip fix for ARS-39168. */
  2522. ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
  2523. (ISP_SERIAL_PORT_IF_SDE |
  2524. (ISP_SERIAL_PORT_IF_SDE << 16)));
  2525. /* Request Queue Registers */
  2526. *((u32 *) (qdev->preq_consumer_index)) = 0;
  2527. atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
  2528. qdev->req_producer_index = 0;
  2529. ql_write_page1_reg(qdev,
  2530. &hmem_regs->reqConsumerIndexAddrHigh,
  2531. qdev->req_consumer_index_phy_addr_high);
  2532. ql_write_page1_reg(qdev,
  2533. &hmem_regs->reqConsumerIndexAddrLow,
  2534. qdev->req_consumer_index_phy_addr_low);
  2535. ql_write_page1_reg(qdev,
  2536. &hmem_regs->reqBaseAddrHigh,
  2537. MS_64BITS(qdev->req_q_phy_addr));
  2538. ql_write_page1_reg(qdev,
  2539. &hmem_regs->reqBaseAddrLow,
  2540. LS_64BITS(qdev->req_q_phy_addr));
  2541. ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
  2542. /* Response Queue Registers */
  2543. *((u16 *) (qdev->prsp_producer_index)) = 0;
  2544. qdev->rsp_consumer_index = 0;
  2545. qdev->rsp_current = qdev->rsp_q_virt_addr;
  2546. ql_write_page1_reg(qdev,
  2547. &hmem_regs->rspProducerIndexAddrHigh,
  2548. qdev->rsp_producer_index_phy_addr_high);
  2549. ql_write_page1_reg(qdev,
  2550. &hmem_regs->rspProducerIndexAddrLow,
  2551. qdev->rsp_producer_index_phy_addr_low);
  2552. ql_write_page1_reg(qdev,
  2553. &hmem_regs->rspBaseAddrHigh,
  2554. MS_64BITS(qdev->rsp_q_phy_addr));
  2555. ql_write_page1_reg(qdev,
  2556. &hmem_regs->rspBaseAddrLow,
  2557. LS_64BITS(qdev->rsp_q_phy_addr));
  2558. ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
  2559. /* Large Buffer Queue */
  2560. ql_write_page1_reg(qdev,
  2561. &hmem_regs->rxLargeQBaseAddrHigh,
  2562. MS_64BITS(qdev->lrg_buf_q_phy_addr));
  2563. ql_write_page1_reg(qdev,
  2564. &hmem_regs->rxLargeQBaseAddrLow,
  2565. LS_64BITS(qdev->lrg_buf_q_phy_addr));
  2566. ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
  2567. ql_write_page1_reg(qdev,
  2568. &hmem_regs->rxLargeBufferLength,
  2569. qdev->lrg_buffer_len);
  2570. /* Small Buffer Queue */
  2571. ql_write_page1_reg(qdev,
  2572. &hmem_regs->rxSmallQBaseAddrHigh,
  2573. MS_64BITS(qdev->small_buf_q_phy_addr));
  2574. ql_write_page1_reg(qdev,
  2575. &hmem_regs->rxSmallQBaseAddrLow,
  2576. LS_64BITS(qdev->small_buf_q_phy_addr));
  2577. ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
  2578. ql_write_page1_reg(qdev,
  2579. &hmem_regs->rxSmallBufferLength,
  2580. QL_SMALL_BUFFER_SIZE);
  2581. qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
  2582. qdev->small_buf_release_cnt = 8;
  2583. qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
  2584. qdev->lrg_buf_release_cnt = 8;
  2585. qdev->lrg_buf_next_free =
  2586. (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
  2587. qdev->small_buf_index = 0;
  2588. qdev->lrg_buf_index = 0;
  2589. qdev->lrg_buf_free_count = 0;
  2590. qdev->lrg_buf_free_head = NULL;
  2591. qdev->lrg_buf_free_tail = NULL;
  2592. ql_write_common_reg(qdev,
  2593. &port_regs->CommonRegs.
  2594. rxSmallQProducerIndex,
  2595. qdev->small_buf_q_producer_index);
  2596. ql_write_common_reg(qdev,
  2597. &port_regs->CommonRegs.
  2598. rxLargeQProducerIndex,
  2599. qdev->lrg_buf_q_producer_index);
  2600. /*
  2601. * Find out if the chip has already been initialized. If it has, then
  2602. * we skip some of the initialization.
  2603. */
  2604. clear_bit(QL_LINK_MASTER, &qdev->flags);
  2605. value = ql_read_page0_reg(qdev, &port_regs->portStatus);
  2606. if ((value & PORT_STATUS_IC) == 0) {
  2607. /* Chip has not been configured yet, so let it rip. */
  2608. if(ql_init_misc_registers(qdev)) {
  2609. status = -1;
  2610. goto out;
  2611. }
  2612. value = qdev->nvram_data.tcpMaxWindowSize;
  2613. ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
  2614. value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
  2615. if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
  2616. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
  2617. * 2) << 13)) {
  2618. status = -1;
  2619. goto out;
  2620. }
  2621. ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
  2622. ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
  2623. (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
  2624. 16) | (INTERNAL_CHIP_SD |
  2625. INTERNAL_CHIP_WE)));
  2626. ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
  2627. }
  2628. if (qdev->mac_index)
  2629. ql_write_page0_reg(qdev,
  2630. &port_regs->mac1MaxFrameLengthReg,
  2631. qdev->max_frame_size);
  2632. else
  2633. ql_write_page0_reg(qdev,
  2634. &port_regs->mac0MaxFrameLengthReg,
  2635. qdev->max_frame_size);
  2636. if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
  2637. (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
  2638. 2) << 7)) {
  2639. status = -1;
  2640. goto out;
  2641. }
  2642. ql_init_scan_mode(qdev);
  2643. ql_get_phy_owner(qdev);
  2644. /* Load the MAC Configuration */
  2645. /* Program lower 32 bits of the MAC address */
  2646. ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
  2647. (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
  2648. ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
  2649. ((qdev->ndev->dev_addr[2] << 24)
  2650. | (qdev->ndev->dev_addr[3] << 16)
  2651. | (qdev->ndev->dev_addr[4] << 8)
  2652. | qdev->ndev->dev_addr[5]));
  2653. /* Program top 16 bits of the MAC address */
  2654. ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
  2655. ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
  2656. ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
  2657. ((qdev->ndev->dev_addr[0] << 8)
  2658. | qdev->ndev->dev_addr[1]));
  2659. /* Enable Primary MAC */
  2660. ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
  2661. ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
  2662. MAC_ADDR_INDIRECT_PTR_REG_PE));
  2663. /* Clear Primary and Secondary IP addresses */
  2664. ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
  2665. ((IP_ADDR_INDEX_REG_MASK << 16) |
  2666. (qdev->mac_index << 2)));
  2667. ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
  2668. ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
  2669. ((IP_ADDR_INDEX_REG_MASK << 16) |
  2670. ((qdev->mac_index << 2) + 1)));
  2671. ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
  2672. ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
  2673. /* Indicate Configuration Complete */
  2674. ql_write_page0_reg(qdev,
  2675. &port_regs->portControl,
  2676. ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
  2677. do {
  2678. value = ql_read_page0_reg(qdev, &port_regs->portStatus);
  2679. if (value & PORT_STATUS_IC)
  2680. break;
  2681. msleep(500);
  2682. } while (--delay);
  2683. if (delay == 0) {
  2684. printk(KERN_ERR PFX
  2685. "%s: Hw Initialization timeout.\n", qdev->ndev->name);
  2686. status = -1;
  2687. goto out;
  2688. }
  2689. /* Enable Ethernet Function */
  2690. if (qdev->device_id == QL3032_DEVICE_ID) {
  2691. value =
  2692. (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
  2693. QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
  2694. QL3032_PORT_CONTROL_ET);
  2695. ql_write_page0_reg(qdev, &port_regs->functionControl,
  2696. ((value << 16) | value));
  2697. } else {
  2698. value =
  2699. (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
  2700. PORT_CONTROL_HH);
  2701. ql_write_page0_reg(qdev, &port_regs->portControl,
  2702. ((value << 16) | value));
  2703. }
  2704. out:
  2705. return status;
  2706. }
  2707. /*
  2708. * Caller holds hw_lock.
  2709. */
  2710. static int ql_adapter_reset(struct ql3_adapter *qdev)
  2711. {
  2712. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  2713. int status = 0;
  2714. u16 value;
  2715. int max_wait_time;
  2716. set_bit(QL_RESET_ACTIVE, &qdev->flags);
  2717. clear_bit(QL_RESET_DONE, &qdev->flags);
  2718. /*
  2719. * Issue soft reset to chip.
  2720. */
  2721. printk(KERN_DEBUG PFX
  2722. "%s: Issue soft reset to chip.\n",
  2723. qdev->ndev->name);
  2724. ql_write_common_reg(qdev,
  2725. &port_regs->CommonRegs.ispControlStatus,
  2726. ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
  2727. /* Wait 3 seconds for reset to complete. */
  2728. printk(KERN_DEBUG PFX
  2729. "%s: Wait 10 milliseconds for reset to complete.\n",
  2730. qdev->ndev->name);
  2731. /* Wait until the firmware tells us the Soft Reset is done */
  2732. max_wait_time = 5;
  2733. do {
  2734. value =
  2735. ql_read_common_reg(qdev,
  2736. &port_regs->CommonRegs.ispControlStatus);
  2737. if ((value & ISP_CONTROL_SR) == 0)
  2738. break;
  2739. ssleep(1);
  2740. } while ((--max_wait_time));
  2741. /*
  2742. * Also, make sure that the Network Reset Interrupt bit has been
  2743. * cleared after the soft reset has taken place.
  2744. */
  2745. value =
  2746. ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
  2747. if (value & ISP_CONTROL_RI) {
  2748. printk(KERN_DEBUG PFX
  2749. "ql_adapter_reset: clearing RI after reset.\n");
  2750. ql_write_common_reg(qdev,
  2751. &port_regs->CommonRegs.
  2752. ispControlStatus,
  2753. ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
  2754. }
  2755. if (max_wait_time == 0) {
  2756. /* Issue Force Soft Reset */
  2757. ql_write_common_reg(qdev,
  2758. &port_regs->CommonRegs.
  2759. ispControlStatus,
  2760. ((ISP_CONTROL_FSR << 16) |
  2761. ISP_CONTROL_FSR));
  2762. /*
  2763. * Wait until the firmware tells us the Force Soft Reset is
  2764. * done
  2765. */
  2766. max_wait_time = 5;
  2767. do {
  2768. value =
  2769. ql_read_common_reg(qdev,
  2770. &port_regs->CommonRegs.
  2771. ispControlStatus);
  2772. if ((value & ISP_CONTROL_FSR) == 0) {
  2773. break;
  2774. }
  2775. ssleep(1);
  2776. } while ((--max_wait_time));
  2777. }
  2778. if (max_wait_time == 0)
  2779. status = 1;
  2780. clear_bit(QL_RESET_ACTIVE, &qdev->flags);
  2781. set_bit(QL_RESET_DONE, &qdev->flags);
  2782. return status;
  2783. }
  2784. static void ql_set_mac_info(struct ql3_adapter *qdev)
  2785. {
  2786. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  2787. u32 value, port_status;
  2788. u8 func_number;
  2789. /* Get the function number */
  2790. value =
  2791. ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
  2792. func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
  2793. port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
  2794. switch (value & ISP_CONTROL_FN_MASK) {
  2795. case ISP_CONTROL_FN0_NET:
  2796. qdev->mac_index = 0;
  2797. qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
  2798. qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
  2799. qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
  2800. qdev->mb_bit_mask = FN0_MA_BITS_MASK;
  2801. qdev->PHYAddr = PORT0_PHY_ADDRESS;
  2802. if (port_status & PORT_STATUS_SM0)
  2803. set_bit(QL_LINK_OPTICAL,&qdev->flags);
  2804. else
  2805. clear_bit(QL_LINK_OPTICAL,&qdev->flags);
  2806. break;
  2807. case ISP_CONTROL_FN1_NET:
  2808. qdev->mac_index = 1;
  2809. qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
  2810. qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
  2811. qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
  2812. qdev->mb_bit_mask = FN1_MA_BITS_MASK;
  2813. qdev->PHYAddr = PORT1_PHY_ADDRESS;
  2814. if (port_status & PORT_STATUS_SM1)
  2815. set_bit(QL_LINK_OPTICAL,&qdev->flags);
  2816. else
  2817. clear_bit(QL_LINK_OPTICAL,&qdev->flags);
  2818. break;
  2819. case ISP_CONTROL_FN0_SCSI:
  2820. case ISP_CONTROL_FN1_SCSI:
  2821. default:
  2822. printk(KERN_DEBUG PFX
  2823. "%s: Invalid function number, ispControlStatus = 0x%x\n",
  2824. qdev->ndev->name,value);
  2825. break;
  2826. }
  2827. qdev->numPorts = qdev->nvram_data.numPorts;
  2828. }
  2829. static void ql_display_dev_info(struct net_device *ndev)
  2830. {
  2831. struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
  2832. struct pci_dev *pdev = qdev->pdev;
  2833. printk(KERN_INFO PFX
  2834. "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
  2835. DRV_NAME, qdev->index, qdev->chip_rev_id,
  2836. (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
  2837. qdev->pci_slot);
  2838. printk(KERN_INFO PFX
  2839. "%s Interface.\n",
  2840. test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
  2841. /*
  2842. * Print PCI bus width/type.
  2843. */
  2844. printk(KERN_INFO PFX
  2845. "Bus interface is %s %s.\n",
  2846. ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
  2847. ((qdev->pci_x) ? "PCI-X" : "PCI"));
  2848. printk(KERN_INFO PFX
  2849. "mem IO base address adjusted = 0x%p\n",
  2850. qdev->mem_map_registers);
  2851. printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
  2852. if (netif_msg_probe(qdev))
  2853. printk(KERN_INFO PFX
  2854. "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
  2855. ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
  2856. ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
  2857. ndev->dev_addr[5]);
  2858. }
  2859. static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
  2860. {
  2861. struct net_device *ndev = qdev->ndev;
  2862. int retval = 0;
  2863. netif_stop_queue(ndev);
  2864. netif_carrier_off(ndev);
  2865. clear_bit(QL_ADAPTER_UP,&qdev->flags);
  2866. clear_bit(QL_LINK_MASTER,&qdev->flags);
  2867. ql_disable_interrupts(qdev);
  2868. free_irq(qdev->pdev->irq, ndev);
  2869. if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
  2870. printk(KERN_INFO PFX
  2871. "%s: calling pci_disable_msi().\n", qdev->ndev->name);
  2872. clear_bit(QL_MSI_ENABLED,&qdev->flags);
  2873. pci_disable_msi(qdev->pdev);
  2874. }
  2875. del_timer_sync(&qdev->adapter_timer);
  2876. netif_poll_disable(ndev);
  2877. if (do_reset) {
  2878. int soft_reset;
  2879. unsigned long hw_flags;
  2880. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  2881. if (ql_wait_for_drvr_lock(qdev)) {
  2882. if ((soft_reset = ql_adapter_reset(qdev))) {
  2883. printk(KERN_ERR PFX
  2884. "%s: ql_adapter_reset(%d) FAILED!\n",
  2885. ndev->name, qdev->index);
  2886. }
  2887. printk(KERN_ERR PFX
  2888. "%s: Releaseing driver lock via chip reset.\n",ndev->name);
  2889. } else {
  2890. printk(KERN_ERR PFX
  2891. "%s: Could not acquire driver lock to do "
  2892. "reset!\n", ndev->name);
  2893. retval = -1;
  2894. }
  2895. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  2896. }
  2897. ql_free_mem_resources(qdev);
  2898. return retval;
  2899. }
  2900. static int ql_adapter_up(struct ql3_adapter *qdev)
  2901. {
  2902. struct net_device *ndev = qdev->ndev;
  2903. int err;
  2904. unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
  2905. unsigned long hw_flags;
  2906. if (ql_alloc_mem_resources(qdev)) {
  2907. printk(KERN_ERR PFX
  2908. "%s Unable to allocate buffers.\n", ndev->name);
  2909. return -ENOMEM;
  2910. }
  2911. if (qdev->msi) {
  2912. if (pci_enable_msi(qdev->pdev)) {
  2913. printk(KERN_ERR PFX
  2914. "%s: User requested MSI, but MSI failed to "
  2915. "initialize. Continuing without MSI.\n",
  2916. qdev->ndev->name);
  2917. qdev->msi = 0;
  2918. } else {
  2919. printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
  2920. set_bit(QL_MSI_ENABLED,&qdev->flags);
  2921. irq_flags &= ~IRQF_SHARED;
  2922. }
  2923. }
  2924. if ((err = request_irq(qdev->pdev->irq,
  2925. ql3xxx_isr,
  2926. irq_flags, ndev->name, ndev))) {
  2927. printk(KERN_ERR PFX
  2928. "%s: Failed to reserve interrupt %d already in use.\n",
  2929. ndev->name, qdev->pdev->irq);
  2930. goto err_irq;
  2931. }
  2932. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  2933. if ((err = ql_wait_for_drvr_lock(qdev))) {
  2934. if ((err = ql_adapter_initialize(qdev))) {
  2935. printk(KERN_ERR PFX
  2936. "%s: Unable to initialize adapter.\n",
  2937. ndev->name);
  2938. goto err_init;
  2939. }
  2940. printk(KERN_ERR PFX
  2941. "%s: Releaseing driver lock.\n",ndev->name);
  2942. ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
  2943. } else {
  2944. printk(KERN_ERR PFX
  2945. "%s: Could not aquire driver lock.\n",
  2946. ndev->name);
  2947. goto err_lock;
  2948. }
  2949. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  2950. set_bit(QL_ADAPTER_UP,&qdev->flags);
  2951. mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
  2952. netif_poll_enable(ndev);
  2953. ql_enable_interrupts(qdev);
  2954. return 0;
  2955. err_init:
  2956. ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
  2957. err_lock:
  2958. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  2959. free_irq(qdev->pdev->irq, ndev);
  2960. err_irq:
  2961. if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
  2962. printk(KERN_INFO PFX
  2963. "%s: calling pci_disable_msi().\n",
  2964. qdev->ndev->name);
  2965. clear_bit(QL_MSI_ENABLED,&qdev->flags);
  2966. pci_disable_msi(qdev->pdev);
  2967. }
  2968. return err;
  2969. }
  2970. static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
  2971. {
  2972. if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
  2973. printk(KERN_ERR PFX
  2974. "%s: Driver up/down cycle failed, "
  2975. "closing device\n",qdev->ndev->name);
  2976. dev_close(qdev->ndev);
  2977. return -1;
  2978. }
  2979. return 0;
  2980. }
  2981. static int ql3xxx_close(struct net_device *ndev)
  2982. {
  2983. struct ql3_adapter *qdev = netdev_priv(ndev);
  2984. /*
  2985. * Wait for device to recover from a reset.
  2986. * (Rarely happens, but possible.)
  2987. */
  2988. while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
  2989. msleep(50);
  2990. ql_adapter_down(qdev,QL_DO_RESET);
  2991. return 0;
  2992. }
  2993. static int ql3xxx_open(struct net_device *ndev)
  2994. {
  2995. struct ql3_adapter *qdev = netdev_priv(ndev);
  2996. return (ql_adapter_up(qdev));
  2997. }
  2998. static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
  2999. {
  3000. struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
  3001. return &qdev->stats;
  3002. }
  3003. static void ql3xxx_set_multicast_list(struct net_device *ndev)
  3004. {
  3005. /*
  3006. * We are manually parsing the list in the net_device structure.
  3007. */
  3008. return;
  3009. }
  3010. static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
  3011. {
  3012. struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
  3013. struct ql3xxx_port_registers __iomem *port_regs =
  3014. qdev->mem_map_registers;
  3015. struct sockaddr *addr = p;
  3016. unsigned long hw_flags;
  3017. if (netif_running(ndev))
  3018. return -EBUSY;
  3019. if (!is_valid_ether_addr(addr->sa_data))
  3020. return -EADDRNOTAVAIL;
  3021. memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
  3022. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  3023. /* Program lower 32 bits of the MAC address */
  3024. ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
  3025. (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
  3026. ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
  3027. ((ndev->dev_addr[2] << 24) | (ndev->
  3028. dev_addr[3] << 16) |
  3029. (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
  3030. /* Program top 16 bits of the MAC address */
  3031. ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
  3032. ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
  3033. ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
  3034. ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
  3035. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  3036. return 0;
  3037. }
  3038. static void ql3xxx_tx_timeout(struct net_device *ndev)
  3039. {
  3040. struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
  3041. printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
  3042. /*
  3043. * Stop the queues, we've got a problem.
  3044. */
  3045. netif_stop_queue(ndev);
  3046. /*
  3047. * Wake up the worker to process this event.
  3048. */
  3049. queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
  3050. }
  3051. static void ql_reset_work(struct work_struct *work)
  3052. {
  3053. struct ql3_adapter *qdev =
  3054. container_of(work, struct ql3_adapter, reset_work.work);
  3055. struct net_device *ndev = qdev->ndev;
  3056. u32 value;
  3057. struct ql_tx_buf_cb *tx_cb;
  3058. int max_wait_time, i;
  3059. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  3060. unsigned long hw_flags;
  3061. if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
  3062. clear_bit(QL_LINK_MASTER,&qdev->flags);
  3063. /*
  3064. * Loop through the active list and return the skb.
  3065. */
  3066. for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
  3067. int j;
  3068. tx_cb = &qdev->tx_buf[i];
  3069. if (tx_cb->skb) {
  3070. printk(KERN_DEBUG PFX
  3071. "%s: Freeing lost SKB.\n",
  3072. qdev->ndev->name);
  3073. pci_unmap_single(qdev->pdev,
  3074. pci_unmap_addr(&tx_cb->map[0], mapaddr),
  3075. pci_unmap_len(&tx_cb->map[0], maplen),
  3076. PCI_DMA_TODEVICE);
  3077. for(j=1;j<tx_cb->seg_count;j++) {
  3078. pci_unmap_page(qdev->pdev,
  3079. pci_unmap_addr(&tx_cb->map[j],mapaddr),
  3080. pci_unmap_len(&tx_cb->map[j],maplen),
  3081. PCI_DMA_TODEVICE);
  3082. }
  3083. dev_kfree_skb(tx_cb->skb);
  3084. tx_cb->skb = NULL;
  3085. }
  3086. }
  3087. printk(KERN_ERR PFX
  3088. "%s: Clearing NRI after reset.\n", qdev->ndev->name);
  3089. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  3090. ql_write_common_reg(qdev,
  3091. &port_regs->CommonRegs.
  3092. ispControlStatus,
  3093. ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
  3094. /*
  3095. * Wait the for Soft Reset to Complete.
  3096. */
  3097. max_wait_time = 10;
  3098. do {
  3099. value = ql_read_common_reg(qdev,
  3100. &port_regs->CommonRegs.
  3101. ispControlStatus);
  3102. if ((value & ISP_CONTROL_SR) == 0) {
  3103. printk(KERN_DEBUG PFX
  3104. "%s: reset completed.\n",
  3105. qdev->ndev->name);
  3106. break;
  3107. }
  3108. if (value & ISP_CONTROL_RI) {
  3109. printk(KERN_DEBUG PFX
  3110. "%s: clearing NRI after reset.\n",
  3111. qdev->ndev->name);
  3112. ql_write_common_reg(qdev,
  3113. &port_regs->
  3114. CommonRegs.
  3115. ispControlStatus,
  3116. ((ISP_CONTROL_RI <<
  3117. 16) | ISP_CONTROL_RI));
  3118. }
  3119. ssleep(1);
  3120. } while (--max_wait_time);
  3121. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  3122. if (value & ISP_CONTROL_SR) {
  3123. /*
  3124. * Set the reset flags and clear the board again.
  3125. * Nothing else to do...
  3126. */
  3127. printk(KERN_ERR PFX
  3128. "%s: Timed out waiting for reset to "
  3129. "complete.\n", ndev->name);
  3130. printk(KERN_ERR PFX
  3131. "%s: Do a reset.\n", ndev->name);
  3132. clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
  3133. clear_bit(QL_RESET_START,&qdev->flags);
  3134. ql_cycle_adapter(qdev,QL_DO_RESET);
  3135. return;
  3136. }
  3137. clear_bit(QL_RESET_ACTIVE,&qdev->flags);
  3138. clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
  3139. clear_bit(QL_RESET_START,&qdev->flags);
  3140. ql_cycle_adapter(qdev,QL_NO_RESET);
  3141. }
  3142. }
  3143. static void ql_tx_timeout_work(struct work_struct *work)
  3144. {
  3145. struct ql3_adapter *qdev =
  3146. container_of(work, struct ql3_adapter, tx_timeout_work.work);
  3147. ql_cycle_adapter(qdev, QL_DO_RESET);
  3148. }
  3149. static void ql_get_board_info(struct ql3_adapter *qdev)
  3150. {
  3151. struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  3152. u32 value;
  3153. value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
  3154. qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
  3155. if (value & PORT_STATUS_64)
  3156. qdev->pci_width = 64;
  3157. else
  3158. qdev->pci_width = 32;
  3159. if (value & PORT_STATUS_X)
  3160. qdev->pci_x = 1;
  3161. else
  3162. qdev->pci_x = 0;
  3163. qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
  3164. }
  3165. static void ql3xxx_timer(unsigned long ptr)
  3166. {
  3167. struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
  3168. if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
  3169. printk(KERN_DEBUG PFX
  3170. "%s: Reset in progress.\n",
  3171. qdev->ndev->name);
  3172. goto end;
  3173. }
  3174. ql_link_state_machine(qdev);
  3175. /* Restart timer on 2 second interval. */
  3176. end:
  3177. mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
  3178. }
  3179. static int __devinit ql3xxx_probe(struct pci_dev *pdev,
  3180. const struct pci_device_id *pci_entry)
  3181. {
  3182. struct net_device *ndev = NULL;
  3183. struct ql3_adapter *qdev = NULL;
  3184. static int cards_found = 0;
  3185. int pci_using_dac, err;
  3186. err = pci_enable_device(pdev);
  3187. if (err) {
  3188. printk(KERN_ERR PFX "%s cannot enable PCI device\n",
  3189. pci_name(pdev));
  3190. goto err_out;
  3191. }
  3192. err = pci_request_regions(pdev, DRV_NAME);
  3193. if (err) {
  3194. printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
  3195. pci_name(pdev));
  3196. goto err_out_disable_pdev;
  3197. }
  3198. pci_set_master(pdev);
  3199. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  3200. pci_using_dac = 1;
  3201. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  3202. } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
  3203. pci_using_dac = 0;
  3204. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  3205. }
  3206. if (err) {
  3207. printk(KERN_ERR PFX "%s no usable DMA configuration\n",
  3208. pci_name(pdev));
  3209. goto err_out_free_regions;
  3210. }
  3211. ndev = alloc_etherdev(sizeof(struct ql3_adapter));
  3212. if (!ndev) {
  3213. printk(KERN_ERR PFX "%s could not alloc etherdev\n",
  3214. pci_name(pdev));
  3215. err = -ENOMEM;
  3216. goto err_out_free_regions;
  3217. }
  3218. SET_MODULE_OWNER(ndev);
  3219. SET_NETDEV_DEV(ndev, &pdev->dev);
  3220. pci_set_drvdata(pdev, ndev);
  3221. qdev = netdev_priv(ndev);
  3222. qdev->index = cards_found;
  3223. qdev->ndev = ndev;
  3224. qdev->pdev = pdev;
  3225. qdev->device_id = pci_entry->device;
  3226. qdev->port_link_state = LS_DOWN;
  3227. if (msi)
  3228. qdev->msi = 1;
  3229. qdev->msg_enable = netif_msg_init(debug, default_msg);
  3230. if (pci_using_dac)
  3231. ndev->features |= NETIF_F_HIGHDMA;
  3232. if (qdev->device_id == QL3032_DEVICE_ID)
  3233. ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
  3234. qdev->mem_map_registers =
  3235. ioremap_nocache(pci_resource_start(pdev, 1),
  3236. pci_resource_len(qdev->pdev, 1));
  3237. if (!qdev->mem_map_registers) {
  3238. printk(KERN_ERR PFX "%s: cannot map device registers\n",
  3239. pci_name(pdev));
  3240. err = -EIO;
  3241. goto err_out_free_ndev;
  3242. }
  3243. spin_lock_init(&qdev->adapter_lock);
  3244. spin_lock_init(&qdev->hw_lock);
  3245. /* Set driver entry points */
  3246. ndev->open = ql3xxx_open;
  3247. ndev->hard_start_xmit = ql3xxx_send;
  3248. ndev->stop = ql3xxx_close;
  3249. ndev->get_stats = ql3xxx_get_stats;
  3250. ndev->set_multicast_list = ql3xxx_set_multicast_list;
  3251. SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
  3252. ndev->set_mac_address = ql3xxx_set_mac_address;
  3253. ndev->tx_timeout = ql3xxx_tx_timeout;
  3254. ndev->watchdog_timeo = 5 * HZ;
  3255. ndev->poll = &ql_poll;
  3256. ndev->weight = 64;
  3257. ndev->irq = pdev->irq;
  3258. /* make sure the EEPROM is good */
  3259. if (ql_get_nvram_params(qdev)) {
  3260. printk(KERN_ALERT PFX
  3261. "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
  3262. qdev->index);
  3263. err = -EIO;
  3264. goto err_out_iounmap;
  3265. }
  3266. ql_set_mac_info(qdev);
  3267. /* Validate and set parameters */
  3268. if (qdev->mac_index) {
  3269. ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
  3270. memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
  3271. ETH_ALEN);
  3272. } else {
  3273. ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
  3274. memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
  3275. ETH_ALEN);
  3276. }
  3277. memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
  3278. ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
  3279. /* Turn off support for multicasting */
  3280. ndev->flags &= ~IFF_MULTICAST;
  3281. /* Record PCI bus information. */
  3282. ql_get_board_info(qdev);
  3283. /*
  3284. * Set the Maximum Memory Read Byte Count value. We do this to handle
  3285. * jumbo frames.
  3286. */
  3287. if (qdev->pci_x) {
  3288. pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
  3289. }
  3290. err = register_netdev(ndev);
  3291. if (err) {
  3292. printk(KERN_ERR PFX "%s: cannot register net device\n",
  3293. pci_name(pdev));
  3294. goto err_out_iounmap;
  3295. }
  3296. /* we're going to reset, so assume we have no link for now */
  3297. netif_carrier_off(ndev);
  3298. netif_stop_queue(ndev);
  3299. qdev->workqueue = create_singlethread_workqueue(ndev->name);
  3300. INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
  3301. INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
  3302. init_timer(&qdev->adapter_timer);
  3303. qdev->adapter_timer.function = ql3xxx_timer;
  3304. qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
  3305. qdev->adapter_timer.data = (unsigned long)qdev;
  3306. if(!cards_found) {
  3307. printk(KERN_ALERT PFX "%s\n", DRV_STRING);
  3308. printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
  3309. DRV_NAME, DRV_VERSION);
  3310. }
  3311. ql_display_dev_info(ndev);
  3312. cards_found++;
  3313. return 0;
  3314. err_out_iounmap:
  3315. iounmap(qdev->mem_map_registers);
  3316. err_out_free_ndev:
  3317. free_netdev(ndev);
  3318. err_out_free_regions:
  3319. pci_release_regions(pdev);
  3320. err_out_disable_pdev:
  3321. pci_disable_device(pdev);
  3322. pci_set_drvdata(pdev, NULL);
  3323. err_out:
  3324. return err;
  3325. }
  3326. static void __devexit ql3xxx_remove(struct pci_dev *pdev)
  3327. {
  3328. struct net_device *ndev = pci_get_drvdata(pdev);
  3329. struct ql3_adapter *qdev = netdev_priv(ndev);
  3330. unregister_netdev(ndev);
  3331. qdev = netdev_priv(ndev);
  3332. ql_disable_interrupts(qdev);
  3333. if (qdev->workqueue) {
  3334. cancel_delayed_work(&qdev->reset_work);
  3335. cancel_delayed_work(&qdev->tx_timeout_work);
  3336. destroy_workqueue(qdev->workqueue);
  3337. qdev->workqueue = NULL;
  3338. }
  3339. iounmap(qdev->mem_map_registers);
  3340. pci_release_regions(pdev);
  3341. pci_set_drvdata(pdev, NULL);
  3342. free_netdev(ndev);
  3343. }
  3344. static struct pci_driver ql3xxx_driver = {
  3345. .name = DRV_NAME,
  3346. .id_table = ql3xxx_pci_tbl,
  3347. .probe = ql3xxx_probe,
  3348. .remove = __devexit_p(ql3xxx_remove),
  3349. };
  3350. static int __init ql3xxx_init_module(void)
  3351. {
  3352. return pci_register_driver(&ql3xxx_driver);
  3353. }
  3354. static void __exit ql3xxx_exit(void)
  3355. {
  3356. pci_unregister_driver(&ql3xxx_driver);
  3357. }
  3358. module_init(ql3xxx_init_module);
  3359. module_exit(ql3xxx_exit);