pcnet32.c 83 KB

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  1. /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
  2. /*
  3. * Copyright 1996-1999 Thomas Bogendoerfer
  4. *
  5. * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
  6. *
  7. * Copyright 1993 United States Government as represented by the
  8. * Director, National Security Agency.
  9. *
  10. * This software may be used and distributed according to the terms
  11. * of the GNU General Public License, incorporated herein by reference.
  12. *
  13. * This driver is for PCnet32 and PCnetPCI based ethercards
  14. */
  15. /**************************************************************************
  16. * 23 Oct, 2000.
  17. * Fixed a few bugs, related to running the controller in 32bit mode.
  18. *
  19. * Carsten Langgaard, carstenl@mips.com
  20. * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  21. *
  22. *************************************************************************/
  23. #define DRV_NAME "pcnet32"
  24. #ifdef CONFIG_PCNET32_NAPI
  25. #define DRV_VERSION "1.33-NAPI"
  26. #else
  27. #define DRV_VERSION "1.33"
  28. #endif
  29. #define DRV_RELDATE "27.Jun.2006"
  30. #define PFX DRV_NAME ": "
  31. static const char *const version =
  32. DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  33. #include <linux/module.h>
  34. #include <linux/kernel.h>
  35. #include <linux/string.h>
  36. #include <linux/errno.h>
  37. #include <linux/ioport.h>
  38. #include <linux/slab.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/pci.h>
  41. #include <linux/delay.h>
  42. #include <linux/init.h>
  43. #include <linux/ethtool.h>
  44. #include <linux/mii.h>
  45. #include <linux/crc32.h>
  46. #include <linux/netdevice.h>
  47. #include <linux/etherdevice.h>
  48. #include <linux/skbuff.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/moduleparam.h>
  51. #include <linux/bitops.h>
  52. #include <asm/dma.h>
  53. #include <asm/io.h>
  54. #include <asm/uaccess.h>
  55. #include <asm/irq.h>
  56. /*
  57. * PCI device identifiers for "new style" Linux PCI Device Drivers
  58. */
  59. static struct pci_device_id pcnet32_pci_tbl[] = {
  60. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  61. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  62. /*
  63. * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  64. * the incorrect vendor id.
  65. */
  66. { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  67. .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  68. { } /* terminate list */
  69. };
  70. MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  71. static int cards_found;
  72. /*
  73. * VLB I/O addresses
  74. */
  75. static unsigned int pcnet32_portlist[] __initdata =
  76. { 0x300, 0x320, 0x340, 0x360, 0 };
  77. static int pcnet32_debug = 0;
  78. static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  79. static int pcnet32vlb; /* check for VLB cards ? */
  80. static struct net_device *pcnet32_dev;
  81. static int max_interrupt_work = 2;
  82. static int rx_copybreak = 200;
  83. #define PCNET32_PORT_AUI 0x00
  84. #define PCNET32_PORT_10BT 0x01
  85. #define PCNET32_PORT_GPSI 0x02
  86. #define PCNET32_PORT_MII 0x03
  87. #define PCNET32_PORT_PORTSEL 0x03
  88. #define PCNET32_PORT_ASEL 0x04
  89. #define PCNET32_PORT_100 0x40
  90. #define PCNET32_PORT_FD 0x80
  91. #define PCNET32_DMA_MASK 0xffffffff
  92. #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
  93. #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
  94. /*
  95. * table to translate option values from tulip
  96. * to internal options
  97. */
  98. static const unsigned char options_mapping[] = {
  99. PCNET32_PORT_ASEL, /* 0 Auto-select */
  100. PCNET32_PORT_AUI, /* 1 BNC/AUI */
  101. PCNET32_PORT_AUI, /* 2 AUI/BNC */
  102. PCNET32_PORT_ASEL, /* 3 not supported */
  103. PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
  104. PCNET32_PORT_ASEL, /* 5 not supported */
  105. PCNET32_PORT_ASEL, /* 6 not supported */
  106. PCNET32_PORT_ASEL, /* 7 not supported */
  107. PCNET32_PORT_ASEL, /* 8 not supported */
  108. PCNET32_PORT_MII, /* 9 MII 10baseT */
  109. PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
  110. PCNET32_PORT_MII, /* 11 MII (autosel) */
  111. PCNET32_PORT_10BT, /* 12 10BaseT */
  112. PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
  113. /* 14 MII 100BaseTx-FD */
  114. PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
  115. PCNET32_PORT_ASEL /* 15 not supported */
  116. };
  117. static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
  118. "Loopback test (offline)"
  119. };
  120. #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
  121. #define PCNET32_NUM_REGS 136
  122. #define MAX_UNITS 8 /* More are supported, limit only on options */
  123. static int options[MAX_UNITS];
  124. static int full_duplex[MAX_UNITS];
  125. static int homepna[MAX_UNITS];
  126. /*
  127. * Theory of Operation
  128. *
  129. * This driver uses the same software structure as the normal lance
  130. * driver. So look for a verbose description in lance.c. The differences
  131. * to the normal lance driver is the use of the 32bit mode of PCnet32
  132. * and PCnetPCI chips. Because these chips are 32bit chips, there is no
  133. * 16MB limitation and we don't need bounce buffers.
  134. */
  135. /*
  136. * Set the number of Tx and Rx buffers, using Log_2(# buffers).
  137. * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
  138. * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
  139. */
  140. #ifndef PCNET32_LOG_TX_BUFFERS
  141. #define PCNET32_LOG_TX_BUFFERS 4
  142. #define PCNET32_LOG_RX_BUFFERS 5
  143. #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
  144. #define PCNET32_LOG_MAX_RX_BUFFERS 9
  145. #endif
  146. #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
  147. #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
  148. #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
  149. #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
  150. #define PKT_BUF_SZ 1544
  151. /* Offsets from base I/O address. */
  152. #define PCNET32_WIO_RDP 0x10
  153. #define PCNET32_WIO_RAP 0x12
  154. #define PCNET32_WIO_RESET 0x14
  155. #define PCNET32_WIO_BDP 0x16
  156. #define PCNET32_DWIO_RDP 0x10
  157. #define PCNET32_DWIO_RAP 0x14
  158. #define PCNET32_DWIO_RESET 0x18
  159. #define PCNET32_DWIO_BDP 0x1C
  160. #define PCNET32_TOTAL_SIZE 0x20
  161. #define CSR0 0
  162. #define CSR0_INIT 0x1
  163. #define CSR0_START 0x2
  164. #define CSR0_STOP 0x4
  165. #define CSR0_TXPOLL 0x8
  166. #define CSR0_INTEN 0x40
  167. #define CSR0_IDON 0x0100
  168. #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
  169. #define PCNET32_INIT_LOW 1
  170. #define PCNET32_INIT_HIGH 2
  171. #define CSR3 3
  172. #define CSR4 4
  173. #define CSR5 5
  174. #define CSR5_SUSPEND 0x0001
  175. #define CSR15 15
  176. #define PCNET32_MC_FILTER 8
  177. #define PCNET32_79C970A 0x2621
  178. /* The PCNET32 Rx and Tx ring descriptors. */
  179. struct pcnet32_rx_head {
  180. u32 base;
  181. s16 buf_length; /* two`s complement of length */
  182. s16 status;
  183. u32 msg_length;
  184. u32 reserved;
  185. };
  186. struct pcnet32_tx_head {
  187. u32 base;
  188. s16 length; /* two`s complement of length */
  189. s16 status;
  190. u32 misc;
  191. u32 reserved;
  192. };
  193. /* The PCNET32 32-Bit initialization block, described in databook. */
  194. struct pcnet32_init_block {
  195. u16 mode;
  196. u16 tlen_rlen;
  197. u8 phys_addr[6];
  198. u16 reserved;
  199. u32 filter[2];
  200. /* Receive and transmit ring base, along with extra bits. */
  201. u32 rx_ring;
  202. u32 tx_ring;
  203. };
  204. /* PCnet32 access functions */
  205. struct pcnet32_access {
  206. u16 (*read_csr) (unsigned long, int);
  207. void (*write_csr) (unsigned long, int, u16);
  208. u16 (*read_bcr) (unsigned long, int);
  209. void (*write_bcr) (unsigned long, int, u16);
  210. u16 (*read_rap) (unsigned long);
  211. void (*write_rap) (unsigned long, u16);
  212. void (*reset) (unsigned long);
  213. };
  214. /*
  215. * The first field of pcnet32_private is read by the ethernet device
  216. * so the structure should be allocated using pci_alloc_consistent().
  217. */
  218. struct pcnet32_private {
  219. struct pcnet32_init_block init_block;
  220. /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
  221. struct pcnet32_rx_head *rx_ring;
  222. struct pcnet32_tx_head *tx_ring;
  223. dma_addr_t dma_addr;/* DMA address of beginning of this
  224. object, returned by pci_alloc_consistent */
  225. struct pci_dev *pci_dev;
  226. const char *name;
  227. /* The saved address of a sent-in-place packet/buffer, for skfree(). */
  228. struct sk_buff **tx_skbuff;
  229. struct sk_buff **rx_skbuff;
  230. dma_addr_t *tx_dma_addr;
  231. dma_addr_t *rx_dma_addr;
  232. struct pcnet32_access a;
  233. spinlock_t lock; /* Guard lock */
  234. unsigned int cur_rx, cur_tx; /* The next free ring entry */
  235. unsigned int rx_ring_size; /* current rx ring size */
  236. unsigned int tx_ring_size; /* current tx ring size */
  237. unsigned int rx_mod_mask; /* rx ring modular mask */
  238. unsigned int tx_mod_mask; /* tx ring modular mask */
  239. unsigned short rx_len_bits;
  240. unsigned short tx_len_bits;
  241. dma_addr_t rx_ring_dma_addr;
  242. dma_addr_t tx_ring_dma_addr;
  243. unsigned int dirty_rx, /* ring entries to be freed. */
  244. dirty_tx;
  245. struct net_device_stats stats;
  246. char tx_full;
  247. char phycount; /* number of phys found */
  248. int options;
  249. unsigned int shared_irq:1, /* shared irq possible */
  250. dxsuflo:1, /* disable transmit stop on uflo */
  251. mii:1; /* mii port available */
  252. struct net_device *next;
  253. struct mii_if_info mii_if;
  254. struct timer_list watchdog_timer;
  255. struct timer_list blink_timer;
  256. u32 msg_enable; /* debug message level */
  257. /* each bit indicates an available PHY */
  258. u32 phymask;
  259. unsigned short chip_version; /* which variant this is */
  260. };
  261. static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
  262. static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
  263. static int pcnet32_open(struct net_device *);
  264. static int pcnet32_init_ring(struct net_device *);
  265. static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
  266. static void pcnet32_tx_timeout(struct net_device *dev);
  267. static irqreturn_t pcnet32_interrupt(int, void *);
  268. static int pcnet32_close(struct net_device *);
  269. static struct net_device_stats *pcnet32_get_stats(struct net_device *);
  270. static void pcnet32_load_multicast(struct net_device *dev);
  271. static void pcnet32_set_multicast_list(struct net_device *);
  272. static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
  273. static void pcnet32_watchdog(struct net_device *);
  274. static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
  275. static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
  276. int val);
  277. static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
  278. static void pcnet32_ethtool_test(struct net_device *dev,
  279. struct ethtool_test *eth_test, u64 * data);
  280. static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
  281. static int pcnet32_phys_id(struct net_device *dev, u32 data);
  282. static void pcnet32_led_blink_callback(struct net_device *dev);
  283. static int pcnet32_get_regs_len(struct net_device *dev);
  284. static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  285. void *ptr);
  286. static void pcnet32_purge_tx_ring(struct net_device *dev);
  287. static int pcnet32_alloc_ring(struct net_device *dev, char *name);
  288. static void pcnet32_free_ring(struct net_device *dev);
  289. static void pcnet32_check_media(struct net_device *dev, int verbose);
  290. static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
  291. {
  292. outw(index, addr + PCNET32_WIO_RAP);
  293. return inw(addr + PCNET32_WIO_RDP);
  294. }
  295. static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
  296. {
  297. outw(index, addr + PCNET32_WIO_RAP);
  298. outw(val, addr + PCNET32_WIO_RDP);
  299. }
  300. static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
  301. {
  302. outw(index, addr + PCNET32_WIO_RAP);
  303. return inw(addr + PCNET32_WIO_BDP);
  304. }
  305. static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
  306. {
  307. outw(index, addr + PCNET32_WIO_RAP);
  308. outw(val, addr + PCNET32_WIO_BDP);
  309. }
  310. static u16 pcnet32_wio_read_rap(unsigned long addr)
  311. {
  312. return inw(addr + PCNET32_WIO_RAP);
  313. }
  314. static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
  315. {
  316. outw(val, addr + PCNET32_WIO_RAP);
  317. }
  318. static void pcnet32_wio_reset(unsigned long addr)
  319. {
  320. inw(addr + PCNET32_WIO_RESET);
  321. }
  322. static int pcnet32_wio_check(unsigned long addr)
  323. {
  324. outw(88, addr + PCNET32_WIO_RAP);
  325. return (inw(addr + PCNET32_WIO_RAP) == 88);
  326. }
  327. static struct pcnet32_access pcnet32_wio = {
  328. .read_csr = pcnet32_wio_read_csr,
  329. .write_csr = pcnet32_wio_write_csr,
  330. .read_bcr = pcnet32_wio_read_bcr,
  331. .write_bcr = pcnet32_wio_write_bcr,
  332. .read_rap = pcnet32_wio_read_rap,
  333. .write_rap = pcnet32_wio_write_rap,
  334. .reset = pcnet32_wio_reset
  335. };
  336. static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
  337. {
  338. outl(index, addr + PCNET32_DWIO_RAP);
  339. return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
  340. }
  341. static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
  342. {
  343. outl(index, addr + PCNET32_DWIO_RAP);
  344. outl(val, addr + PCNET32_DWIO_RDP);
  345. }
  346. static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
  347. {
  348. outl(index, addr + PCNET32_DWIO_RAP);
  349. return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
  350. }
  351. static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
  352. {
  353. outl(index, addr + PCNET32_DWIO_RAP);
  354. outl(val, addr + PCNET32_DWIO_BDP);
  355. }
  356. static u16 pcnet32_dwio_read_rap(unsigned long addr)
  357. {
  358. return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
  359. }
  360. static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
  361. {
  362. outl(val, addr + PCNET32_DWIO_RAP);
  363. }
  364. static void pcnet32_dwio_reset(unsigned long addr)
  365. {
  366. inl(addr + PCNET32_DWIO_RESET);
  367. }
  368. static int pcnet32_dwio_check(unsigned long addr)
  369. {
  370. outl(88, addr + PCNET32_DWIO_RAP);
  371. return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
  372. }
  373. static struct pcnet32_access pcnet32_dwio = {
  374. .read_csr = pcnet32_dwio_read_csr,
  375. .write_csr = pcnet32_dwio_write_csr,
  376. .read_bcr = pcnet32_dwio_read_bcr,
  377. .write_bcr = pcnet32_dwio_write_bcr,
  378. .read_rap = pcnet32_dwio_read_rap,
  379. .write_rap = pcnet32_dwio_write_rap,
  380. .reset = pcnet32_dwio_reset
  381. };
  382. static void pcnet32_netif_stop(struct net_device *dev)
  383. {
  384. dev->trans_start = jiffies;
  385. netif_poll_disable(dev);
  386. netif_tx_disable(dev);
  387. }
  388. static void pcnet32_netif_start(struct net_device *dev)
  389. {
  390. netif_wake_queue(dev);
  391. netif_poll_enable(dev);
  392. }
  393. /*
  394. * Allocate space for the new sized tx ring.
  395. * Free old resources
  396. * Save new resources.
  397. * Any failure keeps old resources.
  398. * Must be called with lp->lock held.
  399. */
  400. static void pcnet32_realloc_tx_ring(struct net_device *dev,
  401. struct pcnet32_private *lp,
  402. unsigned int size)
  403. {
  404. dma_addr_t new_ring_dma_addr;
  405. dma_addr_t *new_dma_addr_list;
  406. struct pcnet32_tx_head *new_tx_ring;
  407. struct sk_buff **new_skb_list;
  408. pcnet32_purge_tx_ring(dev);
  409. new_tx_ring = pci_alloc_consistent(lp->pci_dev,
  410. sizeof(struct pcnet32_tx_head) *
  411. (1 << size),
  412. &new_ring_dma_addr);
  413. if (new_tx_ring == NULL) {
  414. if (netif_msg_drv(lp))
  415. printk("\n" KERN_ERR
  416. "%s: Consistent memory allocation failed.\n",
  417. dev->name);
  418. return;
  419. }
  420. memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
  421. new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
  422. GFP_ATOMIC);
  423. if (!new_dma_addr_list) {
  424. if (netif_msg_drv(lp))
  425. printk("\n" KERN_ERR
  426. "%s: Memory allocation failed.\n", dev->name);
  427. goto free_new_tx_ring;
  428. }
  429. new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
  430. GFP_ATOMIC);
  431. if (!new_skb_list) {
  432. if (netif_msg_drv(lp))
  433. printk("\n" KERN_ERR
  434. "%s: Memory allocation failed.\n", dev->name);
  435. goto free_new_lists;
  436. }
  437. kfree(lp->tx_skbuff);
  438. kfree(lp->tx_dma_addr);
  439. pci_free_consistent(lp->pci_dev,
  440. sizeof(struct pcnet32_tx_head) *
  441. lp->tx_ring_size, lp->tx_ring,
  442. lp->tx_ring_dma_addr);
  443. lp->tx_ring_size = (1 << size);
  444. lp->tx_mod_mask = lp->tx_ring_size - 1;
  445. lp->tx_len_bits = (size << 12);
  446. lp->tx_ring = new_tx_ring;
  447. lp->tx_ring_dma_addr = new_ring_dma_addr;
  448. lp->tx_dma_addr = new_dma_addr_list;
  449. lp->tx_skbuff = new_skb_list;
  450. return;
  451. free_new_lists:
  452. kfree(new_dma_addr_list);
  453. free_new_tx_ring:
  454. pci_free_consistent(lp->pci_dev,
  455. sizeof(struct pcnet32_tx_head) *
  456. (1 << size),
  457. new_tx_ring,
  458. new_ring_dma_addr);
  459. return;
  460. }
  461. /*
  462. * Allocate space for the new sized rx ring.
  463. * Re-use old receive buffers.
  464. * alloc extra buffers
  465. * free unneeded buffers
  466. * free unneeded buffers
  467. * Save new resources.
  468. * Any failure keeps old resources.
  469. * Must be called with lp->lock held.
  470. */
  471. static void pcnet32_realloc_rx_ring(struct net_device *dev,
  472. struct pcnet32_private *lp,
  473. unsigned int size)
  474. {
  475. dma_addr_t new_ring_dma_addr;
  476. dma_addr_t *new_dma_addr_list;
  477. struct pcnet32_rx_head *new_rx_ring;
  478. struct sk_buff **new_skb_list;
  479. int new, overlap;
  480. new_rx_ring = pci_alloc_consistent(lp->pci_dev,
  481. sizeof(struct pcnet32_rx_head) *
  482. (1 << size),
  483. &new_ring_dma_addr);
  484. if (new_rx_ring == NULL) {
  485. if (netif_msg_drv(lp))
  486. printk("\n" KERN_ERR
  487. "%s: Consistent memory allocation failed.\n",
  488. dev->name);
  489. return;
  490. }
  491. memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
  492. new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
  493. GFP_ATOMIC);
  494. if (!new_dma_addr_list) {
  495. if (netif_msg_drv(lp))
  496. printk("\n" KERN_ERR
  497. "%s: Memory allocation failed.\n", dev->name);
  498. goto free_new_rx_ring;
  499. }
  500. new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
  501. GFP_ATOMIC);
  502. if (!new_skb_list) {
  503. if (netif_msg_drv(lp))
  504. printk("\n" KERN_ERR
  505. "%s: Memory allocation failed.\n", dev->name);
  506. goto free_new_lists;
  507. }
  508. /* first copy the current receive buffers */
  509. overlap = min(size, lp->rx_ring_size);
  510. for (new = 0; new < overlap; new++) {
  511. new_rx_ring[new] = lp->rx_ring[new];
  512. new_dma_addr_list[new] = lp->rx_dma_addr[new];
  513. new_skb_list[new] = lp->rx_skbuff[new];
  514. }
  515. /* now allocate any new buffers needed */
  516. for (; new < size; new++ ) {
  517. struct sk_buff *rx_skbuff;
  518. new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
  519. if (!(rx_skbuff = new_skb_list[new])) {
  520. /* keep the original lists and buffers */
  521. if (netif_msg_drv(lp))
  522. printk(KERN_ERR
  523. "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
  524. dev->name);
  525. goto free_all_new;
  526. }
  527. skb_reserve(rx_skbuff, 2);
  528. new_dma_addr_list[new] =
  529. pci_map_single(lp->pci_dev, rx_skbuff->data,
  530. PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
  531. new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
  532. new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
  533. new_rx_ring[new].status = le16_to_cpu(0x8000);
  534. }
  535. /* and free any unneeded buffers */
  536. for (; new < lp->rx_ring_size; new++) {
  537. if (lp->rx_skbuff[new]) {
  538. pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
  539. PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
  540. dev_kfree_skb(lp->rx_skbuff[new]);
  541. }
  542. }
  543. kfree(lp->rx_skbuff);
  544. kfree(lp->rx_dma_addr);
  545. pci_free_consistent(lp->pci_dev,
  546. sizeof(struct pcnet32_rx_head) *
  547. lp->rx_ring_size, lp->rx_ring,
  548. lp->rx_ring_dma_addr);
  549. lp->rx_ring_size = (1 << size);
  550. lp->rx_mod_mask = lp->rx_ring_size - 1;
  551. lp->rx_len_bits = (size << 4);
  552. lp->rx_ring = new_rx_ring;
  553. lp->rx_ring_dma_addr = new_ring_dma_addr;
  554. lp->rx_dma_addr = new_dma_addr_list;
  555. lp->rx_skbuff = new_skb_list;
  556. return;
  557. free_all_new:
  558. for (; --new >= lp->rx_ring_size; ) {
  559. if (new_skb_list[new]) {
  560. pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
  561. PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
  562. dev_kfree_skb(new_skb_list[new]);
  563. }
  564. }
  565. kfree(new_skb_list);
  566. free_new_lists:
  567. kfree(new_dma_addr_list);
  568. free_new_rx_ring:
  569. pci_free_consistent(lp->pci_dev,
  570. sizeof(struct pcnet32_rx_head) *
  571. (1 << size),
  572. new_rx_ring,
  573. new_ring_dma_addr);
  574. return;
  575. }
  576. static void pcnet32_purge_rx_ring(struct net_device *dev)
  577. {
  578. struct pcnet32_private *lp = dev->priv;
  579. int i;
  580. /* free all allocated skbuffs */
  581. for (i = 0; i < lp->rx_ring_size; i++) {
  582. lp->rx_ring[i].status = 0; /* CPU owns buffer */
  583. wmb(); /* Make sure adapter sees owner change */
  584. if (lp->rx_skbuff[i]) {
  585. pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
  586. PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
  587. dev_kfree_skb_any(lp->rx_skbuff[i]);
  588. }
  589. lp->rx_skbuff[i] = NULL;
  590. lp->rx_dma_addr[i] = 0;
  591. }
  592. }
  593. #ifdef CONFIG_NET_POLL_CONTROLLER
  594. static void pcnet32_poll_controller(struct net_device *dev)
  595. {
  596. disable_irq(dev->irq);
  597. pcnet32_interrupt(0, dev);
  598. enable_irq(dev->irq);
  599. }
  600. #endif
  601. static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  602. {
  603. struct pcnet32_private *lp = dev->priv;
  604. unsigned long flags;
  605. int r = -EOPNOTSUPP;
  606. if (lp->mii) {
  607. spin_lock_irqsave(&lp->lock, flags);
  608. mii_ethtool_gset(&lp->mii_if, cmd);
  609. spin_unlock_irqrestore(&lp->lock, flags);
  610. r = 0;
  611. }
  612. return r;
  613. }
  614. static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  615. {
  616. struct pcnet32_private *lp = dev->priv;
  617. unsigned long flags;
  618. int r = -EOPNOTSUPP;
  619. if (lp->mii) {
  620. spin_lock_irqsave(&lp->lock, flags);
  621. r = mii_ethtool_sset(&lp->mii_if, cmd);
  622. spin_unlock_irqrestore(&lp->lock, flags);
  623. }
  624. return r;
  625. }
  626. static void pcnet32_get_drvinfo(struct net_device *dev,
  627. struct ethtool_drvinfo *info)
  628. {
  629. struct pcnet32_private *lp = dev->priv;
  630. strcpy(info->driver, DRV_NAME);
  631. strcpy(info->version, DRV_VERSION);
  632. if (lp->pci_dev)
  633. strcpy(info->bus_info, pci_name(lp->pci_dev));
  634. else
  635. sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
  636. }
  637. static u32 pcnet32_get_link(struct net_device *dev)
  638. {
  639. struct pcnet32_private *lp = dev->priv;
  640. unsigned long flags;
  641. int r;
  642. spin_lock_irqsave(&lp->lock, flags);
  643. if (lp->mii) {
  644. r = mii_link_ok(&lp->mii_if);
  645. } else if (lp->chip_version >= PCNET32_79C970A) {
  646. ulong ioaddr = dev->base_addr; /* card base I/O address */
  647. r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
  648. } else { /* can not detect link on really old chips */
  649. r = 1;
  650. }
  651. spin_unlock_irqrestore(&lp->lock, flags);
  652. return r;
  653. }
  654. static u32 pcnet32_get_msglevel(struct net_device *dev)
  655. {
  656. struct pcnet32_private *lp = dev->priv;
  657. return lp->msg_enable;
  658. }
  659. static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
  660. {
  661. struct pcnet32_private *lp = dev->priv;
  662. lp->msg_enable = value;
  663. }
  664. static int pcnet32_nway_reset(struct net_device *dev)
  665. {
  666. struct pcnet32_private *lp = dev->priv;
  667. unsigned long flags;
  668. int r = -EOPNOTSUPP;
  669. if (lp->mii) {
  670. spin_lock_irqsave(&lp->lock, flags);
  671. r = mii_nway_restart(&lp->mii_if);
  672. spin_unlock_irqrestore(&lp->lock, flags);
  673. }
  674. return r;
  675. }
  676. static void pcnet32_get_ringparam(struct net_device *dev,
  677. struct ethtool_ringparam *ering)
  678. {
  679. struct pcnet32_private *lp = dev->priv;
  680. ering->tx_max_pending = TX_MAX_RING_SIZE;
  681. ering->tx_pending = lp->tx_ring_size;
  682. ering->rx_max_pending = RX_MAX_RING_SIZE;
  683. ering->rx_pending = lp->rx_ring_size;
  684. }
  685. static int pcnet32_set_ringparam(struct net_device *dev,
  686. struct ethtool_ringparam *ering)
  687. {
  688. struct pcnet32_private *lp = dev->priv;
  689. unsigned long flags;
  690. unsigned int size;
  691. ulong ioaddr = dev->base_addr;
  692. int i;
  693. if (ering->rx_mini_pending || ering->rx_jumbo_pending)
  694. return -EINVAL;
  695. if (netif_running(dev))
  696. pcnet32_netif_stop(dev);
  697. spin_lock_irqsave(&lp->lock, flags);
  698. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
  699. size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
  700. /* set the minimum ring size to 4, to allow the loopback test to work
  701. * unchanged.
  702. */
  703. for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
  704. if (size <= (1 << i))
  705. break;
  706. }
  707. if ((1 << i) != lp->tx_ring_size)
  708. pcnet32_realloc_tx_ring(dev, lp, i);
  709. size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
  710. for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
  711. if (size <= (1 << i))
  712. break;
  713. }
  714. if ((1 << i) != lp->rx_ring_size)
  715. pcnet32_realloc_rx_ring(dev, lp, i);
  716. dev->weight = lp->rx_ring_size / 2;
  717. if (netif_running(dev)) {
  718. pcnet32_netif_start(dev);
  719. pcnet32_restart(dev, CSR0_NORMAL);
  720. }
  721. spin_unlock_irqrestore(&lp->lock, flags);
  722. if (netif_msg_drv(lp))
  723. printk(KERN_INFO
  724. "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
  725. lp->rx_ring_size, lp->tx_ring_size);
  726. return 0;
  727. }
  728. static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
  729. u8 * data)
  730. {
  731. memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
  732. }
  733. static int pcnet32_self_test_count(struct net_device *dev)
  734. {
  735. return PCNET32_TEST_LEN;
  736. }
  737. static void pcnet32_ethtool_test(struct net_device *dev,
  738. struct ethtool_test *test, u64 * data)
  739. {
  740. struct pcnet32_private *lp = dev->priv;
  741. int rc;
  742. if (test->flags == ETH_TEST_FL_OFFLINE) {
  743. rc = pcnet32_loopback_test(dev, data);
  744. if (rc) {
  745. if (netif_msg_hw(lp))
  746. printk(KERN_DEBUG "%s: Loopback test failed.\n",
  747. dev->name);
  748. test->flags |= ETH_TEST_FL_FAILED;
  749. } else if (netif_msg_hw(lp))
  750. printk(KERN_DEBUG "%s: Loopback test passed.\n",
  751. dev->name);
  752. } else if (netif_msg_hw(lp))
  753. printk(KERN_DEBUG
  754. "%s: No tests to run (specify 'Offline' on ethtool).",
  755. dev->name);
  756. } /* end pcnet32_ethtool_test */
  757. static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
  758. {
  759. struct pcnet32_private *lp = dev->priv;
  760. struct pcnet32_access *a = &lp->a; /* access to registers */
  761. ulong ioaddr = dev->base_addr; /* card base I/O address */
  762. struct sk_buff *skb; /* sk buff */
  763. int x, i; /* counters */
  764. int numbuffs = 4; /* number of TX/RX buffers and descs */
  765. u16 status = 0x8300; /* TX ring status */
  766. u16 teststatus; /* test of ring status */
  767. int rc; /* return code */
  768. int size; /* size of packets */
  769. unsigned char *packet; /* source packet data */
  770. static const int data_len = 60; /* length of source packets */
  771. unsigned long flags;
  772. unsigned long ticks;
  773. rc = 1; /* default to fail */
  774. if (netif_running(dev))
  775. #ifdef CONFIG_PCNET32_NAPI
  776. pcnet32_netif_stop(dev);
  777. #else
  778. pcnet32_close(dev);
  779. #endif
  780. spin_lock_irqsave(&lp->lock, flags);
  781. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
  782. numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
  783. /* Reset the PCNET32 */
  784. lp->a.reset(ioaddr);
  785. lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
  786. /* switch pcnet32 to 32bit mode */
  787. lp->a.write_bcr(ioaddr, 20, 2);
  788. /* purge & init rings but don't actually restart */
  789. pcnet32_restart(dev, 0x0000);
  790. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
  791. /* Initialize Transmit buffers. */
  792. size = data_len + 15;
  793. for (x = 0; x < numbuffs; x++) {
  794. if (!(skb = dev_alloc_skb(size))) {
  795. if (netif_msg_hw(lp))
  796. printk(KERN_DEBUG
  797. "%s: Cannot allocate skb at line: %d!\n",
  798. dev->name, __LINE__);
  799. goto clean_up;
  800. } else {
  801. packet = skb->data;
  802. skb_put(skb, size); /* create space for data */
  803. lp->tx_skbuff[x] = skb;
  804. lp->tx_ring[x].length = le16_to_cpu(-skb->len);
  805. lp->tx_ring[x].misc = 0;
  806. /* put DA and SA into the skb */
  807. for (i = 0; i < 6; i++)
  808. *packet++ = dev->dev_addr[i];
  809. for (i = 0; i < 6; i++)
  810. *packet++ = dev->dev_addr[i];
  811. /* type */
  812. *packet++ = 0x08;
  813. *packet++ = 0x06;
  814. /* packet number */
  815. *packet++ = x;
  816. /* fill packet with data */
  817. for (i = 0; i < data_len; i++)
  818. *packet++ = i;
  819. lp->tx_dma_addr[x] =
  820. pci_map_single(lp->pci_dev, skb->data, skb->len,
  821. PCI_DMA_TODEVICE);
  822. lp->tx_ring[x].base =
  823. (u32) le32_to_cpu(lp->tx_dma_addr[x]);
  824. wmb(); /* Make sure owner changes after all others are visible */
  825. lp->tx_ring[x].status = le16_to_cpu(status);
  826. }
  827. }
  828. x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
  829. a->write_bcr(ioaddr, 32, x | 0x0002);
  830. /* set int loopback in CSR15 */
  831. x = a->read_csr(ioaddr, CSR15) & 0xfffc;
  832. lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
  833. teststatus = le16_to_cpu(0x8000);
  834. lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
  835. /* Check status of descriptors */
  836. for (x = 0; x < numbuffs; x++) {
  837. ticks = 0;
  838. rmb();
  839. while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
  840. spin_unlock_irqrestore(&lp->lock, flags);
  841. msleep(1);
  842. spin_lock_irqsave(&lp->lock, flags);
  843. rmb();
  844. ticks++;
  845. }
  846. if (ticks == 200) {
  847. if (netif_msg_hw(lp))
  848. printk("%s: Desc %d failed to reset!\n",
  849. dev->name, x);
  850. break;
  851. }
  852. }
  853. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
  854. wmb();
  855. if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
  856. printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
  857. for (x = 0; x < numbuffs; x++) {
  858. printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
  859. skb = lp->rx_skbuff[x];
  860. for (i = 0; i < size; i++) {
  861. printk("%02x ", *(skb->data + i));
  862. }
  863. printk("\n");
  864. }
  865. }
  866. x = 0;
  867. rc = 0;
  868. while (x < numbuffs && !rc) {
  869. skb = lp->rx_skbuff[x];
  870. packet = lp->tx_skbuff[x]->data;
  871. for (i = 0; i < size; i++) {
  872. if (*(skb->data + i) != packet[i]) {
  873. if (netif_msg_hw(lp))
  874. printk(KERN_DEBUG
  875. "%s: Error in compare! %2x - %02x %02x\n",
  876. dev->name, i, *(skb->data + i),
  877. packet[i]);
  878. rc = 1;
  879. break;
  880. }
  881. }
  882. x++;
  883. }
  884. clean_up:
  885. *data1 = rc;
  886. pcnet32_purge_tx_ring(dev);
  887. x = a->read_csr(ioaddr, CSR15);
  888. a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
  889. x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
  890. a->write_bcr(ioaddr, 32, (x & ~0x0002));
  891. #ifdef CONFIG_PCNET32_NAPI
  892. if (netif_running(dev)) {
  893. pcnet32_netif_start(dev);
  894. pcnet32_restart(dev, CSR0_NORMAL);
  895. } else {
  896. pcnet32_purge_rx_ring(dev);
  897. lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
  898. }
  899. spin_unlock_irqrestore(&lp->lock, flags);
  900. #else
  901. if (netif_running(dev)) {
  902. spin_unlock_irqrestore(&lp->lock, flags);
  903. pcnet32_open(dev);
  904. } else {
  905. pcnet32_purge_rx_ring(dev);
  906. lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
  907. spin_unlock_irqrestore(&lp->lock, flags);
  908. }
  909. #endif
  910. return (rc);
  911. } /* end pcnet32_loopback_test */
  912. static void pcnet32_led_blink_callback(struct net_device *dev)
  913. {
  914. struct pcnet32_private *lp = dev->priv;
  915. struct pcnet32_access *a = &lp->a;
  916. ulong ioaddr = dev->base_addr;
  917. unsigned long flags;
  918. int i;
  919. spin_lock_irqsave(&lp->lock, flags);
  920. for (i = 4; i < 8; i++) {
  921. a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
  922. }
  923. spin_unlock_irqrestore(&lp->lock, flags);
  924. mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
  925. }
  926. static int pcnet32_phys_id(struct net_device *dev, u32 data)
  927. {
  928. struct pcnet32_private *lp = dev->priv;
  929. struct pcnet32_access *a = &lp->a;
  930. ulong ioaddr = dev->base_addr;
  931. unsigned long flags;
  932. int i, regs[4];
  933. if (!lp->blink_timer.function) {
  934. init_timer(&lp->blink_timer);
  935. lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
  936. lp->blink_timer.data = (unsigned long)dev;
  937. }
  938. /* Save the current value of the bcrs */
  939. spin_lock_irqsave(&lp->lock, flags);
  940. for (i = 4; i < 8; i++) {
  941. regs[i - 4] = a->read_bcr(ioaddr, i);
  942. }
  943. spin_unlock_irqrestore(&lp->lock, flags);
  944. mod_timer(&lp->blink_timer, jiffies);
  945. set_current_state(TASK_INTERRUPTIBLE);
  946. if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
  947. data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
  948. msleep_interruptible(data * 1000);
  949. del_timer_sync(&lp->blink_timer);
  950. /* Restore the original value of the bcrs */
  951. spin_lock_irqsave(&lp->lock, flags);
  952. for (i = 4; i < 8; i++) {
  953. a->write_bcr(ioaddr, i, regs[i - 4]);
  954. }
  955. spin_unlock_irqrestore(&lp->lock, flags);
  956. return 0;
  957. }
  958. /*
  959. * lp->lock must be held.
  960. */
  961. static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
  962. int can_sleep)
  963. {
  964. int csr5;
  965. struct pcnet32_private *lp = dev->priv;
  966. struct pcnet32_access *a = &lp->a;
  967. ulong ioaddr = dev->base_addr;
  968. int ticks;
  969. /* really old chips have to be stopped. */
  970. if (lp->chip_version < PCNET32_79C970A)
  971. return 0;
  972. /* set SUSPEND (SPND) - CSR5 bit 0 */
  973. csr5 = a->read_csr(ioaddr, CSR5);
  974. a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
  975. /* poll waiting for bit to be set */
  976. ticks = 0;
  977. while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
  978. spin_unlock_irqrestore(&lp->lock, *flags);
  979. if (can_sleep)
  980. msleep(1);
  981. else
  982. mdelay(1);
  983. spin_lock_irqsave(&lp->lock, *flags);
  984. ticks++;
  985. if (ticks > 200) {
  986. if (netif_msg_hw(lp))
  987. printk(KERN_DEBUG
  988. "%s: Error getting into suspend!\n",
  989. dev->name);
  990. return 0;
  991. }
  992. }
  993. return 1;
  994. }
  995. /*
  996. * process one receive descriptor entry
  997. */
  998. static void pcnet32_rx_entry(struct net_device *dev,
  999. struct pcnet32_private *lp,
  1000. struct pcnet32_rx_head *rxp,
  1001. int entry)
  1002. {
  1003. int status = (short)le16_to_cpu(rxp->status) >> 8;
  1004. int rx_in_place = 0;
  1005. struct sk_buff *skb;
  1006. short pkt_len;
  1007. if (status != 0x03) { /* There was an error. */
  1008. /*
  1009. * There is a tricky error noted by John Murphy,
  1010. * <murf@perftech.com> to Russ Nelson: Even with full-sized
  1011. * buffers it's possible for a jabber packet to use two
  1012. * buffers, with only the last correctly noting the error.
  1013. */
  1014. if (status & 0x01) /* Only count a general error at the */
  1015. lp->stats.rx_errors++; /* end of a packet. */
  1016. if (status & 0x20)
  1017. lp->stats.rx_frame_errors++;
  1018. if (status & 0x10)
  1019. lp->stats.rx_over_errors++;
  1020. if (status & 0x08)
  1021. lp->stats.rx_crc_errors++;
  1022. if (status & 0x04)
  1023. lp->stats.rx_fifo_errors++;
  1024. return;
  1025. }
  1026. pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
  1027. /* Discard oversize frames. */
  1028. if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
  1029. if (netif_msg_drv(lp))
  1030. printk(KERN_ERR "%s: Impossible packet size %d!\n",
  1031. dev->name, pkt_len);
  1032. lp->stats.rx_errors++;
  1033. return;
  1034. }
  1035. if (pkt_len < 60) {
  1036. if (netif_msg_rx_err(lp))
  1037. printk(KERN_ERR "%s: Runt packet!\n", dev->name);
  1038. lp->stats.rx_errors++;
  1039. return;
  1040. }
  1041. if (pkt_len > rx_copybreak) {
  1042. struct sk_buff *newskb;
  1043. if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
  1044. skb_reserve(newskb, 2);
  1045. skb = lp->rx_skbuff[entry];
  1046. pci_unmap_single(lp->pci_dev,
  1047. lp->rx_dma_addr[entry],
  1048. PKT_BUF_SZ - 2,
  1049. PCI_DMA_FROMDEVICE);
  1050. skb_put(skb, pkt_len);
  1051. lp->rx_skbuff[entry] = newskb;
  1052. newskb->dev = dev;
  1053. lp->rx_dma_addr[entry] =
  1054. pci_map_single(lp->pci_dev,
  1055. newskb->data,
  1056. PKT_BUF_SZ - 2,
  1057. PCI_DMA_FROMDEVICE);
  1058. rxp->base = le32_to_cpu(lp->rx_dma_addr[entry]);
  1059. rx_in_place = 1;
  1060. } else
  1061. skb = NULL;
  1062. } else {
  1063. skb = dev_alloc_skb(pkt_len + 2);
  1064. }
  1065. if (skb == NULL) {
  1066. if (netif_msg_drv(lp))
  1067. printk(KERN_ERR
  1068. "%s: Memory squeeze, dropping packet.\n",
  1069. dev->name);
  1070. lp->stats.rx_dropped++;
  1071. return;
  1072. }
  1073. skb->dev = dev;
  1074. if (!rx_in_place) {
  1075. skb_reserve(skb, 2); /* 16 byte align */
  1076. skb_put(skb, pkt_len); /* Make room */
  1077. pci_dma_sync_single_for_cpu(lp->pci_dev,
  1078. lp->rx_dma_addr[entry],
  1079. pkt_len,
  1080. PCI_DMA_FROMDEVICE);
  1081. eth_copy_and_sum(skb,
  1082. (unsigned char *)(lp->rx_skbuff[entry]->data),
  1083. pkt_len, 0);
  1084. pci_dma_sync_single_for_device(lp->pci_dev,
  1085. lp->rx_dma_addr[entry],
  1086. pkt_len,
  1087. PCI_DMA_FROMDEVICE);
  1088. }
  1089. lp->stats.rx_bytes += skb->len;
  1090. skb->protocol = eth_type_trans(skb, dev);
  1091. #ifdef CONFIG_PCNET32_NAPI
  1092. netif_receive_skb(skb);
  1093. #else
  1094. netif_rx(skb);
  1095. #endif
  1096. dev->last_rx = jiffies;
  1097. lp->stats.rx_packets++;
  1098. return;
  1099. }
  1100. static int pcnet32_rx(struct net_device *dev, int quota)
  1101. {
  1102. struct pcnet32_private *lp = dev->priv;
  1103. int entry = lp->cur_rx & lp->rx_mod_mask;
  1104. struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
  1105. int npackets = 0;
  1106. /* If we own the next entry, it's a new packet. Send it up. */
  1107. while (quota > npackets && (short)le16_to_cpu(rxp->status) >= 0) {
  1108. pcnet32_rx_entry(dev, lp, rxp, entry);
  1109. npackets += 1;
  1110. /*
  1111. * The docs say that the buffer length isn't touched, but Andrew
  1112. * Boyd of QNX reports that some revs of the 79C965 clear it.
  1113. */
  1114. rxp->buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
  1115. wmb(); /* Make sure owner changes after others are visible */
  1116. rxp->status = le16_to_cpu(0x8000);
  1117. entry = (++lp->cur_rx) & lp->rx_mod_mask;
  1118. rxp = &lp->rx_ring[entry];
  1119. }
  1120. return npackets;
  1121. }
  1122. static int pcnet32_tx(struct net_device *dev)
  1123. {
  1124. struct pcnet32_private *lp = dev->priv;
  1125. unsigned int dirty_tx = lp->dirty_tx;
  1126. int delta;
  1127. int must_restart = 0;
  1128. while (dirty_tx != lp->cur_tx) {
  1129. int entry = dirty_tx & lp->tx_mod_mask;
  1130. int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
  1131. if (status < 0)
  1132. break; /* It still hasn't been Txed */
  1133. lp->tx_ring[entry].base = 0;
  1134. if (status & 0x4000) {
  1135. /* There was a major error, log it. */
  1136. int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
  1137. lp->stats.tx_errors++;
  1138. if (netif_msg_tx_err(lp))
  1139. printk(KERN_ERR
  1140. "%s: Tx error status=%04x err_status=%08x\n",
  1141. dev->name, status,
  1142. err_status);
  1143. if (err_status & 0x04000000)
  1144. lp->stats.tx_aborted_errors++;
  1145. if (err_status & 0x08000000)
  1146. lp->stats.tx_carrier_errors++;
  1147. if (err_status & 0x10000000)
  1148. lp->stats.tx_window_errors++;
  1149. #ifndef DO_DXSUFLO
  1150. if (err_status & 0x40000000) {
  1151. lp->stats.tx_fifo_errors++;
  1152. /* Ackk! On FIFO errors the Tx unit is turned off! */
  1153. /* Remove this verbosity later! */
  1154. if (netif_msg_tx_err(lp))
  1155. printk(KERN_ERR
  1156. "%s: Tx FIFO error!\n",
  1157. dev->name);
  1158. must_restart = 1;
  1159. }
  1160. #else
  1161. if (err_status & 0x40000000) {
  1162. lp->stats.tx_fifo_errors++;
  1163. if (!lp->dxsuflo) { /* If controller doesn't recover ... */
  1164. /* Ackk! On FIFO errors the Tx unit is turned off! */
  1165. /* Remove this verbosity later! */
  1166. if (netif_msg_tx_err(lp))
  1167. printk(KERN_ERR
  1168. "%s: Tx FIFO error!\n",
  1169. dev->name);
  1170. must_restart = 1;
  1171. }
  1172. }
  1173. #endif
  1174. } else {
  1175. if (status & 0x1800)
  1176. lp->stats.collisions++;
  1177. lp->stats.tx_packets++;
  1178. }
  1179. /* We must free the original skb */
  1180. if (lp->tx_skbuff[entry]) {
  1181. pci_unmap_single(lp->pci_dev,
  1182. lp->tx_dma_addr[entry],
  1183. lp->tx_skbuff[entry]->
  1184. len, PCI_DMA_TODEVICE);
  1185. dev_kfree_skb_any(lp->tx_skbuff[entry]);
  1186. lp->tx_skbuff[entry] = NULL;
  1187. lp->tx_dma_addr[entry] = 0;
  1188. }
  1189. dirty_tx++;
  1190. }
  1191. delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
  1192. if (delta > lp->tx_ring_size) {
  1193. if (netif_msg_drv(lp))
  1194. printk(KERN_ERR
  1195. "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
  1196. dev->name, dirty_tx, lp->cur_tx,
  1197. lp->tx_full);
  1198. dirty_tx += lp->tx_ring_size;
  1199. delta -= lp->tx_ring_size;
  1200. }
  1201. if (lp->tx_full &&
  1202. netif_queue_stopped(dev) &&
  1203. delta < lp->tx_ring_size - 2) {
  1204. /* The ring is no longer full, clear tbusy. */
  1205. lp->tx_full = 0;
  1206. netif_wake_queue(dev);
  1207. }
  1208. lp->dirty_tx = dirty_tx;
  1209. return must_restart;
  1210. }
  1211. #ifdef CONFIG_PCNET32_NAPI
  1212. static int pcnet32_poll(struct net_device *dev, int *budget)
  1213. {
  1214. struct pcnet32_private *lp = dev->priv;
  1215. int quota = min(dev->quota, *budget);
  1216. unsigned long ioaddr = dev->base_addr;
  1217. unsigned long flags;
  1218. u16 val;
  1219. quota = pcnet32_rx(dev, quota);
  1220. spin_lock_irqsave(&lp->lock, flags);
  1221. if (pcnet32_tx(dev)) {
  1222. /* reset the chip to clear the error condition, then restart */
  1223. lp->a.reset(ioaddr);
  1224. lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
  1225. pcnet32_restart(dev, CSR0_START);
  1226. netif_wake_queue(dev);
  1227. }
  1228. spin_unlock_irqrestore(&lp->lock, flags);
  1229. *budget -= quota;
  1230. dev->quota -= quota;
  1231. if (dev->quota == 0) {
  1232. return 1;
  1233. }
  1234. netif_rx_complete(dev);
  1235. spin_lock_irqsave(&lp->lock, flags);
  1236. /* clear interrupt masks */
  1237. val = lp->a.read_csr(ioaddr, CSR3);
  1238. val &= 0x00ff;
  1239. lp->a.write_csr(ioaddr, CSR3, val);
  1240. /* Set interrupt enable. */
  1241. lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
  1242. mmiowb();
  1243. spin_unlock_irqrestore(&lp->lock, flags);
  1244. return 0;
  1245. }
  1246. #endif
  1247. #define PCNET32_REGS_PER_PHY 32
  1248. #define PCNET32_MAX_PHYS 32
  1249. static int pcnet32_get_regs_len(struct net_device *dev)
  1250. {
  1251. struct pcnet32_private *lp = dev->priv;
  1252. int j = lp->phycount * PCNET32_REGS_PER_PHY;
  1253. return ((PCNET32_NUM_REGS + j) * sizeof(u16));
  1254. }
  1255. static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  1256. void *ptr)
  1257. {
  1258. int i, csr0;
  1259. u16 *buff = ptr;
  1260. struct pcnet32_private *lp = dev->priv;
  1261. struct pcnet32_access *a = &lp->a;
  1262. ulong ioaddr = dev->base_addr;
  1263. unsigned long flags;
  1264. spin_lock_irqsave(&lp->lock, flags);
  1265. csr0 = a->read_csr(ioaddr, CSR0);
  1266. if (!(csr0 & CSR0_STOP)) /* If not stopped */
  1267. pcnet32_suspend(dev, &flags, 1);
  1268. /* read address PROM */
  1269. for (i = 0; i < 16; i += 2)
  1270. *buff++ = inw(ioaddr + i);
  1271. /* read control and status registers */
  1272. for (i = 0; i < 90; i++) {
  1273. *buff++ = a->read_csr(ioaddr, i);
  1274. }
  1275. *buff++ = a->read_csr(ioaddr, 112);
  1276. *buff++ = a->read_csr(ioaddr, 114);
  1277. /* read bus configuration registers */
  1278. for (i = 0; i < 30; i++) {
  1279. *buff++ = a->read_bcr(ioaddr, i);
  1280. }
  1281. *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
  1282. for (i = 31; i < 36; i++) {
  1283. *buff++ = a->read_bcr(ioaddr, i);
  1284. }
  1285. /* read mii phy registers */
  1286. if (lp->mii) {
  1287. int j;
  1288. for (j = 0; j < PCNET32_MAX_PHYS; j++) {
  1289. if (lp->phymask & (1 << j)) {
  1290. for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
  1291. lp->a.write_bcr(ioaddr, 33,
  1292. (j << 5) | i);
  1293. *buff++ = lp->a.read_bcr(ioaddr, 34);
  1294. }
  1295. }
  1296. }
  1297. }
  1298. if (!(csr0 & CSR0_STOP)) { /* If not stopped */
  1299. int csr5;
  1300. /* clear SUSPEND (SPND) - CSR5 bit 0 */
  1301. csr5 = a->read_csr(ioaddr, CSR5);
  1302. a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
  1303. }
  1304. spin_unlock_irqrestore(&lp->lock, flags);
  1305. }
  1306. static const struct ethtool_ops pcnet32_ethtool_ops = {
  1307. .get_settings = pcnet32_get_settings,
  1308. .set_settings = pcnet32_set_settings,
  1309. .get_drvinfo = pcnet32_get_drvinfo,
  1310. .get_msglevel = pcnet32_get_msglevel,
  1311. .set_msglevel = pcnet32_set_msglevel,
  1312. .nway_reset = pcnet32_nway_reset,
  1313. .get_link = pcnet32_get_link,
  1314. .get_ringparam = pcnet32_get_ringparam,
  1315. .set_ringparam = pcnet32_set_ringparam,
  1316. .get_tx_csum = ethtool_op_get_tx_csum,
  1317. .get_sg = ethtool_op_get_sg,
  1318. .get_tso = ethtool_op_get_tso,
  1319. .get_strings = pcnet32_get_strings,
  1320. .self_test_count = pcnet32_self_test_count,
  1321. .self_test = pcnet32_ethtool_test,
  1322. .phys_id = pcnet32_phys_id,
  1323. .get_regs_len = pcnet32_get_regs_len,
  1324. .get_regs = pcnet32_get_regs,
  1325. .get_perm_addr = ethtool_op_get_perm_addr,
  1326. };
  1327. /* only probes for non-PCI devices, the rest are handled by
  1328. * pci_register_driver via pcnet32_probe_pci */
  1329. static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
  1330. {
  1331. unsigned int *port, ioaddr;
  1332. /* search for PCnet32 VLB cards at known addresses */
  1333. for (port = pcnet32_portlist; (ioaddr = *port); port++) {
  1334. if (request_region
  1335. (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
  1336. /* check if there is really a pcnet chip on that ioaddr */
  1337. if ((inb(ioaddr + 14) == 0x57)
  1338. && (inb(ioaddr + 15) == 0x57)) {
  1339. pcnet32_probe1(ioaddr, 0, NULL);
  1340. } else {
  1341. release_region(ioaddr, PCNET32_TOTAL_SIZE);
  1342. }
  1343. }
  1344. }
  1345. }
  1346. static int __devinit
  1347. pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
  1348. {
  1349. unsigned long ioaddr;
  1350. int err;
  1351. err = pci_enable_device(pdev);
  1352. if (err < 0) {
  1353. if (pcnet32_debug & NETIF_MSG_PROBE)
  1354. printk(KERN_ERR PFX
  1355. "failed to enable device -- err=%d\n", err);
  1356. return err;
  1357. }
  1358. pci_set_master(pdev);
  1359. ioaddr = pci_resource_start(pdev, 0);
  1360. if (!ioaddr) {
  1361. if (pcnet32_debug & NETIF_MSG_PROBE)
  1362. printk(KERN_ERR PFX
  1363. "card has no PCI IO resources, aborting\n");
  1364. return -ENODEV;
  1365. }
  1366. if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
  1367. if (pcnet32_debug & NETIF_MSG_PROBE)
  1368. printk(KERN_ERR PFX
  1369. "architecture does not support 32bit PCI busmaster DMA\n");
  1370. return -ENODEV;
  1371. }
  1372. if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
  1373. NULL) {
  1374. if (pcnet32_debug & NETIF_MSG_PROBE)
  1375. printk(KERN_ERR PFX
  1376. "io address range already allocated\n");
  1377. return -EBUSY;
  1378. }
  1379. err = pcnet32_probe1(ioaddr, 1, pdev);
  1380. if (err < 0) {
  1381. pci_disable_device(pdev);
  1382. }
  1383. return err;
  1384. }
  1385. /* pcnet32_probe1
  1386. * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
  1387. * pdev will be NULL when called from pcnet32_probe_vlbus.
  1388. */
  1389. static int __devinit
  1390. pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
  1391. {
  1392. struct pcnet32_private *lp;
  1393. dma_addr_t lp_dma_addr;
  1394. int i, media;
  1395. int fdx, mii, fset, dxsuflo;
  1396. int chip_version;
  1397. char *chipname;
  1398. struct net_device *dev;
  1399. struct pcnet32_access *a = NULL;
  1400. u8 promaddr[6];
  1401. int ret = -ENODEV;
  1402. /* reset the chip */
  1403. pcnet32_wio_reset(ioaddr);
  1404. /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
  1405. if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
  1406. a = &pcnet32_wio;
  1407. } else {
  1408. pcnet32_dwio_reset(ioaddr);
  1409. if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
  1410. && pcnet32_dwio_check(ioaddr)) {
  1411. a = &pcnet32_dwio;
  1412. } else
  1413. goto err_release_region;
  1414. }
  1415. chip_version =
  1416. a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
  1417. if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
  1418. printk(KERN_INFO " PCnet chip version is %#x.\n",
  1419. chip_version);
  1420. if ((chip_version & 0xfff) != 0x003) {
  1421. if (pcnet32_debug & NETIF_MSG_PROBE)
  1422. printk(KERN_INFO PFX "Unsupported chip version.\n");
  1423. goto err_release_region;
  1424. }
  1425. /* initialize variables */
  1426. fdx = mii = fset = dxsuflo = 0;
  1427. chip_version = (chip_version >> 12) & 0xffff;
  1428. switch (chip_version) {
  1429. case 0x2420:
  1430. chipname = "PCnet/PCI 79C970"; /* PCI */
  1431. break;
  1432. case 0x2430:
  1433. if (shared)
  1434. chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
  1435. else
  1436. chipname = "PCnet/32 79C965"; /* 486/VL bus */
  1437. break;
  1438. case 0x2621:
  1439. chipname = "PCnet/PCI II 79C970A"; /* PCI */
  1440. fdx = 1;
  1441. break;
  1442. case 0x2623:
  1443. chipname = "PCnet/FAST 79C971"; /* PCI */
  1444. fdx = 1;
  1445. mii = 1;
  1446. fset = 1;
  1447. break;
  1448. case 0x2624:
  1449. chipname = "PCnet/FAST+ 79C972"; /* PCI */
  1450. fdx = 1;
  1451. mii = 1;
  1452. fset = 1;
  1453. break;
  1454. case 0x2625:
  1455. chipname = "PCnet/FAST III 79C973"; /* PCI */
  1456. fdx = 1;
  1457. mii = 1;
  1458. break;
  1459. case 0x2626:
  1460. chipname = "PCnet/Home 79C978"; /* PCI */
  1461. fdx = 1;
  1462. /*
  1463. * This is based on specs published at www.amd.com. This section
  1464. * assumes that a card with a 79C978 wants to go into standard
  1465. * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
  1466. * and the module option homepna=1 can select this instead.
  1467. */
  1468. media = a->read_bcr(ioaddr, 49);
  1469. media &= ~3; /* default to 10Mb ethernet */
  1470. if (cards_found < MAX_UNITS && homepna[cards_found])
  1471. media |= 1; /* switch to home wiring mode */
  1472. if (pcnet32_debug & NETIF_MSG_PROBE)
  1473. printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
  1474. (media & 1) ? "1" : "10");
  1475. a->write_bcr(ioaddr, 49, media);
  1476. break;
  1477. case 0x2627:
  1478. chipname = "PCnet/FAST III 79C975"; /* PCI */
  1479. fdx = 1;
  1480. mii = 1;
  1481. break;
  1482. case 0x2628:
  1483. chipname = "PCnet/PRO 79C976";
  1484. fdx = 1;
  1485. mii = 1;
  1486. break;
  1487. default:
  1488. if (pcnet32_debug & NETIF_MSG_PROBE)
  1489. printk(KERN_INFO PFX
  1490. "PCnet version %#x, no PCnet32 chip.\n",
  1491. chip_version);
  1492. goto err_release_region;
  1493. }
  1494. /*
  1495. * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
  1496. * starting until the packet is loaded. Strike one for reliability, lose
  1497. * one for latency - although on PCI this isnt a big loss. Older chips
  1498. * have FIFO's smaller than a packet, so you can't do this.
  1499. * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
  1500. */
  1501. if (fset) {
  1502. a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
  1503. a->write_csr(ioaddr, 80,
  1504. (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
  1505. dxsuflo = 1;
  1506. }
  1507. dev = alloc_etherdev(0);
  1508. if (!dev) {
  1509. if (pcnet32_debug & NETIF_MSG_PROBE)
  1510. printk(KERN_ERR PFX "Memory allocation failed.\n");
  1511. ret = -ENOMEM;
  1512. goto err_release_region;
  1513. }
  1514. SET_NETDEV_DEV(dev, &pdev->dev);
  1515. if (pcnet32_debug & NETIF_MSG_PROBE)
  1516. printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
  1517. /* In most chips, after a chip reset, the ethernet address is read from the
  1518. * station address PROM at the base address and programmed into the
  1519. * "Physical Address Registers" CSR12-14.
  1520. * As a precautionary measure, we read the PROM values and complain if
  1521. * they disagree with the CSRs. If they miscompare, and the PROM addr
  1522. * is valid, then the PROM addr is used.
  1523. */
  1524. for (i = 0; i < 3; i++) {
  1525. unsigned int val;
  1526. val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
  1527. /* There may be endianness issues here. */
  1528. dev->dev_addr[2 * i] = val & 0x0ff;
  1529. dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
  1530. }
  1531. /* read PROM address and compare with CSR address */
  1532. for (i = 0; i < 6; i++)
  1533. promaddr[i] = inb(ioaddr + i);
  1534. if (memcmp(promaddr, dev->dev_addr, 6)
  1535. || !is_valid_ether_addr(dev->dev_addr)) {
  1536. if (is_valid_ether_addr(promaddr)) {
  1537. if (pcnet32_debug & NETIF_MSG_PROBE) {
  1538. printk(" warning: CSR address invalid,\n");
  1539. printk(KERN_INFO
  1540. " using instead PROM address of");
  1541. }
  1542. memcpy(dev->dev_addr, promaddr, 6);
  1543. }
  1544. }
  1545. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  1546. /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
  1547. if (!is_valid_ether_addr(dev->perm_addr))
  1548. memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
  1549. if (pcnet32_debug & NETIF_MSG_PROBE) {
  1550. for (i = 0; i < 6; i++)
  1551. printk(" %2.2x", dev->dev_addr[i]);
  1552. /* Version 0x2623 and 0x2624 */
  1553. if (((chip_version + 1) & 0xfffe) == 0x2624) {
  1554. i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
  1555. printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
  1556. switch (i >> 10) {
  1557. case 0:
  1558. printk(" 20 bytes,");
  1559. break;
  1560. case 1:
  1561. printk(" 64 bytes,");
  1562. break;
  1563. case 2:
  1564. printk(" 128 bytes,");
  1565. break;
  1566. case 3:
  1567. printk("~220 bytes,");
  1568. break;
  1569. }
  1570. i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
  1571. printk(" BCR18(%x):", i & 0xffff);
  1572. if (i & (1 << 5))
  1573. printk("BurstWrEn ");
  1574. if (i & (1 << 6))
  1575. printk("BurstRdEn ");
  1576. if (i & (1 << 7))
  1577. printk("DWordIO ");
  1578. if (i & (1 << 11))
  1579. printk("NoUFlow ");
  1580. i = a->read_bcr(ioaddr, 25);
  1581. printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
  1582. i = a->read_bcr(ioaddr, 26);
  1583. printk(" SRAM_BND=0x%04x,", i << 8);
  1584. i = a->read_bcr(ioaddr, 27);
  1585. if (i & (1 << 14))
  1586. printk("LowLatRx");
  1587. }
  1588. }
  1589. dev->base_addr = ioaddr;
  1590. /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
  1591. if ((lp =
  1592. pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
  1593. if (pcnet32_debug & NETIF_MSG_PROBE)
  1594. printk(KERN_ERR PFX
  1595. "Consistent memory allocation failed.\n");
  1596. ret = -ENOMEM;
  1597. goto err_free_netdev;
  1598. }
  1599. memset(lp, 0, sizeof(*lp));
  1600. lp->dma_addr = lp_dma_addr;
  1601. lp->pci_dev = pdev;
  1602. spin_lock_init(&lp->lock);
  1603. SET_MODULE_OWNER(dev);
  1604. SET_NETDEV_DEV(dev, &pdev->dev);
  1605. dev->priv = lp;
  1606. lp->name = chipname;
  1607. lp->shared_irq = shared;
  1608. lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
  1609. lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
  1610. lp->tx_mod_mask = lp->tx_ring_size - 1;
  1611. lp->rx_mod_mask = lp->rx_ring_size - 1;
  1612. lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
  1613. lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
  1614. lp->mii_if.full_duplex = fdx;
  1615. lp->mii_if.phy_id_mask = 0x1f;
  1616. lp->mii_if.reg_num_mask = 0x1f;
  1617. lp->dxsuflo = dxsuflo;
  1618. lp->mii = mii;
  1619. lp->chip_version = chip_version;
  1620. lp->msg_enable = pcnet32_debug;
  1621. if ((cards_found >= MAX_UNITS)
  1622. || (options[cards_found] > sizeof(options_mapping)))
  1623. lp->options = PCNET32_PORT_ASEL;
  1624. else
  1625. lp->options = options_mapping[options[cards_found]];
  1626. lp->mii_if.dev = dev;
  1627. lp->mii_if.mdio_read = mdio_read;
  1628. lp->mii_if.mdio_write = mdio_write;
  1629. if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
  1630. ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
  1631. lp->options |= PCNET32_PORT_FD;
  1632. if (!a) {
  1633. if (pcnet32_debug & NETIF_MSG_PROBE)
  1634. printk(KERN_ERR PFX "No access methods\n");
  1635. ret = -ENODEV;
  1636. goto err_free_consistent;
  1637. }
  1638. lp->a = *a;
  1639. /* prior to register_netdev, dev->name is not yet correct */
  1640. if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
  1641. ret = -ENOMEM;
  1642. goto err_free_ring;
  1643. }
  1644. /* detect special T1/E1 WAN card by checking for MAC address */
  1645. if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
  1646. && dev->dev_addr[2] == 0x75)
  1647. lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
  1648. lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
  1649. lp->init_block.tlen_rlen =
  1650. le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
  1651. for (i = 0; i < 6; i++)
  1652. lp->init_block.phys_addr[i] = dev->dev_addr[i];
  1653. lp->init_block.filter[0] = 0x00000000;
  1654. lp->init_block.filter[1] = 0x00000000;
  1655. lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
  1656. lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
  1657. /* switch pcnet32 to 32bit mode */
  1658. a->write_bcr(ioaddr, 20, 2);
  1659. a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
  1660. init_block)) & 0xffff);
  1661. a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
  1662. init_block)) >> 16);
  1663. if (pdev) { /* use the IRQ provided by PCI */
  1664. dev->irq = pdev->irq;
  1665. if (pcnet32_debug & NETIF_MSG_PROBE)
  1666. printk(" assigned IRQ %d.\n", dev->irq);
  1667. } else {
  1668. unsigned long irq_mask = probe_irq_on();
  1669. /*
  1670. * To auto-IRQ we enable the initialization-done and DMA error
  1671. * interrupts. For ISA boards we get a DMA error, but VLB and PCI
  1672. * boards will work.
  1673. */
  1674. /* Trigger an initialization just for the interrupt. */
  1675. a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
  1676. mdelay(1);
  1677. dev->irq = probe_irq_off(irq_mask);
  1678. if (!dev->irq) {
  1679. if (pcnet32_debug & NETIF_MSG_PROBE)
  1680. printk(", failed to detect IRQ line.\n");
  1681. ret = -ENODEV;
  1682. goto err_free_ring;
  1683. }
  1684. if (pcnet32_debug & NETIF_MSG_PROBE)
  1685. printk(", probed IRQ %d.\n", dev->irq);
  1686. }
  1687. /* Set the mii phy_id so that we can query the link state */
  1688. if (lp->mii) {
  1689. /* lp->phycount and lp->phymask are set to 0 by memset above */
  1690. lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
  1691. /* scan for PHYs */
  1692. for (i = 0; i < PCNET32_MAX_PHYS; i++) {
  1693. unsigned short id1, id2;
  1694. id1 = mdio_read(dev, i, MII_PHYSID1);
  1695. if (id1 == 0xffff)
  1696. continue;
  1697. id2 = mdio_read(dev, i, MII_PHYSID2);
  1698. if (id2 == 0xffff)
  1699. continue;
  1700. if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
  1701. continue; /* 79C971 & 79C972 have phantom phy at id 31 */
  1702. lp->phycount++;
  1703. lp->phymask |= (1 << i);
  1704. lp->mii_if.phy_id = i;
  1705. if (pcnet32_debug & NETIF_MSG_PROBE)
  1706. printk(KERN_INFO PFX
  1707. "Found PHY %04x:%04x at address %d.\n",
  1708. id1, id2, i);
  1709. }
  1710. lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
  1711. if (lp->phycount > 1) {
  1712. lp->options |= PCNET32_PORT_MII;
  1713. }
  1714. }
  1715. init_timer(&lp->watchdog_timer);
  1716. lp->watchdog_timer.data = (unsigned long)dev;
  1717. lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
  1718. /* The PCNET32-specific entries in the device structure. */
  1719. dev->open = &pcnet32_open;
  1720. dev->hard_start_xmit = &pcnet32_start_xmit;
  1721. dev->stop = &pcnet32_close;
  1722. dev->get_stats = &pcnet32_get_stats;
  1723. dev->set_multicast_list = &pcnet32_set_multicast_list;
  1724. dev->do_ioctl = &pcnet32_ioctl;
  1725. dev->ethtool_ops = &pcnet32_ethtool_ops;
  1726. dev->tx_timeout = pcnet32_tx_timeout;
  1727. dev->watchdog_timeo = (5 * HZ);
  1728. dev->weight = lp->rx_ring_size / 2;
  1729. #ifdef CONFIG_PCNET32_NAPI
  1730. dev->poll = pcnet32_poll;
  1731. #endif
  1732. #ifdef CONFIG_NET_POLL_CONTROLLER
  1733. dev->poll_controller = pcnet32_poll_controller;
  1734. #endif
  1735. /* Fill in the generic fields of the device structure. */
  1736. if (register_netdev(dev))
  1737. goto err_free_ring;
  1738. if (pdev) {
  1739. pci_set_drvdata(pdev, dev);
  1740. } else {
  1741. lp->next = pcnet32_dev;
  1742. pcnet32_dev = dev;
  1743. }
  1744. if (pcnet32_debug & NETIF_MSG_PROBE)
  1745. printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
  1746. cards_found++;
  1747. /* enable LED writes */
  1748. a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
  1749. return 0;
  1750. err_free_ring:
  1751. pcnet32_free_ring(dev);
  1752. err_free_consistent:
  1753. pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
  1754. err_free_netdev:
  1755. free_netdev(dev);
  1756. err_release_region:
  1757. release_region(ioaddr, PCNET32_TOTAL_SIZE);
  1758. return ret;
  1759. }
  1760. /* if any allocation fails, caller must also call pcnet32_free_ring */
  1761. static int pcnet32_alloc_ring(struct net_device *dev, char *name)
  1762. {
  1763. struct pcnet32_private *lp = dev->priv;
  1764. lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
  1765. sizeof(struct pcnet32_tx_head) *
  1766. lp->tx_ring_size,
  1767. &lp->tx_ring_dma_addr);
  1768. if (lp->tx_ring == NULL) {
  1769. if (netif_msg_drv(lp))
  1770. printk("\n" KERN_ERR PFX
  1771. "%s: Consistent memory allocation failed.\n",
  1772. name);
  1773. return -ENOMEM;
  1774. }
  1775. lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
  1776. sizeof(struct pcnet32_rx_head) *
  1777. lp->rx_ring_size,
  1778. &lp->rx_ring_dma_addr);
  1779. if (lp->rx_ring == NULL) {
  1780. if (netif_msg_drv(lp))
  1781. printk("\n" KERN_ERR PFX
  1782. "%s: Consistent memory allocation failed.\n",
  1783. name);
  1784. return -ENOMEM;
  1785. }
  1786. lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
  1787. GFP_ATOMIC);
  1788. if (!lp->tx_dma_addr) {
  1789. if (netif_msg_drv(lp))
  1790. printk("\n" KERN_ERR PFX
  1791. "%s: Memory allocation failed.\n", name);
  1792. return -ENOMEM;
  1793. }
  1794. lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
  1795. GFP_ATOMIC);
  1796. if (!lp->rx_dma_addr) {
  1797. if (netif_msg_drv(lp))
  1798. printk("\n" KERN_ERR PFX
  1799. "%s: Memory allocation failed.\n", name);
  1800. return -ENOMEM;
  1801. }
  1802. lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
  1803. GFP_ATOMIC);
  1804. if (!lp->tx_skbuff) {
  1805. if (netif_msg_drv(lp))
  1806. printk("\n" KERN_ERR PFX
  1807. "%s: Memory allocation failed.\n", name);
  1808. return -ENOMEM;
  1809. }
  1810. lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
  1811. GFP_ATOMIC);
  1812. if (!lp->rx_skbuff) {
  1813. if (netif_msg_drv(lp))
  1814. printk("\n" KERN_ERR PFX
  1815. "%s: Memory allocation failed.\n", name);
  1816. return -ENOMEM;
  1817. }
  1818. return 0;
  1819. }
  1820. static void pcnet32_free_ring(struct net_device *dev)
  1821. {
  1822. struct pcnet32_private *lp = dev->priv;
  1823. kfree(lp->tx_skbuff);
  1824. lp->tx_skbuff = NULL;
  1825. kfree(lp->rx_skbuff);
  1826. lp->rx_skbuff = NULL;
  1827. kfree(lp->tx_dma_addr);
  1828. lp->tx_dma_addr = NULL;
  1829. kfree(lp->rx_dma_addr);
  1830. lp->rx_dma_addr = NULL;
  1831. if (lp->tx_ring) {
  1832. pci_free_consistent(lp->pci_dev,
  1833. sizeof(struct pcnet32_tx_head) *
  1834. lp->tx_ring_size, lp->tx_ring,
  1835. lp->tx_ring_dma_addr);
  1836. lp->tx_ring = NULL;
  1837. }
  1838. if (lp->rx_ring) {
  1839. pci_free_consistent(lp->pci_dev,
  1840. sizeof(struct pcnet32_rx_head) *
  1841. lp->rx_ring_size, lp->rx_ring,
  1842. lp->rx_ring_dma_addr);
  1843. lp->rx_ring = NULL;
  1844. }
  1845. }
  1846. static int pcnet32_open(struct net_device *dev)
  1847. {
  1848. struct pcnet32_private *lp = dev->priv;
  1849. unsigned long ioaddr = dev->base_addr;
  1850. u16 val;
  1851. int i;
  1852. int rc;
  1853. unsigned long flags;
  1854. if (request_irq(dev->irq, &pcnet32_interrupt,
  1855. lp->shared_irq ? IRQF_SHARED : 0, dev->name,
  1856. (void *)dev)) {
  1857. return -EAGAIN;
  1858. }
  1859. spin_lock_irqsave(&lp->lock, flags);
  1860. /* Check for a valid station address */
  1861. if (!is_valid_ether_addr(dev->dev_addr)) {
  1862. rc = -EINVAL;
  1863. goto err_free_irq;
  1864. }
  1865. /* Reset the PCNET32 */
  1866. lp->a.reset(ioaddr);
  1867. /* switch pcnet32 to 32bit mode */
  1868. lp->a.write_bcr(ioaddr, 20, 2);
  1869. if (netif_msg_ifup(lp))
  1870. printk(KERN_DEBUG
  1871. "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
  1872. dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
  1873. (u32) (lp->rx_ring_dma_addr),
  1874. (u32) (lp->dma_addr +
  1875. offsetof(struct pcnet32_private, init_block)));
  1876. /* set/reset autoselect bit */
  1877. val = lp->a.read_bcr(ioaddr, 2) & ~2;
  1878. if (lp->options & PCNET32_PORT_ASEL)
  1879. val |= 2;
  1880. lp->a.write_bcr(ioaddr, 2, val);
  1881. /* handle full duplex setting */
  1882. if (lp->mii_if.full_duplex) {
  1883. val = lp->a.read_bcr(ioaddr, 9) & ~3;
  1884. if (lp->options & PCNET32_PORT_FD) {
  1885. val |= 1;
  1886. if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
  1887. val |= 2;
  1888. } else if (lp->options & PCNET32_PORT_ASEL) {
  1889. /* workaround of xSeries250, turn on for 79C975 only */
  1890. if (lp->chip_version == 0x2627)
  1891. val |= 3;
  1892. }
  1893. lp->a.write_bcr(ioaddr, 9, val);
  1894. }
  1895. /* set/reset GPSI bit in test register */
  1896. val = lp->a.read_csr(ioaddr, 124) & ~0x10;
  1897. if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
  1898. val |= 0x10;
  1899. lp->a.write_csr(ioaddr, 124, val);
  1900. /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
  1901. if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
  1902. (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
  1903. lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
  1904. if (lp->options & PCNET32_PORT_ASEL) {
  1905. lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
  1906. if (netif_msg_link(lp))
  1907. printk(KERN_DEBUG
  1908. "%s: Setting 100Mb-Full Duplex.\n",
  1909. dev->name);
  1910. }
  1911. }
  1912. if (lp->phycount < 2) {
  1913. /*
  1914. * 24 Jun 2004 according AMD, in order to change the PHY,
  1915. * DANAS (or DISPM for 79C976) must be set; then select the speed,
  1916. * duplex, and/or enable auto negotiation, and clear DANAS
  1917. */
  1918. if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
  1919. lp->a.write_bcr(ioaddr, 32,
  1920. lp->a.read_bcr(ioaddr, 32) | 0x0080);
  1921. /* disable Auto Negotiation, set 10Mpbs, HD */
  1922. val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
  1923. if (lp->options & PCNET32_PORT_FD)
  1924. val |= 0x10;
  1925. if (lp->options & PCNET32_PORT_100)
  1926. val |= 0x08;
  1927. lp->a.write_bcr(ioaddr, 32, val);
  1928. } else {
  1929. if (lp->options & PCNET32_PORT_ASEL) {
  1930. lp->a.write_bcr(ioaddr, 32,
  1931. lp->a.read_bcr(ioaddr,
  1932. 32) | 0x0080);
  1933. /* enable auto negotiate, setup, disable fd */
  1934. val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
  1935. val |= 0x20;
  1936. lp->a.write_bcr(ioaddr, 32, val);
  1937. }
  1938. }
  1939. } else {
  1940. int first_phy = -1;
  1941. u16 bmcr;
  1942. u32 bcr9;
  1943. struct ethtool_cmd ecmd;
  1944. /*
  1945. * There is really no good other way to handle multiple PHYs
  1946. * other than turning off all automatics
  1947. */
  1948. val = lp->a.read_bcr(ioaddr, 2);
  1949. lp->a.write_bcr(ioaddr, 2, val & ~2);
  1950. val = lp->a.read_bcr(ioaddr, 32);
  1951. lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
  1952. if (!(lp->options & PCNET32_PORT_ASEL)) {
  1953. /* setup ecmd */
  1954. ecmd.port = PORT_MII;
  1955. ecmd.transceiver = XCVR_INTERNAL;
  1956. ecmd.autoneg = AUTONEG_DISABLE;
  1957. ecmd.speed =
  1958. lp->
  1959. options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
  1960. bcr9 = lp->a.read_bcr(ioaddr, 9);
  1961. if (lp->options & PCNET32_PORT_FD) {
  1962. ecmd.duplex = DUPLEX_FULL;
  1963. bcr9 |= (1 << 0);
  1964. } else {
  1965. ecmd.duplex = DUPLEX_HALF;
  1966. bcr9 |= ~(1 << 0);
  1967. }
  1968. lp->a.write_bcr(ioaddr, 9, bcr9);
  1969. }
  1970. for (i = 0; i < PCNET32_MAX_PHYS; i++) {
  1971. if (lp->phymask & (1 << i)) {
  1972. /* isolate all but the first PHY */
  1973. bmcr = mdio_read(dev, i, MII_BMCR);
  1974. if (first_phy == -1) {
  1975. first_phy = i;
  1976. mdio_write(dev, i, MII_BMCR,
  1977. bmcr & ~BMCR_ISOLATE);
  1978. } else {
  1979. mdio_write(dev, i, MII_BMCR,
  1980. bmcr | BMCR_ISOLATE);
  1981. }
  1982. /* use mii_ethtool_sset to setup PHY */
  1983. lp->mii_if.phy_id = i;
  1984. ecmd.phy_address = i;
  1985. if (lp->options & PCNET32_PORT_ASEL) {
  1986. mii_ethtool_gset(&lp->mii_if, &ecmd);
  1987. ecmd.autoneg = AUTONEG_ENABLE;
  1988. }
  1989. mii_ethtool_sset(&lp->mii_if, &ecmd);
  1990. }
  1991. }
  1992. lp->mii_if.phy_id = first_phy;
  1993. if (netif_msg_link(lp))
  1994. printk(KERN_INFO "%s: Using PHY number %d.\n",
  1995. dev->name, first_phy);
  1996. }
  1997. #ifdef DO_DXSUFLO
  1998. if (lp->dxsuflo) { /* Disable transmit stop on underflow */
  1999. val = lp->a.read_csr(ioaddr, CSR3);
  2000. val |= 0x40;
  2001. lp->a.write_csr(ioaddr, CSR3, val);
  2002. }
  2003. #endif
  2004. lp->init_block.mode =
  2005. le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
  2006. pcnet32_load_multicast(dev);
  2007. if (pcnet32_init_ring(dev)) {
  2008. rc = -ENOMEM;
  2009. goto err_free_ring;
  2010. }
  2011. /* Re-initialize the PCNET32, and start it when done. */
  2012. lp->a.write_csr(ioaddr, 1, (lp->dma_addr +
  2013. offsetof(struct pcnet32_private,
  2014. init_block)) & 0xffff);
  2015. lp->a.write_csr(ioaddr, 2,
  2016. (lp->dma_addr +
  2017. offsetof(struct pcnet32_private, init_block)) >> 16);
  2018. lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
  2019. lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
  2020. netif_start_queue(dev);
  2021. if (lp->chip_version >= PCNET32_79C970A) {
  2022. /* Print the link status and start the watchdog */
  2023. pcnet32_check_media(dev, 1);
  2024. mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
  2025. }
  2026. i = 0;
  2027. while (i++ < 100)
  2028. if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
  2029. break;
  2030. /*
  2031. * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
  2032. * reports that doing so triggers a bug in the '974.
  2033. */
  2034. lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
  2035. if (netif_msg_ifup(lp))
  2036. printk(KERN_DEBUG
  2037. "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
  2038. dev->name, i,
  2039. (u32) (lp->dma_addr +
  2040. offsetof(struct pcnet32_private, init_block)),
  2041. lp->a.read_csr(ioaddr, CSR0));
  2042. spin_unlock_irqrestore(&lp->lock, flags);
  2043. return 0; /* Always succeed */
  2044. err_free_ring:
  2045. /* free any allocated skbuffs */
  2046. pcnet32_purge_rx_ring(dev);
  2047. /*
  2048. * Switch back to 16bit mode to avoid problems with dumb
  2049. * DOS packet driver after a warm reboot
  2050. */
  2051. lp->a.write_bcr(ioaddr, 20, 4);
  2052. err_free_irq:
  2053. spin_unlock_irqrestore(&lp->lock, flags);
  2054. free_irq(dev->irq, dev);
  2055. return rc;
  2056. }
  2057. /*
  2058. * The LANCE has been halted for one reason or another (busmaster memory
  2059. * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
  2060. * etc.). Modern LANCE variants always reload their ring-buffer
  2061. * configuration when restarted, so we must reinitialize our ring
  2062. * context before restarting. As part of this reinitialization,
  2063. * find all packets still on the Tx ring and pretend that they had been
  2064. * sent (in effect, drop the packets on the floor) - the higher-level
  2065. * protocols will time out and retransmit. It'd be better to shuffle
  2066. * these skbs to a temp list and then actually re-Tx them after
  2067. * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
  2068. */
  2069. static void pcnet32_purge_tx_ring(struct net_device *dev)
  2070. {
  2071. struct pcnet32_private *lp = dev->priv;
  2072. int i;
  2073. for (i = 0; i < lp->tx_ring_size; i++) {
  2074. lp->tx_ring[i].status = 0; /* CPU owns buffer */
  2075. wmb(); /* Make sure adapter sees owner change */
  2076. if (lp->tx_skbuff[i]) {
  2077. pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
  2078. lp->tx_skbuff[i]->len,
  2079. PCI_DMA_TODEVICE);
  2080. dev_kfree_skb_any(lp->tx_skbuff[i]);
  2081. }
  2082. lp->tx_skbuff[i] = NULL;
  2083. lp->tx_dma_addr[i] = 0;
  2084. }
  2085. }
  2086. /* Initialize the PCNET32 Rx and Tx rings. */
  2087. static int pcnet32_init_ring(struct net_device *dev)
  2088. {
  2089. struct pcnet32_private *lp = dev->priv;
  2090. int i;
  2091. lp->tx_full = 0;
  2092. lp->cur_rx = lp->cur_tx = 0;
  2093. lp->dirty_rx = lp->dirty_tx = 0;
  2094. for (i = 0; i < lp->rx_ring_size; i++) {
  2095. struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
  2096. if (rx_skbuff == NULL) {
  2097. if (!
  2098. (rx_skbuff = lp->rx_skbuff[i] =
  2099. dev_alloc_skb(PKT_BUF_SZ))) {
  2100. /* there is not much, we can do at this point */
  2101. if (netif_msg_drv(lp))
  2102. printk(KERN_ERR
  2103. "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
  2104. dev->name);
  2105. return -1;
  2106. }
  2107. skb_reserve(rx_skbuff, 2);
  2108. }
  2109. rmb();
  2110. if (lp->rx_dma_addr[i] == 0)
  2111. lp->rx_dma_addr[i] =
  2112. pci_map_single(lp->pci_dev, rx_skbuff->data,
  2113. PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
  2114. lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
  2115. lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
  2116. wmb(); /* Make sure owner changes after all others are visible */
  2117. lp->rx_ring[i].status = le16_to_cpu(0x8000);
  2118. }
  2119. /* The Tx buffer address is filled in as needed, but we do need to clear
  2120. * the upper ownership bit. */
  2121. for (i = 0; i < lp->tx_ring_size; i++) {
  2122. lp->tx_ring[i].status = 0; /* CPU owns buffer */
  2123. wmb(); /* Make sure adapter sees owner change */
  2124. lp->tx_ring[i].base = 0;
  2125. lp->tx_dma_addr[i] = 0;
  2126. }
  2127. lp->init_block.tlen_rlen =
  2128. le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
  2129. for (i = 0; i < 6; i++)
  2130. lp->init_block.phys_addr[i] = dev->dev_addr[i];
  2131. lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
  2132. lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
  2133. wmb(); /* Make sure all changes are visible */
  2134. return 0;
  2135. }
  2136. /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
  2137. * then flush the pending transmit operations, re-initialize the ring,
  2138. * and tell the chip to initialize.
  2139. */
  2140. static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
  2141. {
  2142. struct pcnet32_private *lp = dev->priv;
  2143. unsigned long ioaddr = dev->base_addr;
  2144. int i;
  2145. /* wait for stop */
  2146. for (i = 0; i < 100; i++)
  2147. if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
  2148. break;
  2149. if (i >= 100 && netif_msg_drv(lp))
  2150. printk(KERN_ERR
  2151. "%s: pcnet32_restart timed out waiting for stop.\n",
  2152. dev->name);
  2153. pcnet32_purge_tx_ring(dev);
  2154. if (pcnet32_init_ring(dev))
  2155. return;
  2156. /* ReInit Ring */
  2157. lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
  2158. i = 0;
  2159. while (i++ < 1000)
  2160. if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
  2161. break;
  2162. lp->a.write_csr(ioaddr, CSR0, csr0_bits);
  2163. }
  2164. static void pcnet32_tx_timeout(struct net_device *dev)
  2165. {
  2166. struct pcnet32_private *lp = dev->priv;
  2167. unsigned long ioaddr = dev->base_addr, flags;
  2168. spin_lock_irqsave(&lp->lock, flags);
  2169. /* Transmitter timeout, serious problems. */
  2170. if (pcnet32_debug & NETIF_MSG_DRV)
  2171. printk(KERN_ERR
  2172. "%s: transmit timed out, status %4.4x, resetting.\n",
  2173. dev->name, lp->a.read_csr(ioaddr, CSR0));
  2174. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
  2175. lp->stats.tx_errors++;
  2176. if (netif_msg_tx_err(lp)) {
  2177. int i;
  2178. printk(KERN_DEBUG
  2179. " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
  2180. lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
  2181. lp->cur_rx);
  2182. for (i = 0; i < lp->rx_ring_size; i++)
  2183. printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
  2184. le32_to_cpu(lp->rx_ring[i].base),
  2185. (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
  2186. 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
  2187. le16_to_cpu(lp->rx_ring[i].status));
  2188. for (i = 0; i < lp->tx_ring_size; i++)
  2189. printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
  2190. le32_to_cpu(lp->tx_ring[i].base),
  2191. (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
  2192. le32_to_cpu(lp->tx_ring[i].misc),
  2193. le16_to_cpu(lp->tx_ring[i].status));
  2194. printk("\n");
  2195. }
  2196. pcnet32_restart(dev, CSR0_NORMAL);
  2197. dev->trans_start = jiffies;
  2198. netif_wake_queue(dev);
  2199. spin_unlock_irqrestore(&lp->lock, flags);
  2200. }
  2201. static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
  2202. {
  2203. struct pcnet32_private *lp = dev->priv;
  2204. unsigned long ioaddr = dev->base_addr;
  2205. u16 status;
  2206. int entry;
  2207. unsigned long flags;
  2208. spin_lock_irqsave(&lp->lock, flags);
  2209. if (netif_msg_tx_queued(lp)) {
  2210. printk(KERN_DEBUG
  2211. "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
  2212. dev->name, lp->a.read_csr(ioaddr, CSR0));
  2213. }
  2214. /* Default status -- will not enable Successful-TxDone
  2215. * interrupt when that option is available to us.
  2216. */
  2217. status = 0x8300;
  2218. /* Fill in a Tx ring entry */
  2219. /* Mask to ring buffer boundary. */
  2220. entry = lp->cur_tx & lp->tx_mod_mask;
  2221. /* Caution: the write order is important here, set the status
  2222. * with the "ownership" bits last. */
  2223. lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
  2224. lp->tx_ring[entry].misc = 0x00000000;
  2225. lp->tx_skbuff[entry] = skb;
  2226. lp->tx_dma_addr[entry] =
  2227. pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
  2228. lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
  2229. wmb(); /* Make sure owner changes after all others are visible */
  2230. lp->tx_ring[entry].status = le16_to_cpu(status);
  2231. lp->cur_tx++;
  2232. lp->stats.tx_bytes += skb->len;
  2233. /* Trigger an immediate send poll. */
  2234. lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
  2235. dev->trans_start = jiffies;
  2236. if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
  2237. lp->tx_full = 1;
  2238. netif_stop_queue(dev);
  2239. }
  2240. spin_unlock_irqrestore(&lp->lock, flags);
  2241. return 0;
  2242. }
  2243. /* The PCNET32 interrupt handler. */
  2244. static irqreturn_t
  2245. pcnet32_interrupt(int irq, void *dev_id)
  2246. {
  2247. struct net_device *dev = dev_id;
  2248. struct pcnet32_private *lp;
  2249. unsigned long ioaddr;
  2250. u16 csr0;
  2251. int boguscnt = max_interrupt_work;
  2252. ioaddr = dev->base_addr;
  2253. lp = dev->priv;
  2254. spin_lock(&lp->lock);
  2255. csr0 = lp->a.read_csr(ioaddr, CSR0);
  2256. while ((csr0 & 0x8f00) && --boguscnt >= 0) {
  2257. if (csr0 == 0xffff) {
  2258. break; /* PCMCIA remove happened */
  2259. }
  2260. /* Acknowledge all of the current interrupt sources ASAP. */
  2261. lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
  2262. if (netif_msg_intr(lp))
  2263. printk(KERN_DEBUG
  2264. "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
  2265. dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
  2266. /* Log misc errors. */
  2267. if (csr0 & 0x4000)
  2268. lp->stats.tx_errors++; /* Tx babble. */
  2269. if (csr0 & 0x1000) {
  2270. /*
  2271. * This happens when our receive ring is full. This
  2272. * shouldn't be a problem as we will see normal rx
  2273. * interrupts for the frames in the receive ring. But
  2274. * there are some PCI chipsets (I can reproduce this
  2275. * on SP3G with Intel saturn chipset) which have
  2276. * sometimes problems and will fill up the receive
  2277. * ring with error descriptors. In this situation we
  2278. * don't get a rx interrupt, but a missed frame
  2279. * interrupt sooner or later.
  2280. */
  2281. lp->stats.rx_errors++; /* Missed a Rx frame. */
  2282. }
  2283. if (csr0 & 0x0800) {
  2284. if (netif_msg_drv(lp))
  2285. printk(KERN_ERR
  2286. "%s: Bus master arbitration failure, status %4.4x.\n",
  2287. dev->name, csr0);
  2288. /* unlike for the lance, there is no restart needed */
  2289. }
  2290. #ifdef CONFIG_PCNET32_NAPI
  2291. if (netif_rx_schedule_prep(dev)) {
  2292. u16 val;
  2293. /* set interrupt masks */
  2294. val = lp->a.read_csr(ioaddr, CSR3);
  2295. val |= 0x5f00;
  2296. lp->a.write_csr(ioaddr, CSR3, val);
  2297. mmiowb();
  2298. __netif_rx_schedule(dev);
  2299. break;
  2300. }
  2301. #else
  2302. pcnet32_rx(dev, dev->weight);
  2303. if (pcnet32_tx(dev)) {
  2304. /* reset the chip to clear the error condition, then restart */
  2305. lp->a.reset(ioaddr);
  2306. lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
  2307. pcnet32_restart(dev, CSR0_START);
  2308. netif_wake_queue(dev);
  2309. }
  2310. #endif
  2311. csr0 = lp->a.read_csr(ioaddr, CSR0);
  2312. }
  2313. #ifndef CONFIG_PCNET32_NAPI
  2314. /* Set interrupt enable. */
  2315. lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
  2316. #endif
  2317. if (netif_msg_intr(lp))
  2318. printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
  2319. dev->name, lp->a.read_csr(ioaddr, CSR0));
  2320. spin_unlock(&lp->lock);
  2321. return IRQ_HANDLED;
  2322. }
  2323. static int pcnet32_close(struct net_device *dev)
  2324. {
  2325. unsigned long ioaddr = dev->base_addr;
  2326. struct pcnet32_private *lp = dev->priv;
  2327. unsigned long flags;
  2328. del_timer_sync(&lp->watchdog_timer);
  2329. netif_stop_queue(dev);
  2330. spin_lock_irqsave(&lp->lock, flags);
  2331. lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
  2332. if (netif_msg_ifdown(lp))
  2333. printk(KERN_DEBUG
  2334. "%s: Shutting down ethercard, status was %2.2x.\n",
  2335. dev->name, lp->a.read_csr(ioaddr, CSR0));
  2336. /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
  2337. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
  2338. /*
  2339. * Switch back to 16bit mode to avoid problems with dumb
  2340. * DOS packet driver after a warm reboot
  2341. */
  2342. lp->a.write_bcr(ioaddr, 20, 4);
  2343. spin_unlock_irqrestore(&lp->lock, flags);
  2344. free_irq(dev->irq, dev);
  2345. spin_lock_irqsave(&lp->lock, flags);
  2346. pcnet32_purge_rx_ring(dev);
  2347. pcnet32_purge_tx_ring(dev);
  2348. spin_unlock_irqrestore(&lp->lock, flags);
  2349. return 0;
  2350. }
  2351. static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
  2352. {
  2353. struct pcnet32_private *lp = dev->priv;
  2354. unsigned long ioaddr = dev->base_addr;
  2355. unsigned long flags;
  2356. spin_lock_irqsave(&lp->lock, flags);
  2357. lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
  2358. spin_unlock_irqrestore(&lp->lock, flags);
  2359. return &lp->stats;
  2360. }
  2361. /* taken from the sunlance driver, which it took from the depca driver */
  2362. static void pcnet32_load_multicast(struct net_device *dev)
  2363. {
  2364. struct pcnet32_private *lp = dev->priv;
  2365. volatile struct pcnet32_init_block *ib = &lp->init_block;
  2366. volatile u16 *mcast_table = (u16 *) & ib->filter;
  2367. struct dev_mc_list *dmi = dev->mc_list;
  2368. unsigned long ioaddr = dev->base_addr;
  2369. char *addrs;
  2370. int i;
  2371. u32 crc;
  2372. /* set all multicast bits */
  2373. if (dev->flags & IFF_ALLMULTI) {
  2374. ib->filter[0] = 0xffffffff;
  2375. ib->filter[1] = 0xffffffff;
  2376. lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
  2377. lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
  2378. lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
  2379. lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
  2380. return;
  2381. }
  2382. /* clear the multicast filter */
  2383. ib->filter[0] = 0;
  2384. ib->filter[1] = 0;
  2385. /* Add addresses */
  2386. for (i = 0; i < dev->mc_count; i++) {
  2387. addrs = dmi->dmi_addr;
  2388. dmi = dmi->next;
  2389. /* multicast address? */
  2390. if (!(*addrs & 1))
  2391. continue;
  2392. crc = ether_crc_le(6, addrs);
  2393. crc = crc >> 26;
  2394. mcast_table[crc >> 4] =
  2395. le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
  2396. (1 << (crc & 0xf)));
  2397. }
  2398. for (i = 0; i < 4; i++)
  2399. lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
  2400. le16_to_cpu(mcast_table[i]));
  2401. return;
  2402. }
  2403. /*
  2404. * Set or clear the multicast filter for this adaptor.
  2405. */
  2406. static void pcnet32_set_multicast_list(struct net_device *dev)
  2407. {
  2408. unsigned long ioaddr = dev->base_addr, flags;
  2409. struct pcnet32_private *lp = dev->priv;
  2410. int csr15, suspended;
  2411. spin_lock_irqsave(&lp->lock, flags);
  2412. suspended = pcnet32_suspend(dev, &flags, 0);
  2413. csr15 = lp->a.read_csr(ioaddr, CSR15);
  2414. if (dev->flags & IFF_PROMISC) {
  2415. /* Log any net taps. */
  2416. if (netif_msg_hw(lp))
  2417. printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
  2418. dev->name);
  2419. lp->init_block.mode =
  2420. le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
  2421. 7);
  2422. lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
  2423. } else {
  2424. lp->init_block.mode =
  2425. le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
  2426. lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
  2427. pcnet32_load_multicast(dev);
  2428. }
  2429. if (suspended) {
  2430. int csr5;
  2431. /* clear SUSPEND (SPND) - CSR5 bit 0 */
  2432. csr5 = lp->a.read_csr(ioaddr, CSR5);
  2433. lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
  2434. } else {
  2435. lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
  2436. pcnet32_restart(dev, CSR0_NORMAL);
  2437. netif_wake_queue(dev);
  2438. }
  2439. spin_unlock_irqrestore(&lp->lock, flags);
  2440. }
  2441. /* This routine assumes that the lp->lock is held */
  2442. static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
  2443. {
  2444. struct pcnet32_private *lp = dev->priv;
  2445. unsigned long ioaddr = dev->base_addr;
  2446. u16 val_out;
  2447. if (!lp->mii)
  2448. return 0;
  2449. lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
  2450. val_out = lp->a.read_bcr(ioaddr, 34);
  2451. return val_out;
  2452. }
  2453. /* This routine assumes that the lp->lock is held */
  2454. static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
  2455. {
  2456. struct pcnet32_private *lp = dev->priv;
  2457. unsigned long ioaddr = dev->base_addr;
  2458. if (!lp->mii)
  2459. return;
  2460. lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
  2461. lp->a.write_bcr(ioaddr, 34, val);
  2462. }
  2463. static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  2464. {
  2465. struct pcnet32_private *lp = dev->priv;
  2466. int rc;
  2467. unsigned long flags;
  2468. /* SIOC[GS]MIIxxx ioctls */
  2469. if (lp->mii) {
  2470. spin_lock_irqsave(&lp->lock, flags);
  2471. rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
  2472. spin_unlock_irqrestore(&lp->lock, flags);
  2473. } else {
  2474. rc = -EOPNOTSUPP;
  2475. }
  2476. return rc;
  2477. }
  2478. static int pcnet32_check_otherphy(struct net_device *dev)
  2479. {
  2480. struct pcnet32_private *lp = dev->priv;
  2481. struct mii_if_info mii = lp->mii_if;
  2482. u16 bmcr;
  2483. int i;
  2484. for (i = 0; i < PCNET32_MAX_PHYS; i++) {
  2485. if (i == lp->mii_if.phy_id)
  2486. continue; /* skip active phy */
  2487. if (lp->phymask & (1 << i)) {
  2488. mii.phy_id = i;
  2489. if (mii_link_ok(&mii)) {
  2490. /* found PHY with active link */
  2491. if (netif_msg_link(lp))
  2492. printk(KERN_INFO
  2493. "%s: Using PHY number %d.\n",
  2494. dev->name, i);
  2495. /* isolate inactive phy */
  2496. bmcr =
  2497. mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
  2498. mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
  2499. bmcr | BMCR_ISOLATE);
  2500. /* de-isolate new phy */
  2501. bmcr = mdio_read(dev, i, MII_BMCR);
  2502. mdio_write(dev, i, MII_BMCR,
  2503. bmcr & ~BMCR_ISOLATE);
  2504. /* set new phy address */
  2505. lp->mii_if.phy_id = i;
  2506. return 1;
  2507. }
  2508. }
  2509. }
  2510. return 0;
  2511. }
  2512. /*
  2513. * Show the status of the media. Similar to mii_check_media however it
  2514. * correctly shows the link speed for all (tested) pcnet32 variants.
  2515. * Devices with no mii just report link state without speed.
  2516. *
  2517. * Caller is assumed to hold and release the lp->lock.
  2518. */
  2519. static void pcnet32_check_media(struct net_device *dev, int verbose)
  2520. {
  2521. struct pcnet32_private *lp = dev->priv;
  2522. int curr_link;
  2523. int prev_link = netif_carrier_ok(dev) ? 1 : 0;
  2524. u32 bcr9;
  2525. if (lp->mii) {
  2526. curr_link = mii_link_ok(&lp->mii_if);
  2527. } else {
  2528. ulong ioaddr = dev->base_addr; /* card base I/O address */
  2529. curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
  2530. }
  2531. if (!curr_link) {
  2532. if (prev_link || verbose) {
  2533. netif_carrier_off(dev);
  2534. if (netif_msg_link(lp))
  2535. printk(KERN_INFO "%s: link down\n", dev->name);
  2536. }
  2537. if (lp->phycount > 1) {
  2538. curr_link = pcnet32_check_otherphy(dev);
  2539. prev_link = 0;
  2540. }
  2541. } else if (verbose || !prev_link) {
  2542. netif_carrier_on(dev);
  2543. if (lp->mii) {
  2544. if (netif_msg_link(lp)) {
  2545. struct ethtool_cmd ecmd;
  2546. mii_ethtool_gset(&lp->mii_if, &ecmd);
  2547. printk(KERN_INFO
  2548. "%s: link up, %sMbps, %s-duplex\n",
  2549. dev->name,
  2550. (ecmd.speed == SPEED_100) ? "100" : "10",
  2551. (ecmd.duplex ==
  2552. DUPLEX_FULL) ? "full" : "half");
  2553. }
  2554. bcr9 = lp->a.read_bcr(dev->base_addr, 9);
  2555. if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
  2556. if (lp->mii_if.full_duplex)
  2557. bcr9 |= (1 << 0);
  2558. else
  2559. bcr9 &= ~(1 << 0);
  2560. lp->a.write_bcr(dev->base_addr, 9, bcr9);
  2561. }
  2562. } else {
  2563. if (netif_msg_link(lp))
  2564. printk(KERN_INFO "%s: link up\n", dev->name);
  2565. }
  2566. }
  2567. }
  2568. /*
  2569. * Check for loss of link and link establishment.
  2570. * Can not use mii_check_media because it does nothing if mode is forced.
  2571. */
  2572. static void pcnet32_watchdog(struct net_device *dev)
  2573. {
  2574. struct pcnet32_private *lp = dev->priv;
  2575. unsigned long flags;
  2576. /* Print the link status if it has changed */
  2577. spin_lock_irqsave(&lp->lock, flags);
  2578. pcnet32_check_media(dev, 0);
  2579. spin_unlock_irqrestore(&lp->lock, flags);
  2580. mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
  2581. }
  2582. static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
  2583. {
  2584. struct net_device *dev = pci_get_drvdata(pdev);
  2585. if (dev) {
  2586. struct pcnet32_private *lp = dev->priv;
  2587. unregister_netdev(dev);
  2588. pcnet32_free_ring(dev);
  2589. release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
  2590. pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
  2591. free_netdev(dev);
  2592. pci_disable_device(pdev);
  2593. pci_set_drvdata(pdev, NULL);
  2594. }
  2595. }
  2596. static struct pci_driver pcnet32_driver = {
  2597. .name = DRV_NAME,
  2598. .probe = pcnet32_probe_pci,
  2599. .remove = __devexit_p(pcnet32_remove_one),
  2600. .id_table = pcnet32_pci_tbl,
  2601. };
  2602. /* An additional parameter that may be passed in... */
  2603. static int debug = -1;
  2604. static int tx_start_pt = -1;
  2605. static int pcnet32_have_pci;
  2606. module_param(debug, int, 0);
  2607. MODULE_PARM_DESC(debug, DRV_NAME " debug level");
  2608. module_param(max_interrupt_work, int, 0);
  2609. MODULE_PARM_DESC(max_interrupt_work,
  2610. DRV_NAME " maximum events handled per interrupt");
  2611. module_param(rx_copybreak, int, 0);
  2612. MODULE_PARM_DESC(rx_copybreak,
  2613. DRV_NAME " copy breakpoint for copy-only-tiny-frames");
  2614. module_param(tx_start_pt, int, 0);
  2615. MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
  2616. module_param(pcnet32vlb, int, 0);
  2617. MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
  2618. module_param_array(options, int, NULL, 0);
  2619. MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
  2620. module_param_array(full_duplex, int, NULL, 0);
  2621. MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
  2622. /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
  2623. module_param_array(homepna, int, NULL, 0);
  2624. MODULE_PARM_DESC(homepna,
  2625. DRV_NAME
  2626. " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
  2627. MODULE_AUTHOR("Thomas Bogendoerfer");
  2628. MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
  2629. MODULE_LICENSE("GPL");
  2630. #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  2631. static int __init pcnet32_init_module(void)
  2632. {
  2633. printk(KERN_INFO "%s", version);
  2634. pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
  2635. if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
  2636. tx_start = tx_start_pt;
  2637. /* find the PCI devices */
  2638. if (!pci_register_driver(&pcnet32_driver))
  2639. pcnet32_have_pci = 1;
  2640. /* should we find any remaining VLbus devices ? */
  2641. if (pcnet32vlb)
  2642. pcnet32_probe_vlbus(pcnet32_portlist);
  2643. if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
  2644. printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
  2645. return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
  2646. }
  2647. static void __exit pcnet32_cleanup_module(void)
  2648. {
  2649. struct net_device *next_dev;
  2650. while (pcnet32_dev) {
  2651. struct pcnet32_private *lp = pcnet32_dev->priv;
  2652. next_dev = lp->next;
  2653. unregister_netdev(pcnet32_dev);
  2654. pcnet32_free_ring(pcnet32_dev);
  2655. release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
  2656. pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
  2657. free_netdev(pcnet32_dev);
  2658. pcnet32_dev = next_dev;
  2659. }
  2660. if (pcnet32_have_pci)
  2661. pci_unregister_driver(&pcnet32_driver);
  2662. }
  2663. module_init(pcnet32_init_module);
  2664. module_exit(pcnet32_cleanup_module);
  2665. /*
  2666. * Local variables:
  2667. * c-indent-level: 4
  2668. * tab-width: 8
  2669. * End:
  2670. */