pasemi_mac.h 18 KB

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  1. /*
  2. * Copyright (C) 2006 PA Semi, Inc
  3. *
  4. * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
  5. * hardware register layouts.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #ifndef PASEMI_MAC_H
  21. #define PASEMI_MAC_H
  22. #include <linux/ethtool.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/spinlock.h>
  25. struct pasemi_mac_txring {
  26. spinlock_t lock;
  27. struct pas_dma_xct_descr *desc;
  28. dma_addr_t dma;
  29. unsigned int size;
  30. unsigned int next_to_use;
  31. unsigned int next_to_clean;
  32. struct pasemi_mac_buffer *desc_info;
  33. char irq_name[10]; /* "eth%d tx" */
  34. };
  35. struct pasemi_mac_rxring {
  36. spinlock_t lock;
  37. struct pas_dma_xct_descr *desc; /* RX channel descriptor ring */
  38. dma_addr_t dma;
  39. u64 *buffers; /* RX interface buffer ring */
  40. dma_addr_t buf_dma;
  41. unsigned int size;
  42. unsigned int next_to_fill;
  43. unsigned int next_to_clean;
  44. struct pasemi_mac_buffer *desc_info;
  45. char irq_name[10]; /* "eth%d rx" */
  46. };
  47. struct pasemi_mac {
  48. struct net_device *netdev;
  49. struct pci_dev *pdev;
  50. struct pci_dev *dma_pdev;
  51. struct pci_dev *iob_pdev;
  52. struct net_device_stats stats;
  53. /* Pointer to the cacheable per-channel status registers */
  54. u64 *rx_status;
  55. u64 *tx_status;
  56. u8 type;
  57. #define MAC_TYPE_GMAC 1
  58. #define MAC_TYPE_XAUI 2
  59. u32 dma_txch;
  60. u32 dma_if;
  61. u32 dma_rxch;
  62. u8 mac_addr[6];
  63. struct timer_list rxtimer;
  64. struct pasemi_mac_txring *tx;
  65. struct pasemi_mac_rxring *rx;
  66. };
  67. /* Software status descriptor (desc_info) */
  68. struct pasemi_mac_buffer {
  69. struct sk_buff *skb;
  70. dma_addr_t dma;
  71. };
  72. /* status register layout in IOB region, at 0xfb800000 */
  73. struct pasdma_status {
  74. u64 rx_sta[64];
  75. u64 tx_sta[20];
  76. };
  77. /* descriptor structure */
  78. struct pas_dma_xct_descr {
  79. union {
  80. u64 mactx;
  81. u64 macrx;
  82. };
  83. union {
  84. u64 ptr;
  85. u64 rxb;
  86. };
  87. };
  88. /* MAC CFG register offsets */
  89. enum {
  90. PAS_MAC_CFG_PCFG = 0x80,
  91. PAS_MAC_CFG_TXP = 0x98,
  92. PAS_MAC_IPC_CHNL = 0x208,
  93. };
  94. /* MAC CFG register fields */
  95. #define PAS_MAC_CFG_PCFG_PE 0x80000000
  96. #define PAS_MAC_CFG_PCFG_CE 0x40000000
  97. #define PAS_MAC_CFG_PCFG_BU 0x20000000
  98. #define PAS_MAC_CFG_PCFG_TT 0x10000000
  99. #define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000
  100. #define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000
  101. #define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000
  102. #define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000
  103. #define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000
  104. #define PAS_MAC_CFG_PCFG_T24 0x02000000
  105. #define PAS_MAC_CFG_PCFG_PR 0x01000000
  106. #define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000
  107. #define PAS_MAC_CFG_PCFG_CRO_S 16
  108. #define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00
  109. #define PAS_MAC_CFG_PCFG_IPO_S 8
  110. #define PAS_MAC_CFG_PCFG_S1 0x00000080
  111. #define PAS_MAC_CFG_PCFG_IO_M 0x00000060
  112. #define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000
  113. #define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020
  114. #define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040
  115. #define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060
  116. #define PAS_MAC_CFG_PCFG_LP 0x00000010
  117. #define PAS_MAC_CFG_PCFG_TS 0x00000008
  118. #define PAS_MAC_CFG_PCFG_HD 0x00000004
  119. #define PAS_MAC_CFG_PCFG_SPD_M 0x00000003
  120. #define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000
  121. #define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001
  122. #define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002
  123. #define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003
  124. #define PAS_MAC_CFG_TXP_FCF 0x01000000
  125. #define PAS_MAC_CFG_TXP_FCE 0x00800000
  126. #define PAS_MAC_CFG_TXP_FC 0x00400000
  127. #define PAS_MAC_CFG_TXP_FPC_M 0x00300000
  128. #define PAS_MAC_CFG_TXP_FPC_S 20
  129. #define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
  130. PAS_MAC_CFG_TXP_FPC_M)
  131. #define PAS_MAC_CFG_TXP_RT 0x00080000
  132. #define PAS_MAC_CFG_TXP_BL 0x00040000
  133. #define PAS_MAC_CFG_TXP_SL_M 0x00030000
  134. #define PAS_MAC_CFG_TXP_SL_S 16
  135. #define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \
  136. PAS_MAC_CFG_TXP_SL_M)
  137. #define PAS_MAC_CFG_TXP_COB_M 0x0000f000
  138. #define PAS_MAC_CFG_TXP_COB_S 12
  139. #define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \
  140. PAS_MAC_CFG_TXP_COB_M)
  141. #define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00
  142. #define PAS_MAC_CFG_TXP_TIFT_S 8
  143. #define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
  144. PAS_MAC_CFG_TXP_TIFT_M)
  145. #define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff
  146. #define PAS_MAC_CFG_TXP_TIFG_S 0
  147. #define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
  148. PAS_MAC_CFG_TXP_TIFG_M)
  149. #define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000
  150. #define PAS_MAC_IPC_CHNL_DCHNO_S 16
  151. #define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
  152. PAS_MAC_IPC_CHNL_DCHNO_M)
  153. #define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f
  154. #define PAS_MAC_IPC_CHNL_BCH_S 0
  155. #define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
  156. PAS_MAC_IPC_CHNL_BCH_M)
  157. /* All these registers live in the PCI configuration space for the DMA PCI
  158. * device. Use the normal PCI config access functions for them.
  159. */
  160. enum {
  161. PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
  162. PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
  163. PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
  164. PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
  165. };
  166. #define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
  167. #define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
  168. #define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
  169. #define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */
  170. /* Per-interface and per-channel registers */
  171. #define _PAS_DMA_RXINT_STRIDE 0x20
  172. #define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
  173. #define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001
  174. #define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002
  175. #define PAS_DMA_RXINT_RCMDSTA_OO 0x00000100
  176. #define PAS_DMA_RXINT_RCMDSTA_BP 0x00000200
  177. #define PAS_DMA_RXINT_RCMDSTA_DR 0x00000400
  178. #define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800
  179. #define PAS_DMA_RXINT_RCMDSTA_TB 0x00001000
  180. #define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
  181. #define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
  182. #define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
  183. #define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
  184. #define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
  185. #define PAS_DMA_RXINT_INCR_INCR_S 0
  186. #define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff)
  187. #define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
  188. #define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f)
  189. #define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
  190. #define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff)
  191. #define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */
  192. #define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */
  193. #define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
  194. PAS_DMA_RXINT_BASEU_SIZ_M)
  195. #define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */
  196. #define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */
  197. #define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */
  198. #define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */
  199. #define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */
  200. #define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */
  201. #define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */
  202. #define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */
  203. #define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
  204. #define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */
  205. #define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */
  206. #define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */
  207. #define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
  208. #define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
  209. #define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
  210. #define PAS_DMA_TXCHAN_CFG_TATTR_S 2
  211. #define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
  212. PAS_DMA_TXCHAN_CFG_TATTR_M)
  213. #define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0
  214. #define PAS_DMA_TXCHAN_CFG_WT_S 6
  215. #define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
  216. PAS_DMA_TXCHAN_CFG_WT_M)
  217. #define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */
  218. #define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */
  219. #define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */
  220. #define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
  221. #define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
  222. #define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0
  223. #define PAS_DMA_TXCHAN_BASEL_BRBL_S 0
  224. #define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
  225. PAS_DMA_TXCHAN_BASEL_BRBL_M)
  226. #define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
  227. #define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff
  228. #define PAS_DMA_TXCHAN_BASEU_BRBH_S 0
  229. #define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
  230. PAS_DMA_TXCHAN_BASEU_BRBH_M)
  231. /* # of cache lines worth of buffer ring */
  232. #define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000
  233. #define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
  234. #define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
  235. PAS_DMA_TXCHAN_BASEU_SIZ_M)
  236. #define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */
  237. #define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */
  238. #define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */
  239. #define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */
  240. #define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */
  241. #define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */
  242. #define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */
  243. #define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
  244. #define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */
  245. #define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */
  246. #define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */
  247. #define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000
  248. #define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
  249. #define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380
  250. #define PAS_DMA_RXCHAN_CFG_HBU_S 7
  251. #define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
  252. PAS_DMA_RXCHAN_CFG_HBU_M)
  253. #define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
  254. #define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
  255. #define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0
  256. #define PAS_DMA_RXCHAN_BASEL_BRBL_S 0
  257. #define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
  258. PAS_DMA_RXCHAN_BASEL_BRBL_M)
  259. #define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
  260. #define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff
  261. #define PAS_DMA_RXCHAN_BASEU_BRBH_S 0
  262. #define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
  263. PAS_DMA_RXCHAN_BASEU_BRBH_M)
  264. /* # of cache lines worth of buffer ring */
  265. #define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000
  266. #define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
  267. #define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
  268. PAS_DMA_RXCHAN_BASEU_SIZ_M)
  269. #define PAS_STATUS_PCNT_M 0x000000000000ffffull
  270. #define PAS_STATUS_PCNT_S 0
  271. #define PAS_STATUS_DCNT_M 0x00000000ffff0000ull
  272. #define PAS_STATUS_DCNT_S 16
  273. #define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull
  274. #define PAS_STATUS_BPCNT_S 32
  275. #define PAS_STATUS_TIMER 0x1000000000000000ull
  276. #define PAS_STATUS_ERROR 0x2000000000000000ull
  277. #define PAS_STATUS_SOFT 0x4000000000000000ull
  278. #define PAS_STATUS_INT 0x8000000000000000ull
  279. #define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4)
  280. #define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff
  281. #define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0
  282. #define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
  283. PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
  284. #define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4)
  285. #define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff
  286. #define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0
  287. #define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
  288. PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
  289. #define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4)
  290. #define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
  291. #define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff
  292. #define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0
  293. #define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
  294. PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
  295. #define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4)
  296. #define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
  297. #define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff
  298. #define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0
  299. #define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
  300. PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
  301. #define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4)
  302. #define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000
  303. #define PAS_IOB_DMA_RXCH_RESET_PCNT_S 0
  304. #define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
  305. PAS_IOB_DMA_RXCH_RESET_PCNT_M)
  306. #define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020
  307. #define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010
  308. #define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008
  309. #define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004
  310. #define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002
  311. #define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001
  312. #define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4)
  313. #define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000
  314. #define PAS_IOB_DMA_TXCH_RESET_PCNT_S 0
  315. #define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
  316. PAS_IOB_DMA_TXCH_RESET_PCNT_M)
  317. #define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020
  318. #define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010
  319. #define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008
  320. #define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004
  321. #define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002
  322. #define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001
  323. #define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700
  324. #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff
  325. #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0
  326. #define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
  327. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
  328. /* Transmit descriptor fields */
  329. #define XCT_MACTX_T 0x8000000000000000ull
  330. #define XCT_MACTX_ST 0x4000000000000000ull
  331. #define XCT_MACTX_NORES 0x0000000000000000ull
  332. #define XCT_MACTX_8BRES 0x1000000000000000ull
  333. #define XCT_MACTX_24BRES 0x2000000000000000ull
  334. #define XCT_MACTX_40BRES 0x3000000000000000ull
  335. #define XCT_MACTX_I 0x0800000000000000ull
  336. #define XCT_MACTX_O 0x0400000000000000ull
  337. #define XCT_MACTX_E 0x0200000000000000ull
  338. #define XCT_MACTX_VLAN_M 0x0180000000000000ull
  339. #define XCT_MACTX_VLAN_NOP 0x0000000000000000ull
  340. #define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull
  341. #define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull
  342. #define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull
  343. #define XCT_MACTX_CRC_M 0x0060000000000000ull
  344. #define XCT_MACTX_CRC_NOP 0x0000000000000000ull
  345. #define XCT_MACTX_CRC_INSERT 0x0020000000000000ull
  346. #define XCT_MACTX_CRC_PAD 0x0040000000000000ull
  347. #define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull
  348. #define XCT_MACTX_SS 0x0010000000000000ull
  349. #define XCT_MACTX_LLEN_M 0x00007fff00000000ull
  350. #define XCT_MACTX_LLEN_S 32ull
  351. #define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \
  352. XCT_MACTX_LLEN_M)
  353. #define XCT_MACTX_IPH_M 0x00000000f8000000ull
  354. #define XCT_MACTX_IPH_S 27ull
  355. #define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \
  356. XCT_MACTX_IPH_M)
  357. #define XCT_MACTX_IPO_M 0x0000000007c00000ull
  358. #define XCT_MACTX_IPO_S 22ull
  359. #define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \
  360. XCT_MACTX_IPO_M)
  361. #define XCT_MACTX_CSUM_M 0x0000000000000060ull
  362. #define XCT_MACTX_CSUM_NOP 0x0000000000000000ull
  363. #define XCT_MACTX_CSUM_TCP 0x0000000000000040ull
  364. #define XCT_MACTX_CSUM_UDP 0x0000000000000060ull
  365. #define XCT_MACTX_V6 0x0000000000000010ull
  366. #define XCT_MACTX_C 0x0000000000000004ull
  367. #define XCT_MACTX_AL2 0x0000000000000002ull
  368. /* Receive descriptor fields */
  369. #define XCT_MACRX_T 0x8000000000000000ull
  370. #define XCT_MACRX_ST 0x4000000000000000ull
  371. #define XCT_MACRX_NORES 0x0000000000000000ull
  372. #define XCT_MACRX_8BRES 0x1000000000000000ull
  373. #define XCT_MACRX_24BRES 0x2000000000000000ull
  374. #define XCT_MACRX_40BRES 0x3000000000000000ull
  375. #define XCT_MACRX_O 0x0400000000000000ull
  376. #define XCT_MACRX_E 0x0200000000000000ull
  377. #define XCT_MACRX_FF 0x0100000000000000ull
  378. #define XCT_MACRX_PF 0x0080000000000000ull
  379. #define XCT_MACRX_OB 0x0040000000000000ull
  380. #define XCT_MACRX_OD 0x0020000000000000ull
  381. #define XCT_MACRX_FS 0x0010000000000000ull
  382. #define XCT_MACRX_NB_M 0x000fc00000000000ull
  383. #define XCT_MACRX_NB_S 46ULL
  384. #define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \
  385. XCT_MACRX_NB_M)
  386. #define XCT_MACRX_LLEN_M 0x00003fff00000000ull
  387. #define XCT_MACRX_LLEN_S 32ULL
  388. #define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \
  389. XCT_MACRX_LLEN_M)
  390. #define XCT_MACRX_CRC 0x0000000080000000ull
  391. #define XCT_MACRX_LEN_M 0x0000000060000000ull
  392. #define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull
  393. #define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull
  394. #define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull
  395. #define XCT_MACRX_CAST_M 0x0000000018000000ull
  396. #define XCT_MACRX_CAST_UNI 0x0000000000000000ull
  397. #define XCT_MACRX_CAST_MULTI 0x0000000008000000ull
  398. #define XCT_MACRX_CAST_BROAD 0x0000000010000000ull
  399. #define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull
  400. #define XCT_MACRX_VLC_M 0x0000000006000000ull
  401. #define XCT_MACRX_FM 0x0000000001000000ull
  402. #define XCT_MACRX_HTY_M 0x0000000000c00000ull
  403. #define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull
  404. #define XCT_MACRX_HTY_IPV6 0x0000000000400000ull
  405. #define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull
  406. #define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull
  407. #define XCT_MACRX_IPP_M 0x00000000003f0000ull
  408. #define XCT_MACRX_IPP_S 16
  409. #define XCT_MACRX_CSUM_M 0x000000000000ffffull
  410. #define XCT_MACRX_CSUM_S 0
  411. #define XCT_PTR_T 0x8000000000000000ull
  412. #define XCT_PTR_LEN_M 0x7ffff00000000000ull
  413. #define XCT_PTR_LEN_S 44
  414. #define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \
  415. XCT_PTR_LEN_M)
  416. #define XCT_PTR_ADDR_M 0x00000fffffffffffull
  417. #define XCT_PTR_ADDR_S 0
  418. #define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \
  419. XCT_PTR_ADDR_M)
  420. /* Receive interface buffer fields */
  421. #define XCT_RXB_LEN_M 0x0ffff00000000000ull
  422. #define XCT_RXB_LEN_S 44
  423. #define XCT_RXB_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & XCT_PTR_LEN_M)
  424. #define XCT_RXB_ADDR_M 0x00000fffffffffffull
  425. #define XCT_RXB_ADDR_S 0
  426. #define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & XCT_PTR_ADDR_M)
  427. #endif /* PASEMI_MAC_H */