pasemi_mac.c 25 KB

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  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <asm/dma-mapping.h>
  28. #include <linux/in.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/ip.h>
  31. #include <linux/tcp.h>
  32. #include <net/checksum.h>
  33. #include "pasemi_mac.h"
  34. /* TODO list
  35. *
  36. * - Get rid of pci_{read,write}_config(), map registers with ioremap
  37. * for performance
  38. * - PHY support
  39. * - Multicast support
  40. * - Large MTU support
  41. * - Other performance improvements
  42. */
  43. /* Must be a power of two */
  44. #define RX_RING_SIZE 512
  45. #define TX_RING_SIZE 512
  46. #define TX_DESC(mac, num) ((mac)->tx->desc[(num) & (TX_RING_SIZE-1)])
  47. #define TX_DESC_INFO(mac, num) ((mac)->tx->desc_info[(num) & (TX_RING_SIZE-1)])
  48. #define RX_DESC(mac, num) ((mac)->rx->desc[(num) & (RX_RING_SIZE-1)])
  49. #define RX_DESC_INFO(mac, num) ((mac)->rx->desc_info[(num) & (RX_RING_SIZE-1)])
  50. #define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)])
  51. #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
  52. /* XXXOJN these should come out of the device tree some day */
  53. #define PAS_DMA_CAP_BASE 0xe00d0040
  54. #define PAS_DMA_CAP_SIZE 0x100
  55. #define PAS_DMA_COM_BASE 0xe00d0100
  56. #define PAS_DMA_COM_SIZE 0x100
  57. static struct pasdma_status *dma_status;
  58. static int pasemi_get_mac_addr(struct pasemi_mac *mac)
  59. {
  60. struct pci_dev *pdev = mac->pdev;
  61. struct device_node *dn = pci_device_to_OF_node(pdev);
  62. const u8 *maddr;
  63. u8 addr[6];
  64. if (!dn) {
  65. dev_dbg(&pdev->dev,
  66. "No device node for mac, not configuring\n");
  67. return -ENOENT;
  68. }
  69. maddr = get_property(dn, "mac-address", NULL);
  70. if (maddr == NULL) {
  71. dev_warn(&pdev->dev,
  72. "no mac address in device tree, not configuring\n");
  73. return -ENOENT;
  74. }
  75. if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
  76. &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
  77. dev_warn(&pdev->dev,
  78. "can't parse mac address, not configuring\n");
  79. return -EINVAL;
  80. }
  81. memcpy(mac->mac_addr, addr, sizeof(addr));
  82. return 0;
  83. }
  84. static int pasemi_mac_setup_rx_resources(struct net_device *dev)
  85. {
  86. struct pasemi_mac_rxring *ring;
  87. struct pasemi_mac *mac = netdev_priv(dev);
  88. int chan_id = mac->dma_rxch;
  89. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  90. if (!ring)
  91. goto out_ring;
  92. spin_lock_init(&ring->lock);
  93. ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  94. RX_RING_SIZE, GFP_KERNEL);
  95. if (!ring->desc_info)
  96. goto out_desc_info;
  97. /* Allocate descriptors */
  98. ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
  99. RX_RING_SIZE *
  100. sizeof(struct pas_dma_xct_descr),
  101. &ring->dma, GFP_KERNEL);
  102. if (!ring->desc)
  103. goto out_desc;
  104. memset(ring->desc, 0, RX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
  105. ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
  106. RX_RING_SIZE * sizeof(u64),
  107. &ring->buf_dma, GFP_KERNEL);
  108. if (!ring->buffers)
  109. goto out_buffers;
  110. memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
  111. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEL(chan_id),
  112. PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma));
  113. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEU(chan_id),
  114. PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) |
  115. PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2));
  116. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_CFG(chan_id),
  117. PAS_DMA_RXCHAN_CFG_HBU(1));
  118. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEL(mac->dma_if),
  119. PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
  120. pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEU(mac->dma_if),
  121. PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
  122. PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
  123. ring->next_to_fill = 0;
  124. ring->next_to_clean = 0;
  125. snprintf(ring->irq_name, sizeof(ring->irq_name),
  126. "%s rx", dev->name);
  127. mac->rx = ring;
  128. return 0;
  129. out_buffers:
  130. dma_free_coherent(&mac->dma_pdev->dev,
  131. RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
  132. mac->rx->desc, mac->rx->dma);
  133. out_desc:
  134. kfree(ring->desc_info);
  135. out_desc_info:
  136. kfree(ring);
  137. out_ring:
  138. return -ENOMEM;
  139. }
  140. static int pasemi_mac_setup_tx_resources(struct net_device *dev)
  141. {
  142. struct pasemi_mac *mac = netdev_priv(dev);
  143. u32 val;
  144. int chan_id = mac->dma_txch;
  145. struct pasemi_mac_txring *ring;
  146. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  147. if (!ring)
  148. goto out_ring;
  149. spin_lock_init(&ring->lock);
  150. ring->desc_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  151. TX_RING_SIZE, GFP_KERNEL);
  152. if (!ring->desc_info)
  153. goto out_desc_info;
  154. /* Allocate descriptors */
  155. ring->desc = dma_alloc_coherent(&mac->dma_pdev->dev,
  156. TX_RING_SIZE *
  157. sizeof(struct pas_dma_xct_descr),
  158. &ring->dma, GFP_KERNEL);
  159. if (!ring->desc)
  160. goto out_desc;
  161. memset(ring->desc, 0, TX_RING_SIZE * sizeof(struct pas_dma_xct_descr));
  162. pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEL(chan_id),
  163. PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma));
  164. val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32);
  165. val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2);
  166. pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEU(chan_id), val);
  167. pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_CFG(chan_id),
  168. PAS_DMA_TXCHAN_CFG_TY_IFACE |
  169. PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
  170. PAS_DMA_TXCHAN_CFG_UP |
  171. PAS_DMA_TXCHAN_CFG_WT(2));
  172. ring->next_to_use = 0;
  173. ring->next_to_clean = 0;
  174. snprintf(ring->irq_name, sizeof(ring->irq_name),
  175. "%s tx", dev->name);
  176. mac->tx = ring;
  177. return 0;
  178. out_desc:
  179. kfree(ring->desc_info);
  180. out_desc_info:
  181. kfree(ring);
  182. out_ring:
  183. return -ENOMEM;
  184. }
  185. static void pasemi_mac_free_tx_resources(struct net_device *dev)
  186. {
  187. struct pasemi_mac *mac = netdev_priv(dev);
  188. unsigned int i;
  189. struct pasemi_mac_buffer *info;
  190. struct pas_dma_xct_descr *dp;
  191. for (i = 0; i < TX_RING_SIZE; i++) {
  192. info = &TX_DESC_INFO(mac, i);
  193. dp = &TX_DESC(mac, i);
  194. if (info->dma) {
  195. if (info->skb) {
  196. pci_unmap_single(mac->dma_pdev,
  197. info->dma,
  198. info->skb->len,
  199. PCI_DMA_TODEVICE);
  200. dev_kfree_skb_any(info->skb);
  201. }
  202. info->dma = 0;
  203. info->skb = NULL;
  204. dp->mactx = 0;
  205. dp->ptr = 0;
  206. }
  207. }
  208. dma_free_coherent(&mac->dma_pdev->dev,
  209. TX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
  210. mac->tx->desc, mac->tx->dma);
  211. kfree(mac->tx->desc_info);
  212. kfree(mac->tx);
  213. mac->tx = NULL;
  214. }
  215. static void pasemi_mac_free_rx_resources(struct net_device *dev)
  216. {
  217. struct pasemi_mac *mac = netdev_priv(dev);
  218. unsigned int i;
  219. struct pasemi_mac_buffer *info;
  220. struct pas_dma_xct_descr *dp;
  221. for (i = 0; i < RX_RING_SIZE; i++) {
  222. info = &RX_DESC_INFO(mac, i);
  223. dp = &RX_DESC(mac, i);
  224. if (info->dma) {
  225. if (info->skb) {
  226. pci_unmap_single(mac->dma_pdev,
  227. info->dma,
  228. info->skb->len,
  229. PCI_DMA_FROMDEVICE);
  230. dev_kfree_skb_any(info->skb);
  231. }
  232. info->dma = 0;
  233. info->skb = NULL;
  234. dp->macrx = 0;
  235. dp->ptr = 0;
  236. }
  237. }
  238. dma_free_coherent(&mac->dma_pdev->dev,
  239. RX_RING_SIZE * sizeof(struct pas_dma_xct_descr),
  240. mac->rx->desc, mac->rx->dma);
  241. dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
  242. mac->rx->buffers, mac->rx->buf_dma);
  243. kfree(mac->rx->desc_info);
  244. kfree(mac->rx);
  245. mac->rx = NULL;
  246. }
  247. static void pasemi_mac_replenish_rx_ring(struct net_device *dev)
  248. {
  249. struct pasemi_mac *mac = netdev_priv(dev);
  250. unsigned int i;
  251. int start = mac->rx->next_to_fill;
  252. unsigned int count;
  253. count = (mac->rx->next_to_clean + RX_RING_SIZE -
  254. mac->rx->next_to_fill) & (RX_RING_SIZE - 1);
  255. /* Check to see if we're doing first-time setup */
  256. if (unlikely(mac->rx->next_to_clean == 0 && mac->rx->next_to_fill == 0))
  257. count = RX_RING_SIZE;
  258. if (count <= 0)
  259. return;
  260. for (i = start; i < start + count; i++) {
  261. struct pasemi_mac_buffer *info = &RX_DESC_INFO(mac, i);
  262. u64 *buff = &RX_BUFF(mac, i);
  263. struct sk_buff *skb;
  264. dma_addr_t dma;
  265. skb = dev_alloc_skb(BUF_SIZE);
  266. if (!skb) {
  267. count = i - start;
  268. break;
  269. }
  270. skb->dev = dev;
  271. dma = pci_map_single(mac->dma_pdev, skb->data, skb->len,
  272. PCI_DMA_FROMDEVICE);
  273. if (dma_mapping_error(dma)) {
  274. dev_kfree_skb_irq(info->skb);
  275. count = i - start;
  276. break;
  277. }
  278. info->skb = skb;
  279. info->dma = dma;
  280. *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
  281. }
  282. wmb();
  283. pci_write_config_dword(mac->dma_pdev,
  284. PAS_DMA_RXCHAN_INCR(mac->dma_rxch),
  285. count);
  286. pci_write_config_dword(mac->dma_pdev,
  287. PAS_DMA_RXINT_INCR(mac->dma_if),
  288. count);
  289. mac->rx->next_to_fill += count;
  290. }
  291. static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit)
  292. {
  293. unsigned int i;
  294. int start, count;
  295. spin_lock(&mac->rx->lock);
  296. start = mac->rx->next_to_clean;
  297. count = 0;
  298. for (i = start; i < (start + RX_RING_SIZE) && count < limit; i++) {
  299. struct pas_dma_xct_descr *dp;
  300. struct pasemi_mac_buffer *info;
  301. struct sk_buff *skb;
  302. unsigned int j, len;
  303. dma_addr_t dma;
  304. rmb();
  305. dp = &RX_DESC(mac, i);
  306. if (!(dp->macrx & XCT_MACRX_O))
  307. break;
  308. count++;
  309. info = NULL;
  310. /* We have to scan for our skb since there's no way
  311. * to back-map them from the descriptor, and if we
  312. * have several receive channels then they might not
  313. * show up in the same order as they were put on the
  314. * interface ring.
  315. */
  316. dma = (dp->ptr & XCT_PTR_ADDR_M);
  317. for (j = start; j < (start + RX_RING_SIZE); j++) {
  318. info = &RX_DESC_INFO(mac, j);
  319. if (info->dma == dma)
  320. break;
  321. }
  322. BUG_ON(!info);
  323. BUG_ON(info->dma != dma);
  324. pci_unmap_single(mac->dma_pdev, info->dma, info->skb->len,
  325. PCI_DMA_FROMDEVICE);
  326. skb = info->skb;
  327. len = (dp->macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
  328. skb_put(skb, len);
  329. skb->protocol = eth_type_trans(skb, mac->netdev);
  330. if ((dp->macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK) {
  331. skb->ip_summed = CHECKSUM_COMPLETE;
  332. skb->csum = (dp->macrx & XCT_MACRX_CSUM_M) >>
  333. XCT_MACRX_CSUM_S;
  334. } else
  335. skb->ip_summed = CHECKSUM_NONE;
  336. mac->stats.rx_bytes += len;
  337. mac->stats.rx_packets++;
  338. netif_receive_skb(skb);
  339. info->dma = 0;
  340. info->skb = NULL;
  341. dp->ptr = 0;
  342. dp->macrx = 0;
  343. }
  344. mac->rx->next_to_clean += count;
  345. pasemi_mac_replenish_rx_ring(mac->netdev);
  346. spin_unlock(&mac->rx->lock);
  347. return count;
  348. }
  349. static int pasemi_mac_clean_tx(struct pasemi_mac *mac)
  350. {
  351. int i;
  352. struct pasemi_mac_buffer *info;
  353. struct pas_dma_xct_descr *dp;
  354. int start, count;
  355. int flags;
  356. spin_lock_irqsave(&mac->tx->lock, flags);
  357. start = mac->tx->next_to_clean;
  358. count = 0;
  359. for (i = start; i < mac->tx->next_to_use; i++) {
  360. dp = &TX_DESC(mac, i);
  361. if (!dp || (dp->mactx & XCT_MACTX_O))
  362. break;
  363. count++;
  364. info = &TX_DESC_INFO(mac, i);
  365. pci_unmap_single(mac->dma_pdev, info->dma,
  366. info->skb->len, PCI_DMA_TODEVICE);
  367. dev_kfree_skb_irq(info->skb);
  368. info->skb = NULL;
  369. info->dma = 0;
  370. dp->mactx = 0;
  371. dp->ptr = 0;
  372. }
  373. mac->tx->next_to_clean += count;
  374. spin_unlock_irqrestore(&mac->tx->lock, flags);
  375. return count;
  376. }
  377. static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
  378. {
  379. struct net_device *dev = data;
  380. struct pasemi_mac *mac = netdev_priv(dev);
  381. unsigned int reg;
  382. if (!(*mac->rx_status & PAS_STATUS_INT))
  383. return IRQ_NONE;
  384. netif_rx_schedule(dev);
  385. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG,
  386. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0));
  387. reg = PAS_IOB_DMA_RXCH_RESET_PINTC | PAS_IOB_DMA_RXCH_RESET_SINTC |
  388. PAS_IOB_DMA_RXCH_RESET_DINTC;
  389. if (*mac->rx_status & PAS_STATUS_TIMER)
  390. reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
  391. pci_write_config_dword(mac->iob_pdev,
  392. PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
  393. return IRQ_HANDLED;
  394. }
  395. static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
  396. {
  397. struct net_device *dev = data;
  398. struct pasemi_mac *mac = netdev_priv(dev);
  399. unsigned int reg;
  400. int was_full;
  401. was_full = mac->tx->next_to_clean - mac->tx->next_to_use == TX_RING_SIZE;
  402. if (!(*mac->tx_status & PAS_STATUS_INT))
  403. return IRQ_NONE;
  404. pasemi_mac_clean_tx(mac);
  405. reg = PAS_IOB_DMA_TXCH_RESET_PINTC | PAS_IOB_DMA_TXCH_RESET_SINTC;
  406. if (*mac->tx_status & PAS_STATUS_TIMER)
  407. reg |= PAS_IOB_DMA_TXCH_RESET_TINTC;
  408. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch),
  409. reg);
  410. if (was_full)
  411. netif_wake_queue(dev);
  412. return IRQ_HANDLED;
  413. }
  414. static int pasemi_mac_open(struct net_device *dev)
  415. {
  416. struct pasemi_mac *mac = netdev_priv(dev);
  417. unsigned int flags;
  418. int ret;
  419. /* enable rx section */
  420. pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_RXCMD,
  421. PAS_DMA_COM_RXCMD_EN);
  422. /* enable tx section */
  423. pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_TXCMD,
  424. PAS_DMA_COM_TXCMD_EN);
  425. flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
  426. PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
  427. PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
  428. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_TXP, flags);
  429. flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
  430. PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
  431. flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
  432. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch),
  433. PAS_IOB_DMA_RXCH_CFG_CNTTH(30));
  434. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG,
  435. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(1000000));
  436. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
  437. ret = pasemi_mac_setup_rx_resources(dev);
  438. if (ret)
  439. goto out_rx_resources;
  440. ret = pasemi_mac_setup_tx_resources(dev);
  441. if (ret)
  442. goto out_tx_resources;
  443. pci_write_config_dword(mac->pdev, PAS_MAC_IPC_CHNL,
  444. PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) |
  445. PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch));
  446. /* enable rx if */
  447. pci_write_config_dword(mac->dma_pdev,
  448. PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  449. PAS_DMA_RXINT_RCMDSTA_EN);
  450. /* enable rx channel */
  451. pci_write_config_dword(mac->dma_pdev,
  452. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  453. PAS_DMA_RXCHAN_CCMDSTA_EN |
  454. PAS_DMA_RXCHAN_CCMDSTA_DU);
  455. /* enable tx channel */
  456. pci_write_config_dword(mac->dma_pdev,
  457. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  458. PAS_DMA_TXCHAN_TCMDSTA_EN);
  459. pasemi_mac_replenish_rx_ring(dev);
  460. netif_start_queue(dev);
  461. netif_poll_enable(dev);
  462. ret = request_irq(mac->dma_pdev->irq + mac->dma_txch,
  463. &pasemi_mac_tx_intr, IRQF_DISABLED,
  464. mac->tx->irq_name, dev);
  465. if (ret) {
  466. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  467. mac->dma_pdev->irq + mac->dma_txch, ret);
  468. goto out_tx_int;
  469. }
  470. ret = request_irq(mac->dma_pdev->irq + 20 + mac->dma_rxch,
  471. &pasemi_mac_rx_intr, IRQF_DISABLED,
  472. mac->rx->irq_name, dev);
  473. if (ret) {
  474. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  475. mac->dma_pdev->irq + 20 + mac->dma_rxch, ret);
  476. goto out_rx_int;
  477. }
  478. return 0;
  479. out_rx_int:
  480. free_irq(mac->dma_pdev->irq + mac->dma_txch, dev);
  481. out_tx_int:
  482. netif_poll_disable(dev);
  483. netif_stop_queue(dev);
  484. pasemi_mac_free_tx_resources(dev);
  485. out_tx_resources:
  486. pasemi_mac_free_rx_resources(dev);
  487. out_rx_resources:
  488. return ret;
  489. }
  490. #define MAX_RETRIES 5000
  491. static int pasemi_mac_close(struct net_device *dev)
  492. {
  493. struct pasemi_mac *mac = netdev_priv(dev);
  494. unsigned int stat;
  495. int retries;
  496. netif_stop_queue(dev);
  497. /* Clean out any pending buffers */
  498. pasemi_mac_clean_tx(mac);
  499. pasemi_mac_clean_rx(mac, RX_RING_SIZE);
  500. /* Disable interface */
  501. pci_write_config_dword(mac->dma_pdev,
  502. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  503. PAS_DMA_TXCHAN_TCMDSTA_ST);
  504. pci_write_config_dword(mac->dma_pdev,
  505. PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  506. PAS_DMA_RXINT_RCMDSTA_ST);
  507. pci_write_config_dword(mac->dma_pdev,
  508. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  509. PAS_DMA_RXCHAN_CCMDSTA_ST);
  510. for (retries = 0; retries < MAX_RETRIES; retries++) {
  511. pci_read_config_dword(mac->dma_pdev,
  512. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  513. &stat);
  514. if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)
  515. break;
  516. cond_resched();
  517. }
  518. if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) {
  519. dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
  520. }
  521. for (retries = 0; retries < MAX_RETRIES; retries++) {
  522. pci_read_config_dword(mac->dma_pdev,
  523. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  524. &stat);
  525. if (stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)
  526. break;
  527. cond_resched();
  528. }
  529. if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)) {
  530. dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
  531. }
  532. for (retries = 0; retries < MAX_RETRIES; retries++) {
  533. pci_read_config_dword(mac->dma_pdev,
  534. PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  535. &stat);
  536. if (stat & PAS_DMA_RXINT_RCMDSTA_ACT)
  537. break;
  538. cond_resched();
  539. }
  540. if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT)) {
  541. dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
  542. }
  543. /* Then, disable the channel. This must be done separately from
  544. * stopping, since you can't disable when active.
  545. */
  546. pci_write_config_dword(mac->dma_pdev,
  547. PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0);
  548. pci_write_config_dword(mac->dma_pdev,
  549. PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0);
  550. pci_write_config_dword(mac->dma_pdev,
  551. PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
  552. free_irq(mac->dma_pdev->irq + mac->dma_txch, dev);
  553. free_irq(mac->dma_pdev->irq + 20 + mac->dma_rxch, dev);
  554. /* Free resources */
  555. pasemi_mac_free_rx_resources(dev);
  556. pasemi_mac_free_tx_resources(dev);
  557. return 0;
  558. }
  559. static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
  560. {
  561. struct pasemi_mac *mac = netdev_priv(dev);
  562. struct pasemi_mac_txring *txring;
  563. struct pasemi_mac_buffer *info;
  564. struct pas_dma_xct_descr *dp;
  565. u64 dflags;
  566. dma_addr_t map;
  567. int flags;
  568. dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD;
  569. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  570. switch (skb->nh.iph->protocol) {
  571. case IPPROTO_TCP:
  572. dflags |= XCT_MACTX_CSUM_TCP;
  573. dflags |= XCT_MACTX_IPH((skb->h.raw - skb->nh.raw) >> 2);
  574. dflags |= XCT_MACTX_IPO(skb->nh.raw - skb->data);
  575. break;
  576. case IPPROTO_UDP:
  577. dflags |= XCT_MACTX_CSUM_UDP;
  578. dflags |= XCT_MACTX_IPH((skb->h.raw - skb->nh.raw) >> 2);
  579. dflags |= XCT_MACTX_IPO(skb->nh.raw - skb->data);
  580. break;
  581. }
  582. }
  583. map = pci_map_single(mac->dma_pdev, skb->data, skb->len, PCI_DMA_TODEVICE);
  584. if (dma_mapping_error(map))
  585. return NETDEV_TX_BUSY;
  586. txring = mac->tx;
  587. spin_lock_irqsave(&txring->lock, flags);
  588. if (txring->next_to_clean - txring->next_to_use == TX_RING_SIZE) {
  589. spin_unlock_irqrestore(&txring->lock, flags);
  590. pasemi_mac_clean_tx(mac);
  591. spin_lock_irqsave(&txring->lock, flags);
  592. if (txring->next_to_clean - txring->next_to_use ==
  593. TX_RING_SIZE) {
  594. /* Still no room -- stop the queue and wait for tx
  595. * intr when there's room.
  596. */
  597. netif_stop_queue(dev);
  598. goto out_err;
  599. }
  600. }
  601. dp = &TX_DESC(mac, txring->next_to_use);
  602. info = &TX_DESC_INFO(mac, txring->next_to_use);
  603. dp->mactx = dflags | XCT_MACTX_LLEN(skb->len);
  604. dp->ptr = XCT_PTR_LEN(skb->len) | XCT_PTR_ADDR(map);
  605. info->dma = map;
  606. info->skb = skb;
  607. txring->next_to_use++;
  608. mac->stats.tx_packets++;
  609. mac->stats.tx_bytes += skb->len;
  610. spin_unlock_irqrestore(&txring->lock, flags);
  611. pci_write_config_dword(mac->dma_pdev,
  612. PAS_DMA_TXCHAN_INCR(mac->dma_txch), 1);
  613. return NETDEV_TX_OK;
  614. out_err:
  615. spin_unlock_irqrestore(&txring->lock, flags);
  616. pci_unmap_single(mac->dma_pdev, map, skb->len, PCI_DMA_TODEVICE);
  617. return NETDEV_TX_BUSY;
  618. }
  619. static struct net_device_stats *pasemi_mac_get_stats(struct net_device *dev)
  620. {
  621. struct pasemi_mac *mac = netdev_priv(dev);
  622. return &mac->stats;
  623. }
  624. static void pasemi_mac_set_rx_mode(struct net_device *dev)
  625. {
  626. struct pasemi_mac *mac = netdev_priv(dev);
  627. unsigned int flags;
  628. pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags);
  629. /* Set promiscuous */
  630. if (dev->flags & IFF_PROMISC)
  631. flags |= PAS_MAC_CFG_PCFG_PR;
  632. else
  633. flags &= ~PAS_MAC_CFG_PCFG_PR;
  634. pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags);
  635. }
  636. static int pasemi_mac_poll(struct net_device *dev, int *budget)
  637. {
  638. int pkts, limit = min(*budget, dev->quota);
  639. struct pasemi_mac *mac = netdev_priv(dev);
  640. pkts = pasemi_mac_clean_rx(mac, limit);
  641. if (pkts < limit) {
  642. /* all done, no more packets present */
  643. netif_rx_complete(dev);
  644. /* re-enable receive interrupts */
  645. pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG,
  646. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(1000000));
  647. return 0;
  648. } else {
  649. /* used up our quantum, so reschedule */
  650. dev->quota -= pkts;
  651. *budget -= pkts;
  652. return 1;
  653. }
  654. }
  655. static int __devinit
  656. pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  657. {
  658. static int index = 0;
  659. struct net_device *dev;
  660. struct pasemi_mac *mac;
  661. int err;
  662. err = pci_enable_device(pdev);
  663. if (err)
  664. return err;
  665. dev = alloc_etherdev(sizeof(struct pasemi_mac));
  666. if (dev == NULL) {
  667. dev_err(&pdev->dev,
  668. "pasemi_mac: Could not allocate ethernet device.\n");
  669. err = -ENOMEM;
  670. goto out_disable_device;
  671. }
  672. SET_MODULE_OWNER(dev);
  673. pci_set_drvdata(pdev, dev);
  674. SET_NETDEV_DEV(dev, &pdev->dev);
  675. mac = netdev_priv(dev);
  676. mac->pdev = pdev;
  677. mac->netdev = dev;
  678. mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
  679. if (!mac->dma_pdev) {
  680. dev_err(&pdev->dev, "Can't find DMA Controller\n");
  681. err = -ENODEV;
  682. goto out_free_netdev;
  683. }
  684. mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
  685. if (!mac->iob_pdev) {
  686. dev_err(&pdev->dev, "Can't find I/O Bridge\n");
  687. err = -ENODEV;
  688. goto out_put_dma_pdev;
  689. }
  690. /* These should come out of the device tree eventually */
  691. mac->dma_txch = index;
  692. mac->dma_rxch = index;
  693. /* We probe GMAC before XAUI, but the DMA interfaces are
  694. * in XAUI, GMAC order.
  695. */
  696. if (index < 4)
  697. mac->dma_if = index + 2;
  698. else
  699. mac->dma_if = index - 4;
  700. index++;
  701. switch (pdev->device) {
  702. case 0xa005:
  703. mac->type = MAC_TYPE_GMAC;
  704. break;
  705. case 0xa006:
  706. mac->type = MAC_TYPE_XAUI;
  707. break;
  708. default:
  709. err = -ENODEV;
  710. goto out;
  711. }
  712. /* get mac addr from device tree */
  713. if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
  714. err = -ENODEV;
  715. goto out;
  716. }
  717. memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
  718. dev->open = pasemi_mac_open;
  719. dev->stop = pasemi_mac_close;
  720. dev->hard_start_xmit = pasemi_mac_start_tx;
  721. dev->get_stats = pasemi_mac_get_stats;
  722. dev->set_multicast_list = pasemi_mac_set_rx_mode;
  723. dev->weight = 64;
  724. dev->poll = pasemi_mac_poll;
  725. dev->features = NETIF_F_HW_CSUM;
  726. /* The dma status structure is located in the I/O bridge, and
  727. * is cache coherent.
  728. */
  729. if (!dma_status)
  730. /* XXXOJN This should come from the device tree */
  731. dma_status = __ioremap(0xfd800000, 0x1000, 0);
  732. mac->rx_status = &dma_status->rx_sta[mac->dma_rxch];
  733. mac->tx_status = &dma_status->tx_sta[mac->dma_txch];
  734. err = register_netdev(dev);
  735. if (err) {
  736. dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
  737. err);
  738. goto out;
  739. } else
  740. printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, "
  741. "hw addr %02x:%02x:%02x:%02x:%02x:%02x\n",
  742. dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
  743. mac->dma_if, mac->dma_txch, mac->dma_rxch,
  744. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  745. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  746. return err;
  747. out:
  748. pci_dev_put(mac->iob_pdev);
  749. out_put_dma_pdev:
  750. pci_dev_put(mac->dma_pdev);
  751. out_free_netdev:
  752. free_netdev(dev);
  753. out_disable_device:
  754. pci_disable_device(pdev);
  755. return err;
  756. }
  757. static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
  758. {
  759. struct net_device *netdev = pci_get_drvdata(pdev);
  760. struct pasemi_mac *mac;
  761. if (!netdev)
  762. return;
  763. mac = netdev_priv(netdev);
  764. unregister_netdev(netdev);
  765. pci_disable_device(pdev);
  766. pci_dev_put(mac->dma_pdev);
  767. pci_dev_put(mac->iob_pdev);
  768. pci_set_drvdata(pdev, NULL);
  769. free_netdev(netdev);
  770. }
  771. static struct pci_device_id pasemi_mac_pci_tbl[] = {
  772. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
  773. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
  774. };
  775. MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
  776. static struct pci_driver pasemi_mac_driver = {
  777. .name = "pasemi_mac",
  778. .id_table = pasemi_mac_pci_tbl,
  779. .probe = pasemi_mac_probe,
  780. .remove = __devexit_p(pasemi_mac_remove),
  781. };
  782. static void __exit pasemi_mac_cleanup_module(void)
  783. {
  784. pci_unregister_driver(&pasemi_mac_driver);
  785. __iounmap(dma_status);
  786. dma_status = NULL;
  787. }
  788. int pasemi_mac_init_module(void)
  789. {
  790. return pci_register_driver(&pasemi_mac_driver);
  791. }
  792. MODULE_LICENSE("GPL");
  793. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  794. MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
  795. module_init(pasemi_mac_init_module);
  796. module_exit(pasemi_mac_cleanup_module);