natsemi.c 91 KB

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  1. /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
  2. /*
  3. Written/copyright 1999-2001 by Donald Becker.
  4. Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
  5. Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
  6. Portions copyright 2004 Harald Welte <laforge@gnumonks.org>
  7. This software may be used and distributed according to the terms of
  8. the GNU General Public License (GPL), incorporated herein by reference.
  9. Drivers based on or derived from this code fall under the GPL and must
  10. retain the authorship, copyright and license notice. This file is not
  11. a complete program and may only be used when the entire operating
  12. system is licensed under the GPL. License for under other terms may be
  13. available. Contact the original author for details.
  14. The original author may be reached as becker@scyld.com, or at
  15. Scyld Computing Corporation
  16. 410 Severn Ave., Suite 210
  17. Annapolis MD 21403
  18. Support information and updates available at
  19. http://www.scyld.com/network/netsemi.html
  20. [link no longer provides useful info -jgarzik]
  21. TODO:
  22. * big endian support with CFG:BEM instead of cpu_to_le32
  23. */
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/string.h>
  27. #include <linux/timer.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/slab.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/pci.h>
  33. #include <linux/netdevice.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/init.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/ethtool.h>
  39. #include <linux/delay.h>
  40. #include <linux/rtnetlink.h>
  41. #include <linux/mii.h>
  42. #include <linux/crc32.h>
  43. #include <linux/bitops.h>
  44. #include <linux/prefetch.h>
  45. #include <asm/processor.h> /* Processor type for cache alignment. */
  46. #include <asm/io.h>
  47. #include <asm/irq.h>
  48. #include <asm/uaccess.h>
  49. #define DRV_NAME "natsemi"
  50. #define DRV_VERSION "2.1"
  51. #define DRV_RELDATE "Sept 11, 2006"
  52. #define RX_OFFSET 2
  53. /* Updated to recommendations in pci-skeleton v2.03. */
  54. /* The user-configurable values.
  55. These may be modified when a driver module is loaded.*/
  56. #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
  57. NETIF_MSG_LINK | \
  58. NETIF_MSG_WOL | \
  59. NETIF_MSG_RX_ERR | \
  60. NETIF_MSG_TX_ERR)
  61. static int debug = -1;
  62. static int mtu;
  63. /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
  64. This chip uses a 512 element hash table based on the Ethernet CRC. */
  65. static const int multicast_filter_limit = 100;
  66. /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  67. Setting to > 1518 effectively disables this feature. */
  68. static int rx_copybreak;
  69. /* Used to pass the media type, etc.
  70. Both 'options[]' and 'full_duplex[]' should exist for driver
  71. interoperability.
  72. The media type is usually passed in 'options[]'.
  73. */
  74. #define MAX_UNITS 8 /* More are supported, limit only on options */
  75. static int options[MAX_UNITS];
  76. static int full_duplex[MAX_UNITS];
  77. /* Operational parameters that are set at compile time. */
  78. /* Keep the ring sizes a power of two for compile efficiency.
  79. The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  80. Making the Tx ring too large decreases the effectiveness of channel
  81. bonding and packet priority.
  82. There are no ill effects from too-large receive rings. */
  83. #define TX_RING_SIZE 16
  84. #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
  85. #define RX_RING_SIZE 32
  86. /* Operational parameters that usually are not changed. */
  87. /* Time in jiffies before concluding the transmitter is hung. */
  88. #define TX_TIMEOUT (2*HZ)
  89. #define NATSEMI_HW_TIMEOUT 400
  90. #define NATSEMI_TIMER_FREQ 3*HZ
  91. #define NATSEMI_PG0_NREGS 64
  92. #define NATSEMI_RFDR_NREGS 8
  93. #define NATSEMI_PG1_NREGS 4
  94. #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
  95. NATSEMI_PG1_NREGS)
  96. #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
  97. #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
  98. /* Buffer sizes:
  99. * The nic writes 32-bit values, even if the upper bytes of
  100. * a 32-bit value are beyond the end of the buffer.
  101. */
  102. #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
  103. #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
  104. #define NATSEMI_LONGPKT 1518 /* limit for normal packets */
  105. #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
  106. /* These identify the driver base version and may not be removed. */
  107. static const char version[] __devinitdata =
  108. KERN_INFO DRV_NAME " dp8381x driver, version "
  109. DRV_VERSION ", " DRV_RELDATE "\n"
  110. KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
  111. KERN_INFO " http://www.scyld.com/network/natsemi.html\n"
  112. KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
  113. MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
  114. MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
  115. MODULE_LICENSE("GPL");
  116. module_param(mtu, int, 0);
  117. module_param(debug, int, 0);
  118. module_param(rx_copybreak, int, 0);
  119. module_param_array(options, int, NULL, 0);
  120. module_param_array(full_duplex, int, NULL, 0);
  121. MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
  122. MODULE_PARM_DESC(debug, "DP8381x default debug level");
  123. MODULE_PARM_DESC(rx_copybreak,
  124. "DP8381x copy breakpoint for copy-only-tiny-frames");
  125. MODULE_PARM_DESC(options,
  126. "DP8381x: Bits 0-3: media type, bit 17: full duplex");
  127. MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
  128. /*
  129. Theory of Operation
  130. I. Board Compatibility
  131. This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
  132. It also works with other chips in in the DP83810 series.
  133. II. Board-specific settings
  134. This driver requires the PCI interrupt line to be valid.
  135. It honors the EEPROM-set values.
  136. III. Driver operation
  137. IIIa. Ring buffers
  138. This driver uses two statically allocated fixed-size descriptor lists
  139. formed into rings by a branch from the final descriptor to the beginning of
  140. the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
  141. The NatSemi design uses a 'next descriptor' pointer that the driver forms
  142. into a list.
  143. IIIb/c. Transmit/Receive Structure
  144. This driver uses a zero-copy receive and transmit scheme.
  145. The driver allocates full frame size skbuffs for the Rx ring buffers at
  146. open() time and passes the skb->data field to the chip as receive data
  147. buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
  148. a fresh skbuff is allocated and the frame is copied to the new skbuff.
  149. When the incoming frame is larger, the skbuff is passed directly up the
  150. protocol stack. Buffers consumed this way are replaced by newly allocated
  151. skbuffs in a later phase of receives.
  152. The RX_COPYBREAK value is chosen to trade-off the memory wasted by
  153. using a full-sized skbuff for small frames vs. the copying costs of larger
  154. frames. New boards are typically used in generously configured machines
  155. and the underfilled buffers have negligible impact compared to the benefit of
  156. a single allocation size, so the default value of zero results in never
  157. copying packets. When copying is done, the cost is usually mitigated by using
  158. a combined copy/checksum routine. Copying also preloads the cache, which is
  159. most useful with small frames.
  160. A subtle aspect of the operation is that unaligned buffers are not permitted
  161. by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
  162. longword aligned for further processing. On copies frames are put into the
  163. skbuff at an offset of "+2", 16-byte aligning the IP header.
  164. IIId. Synchronization
  165. Most operations are synchronized on the np->lock irq spinlock, except the
  166. performance critical codepaths:
  167. The rx process only runs in the interrupt handler. Access from outside
  168. the interrupt handler is only permitted after disable_irq().
  169. The rx process usually runs under the netif_tx_lock. If np->intr_tx_reap
  170. is set, then access is permitted under spin_lock_irq(&np->lock).
  171. Thus configuration functions that want to access everything must call
  172. disable_irq(dev->irq);
  173. netif_tx_lock_bh(dev);
  174. spin_lock_irq(&np->lock);
  175. IV. Notes
  176. NatSemi PCI network controllers are very uncommon.
  177. IVb. References
  178. http://www.scyld.com/expert/100mbps.html
  179. http://www.scyld.com/expert/NWay.html
  180. Datasheet is available from:
  181. http://www.national.com/pf/DP/DP83815.html
  182. IVc. Errata
  183. None characterised.
  184. */
  185. /*
  186. * Support for fibre connections on Am79C874:
  187. * This phy needs a special setup when connected to a fibre cable.
  188. * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
  189. */
  190. #define PHYID_AM79C874 0x0022561b
  191. enum {
  192. MII_MCTRL = 0x15, /* mode control register */
  193. MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
  194. MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */
  195. };
  196. enum {
  197. NATSEMI_FLAG_IGNORE_PHY = 0x1,
  198. };
  199. /* array of board data directly indexed by pci_tbl[x].driver_data */
  200. static const struct {
  201. const char *name;
  202. unsigned long flags;
  203. unsigned int eeprom_size;
  204. } natsemi_pci_info[] __devinitdata = {
  205. { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 },
  206. { "NatSemi DP8381[56]", 0, 24 },
  207. };
  208. static const struct pci_device_id natsemi_pci_tbl[] __devinitdata = {
  209. { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 },
  210. { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
  211. { } /* terminate list */
  212. };
  213. MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
  214. /* Offsets to the device registers.
  215. Unlike software-only systems, device drivers interact with complex hardware.
  216. It's not useful to define symbolic names for every register bit in the
  217. device.
  218. */
  219. enum register_offsets {
  220. ChipCmd = 0x00,
  221. ChipConfig = 0x04,
  222. EECtrl = 0x08,
  223. PCIBusCfg = 0x0C,
  224. IntrStatus = 0x10,
  225. IntrMask = 0x14,
  226. IntrEnable = 0x18,
  227. IntrHoldoff = 0x1C, /* DP83816 only */
  228. TxRingPtr = 0x20,
  229. TxConfig = 0x24,
  230. RxRingPtr = 0x30,
  231. RxConfig = 0x34,
  232. ClkRun = 0x3C,
  233. WOLCmd = 0x40,
  234. PauseCmd = 0x44,
  235. RxFilterAddr = 0x48,
  236. RxFilterData = 0x4C,
  237. BootRomAddr = 0x50,
  238. BootRomData = 0x54,
  239. SiliconRev = 0x58,
  240. StatsCtrl = 0x5C,
  241. StatsData = 0x60,
  242. RxPktErrs = 0x60,
  243. RxMissed = 0x68,
  244. RxCRCErrs = 0x64,
  245. BasicControl = 0x80,
  246. BasicStatus = 0x84,
  247. AnegAdv = 0x90,
  248. AnegPeer = 0x94,
  249. PhyStatus = 0xC0,
  250. MIntrCtrl = 0xC4,
  251. MIntrStatus = 0xC8,
  252. PhyCtrl = 0xE4,
  253. /* These are from the spec, around page 78... on a separate table.
  254. * The meaning of these registers depend on the value of PGSEL. */
  255. PGSEL = 0xCC,
  256. PMDCSR = 0xE4,
  257. TSTDAT = 0xFC,
  258. DSPCFG = 0xF4,
  259. SDCFG = 0xF8
  260. };
  261. /* the values for the 'magic' registers above (PGSEL=1) */
  262. #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
  263. #define TSTDAT_VAL 0x0
  264. #define DSPCFG_VAL 0x5040
  265. #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
  266. #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
  267. #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */
  268. #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
  269. /* misc PCI space registers */
  270. enum pci_register_offsets {
  271. PCIPM = 0x44,
  272. };
  273. enum ChipCmd_bits {
  274. ChipReset = 0x100,
  275. RxReset = 0x20,
  276. TxReset = 0x10,
  277. RxOff = 0x08,
  278. RxOn = 0x04,
  279. TxOff = 0x02,
  280. TxOn = 0x01,
  281. };
  282. enum ChipConfig_bits {
  283. CfgPhyDis = 0x200,
  284. CfgPhyRst = 0x400,
  285. CfgExtPhy = 0x1000,
  286. CfgAnegEnable = 0x2000,
  287. CfgAneg100 = 0x4000,
  288. CfgAnegFull = 0x8000,
  289. CfgAnegDone = 0x8000000,
  290. CfgFullDuplex = 0x20000000,
  291. CfgSpeed100 = 0x40000000,
  292. CfgLink = 0x80000000,
  293. };
  294. enum EECtrl_bits {
  295. EE_ShiftClk = 0x04,
  296. EE_DataIn = 0x01,
  297. EE_ChipSelect = 0x08,
  298. EE_DataOut = 0x02,
  299. MII_Data = 0x10,
  300. MII_Write = 0x20,
  301. MII_ShiftClk = 0x40,
  302. };
  303. enum PCIBusCfg_bits {
  304. EepromReload = 0x4,
  305. };
  306. /* Bits in the interrupt status/mask registers. */
  307. enum IntrStatus_bits {
  308. IntrRxDone = 0x0001,
  309. IntrRxIntr = 0x0002,
  310. IntrRxErr = 0x0004,
  311. IntrRxEarly = 0x0008,
  312. IntrRxIdle = 0x0010,
  313. IntrRxOverrun = 0x0020,
  314. IntrTxDone = 0x0040,
  315. IntrTxIntr = 0x0080,
  316. IntrTxErr = 0x0100,
  317. IntrTxIdle = 0x0200,
  318. IntrTxUnderrun = 0x0400,
  319. StatsMax = 0x0800,
  320. SWInt = 0x1000,
  321. WOLPkt = 0x2000,
  322. LinkChange = 0x4000,
  323. IntrHighBits = 0x8000,
  324. RxStatusFIFOOver = 0x10000,
  325. IntrPCIErr = 0xf00000,
  326. RxResetDone = 0x1000000,
  327. TxResetDone = 0x2000000,
  328. IntrAbnormalSummary = 0xCD20,
  329. };
  330. /*
  331. * Default Interrupts:
  332. * Rx OK, Rx Packet Error, Rx Overrun,
  333. * Tx OK, Tx Packet Error, Tx Underrun,
  334. * MIB Service, Phy Interrupt, High Bits,
  335. * Rx Status FIFO overrun,
  336. * Received Target Abort, Received Master Abort,
  337. * Signalled System Error, Received Parity Error
  338. */
  339. #define DEFAULT_INTR 0x00f1cd65
  340. enum TxConfig_bits {
  341. TxDrthMask = 0x3f,
  342. TxFlthMask = 0x3f00,
  343. TxMxdmaMask = 0x700000,
  344. TxMxdma_512 = 0x0,
  345. TxMxdma_4 = 0x100000,
  346. TxMxdma_8 = 0x200000,
  347. TxMxdma_16 = 0x300000,
  348. TxMxdma_32 = 0x400000,
  349. TxMxdma_64 = 0x500000,
  350. TxMxdma_128 = 0x600000,
  351. TxMxdma_256 = 0x700000,
  352. TxCollRetry = 0x800000,
  353. TxAutoPad = 0x10000000,
  354. TxMacLoop = 0x20000000,
  355. TxHeartIgn = 0x40000000,
  356. TxCarrierIgn = 0x80000000
  357. };
  358. /*
  359. * Tx Configuration:
  360. * - 256 byte DMA burst length
  361. * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
  362. * - 64 bytes initial drain threshold (i.e. begin actual transmission
  363. * when 64 byte are in the fifo)
  364. * - on tx underruns, increase drain threshold by 64.
  365. * - at most use a drain threshold of 1472 bytes: The sum of the fill
  366. * threshold and the drain threshold must be less than 2016 bytes.
  367. *
  368. */
  369. #define TX_FLTH_VAL ((512/32) << 8)
  370. #define TX_DRTH_VAL_START (64/32)
  371. #define TX_DRTH_VAL_INC 2
  372. #define TX_DRTH_VAL_LIMIT (1472/32)
  373. enum RxConfig_bits {
  374. RxDrthMask = 0x3e,
  375. RxMxdmaMask = 0x700000,
  376. RxMxdma_512 = 0x0,
  377. RxMxdma_4 = 0x100000,
  378. RxMxdma_8 = 0x200000,
  379. RxMxdma_16 = 0x300000,
  380. RxMxdma_32 = 0x400000,
  381. RxMxdma_64 = 0x500000,
  382. RxMxdma_128 = 0x600000,
  383. RxMxdma_256 = 0x700000,
  384. RxAcceptLong = 0x8000000,
  385. RxAcceptTx = 0x10000000,
  386. RxAcceptRunt = 0x40000000,
  387. RxAcceptErr = 0x80000000
  388. };
  389. #define RX_DRTH_VAL (128/8)
  390. enum ClkRun_bits {
  391. PMEEnable = 0x100,
  392. PMEStatus = 0x8000,
  393. };
  394. enum WolCmd_bits {
  395. WakePhy = 0x1,
  396. WakeUnicast = 0x2,
  397. WakeMulticast = 0x4,
  398. WakeBroadcast = 0x8,
  399. WakeArp = 0x10,
  400. WakePMatch0 = 0x20,
  401. WakePMatch1 = 0x40,
  402. WakePMatch2 = 0x80,
  403. WakePMatch3 = 0x100,
  404. WakeMagic = 0x200,
  405. WakeMagicSecure = 0x400,
  406. SecureHack = 0x100000,
  407. WokePhy = 0x400000,
  408. WokeUnicast = 0x800000,
  409. WokeMulticast = 0x1000000,
  410. WokeBroadcast = 0x2000000,
  411. WokeArp = 0x4000000,
  412. WokePMatch0 = 0x8000000,
  413. WokePMatch1 = 0x10000000,
  414. WokePMatch2 = 0x20000000,
  415. WokePMatch3 = 0x40000000,
  416. WokeMagic = 0x80000000,
  417. WakeOptsSummary = 0x7ff
  418. };
  419. enum RxFilterAddr_bits {
  420. RFCRAddressMask = 0x3ff,
  421. AcceptMulticast = 0x00200000,
  422. AcceptMyPhys = 0x08000000,
  423. AcceptAllPhys = 0x10000000,
  424. AcceptAllMulticast = 0x20000000,
  425. AcceptBroadcast = 0x40000000,
  426. RxFilterEnable = 0x80000000
  427. };
  428. enum StatsCtrl_bits {
  429. StatsWarn = 0x1,
  430. StatsFreeze = 0x2,
  431. StatsClear = 0x4,
  432. StatsStrobe = 0x8,
  433. };
  434. enum MIntrCtrl_bits {
  435. MICRIntEn = 0x2,
  436. };
  437. enum PhyCtrl_bits {
  438. PhyAddrMask = 0x1f,
  439. };
  440. #define PHY_ADDR_NONE 32
  441. #define PHY_ADDR_INTERNAL 1
  442. /* values we might find in the silicon revision register */
  443. #define SRR_DP83815_C 0x0302
  444. #define SRR_DP83815_D 0x0403
  445. #define SRR_DP83816_A4 0x0504
  446. #define SRR_DP83816_A5 0x0505
  447. /* The Rx and Tx buffer descriptors. */
  448. /* Note that using only 32 bit fields simplifies conversion to big-endian
  449. architectures. */
  450. struct netdev_desc {
  451. u32 next_desc;
  452. s32 cmd_status;
  453. u32 addr;
  454. u32 software_use;
  455. };
  456. /* Bits in network_desc.status */
  457. enum desc_status_bits {
  458. DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
  459. DescNoCRC=0x10000000, DescPktOK=0x08000000,
  460. DescSizeMask=0xfff,
  461. DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
  462. DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
  463. DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
  464. DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
  465. DescRxAbort=0x04000000, DescRxOver=0x02000000,
  466. DescRxDest=0x01800000, DescRxLong=0x00400000,
  467. DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
  468. DescRxCRC=0x00080000, DescRxAlign=0x00040000,
  469. DescRxLoop=0x00020000, DesRxColl=0x00010000,
  470. };
  471. struct netdev_private {
  472. /* Descriptor rings first for alignment */
  473. dma_addr_t ring_dma;
  474. struct netdev_desc *rx_ring;
  475. struct netdev_desc *tx_ring;
  476. /* The addresses of receive-in-place skbuffs */
  477. struct sk_buff *rx_skbuff[RX_RING_SIZE];
  478. dma_addr_t rx_dma[RX_RING_SIZE];
  479. /* address of a sent-in-place packet/buffer, for later free() */
  480. struct sk_buff *tx_skbuff[TX_RING_SIZE];
  481. dma_addr_t tx_dma[TX_RING_SIZE];
  482. struct net_device_stats stats;
  483. /* Media monitoring timer */
  484. struct timer_list timer;
  485. /* Frequently used values: keep some adjacent for cache effect */
  486. struct pci_dev *pci_dev;
  487. struct netdev_desc *rx_head_desc;
  488. /* Producer/consumer ring indices */
  489. unsigned int cur_rx, dirty_rx;
  490. unsigned int cur_tx, dirty_tx;
  491. /* Based on MTU+slack. */
  492. unsigned int rx_buf_sz;
  493. int oom;
  494. /* Interrupt status */
  495. u32 intr_status;
  496. /* Do not touch the nic registers */
  497. int hands_off;
  498. /* Don't pay attention to the reported link state. */
  499. int ignore_phy;
  500. /* external phy that is used: only valid if dev->if_port != PORT_TP */
  501. int mii;
  502. int phy_addr_external;
  503. unsigned int full_duplex;
  504. /* Rx filter */
  505. u32 cur_rx_mode;
  506. u32 rx_filter[16];
  507. /* FIFO and PCI burst thresholds */
  508. u32 tx_config, rx_config;
  509. /* original contents of ClkRun register */
  510. u32 SavedClkRun;
  511. /* silicon revision */
  512. u32 srr;
  513. /* expected DSPCFG value */
  514. u16 dspcfg;
  515. /* parms saved in ethtool format */
  516. u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
  517. u8 duplex; /* Duplex, half or full */
  518. u8 autoneg; /* Autonegotiation enabled */
  519. /* MII transceiver section */
  520. u16 advertising;
  521. unsigned int iosize;
  522. spinlock_t lock;
  523. u32 msg_enable;
  524. /* EEPROM data */
  525. int eeprom_size;
  526. };
  527. static void move_int_phy(struct net_device *dev, int addr);
  528. static int eeprom_read(void __iomem *ioaddr, int location);
  529. static int mdio_read(struct net_device *dev, int reg);
  530. static void mdio_write(struct net_device *dev, int reg, u16 data);
  531. static void init_phy_fixup(struct net_device *dev);
  532. static int miiport_read(struct net_device *dev, int phy_id, int reg);
  533. static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
  534. static int find_mii(struct net_device *dev);
  535. static void natsemi_reset(struct net_device *dev);
  536. static void natsemi_reload_eeprom(struct net_device *dev);
  537. static void natsemi_stop_rxtx(struct net_device *dev);
  538. static int netdev_open(struct net_device *dev);
  539. static void do_cable_magic(struct net_device *dev);
  540. static void undo_cable_magic(struct net_device *dev);
  541. static void check_link(struct net_device *dev);
  542. static void netdev_timer(unsigned long data);
  543. static void dump_ring(struct net_device *dev);
  544. static void tx_timeout(struct net_device *dev);
  545. static int alloc_ring(struct net_device *dev);
  546. static void refill_rx(struct net_device *dev);
  547. static void init_ring(struct net_device *dev);
  548. static void drain_tx(struct net_device *dev);
  549. static void drain_ring(struct net_device *dev);
  550. static void free_ring(struct net_device *dev);
  551. static void reinit_ring(struct net_device *dev);
  552. static void init_registers(struct net_device *dev);
  553. static int start_tx(struct sk_buff *skb, struct net_device *dev);
  554. static irqreturn_t intr_handler(int irq, void *dev_instance);
  555. static void netdev_error(struct net_device *dev, int intr_status);
  556. static int natsemi_poll(struct net_device *dev, int *budget);
  557. static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do);
  558. static void netdev_tx_done(struct net_device *dev);
  559. static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
  560. #ifdef CONFIG_NET_POLL_CONTROLLER
  561. static void natsemi_poll_controller(struct net_device *dev);
  562. #endif
  563. static void __set_rx_mode(struct net_device *dev);
  564. static void set_rx_mode(struct net_device *dev);
  565. static void __get_stats(struct net_device *dev);
  566. static struct net_device_stats *get_stats(struct net_device *dev);
  567. static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  568. static int netdev_set_wol(struct net_device *dev, u32 newval);
  569. static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
  570. static int netdev_set_sopass(struct net_device *dev, u8 *newval);
  571. static int netdev_get_sopass(struct net_device *dev, u8 *data);
  572. static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
  573. static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
  574. static void enable_wol_mode(struct net_device *dev, int enable_intr);
  575. static int netdev_close(struct net_device *dev);
  576. static int netdev_get_regs(struct net_device *dev, u8 *buf);
  577. static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
  578. static const struct ethtool_ops ethtool_ops;
  579. static inline void __iomem *ns_ioaddr(struct net_device *dev)
  580. {
  581. return (void __iomem *) dev->base_addr;
  582. }
  583. static inline void natsemi_irq_enable(struct net_device *dev)
  584. {
  585. writel(1, ns_ioaddr(dev) + IntrEnable);
  586. readl(ns_ioaddr(dev) + IntrEnable);
  587. }
  588. static inline void natsemi_irq_disable(struct net_device *dev)
  589. {
  590. writel(0, ns_ioaddr(dev) + IntrEnable);
  591. readl(ns_ioaddr(dev) + IntrEnable);
  592. }
  593. static void move_int_phy(struct net_device *dev, int addr)
  594. {
  595. struct netdev_private *np = netdev_priv(dev);
  596. void __iomem *ioaddr = ns_ioaddr(dev);
  597. int target = 31;
  598. /*
  599. * The internal phy is visible on the external mii bus. Therefore we must
  600. * move it away before we can send commands to an external phy.
  601. * There are two addresses we must avoid:
  602. * - the address on the external phy that is used for transmission.
  603. * - the address that we want to access. User space can access phys
  604. * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
  605. * phy that is used for transmission.
  606. */
  607. if (target == addr)
  608. target--;
  609. if (target == np->phy_addr_external)
  610. target--;
  611. writew(target, ioaddr + PhyCtrl);
  612. readw(ioaddr + PhyCtrl);
  613. udelay(1);
  614. }
  615. static void __devinit natsemi_init_media (struct net_device *dev)
  616. {
  617. struct netdev_private *np = netdev_priv(dev);
  618. u32 tmp;
  619. if (np->ignore_phy)
  620. netif_carrier_on(dev);
  621. else
  622. netif_carrier_off(dev);
  623. /* get the initial settings from hardware */
  624. tmp = mdio_read(dev, MII_BMCR);
  625. np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
  626. np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
  627. np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
  628. np->advertising= mdio_read(dev, MII_ADVERTISE);
  629. if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
  630. && netif_msg_probe(np)) {
  631. printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
  632. "10%s %s duplex.\n",
  633. pci_name(np->pci_dev),
  634. (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
  635. "enabled, advertise" : "disabled, force",
  636. (np->advertising &
  637. (ADVERTISE_100FULL|ADVERTISE_100HALF))?
  638. "0" : "",
  639. (np->advertising &
  640. (ADVERTISE_100FULL|ADVERTISE_10FULL))?
  641. "full" : "half");
  642. }
  643. if (netif_msg_probe(np))
  644. printk(KERN_INFO
  645. "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
  646. pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
  647. np->advertising);
  648. }
  649. static int __devinit natsemi_probe1 (struct pci_dev *pdev,
  650. const struct pci_device_id *ent)
  651. {
  652. struct net_device *dev;
  653. struct netdev_private *np;
  654. int i, option, irq, chip_idx = ent->driver_data;
  655. static int find_cnt = -1;
  656. unsigned long iostart, iosize;
  657. void __iomem *ioaddr;
  658. const int pcibar = 1; /* PCI base address register */
  659. int prev_eedata;
  660. u32 tmp;
  661. /* when built into the kernel, we only print version if device is found */
  662. #ifndef MODULE
  663. static int printed_version;
  664. if (!printed_version++)
  665. printk(version);
  666. #endif
  667. i = pci_enable_device(pdev);
  668. if (i) return i;
  669. /* natsemi has a non-standard PM control register
  670. * in PCI config space. Some boards apparently need
  671. * to be brought to D0 in this manner.
  672. */
  673. pci_read_config_dword(pdev, PCIPM, &tmp);
  674. if (tmp & PCI_PM_CTRL_STATE_MASK) {
  675. /* D0 state, disable PME assertion */
  676. u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
  677. pci_write_config_dword(pdev, PCIPM, newtmp);
  678. }
  679. find_cnt++;
  680. iostart = pci_resource_start(pdev, pcibar);
  681. iosize = pci_resource_len(pdev, pcibar);
  682. irq = pdev->irq;
  683. pci_set_master(pdev);
  684. dev = alloc_etherdev(sizeof (struct netdev_private));
  685. if (!dev)
  686. return -ENOMEM;
  687. SET_MODULE_OWNER(dev);
  688. SET_NETDEV_DEV(dev, &pdev->dev);
  689. i = pci_request_regions(pdev, DRV_NAME);
  690. if (i)
  691. goto err_pci_request_regions;
  692. ioaddr = ioremap(iostart, iosize);
  693. if (!ioaddr) {
  694. i = -ENOMEM;
  695. goto err_ioremap;
  696. }
  697. /* Work around the dropped serial bit. */
  698. prev_eedata = eeprom_read(ioaddr, 6);
  699. for (i = 0; i < 3; i++) {
  700. int eedata = eeprom_read(ioaddr, i + 7);
  701. dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
  702. dev->dev_addr[i*2+1] = eedata >> 7;
  703. prev_eedata = eedata;
  704. }
  705. dev->base_addr = (unsigned long __force) ioaddr;
  706. dev->irq = irq;
  707. np = netdev_priv(dev);
  708. np->pci_dev = pdev;
  709. pci_set_drvdata(pdev, dev);
  710. np->iosize = iosize;
  711. spin_lock_init(&np->lock);
  712. np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
  713. np->hands_off = 0;
  714. np->intr_status = 0;
  715. np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size;
  716. if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY)
  717. np->ignore_phy = 1;
  718. else
  719. np->ignore_phy = 0;
  720. /* Initial port:
  721. * - If configured to ignore the PHY set up for external.
  722. * - If the nic was configured to use an external phy and if find_mii
  723. * finds a phy: use external port, first phy that replies.
  724. * - Otherwise: internal port.
  725. * Note that the phy address for the internal phy doesn't matter:
  726. * The address would be used to access a phy over the mii bus, but
  727. * the internal phy is accessed through mapped registers.
  728. */
  729. if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy)
  730. dev->if_port = PORT_MII;
  731. else
  732. dev->if_port = PORT_TP;
  733. /* Reset the chip to erase previous misconfiguration. */
  734. natsemi_reload_eeprom(dev);
  735. natsemi_reset(dev);
  736. if (dev->if_port != PORT_TP) {
  737. np->phy_addr_external = find_mii(dev);
  738. /* If we're ignoring the PHY it doesn't matter if we can't
  739. * find one. */
  740. if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) {
  741. dev->if_port = PORT_TP;
  742. np->phy_addr_external = PHY_ADDR_INTERNAL;
  743. }
  744. } else {
  745. np->phy_addr_external = PHY_ADDR_INTERNAL;
  746. }
  747. option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
  748. if (dev->mem_start)
  749. option = dev->mem_start;
  750. /* The lower four bits are the media type. */
  751. if (option) {
  752. if (option & 0x200)
  753. np->full_duplex = 1;
  754. if (option & 15)
  755. printk(KERN_INFO
  756. "natsemi %s: ignoring user supplied media type %d",
  757. pci_name(np->pci_dev), option & 15);
  758. }
  759. if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
  760. np->full_duplex = 1;
  761. /* The chip-specific entries in the device structure. */
  762. dev->open = &netdev_open;
  763. dev->hard_start_xmit = &start_tx;
  764. dev->stop = &netdev_close;
  765. dev->get_stats = &get_stats;
  766. dev->set_multicast_list = &set_rx_mode;
  767. dev->change_mtu = &natsemi_change_mtu;
  768. dev->do_ioctl = &netdev_ioctl;
  769. dev->tx_timeout = &tx_timeout;
  770. dev->watchdog_timeo = TX_TIMEOUT;
  771. dev->poll = natsemi_poll;
  772. dev->weight = 64;
  773. #ifdef CONFIG_NET_POLL_CONTROLLER
  774. dev->poll_controller = &natsemi_poll_controller;
  775. #endif
  776. SET_ETHTOOL_OPS(dev, &ethtool_ops);
  777. if (mtu)
  778. dev->mtu = mtu;
  779. natsemi_init_media(dev);
  780. /* save the silicon revision for later querying */
  781. np->srr = readl(ioaddr + SiliconRev);
  782. if (netif_msg_hw(np))
  783. printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
  784. pci_name(np->pci_dev), np->srr);
  785. i = register_netdev(dev);
  786. if (i)
  787. goto err_register_netdev;
  788. if (netif_msg_drv(np)) {
  789. printk(KERN_INFO "natsemi %s: %s at %#08lx (%s), ",
  790. dev->name, natsemi_pci_info[chip_idx].name, iostart,
  791. pci_name(np->pci_dev));
  792. for (i = 0; i < ETH_ALEN-1; i++)
  793. printk("%02x:", dev->dev_addr[i]);
  794. printk("%02x, IRQ %d", dev->dev_addr[i], irq);
  795. if (dev->if_port == PORT_TP)
  796. printk(", port TP.\n");
  797. else if (np->ignore_phy)
  798. printk(", port MII, ignoring PHY\n");
  799. else
  800. printk(", port MII, phy ad %d.\n", np->phy_addr_external);
  801. }
  802. return 0;
  803. err_register_netdev:
  804. iounmap(ioaddr);
  805. err_ioremap:
  806. pci_release_regions(pdev);
  807. pci_set_drvdata(pdev, NULL);
  808. err_pci_request_regions:
  809. free_netdev(dev);
  810. return i;
  811. }
  812. /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
  813. The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
  814. /* Delay between EEPROM clock transitions.
  815. No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
  816. a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
  817. made udelay() unreliable.
  818. The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
  819. depricated.
  820. */
  821. #define eeprom_delay(ee_addr) readl(ee_addr)
  822. #define EE_Write0 (EE_ChipSelect)
  823. #define EE_Write1 (EE_ChipSelect | EE_DataIn)
  824. /* The EEPROM commands include the alway-set leading bit. */
  825. enum EEPROM_Cmds {
  826. EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
  827. };
  828. static int eeprom_read(void __iomem *addr, int location)
  829. {
  830. int i;
  831. int retval = 0;
  832. void __iomem *ee_addr = addr + EECtrl;
  833. int read_cmd = location | EE_ReadCmd;
  834. writel(EE_Write0, ee_addr);
  835. /* Shift the read command bits out. */
  836. for (i = 10; i >= 0; i--) {
  837. short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
  838. writel(dataval, ee_addr);
  839. eeprom_delay(ee_addr);
  840. writel(dataval | EE_ShiftClk, ee_addr);
  841. eeprom_delay(ee_addr);
  842. }
  843. writel(EE_ChipSelect, ee_addr);
  844. eeprom_delay(ee_addr);
  845. for (i = 0; i < 16; i++) {
  846. writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
  847. eeprom_delay(ee_addr);
  848. retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
  849. writel(EE_ChipSelect, ee_addr);
  850. eeprom_delay(ee_addr);
  851. }
  852. /* Terminate the EEPROM access. */
  853. writel(EE_Write0, ee_addr);
  854. writel(0, ee_addr);
  855. return retval;
  856. }
  857. /* MII transceiver control section.
  858. * The 83815 series has an internal transceiver, and we present the
  859. * internal management registers as if they were MII connected.
  860. * External Phy registers are referenced through the MII interface.
  861. */
  862. /* clock transitions >= 20ns (25MHz)
  863. * One readl should be good to PCI @ 100MHz
  864. */
  865. #define mii_delay(ioaddr) readl(ioaddr + EECtrl)
  866. static int mii_getbit (struct net_device *dev)
  867. {
  868. int data;
  869. void __iomem *ioaddr = ns_ioaddr(dev);
  870. writel(MII_ShiftClk, ioaddr + EECtrl);
  871. data = readl(ioaddr + EECtrl);
  872. writel(0, ioaddr + EECtrl);
  873. mii_delay(ioaddr);
  874. return (data & MII_Data)? 1 : 0;
  875. }
  876. static void mii_send_bits (struct net_device *dev, u32 data, int len)
  877. {
  878. u32 i;
  879. void __iomem *ioaddr = ns_ioaddr(dev);
  880. for (i = (1 << (len-1)); i; i >>= 1)
  881. {
  882. u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
  883. writel(mdio_val, ioaddr + EECtrl);
  884. mii_delay(ioaddr);
  885. writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl);
  886. mii_delay(ioaddr);
  887. }
  888. writel(0, ioaddr + EECtrl);
  889. mii_delay(ioaddr);
  890. }
  891. static int miiport_read(struct net_device *dev, int phy_id, int reg)
  892. {
  893. u32 cmd;
  894. int i;
  895. u32 retval = 0;
  896. /* Ensure sync */
  897. mii_send_bits (dev, 0xffffffff, 32);
  898. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  899. /* ST,OP = 0110'b for read operation */
  900. cmd = (0x06 << 10) | (phy_id << 5) | reg;
  901. mii_send_bits (dev, cmd, 14);
  902. /* Turnaround */
  903. if (mii_getbit (dev))
  904. return 0;
  905. /* Read data */
  906. for (i = 0; i < 16; i++) {
  907. retval <<= 1;
  908. retval |= mii_getbit (dev);
  909. }
  910. /* End cycle */
  911. mii_getbit (dev);
  912. return retval;
  913. }
  914. static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
  915. {
  916. u32 cmd;
  917. /* Ensure sync */
  918. mii_send_bits (dev, 0xffffffff, 32);
  919. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  920. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  921. cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
  922. mii_send_bits (dev, cmd, 32);
  923. /* End cycle */
  924. mii_getbit (dev);
  925. }
  926. static int mdio_read(struct net_device *dev, int reg)
  927. {
  928. struct netdev_private *np = netdev_priv(dev);
  929. void __iomem *ioaddr = ns_ioaddr(dev);
  930. /* The 83815 series has two ports:
  931. * - an internal transceiver
  932. * - an external mii bus
  933. */
  934. if (dev->if_port == PORT_TP)
  935. return readw(ioaddr+BasicControl+(reg<<2));
  936. else
  937. return miiport_read(dev, np->phy_addr_external, reg);
  938. }
  939. static void mdio_write(struct net_device *dev, int reg, u16 data)
  940. {
  941. struct netdev_private *np = netdev_priv(dev);
  942. void __iomem *ioaddr = ns_ioaddr(dev);
  943. /* The 83815 series has an internal transceiver; handle separately */
  944. if (dev->if_port == PORT_TP)
  945. writew(data, ioaddr+BasicControl+(reg<<2));
  946. else
  947. miiport_write(dev, np->phy_addr_external, reg, data);
  948. }
  949. static void init_phy_fixup(struct net_device *dev)
  950. {
  951. struct netdev_private *np = netdev_priv(dev);
  952. void __iomem *ioaddr = ns_ioaddr(dev);
  953. int i;
  954. u32 cfg;
  955. u16 tmp;
  956. /* restore stuff lost when power was out */
  957. tmp = mdio_read(dev, MII_BMCR);
  958. if (np->autoneg == AUTONEG_ENABLE) {
  959. /* renegotiate if something changed */
  960. if ((tmp & BMCR_ANENABLE) == 0
  961. || np->advertising != mdio_read(dev, MII_ADVERTISE))
  962. {
  963. /* turn on autonegotiation and force negotiation */
  964. tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
  965. mdio_write(dev, MII_ADVERTISE, np->advertising);
  966. }
  967. } else {
  968. /* turn off auto negotiation, set speed and duplexity */
  969. tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
  970. if (np->speed == SPEED_100)
  971. tmp |= BMCR_SPEED100;
  972. if (np->duplex == DUPLEX_FULL)
  973. tmp |= BMCR_FULLDPLX;
  974. /*
  975. * Note: there is no good way to inform the link partner
  976. * that our capabilities changed. The user has to unplug
  977. * and replug the network cable after some changes, e.g.
  978. * after switching from 10HD, autoneg off to 100 HD,
  979. * autoneg off.
  980. */
  981. }
  982. mdio_write(dev, MII_BMCR, tmp);
  983. readl(ioaddr + ChipConfig);
  984. udelay(1);
  985. /* find out what phy this is */
  986. np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
  987. + mdio_read(dev, MII_PHYSID2);
  988. /* handle external phys here */
  989. switch (np->mii) {
  990. case PHYID_AM79C874:
  991. /* phy specific configuration for fibre/tp operation */
  992. tmp = mdio_read(dev, MII_MCTRL);
  993. tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
  994. if (dev->if_port == PORT_FIBRE)
  995. tmp |= MII_FX_SEL;
  996. else
  997. tmp |= MII_EN_SCRM;
  998. mdio_write(dev, MII_MCTRL, tmp);
  999. break;
  1000. default:
  1001. break;
  1002. }
  1003. cfg = readl(ioaddr + ChipConfig);
  1004. if (cfg & CfgExtPhy)
  1005. return;
  1006. /* On page 78 of the spec, they recommend some settings for "optimum
  1007. performance" to be done in sequence. These settings optimize some
  1008. of the 100Mbit autodetection circuitry. They say we only want to
  1009. do this for rev C of the chip, but engineers at NSC (Bradley
  1010. Kennedy) recommends always setting them. If you don't, you get
  1011. errors on some autonegotiations that make the device unusable.
  1012. It seems that the DSP needs a few usec to reinitialize after
  1013. the start of the phy. Just retry writing these values until they
  1014. stick.
  1015. */
  1016. for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
  1017. int dspcfg;
  1018. writew(1, ioaddr + PGSEL);
  1019. writew(PMDCSR_VAL, ioaddr + PMDCSR);
  1020. writew(TSTDAT_VAL, ioaddr + TSTDAT);
  1021. np->dspcfg = (np->srr <= SRR_DP83815_C)?
  1022. DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG));
  1023. writew(np->dspcfg, ioaddr + DSPCFG);
  1024. writew(SDCFG_VAL, ioaddr + SDCFG);
  1025. writew(0, ioaddr + PGSEL);
  1026. readl(ioaddr + ChipConfig);
  1027. udelay(10);
  1028. writew(1, ioaddr + PGSEL);
  1029. dspcfg = readw(ioaddr + DSPCFG);
  1030. writew(0, ioaddr + PGSEL);
  1031. if (np->dspcfg == dspcfg)
  1032. break;
  1033. }
  1034. if (netif_msg_link(np)) {
  1035. if (i==NATSEMI_HW_TIMEOUT) {
  1036. printk(KERN_INFO
  1037. "%s: DSPCFG mismatch after retrying for %d usec.\n",
  1038. dev->name, i*10);
  1039. } else {
  1040. printk(KERN_INFO
  1041. "%s: DSPCFG accepted after %d usec.\n",
  1042. dev->name, i*10);
  1043. }
  1044. }
  1045. /*
  1046. * Enable PHY Specific event based interrupts. Link state change
  1047. * and Auto-Negotiation Completion are among the affected.
  1048. * Read the intr status to clear it (needed for wake events).
  1049. */
  1050. readw(ioaddr + MIntrStatus);
  1051. writew(MICRIntEn, ioaddr + MIntrCtrl);
  1052. }
  1053. static int switch_port_external(struct net_device *dev)
  1054. {
  1055. struct netdev_private *np = netdev_priv(dev);
  1056. void __iomem *ioaddr = ns_ioaddr(dev);
  1057. u32 cfg;
  1058. cfg = readl(ioaddr + ChipConfig);
  1059. if (cfg & CfgExtPhy)
  1060. return 0;
  1061. if (netif_msg_link(np)) {
  1062. printk(KERN_INFO "%s: switching to external transceiver.\n",
  1063. dev->name);
  1064. }
  1065. /* 1) switch back to external phy */
  1066. writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig);
  1067. readl(ioaddr + ChipConfig);
  1068. udelay(1);
  1069. /* 2) reset the external phy: */
  1070. /* resetting the external PHY has been known to cause a hub supplying
  1071. * power over Ethernet to kill the power. We don't want to kill
  1072. * power to this computer, so we avoid resetting the phy.
  1073. */
  1074. /* 3) reinit the phy fixup, it got lost during power down. */
  1075. move_int_phy(dev, np->phy_addr_external);
  1076. init_phy_fixup(dev);
  1077. return 1;
  1078. }
  1079. static int switch_port_internal(struct net_device *dev)
  1080. {
  1081. struct netdev_private *np = netdev_priv(dev);
  1082. void __iomem *ioaddr = ns_ioaddr(dev);
  1083. int i;
  1084. u32 cfg;
  1085. u16 bmcr;
  1086. cfg = readl(ioaddr + ChipConfig);
  1087. if (!(cfg &CfgExtPhy))
  1088. return 0;
  1089. if (netif_msg_link(np)) {
  1090. printk(KERN_INFO "%s: switching to internal transceiver.\n",
  1091. dev->name);
  1092. }
  1093. /* 1) switch back to internal phy: */
  1094. cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
  1095. writel(cfg, ioaddr + ChipConfig);
  1096. readl(ioaddr + ChipConfig);
  1097. udelay(1);
  1098. /* 2) reset the internal phy: */
  1099. bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
  1100. writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2));
  1101. readl(ioaddr + ChipConfig);
  1102. udelay(10);
  1103. for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
  1104. bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2));
  1105. if (!(bmcr & BMCR_RESET))
  1106. break;
  1107. udelay(10);
  1108. }
  1109. if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
  1110. printk(KERN_INFO
  1111. "%s: phy reset did not complete in %d usec.\n",
  1112. dev->name, i*10);
  1113. }
  1114. /* 3) reinit the phy fixup, it got lost during power down. */
  1115. init_phy_fixup(dev);
  1116. return 1;
  1117. }
  1118. /* Scan for a PHY on the external mii bus.
  1119. * There are two tricky points:
  1120. * - Do not scan while the internal phy is enabled. The internal phy will
  1121. * crash: e.g. reads from the DSPCFG register will return odd values and
  1122. * the nasty random phy reset code will reset the nic every few seconds.
  1123. * - The internal phy must be moved around, an external phy could
  1124. * have the same address as the internal phy.
  1125. */
  1126. static int find_mii(struct net_device *dev)
  1127. {
  1128. struct netdev_private *np = netdev_priv(dev);
  1129. int tmp;
  1130. int i;
  1131. int did_switch;
  1132. /* Switch to external phy */
  1133. did_switch = switch_port_external(dev);
  1134. /* Scan the possible phy addresses:
  1135. *
  1136. * PHY address 0 means that the phy is in isolate mode. Not yet
  1137. * supported due to lack of test hardware. User space should
  1138. * handle it through ethtool.
  1139. */
  1140. for (i = 1; i <= 31; i++) {
  1141. move_int_phy(dev, i);
  1142. tmp = miiport_read(dev, i, MII_BMSR);
  1143. if (tmp != 0xffff && tmp != 0x0000) {
  1144. /* found something! */
  1145. np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
  1146. + mdio_read(dev, MII_PHYSID2);
  1147. if (netif_msg_probe(np)) {
  1148. printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
  1149. pci_name(np->pci_dev), np->mii, i);
  1150. }
  1151. break;
  1152. }
  1153. }
  1154. /* And switch back to internal phy: */
  1155. if (did_switch)
  1156. switch_port_internal(dev);
  1157. return i;
  1158. }
  1159. /* CFG bits [13:16] [18:23] */
  1160. #define CFG_RESET_SAVE 0xfde000
  1161. /* WCSR bits [0:4] [9:10] */
  1162. #define WCSR_RESET_SAVE 0x61f
  1163. /* RFCR bits [20] [22] [27:31] */
  1164. #define RFCR_RESET_SAVE 0xf8500000;
  1165. static void natsemi_reset(struct net_device *dev)
  1166. {
  1167. int i;
  1168. u32 cfg;
  1169. u32 wcsr;
  1170. u32 rfcr;
  1171. u16 pmatch[3];
  1172. u16 sopass[3];
  1173. struct netdev_private *np = netdev_priv(dev);
  1174. void __iomem *ioaddr = ns_ioaddr(dev);
  1175. /*
  1176. * Resetting the chip causes some registers to be lost.
  1177. * Natsemi suggests NOT reloading the EEPROM while live, so instead
  1178. * we save the state that would have been loaded from EEPROM
  1179. * on a normal power-up (see the spec EEPROM map). This assumes
  1180. * whoever calls this will follow up with init_registers() eventually.
  1181. */
  1182. /* CFG */
  1183. cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE;
  1184. /* WCSR */
  1185. wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE;
  1186. /* RFCR */
  1187. rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE;
  1188. /* PMATCH */
  1189. for (i = 0; i < 3; i++) {
  1190. writel(i*2, ioaddr + RxFilterAddr);
  1191. pmatch[i] = readw(ioaddr + RxFilterData);
  1192. }
  1193. /* SOPAS */
  1194. for (i = 0; i < 3; i++) {
  1195. writel(0xa+(i*2), ioaddr + RxFilterAddr);
  1196. sopass[i] = readw(ioaddr + RxFilterData);
  1197. }
  1198. /* now whack the chip */
  1199. writel(ChipReset, ioaddr + ChipCmd);
  1200. for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
  1201. if (!(readl(ioaddr + ChipCmd) & ChipReset))
  1202. break;
  1203. udelay(5);
  1204. }
  1205. if (i==NATSEMI_HW_TIMEOUT) {
  1206. printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
  1207. dev->name, i*5);
  1208. } else if (netif_msg_hw(np)) {
  1209. printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
  1210. dev->name, i*5);
  1211. }
  1212. /* restore CFG */
  1213. cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE;
  1214. /* turn on external phy if it was selected */
  1215. if (dev->if_port == PORT_TP)
  1216. cfg &= ~(CfgExtPhy | CfgPhyDis);
  1217. else
  1218. cfg |= (CfgExtPhy | CfgPhyDis);
  1219. writel(cfg, ioaddr + ChipConfig);
  1220. /* restore WCSR */
  1221. wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE;
  1222. writel(wcsr, ioaddr + WOLCmd);
  1223. /* read RFCR */
  1224. rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE;
  1225. /* restore PMATCH */
  1226. for (i = 0; i < 3; i++) {
  1227. writel(i*2, ioaddr + RxFilterAddr);
  1228. writew(pmatch[i], ioaddr + RxFilterData);
  1229. }
  1230. for (i = 0; i < 3; i++) {
  1231. writel(0xa+(i*2), ioaddr + RxFilterAddr);
  1232. writew(sopass[i], ioaddr + RxFilterData);
  1233. }
  1234. /* restore RFCR */
  1235. writel(rfcr, ioaddr + RxFilterAddr);
  1236. }
  1237. static void reset_rx(struct net_device *dev)
  1238. {
  1239. int i;
  1240. struct netdev_private *np = netdev_priv(dev);
  1241. void __iomem *ioaddr = ns_ioaddr(dev);
  1242. np->intr_status &= ~RxResetDone;
  1243. writel(RxReset, ioaddr + ChipCmd);
  1244. for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
  1245. np->intr_status |= readl(ioaddr + IntrStatus);
  1246. if (np->intr_status & RxResetDone)
  1247. break;
  1248. udelay(15);
  1249. }
  1250. if (i==NATSEMI_HW_TIMEOUT) {
  1251. printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n",
  1252. dev->name, i*15);
  1253. } else if (netif_msg_hw(np)) {
  1254. printk(KERN_WARNING "%s: RX reset took %d usec.\n",
  1255. dev->name, i*15);
  1256. }
  1257. }
  1258. static void natsemi_reload_eeprom(struct net_device *dev)
  1259. {
  1260. struct netdev_private *np = netdev_priv(dev);
  1261. void __iomem *ioaddr = ns_ioaddr(dev);
  1262. int i;
  1263. writel(EepromReload, ioaddr + PCIBusCfg);
  1264. for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
  1265. udelay(50);
  1266. if (!(readl(ioaddr + PCIBusCfg) & EepromReload))
  1267. break;
  1268. }
  1269. if (i==NATSEMI_HW_TIMEOUT) {
  1270. printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
  1271. pci_name(np->pci_dev), i*50);
  1272. } else if (netif_msg_hw(np)) {
  1273. printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
  1274. pci_name(np->pci_dev), i*50);
  1275. }
  1276. }
  1277. static void natsemi_stop_rxtx(struct net_device *dev)
  1278. {
  1279. void __iomem * ioaddr = ns_ioaddr(dev);
  1280. struct netdev_private *np = netdev_priv(dev);
  1281. int i;
  1282. writel(RxOff | TxOff, ioaddr + ChipCmd);
  1283. for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
  1284. if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
  1285. break;
  1286. udelay(5);
  1287. }
  1288. if (i==NATSEMI_HW_TIMEOUT) {
  1289. printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
  1290. dev->name, i*5);
  1291. } else if (netif_msg_hw(np)) {
  1292. printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
  1293. dev->name, i*5);
  1294. }
  1295. }
  1296. static int netdev_open(struct net_device *dev)
  1297. {
  1298. struct netdev_private *np = netdev_priv(dev);
  1299. void __iomem * ioaddr = ns_ioaddr(dev);
  1300. int i;
  1301. /* Reset the chip, just in case. */
  1302. natsemi_reset(dev);
  1303. i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
  1304. if (i) return i;
  1305. if (netif_msg_ifup(np))
  1306. printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
  1307. dev->name, dev->irq);
  1308. i = alloc_ring(dev);
  1309. if (i < 0) {
  1310. free_irq(dev->irq, dev);
  1311. return i;
  1312. }
  1313. init_ring(dev);
  1314. spin_lock_irq(&np->lock);
  1315. init_registers(dev);
  1316. /* now set the MAC address according to dev->dev_addr */
  1317. for (i = 0; i < 3; i++) {
  1318. u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
  1319. writel(i*2, ioaddr + RxFilterAddr);
  1320. writew(mac, ioaddr + RxFilterData);
  1321. }
  1322. writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
  1323. spin_unlock_irq(&np->lock);
  1324. netif_start_queue(dev);
  1325. if (netif_msg_ifup(np))
  1326. printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
  1327. dev->name, (int)readl(ioaddr + ChipCmd));
  1328. /* Set the timer to check for link beat. */
  1329. init_timer(&np->timer);
  1330. np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
  1331. np->timer.data = (unsigned long)dev;
  1332. np->timer.function = &netdev_timer; /* timer handler */
  1333. add_timer(&np->timer);
  1334. return 0;
  1335. }
  1336. static void do_cable_magic(struct net_device *dev)
  1337. {
  1338. struct netdev_private *np = netdev_priv(dev);
  1339. void __iomem *ioaddr = ns_ioaddr(dev);
  1340. if (dev->if_port != PORT_TP)
  1341. return;
  1342. if (np->srr >= SRR_DP83816_A5)
  1343. return;
  1344. /*
  1345. * 100 MBit links with short cables can trip an issue with the chip.
  1346. * The problem manifests as lots of CRC errors and/or flickering
  1347. * activity LED while idle. This process is based on instructions
  1348. * from engineers at National.
  1349. */
  1350. if (readl(ioaddr + ChipConfig) & CfgSpeed100) {
  1351. u16 data;
  1352. writew(1, ioaddr + PGSEL);
  1353. /*
  1354. * coefficient visibility should already be enabled via
  1355. * DSPCFG | 0x1000
  1356. */
  1357. data = readw(ioaddr + TSTDAT) & 0xff;
  1358. /*
  1359. * the value must be negative, and within certain values
  1360. * (these values all come from National)
  1361. */
  1362. if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
  1363. struct netdev_private *np = netdev_priv(dev);
  1364. /* the bug has been triggered - fix the coefficient */
  1365. writew(TSTDAT_FIXED, ioaddr + TSTDAT);
  1366. /* lock the value */
  1367. data = readw(ioaddr + DSPCFG);
  1368. np->dspcfg = data | DSPCFG_LOCK;
  1369. writew(np->dspcfg, ioaddr + DSPCFG);
  1370. }
  1371. writew(0, ioaddr + PGSEL);
  1372. }
  1373. }
  1374. static void undo_cable_magic(struct net_device *dev)
  1375. {
  1376. u16 data;
  1377. struct netdev_private *np = netdev_priv(dev);
  1378. void __iomem * ioaddr = ns_ioaddr(dev);
  1379. if (dev->if_port != PORT_TP)
  1380. return;
  1381. if (np->srr >= SRR_DP83816_A5)
  1382. return;
  1383. writew(1, ioaddr + PGSEL);
  1384. /* make sure the lock bit is clear */
  1385. data = readw(ioaddr + DSPCFG);
  1386. np->dspcfg = data & ~DSPCFG_LOCK;
  1387. writew(np->dspcfg, ioaddr + DSPCFG);
  1388. writew(0, ioaddr + PGSEL);
  1389. }
  1390. static void check_link(struct net_device *dev)
  1391. {
  1392. struct netdev_private *np = netdev_priv(dev);
  1393. void __iomem * ioaddr = ns_ioaddr(dev);
  1394. int duplex = np->duplex;
  1395. u16 bmsr;
  1396. /* If we are ignoring the PHY then don't try reading it. */
  1397. if (np->ignore_phy)
  1398. goto propagate_state;
  1399. /* The link status field is latched: it remains low after a temporary
  1400. * link failure until it's read. We need the current link status,
  1401. * thus read twice.
  1402. */
  1403. mdio_read(dev, MII_BMSR);
  1404. bmsr = mdio_read(dev, MII_BMSR);
  1405. if (!(bmsr & BMSR_LSTATUS)) {
  1406. if (netif_carrier_ok(dev)) {
  1407. if (netif_msg_link(np))
  1408. printk(KERN_NOTICE "%s: link down.\n",
  1409. dev->name);
  1410. netif_carrier_off(dev);
  1411. undo_cable_magic(dev);
  1412. }
  1413. return;
  1414. }
  1415. if (!netif_carrier_ok(dev)) {
  1416. if (netif_msg_link(np))
  1417. printk(KERN_NOTICE "%s: link up.\n", dev->name);
  1418. netif_carrier_on(dev);
  1419. do_cable_magic(dev);
  1420. }
  1421. duplex = np->full_duplex;
  1422. if (!duplex) {
  1423. if (bmsr & BMSR_ANEGCOMPLETE) {
  1424. int tmp = mii_nway_result(
  1425. np->advertising & mdio_read(dev, MII_LPA));
  1426. if (tmp == LPA_100FULL || tmp == LPA_10FULL)
  1427. duplex = 1;
  1428. } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
  1429. duplex = 1;
  1430. }
  1431. propagate_state:
  1432. /* if duplex is set then bit 28 must be set, too */
  1433. if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
  1434. if (netif_msg_link(np))
  1435. printk(KERN_INFO
  1436. "%s: Setting %s-duplex based on negotiated "
  1437. "link capability.\n", dev->name,
  1438. duplex ? "full" : "half");
  1439. if (duplex) {
  1440. np->rx_config |= RxAcceptTx;
  1441. np->tx_config |= TxCarrierIgn | TxHeartIgn;
  1442. } else {
  1443. np->rx_config &= ~RxAcceptTx;
  1444. np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
  1445. }
  1446. writel(np->tx_config, ioaddr + TxConfig);
  1447. writel(np->rx_config, ioaddr + RxConfig);
  1448. }
  1449. }
  1450. static void init_registers(struct net_device *dev)
  1451. {
  1452. struct netdev_private *np = netdev_priv(dev);
  1453. void __iomem * ioaddr = ns_ioaddr(dev);
  1454. init_phy_fixup(dev);
  1455. /* clear any interrupts that are pending, such as wake events */
  1456. readl(ioaddr + IntrStatus);
  1457. writel(np->ring_dma, ioaddr + RxRingPtr);
  1458. writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
  1459. ioaddr + TxRingPtr);
  1460. /* Initialize other registers.
  1461. * Configure the PCI bus bursts and FIFO thresholds.
  1462. * Configure for standard, in-spec Ethernet.
  1463. * Start with half-duplex. check_link will update
  1464. * to the correct settings.
  1465. */
  1466. /* DRTH: 2: start tx if 64 bytes are in the fifo
  1467. * FLTH: 0x10: refill with next packet if 512 bytes are free
  1468. * MXDMA: 0: up to 256 byte bursts.
  1469. * MXDMA must be <= FLTH
  1470. * ECRETRY=1
  1471. * ATP=1
  1472. */
  1473. np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
  1474. TX_FLTH_VAL | TX_DRTH_VAL_START;
  1475. writel(np->tx_config, ioaddr + TxConfig);
  1476. /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
  1477. * MXDMA 0: up to 256 byte bursts
  1478. */
  1479. np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
  1480. /* if receive ring now has bigger buffers than normal, enable jumbo */
  1481. if (np->rx_buf_sz > NATSEMI_LONGPKT)
  1482. np->rx_config |= RxAcceptLong;
  1483. writel(np->rx_config, ioaddr + RxConfig);
  1484. /* Disable PME:
  1485. * The PME bit is initialized from the EEPROM contents.
  1486. * PCI cards probably have PME disabled, but motherboard
  1487. * implementations may have PME set to enable WakeOnLan.
  1488. * With PME set the chip will scan incoming packets but
  1489. * nothing will be written to memory. */
  1490. np->SavedClkRun = readl(ioaddr + ClkRun);
  1491. writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
  1492. if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
  1493. printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
  1494. dev->name, readl(ioaddr + WOLCmd));
  1495. }
  1496. check_link(dev);
  1497. __set_rx_mode(dev);
  1498. /* Enable interrupts by setting the interrupt mask. */
  1499. writel(DEFAULT_INTR, ioaddr + IntrMask);
  1500. natsemi_irq_enable(dev);
  1501. writel(RxOn | TxOn, ioaddr + ChipCmd);
  1502. writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
  1503. }
  1504. /*
  1505. * netdev_timer:
  1506. * Purpose:
  1507. * 1) check for link changes. Usually they are handled by the MII interrupt
  1508. * but it doesn't hurt to check twice.
  1509. * 2) check for sudden death of the NIC:
  1510. * It seems that a reference set for this chip went out with incorrect info,
  1511. * and there exist boards that aren't quite right. An unexpected voltage
  1512. * drop can cause the PHY to get itself in a weird state (basically reset).
  1513. * NOTE: this only seems to affect revC chips.
  1514. * 3) check of death of the RX path due to OOM
  1515. */
  1516. static void netdev_timer(unsigned long data)
  1517. {
  1518. struct net_device *dev = (struct net_device *)data;
  1519. struct netdev_private *np = netdev_priv(dev);
  1520. void __iomem * ioaddr = ns_ioaddr(dev);
  1521. int next_tick = 5*HZ;
  1522. if (netif_msg_timer(np)) {
  1523. /* DO NOT read the IntrStatus register,
  1524. * a read clears any pending interrupts.
  1525. */
  1526. printk(KERN_DEBUG "%s: Media selection timer tick.\n",
  1527. dev->name);
  1528. }
  1529. if (dev->if_port == PORT_TP) {
  1530. u16 dspcfg;
  1531. spin_lock_irq(&np->lock);
  1532. /* check for a nasty random phy-reset - use dspcfg as a flag */
  1533. writew(1, ioaddr+PGSEL);
  1534. dspcfg = readw(ioaddr+DSPCFG);
  1535. writew(0, ioaddr+PGSEL);
  1536. if (dspcfg != np->dspcfg) {
  1537. if (!netif_queue_stopped(dev)) {
  1538. spin_unlock_irq(&np->lock);
  1539. if (netif_msg_hw(np))
  1540. printk(KERN_NOTICE "%s: possible phy reset: "
  1541. "re-initializing\n", dev->name);
  1542. disable_irq(dev->irq);
  1543. spin_lock_irq(&np->lock);
  1544. natsemi_stop_rxtx(dev);
  1545. dump_ring(dev);
  1546. reinit_ring(dev);
  1547. init_registers(dev);
  1548. spin_unlock_irq(&np->lock);
  1549. enable_irq(dev->irq);
  1550. } else {
  1551. /* hurry back */
  1552. next_tick = HZ;
  1553. spin_unlock_irq(&np->lock);
  1554. }
  1555. } else {
  1556. /* init_registers() calls check_link() for the above case */
  1557. check_link(dev);
  1558. spin_unlock_irq(&np->lock);
  1559. }
  1560. } else {
  1561. spin_lock_irq(&np->lock);
  1562. check_link(dev);
  1563. spin_unlock_irq(&np->lock);
  1564. }
  1565. if (np->oom) {
  1566. disable_irq(dev->irq);
  1567. np->oom = 0;
  1568. refill_rx(dev);
  1569. enable_irq(dev->irq);
  1570. if (!np->oom) {
  1571. writel(RxOn, ioaddr + ChipCmd);
  1572. } else {
  1573. next_tick = 1;
  1574. }
  1575. }
  1576. mod_timer(&np->timer, jiffies + next_tick);
  1577. }
  1578. static void dump_ring(struct net_device *dev)
  1579. {
  1580. struct netdev_private *np = netdev_priv(dev);
  1581. if (netif_msg_pktdata(np)) {
  1582. int i;
  1583. printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
  1584. for (i = 0; i < TX_RING_SIZE; i++) {
  1585. printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
  1586. i, np->tx_ring[i].next_desc,
  1587. np->tx_ring[i].cmd_status,
  1588. np->tx_ring[i].addr);
  1589. }
  1590. printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
  1591. for (i = 0; i < RX_RING_SIZE; i++) {
  1592. printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
  1593. i, np->rx_ring[i].next_desc,
  1594. np->rx_ring[i].cmd_status,
  1595. np->rx_ring[i].addr);
  1596. }
  1597. }
  1598. }
  1599. static void tx_timeout(struct net_device *dev)
  1600. {
  1601. struct netdev_private *np = netdev_priv(dev);
  1602. void __iomem * ioaddr = ns_ioaddr(dev);
  1603. disable_irq(dev->irq);
  1604. spin_lock_irq(&np->lock);
  1605. if (!np->hands_off) {
  1606. if (netif_msg_tx_err(np))
  1607. printk(KERN_WARNING
  1608. "%s: Transmit timed out, status %#08x,"
  1609. " resetting...\n",
  1610. dev->name, readl(ioaddr + IntrStatus));
  1611. dump_ring(dev);
  1612. natsemi_reset(dev);
  1613. reinit_ring(dev);
  1614. init_registers(dev);
  1615. } else {
  1616. printk(KERN_WARNING
  1617. "%s: tx_timeout while in hands_off state?\n",
  1618. dev->name);
  1619. }
  1620. spin_unlock_irq(&np->lock);
  1621. enable_irq(dev->irq);
  1622. dev->trans_start = jiffies;
  1623. np->stats.tx_errors++;
  1624. netif_wake_queue(dev);
  1625. }
  1626. static int alloc_ring(struct net_device *dev)
  1627. {
  1628. struct netdev_private *np = netdev_priv(dev);
  1629. np->rx_ring = pci_alloc_consistent(np->pci_dev,
  1630. sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
  1631. &np->ring_dma);
  1632. if (!np->rx_ring)
  1633. return -ENOMEM;
  1634. np->tx_ring = &np->rx_ring[RX_RING_SIZE];
  1635. return 0;
  1636. }
  1637. static void refill_rx(struct net_device *dev)
  1638. {
  1639. struct netdev_private *np = netdev_priv(dev);
  1640. /* Refill the Rx ring buffers. */
  1641. for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
  1642. struct sk_buff *skb;
  1643. int entry = np->dirty_rx % RX_RING_SIZE;
  1644. if (np->rx_skbuff[entry] == NULL) {
  1645. unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
  1646. skb = dev_alloc_skb(buflen);
  1647. np->rx_skbuff[entry] = skb;
  1648. if (skb == NULL)
  1649. break; /* Better luck next round. */
  1650. skb->dev = dev; /* Mark as being used by this device. */
  1651. np->rx_dma[entry] = pci_map_single(np->pci_dev,
  1652. skb->data, buflen, PCI_DMA_FROMDEVICE);
  1653. np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
  1654. }
  1655. np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
  1656. }
  1657. if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
  1658. if (netif_msg_rx_err(np))
  1659. printk(KERN_WARNING "%s: going OOM.\n", dev->name);
  1660. np->oom = 1;
  1661. }
  1662. }
  1663. static void set_bufsize(struct net_device *dev)
  1664. {
  1665. struct netdev_private *np = netdev_priv(dev);
  1666. if (dev->mtu <= ETH_DATA_LEN)
  1667. np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
  1668. else
  1669. np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
  1670. }
  1671. /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
  1672. static void init_ring(struct net_device *dev)
  1673. {
  1674. struct netdev_private *np = netdev_priv(dev);
  1675. int i;
  1676. /* 1) TX ring */
  1677. np->dirty_tx = np->cur_tx = 0;
  1678. for (i = 0; i < TX_RING_SIZE; i++) {
  1679. np->tx_skbuff[i] = NULL;
  1680. np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
  1681. +sizeof(struct netdev_desc)
  1682. *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
  1683. np->tx_ring[i].cmd_status = 0;
  1684. }
  1685. /* 2) RX ring */
  1686. np->dirty_rx = 0;
  1687. np->cur_rx = RX_RING_SIZE;
  1688. np->oom = 0;
  1689. set_bufsize(dev);
  1690. np->rx_head_desc = &np->rx_ring[0];
  1691. /* Please be carefull before changing this loop - at least gcc-2.95.1
  1692. * miscompiles it otherwise.
  1693. */
  1694. /* Initialize all Rx descriptors. */
  1695. for (i = 0; i < RX_RING_SIZE; i++) {
  1696. np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
  1697. +sizeof(struct netdev_desc)
  1698. *((i+1)%RX_RING_SIZE));
  1699. np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
  1700. np->rx_skbuff[i] = NULL;
  1701. }
  1702. refill_rx(dev);
  1703. dump_ring(dev);
  1704. }
  1705. static void drain_tx(struct net_device *dev)
  1706. {
  1707. struct netdev_private *np = netdev_priv(dev);
  1708. int i;
  1709. for (i = 0; i < TX_RING_SIZE; i++) {
  1710. if (np->tx_skbuff[i]) {
  1711. pci_unmap_single(np->pci_dev,
  1712. np->tx_dma[i], np->tx_skbuff[i]->len,
  1713. PCI_DMA_TODEVICE);
  1714. dev_kfree_skb(np->tx_skbuff[i]);
  1715. np->stats.tx_dropped++;
  1716. }
  1717. np->tx_skbuff[i] = NULL;
  1718. }
  1719. }
  1720. static void drain_rx(struct net_device *dev)
  1721. {
  1722. struct netdev_private *np = netdev_priv(dev);
  1723. unsigned int buflen = np->rx_buf_sz;
  1724. int i;
  1725. /* Free all the skbuffs in the Rx queue. */
  1726. for (i = 0; i < RX_RING_SIZE; i++) {
  1727. np->rx_ring[i].cmd_status = 0;
  1728. np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
  1729. if (np->rx_skbuff[i]) {
  1730. pci_unmap_single(np->pci_dev,
  1731. np->rx_dma[i], buflen,
  1732. PCI_DMA_FROMDEVICE);
  1733. dev_kfree_skb(np->rx_skbuff[i]);
  1734. }
  1735. np->rx_skbuff[i] = NULL;
  1736. }
  1737. }
  1738. static void drain_ring(struct net_device *dev)
  1739. {
  1740. drain_rx(dev);
  1741. drain_tx(dev);
  1742. }
  1743. static void free_ring(struct net_device *dev)
  1744. {
  1745. struct netdev_private *np = netdev_priv(dev);
  1746. pci_free_consistent(np->pci_dev,
  1747. sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
  1748. np->rx_ring, np->ring_dma);
  1749. }
  1750. static void reinit_rx(struct net_device *dev)
  1751. {
  1752. struct netdev_private *np = netdev_priv(dev);
  1753. int i;
  1754. /* RX Ring */
  1755. np->dirty_rx = 0;
  1756. np->cur_rx = RX_RING_SIZE;
  1757. np->rx_head_desc = &np->rx_ring[0];
  1758. /* Initialize all Rx descriptors. */
  1759. for (i = 0; i < RX_RING_SIZE; i++)
  1760. np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
  1761. refill_rx(dev);
  1762. }
  1763. static void reinit_ring(struct net_device *dev)
  1764. {
  1765. struct netdev_private *np = netdev_priv(dev);
  1766. int i;
  1767. /* drain TX ring */
  1768. drain_tx(dev);
  1769. np->dirty_tx = np->cur_tx = 0;
  1770. for (i=0;i<TX_RING_SIZE;i++)
  1771. np->tx_ring[i].cmd_status = 0;
  1772. reinit_rx(dev);
  1773. }
  1774. static int start_tx(struct sk_buff *skb, struct net_device *dev)
  1775. {
  1776. struct netdev_private *np = netdev_priv(dev);
  1777. void __iomem * ioaddr = ns_ioaddr(dev);
  1778. unsigned entry;
  1779. unsigned long flags;
  1780. /* Note: Ordering is important here, set the field with the
  1781. "ownership" bit last, and only then increment cur_tx. */
  1782. /* Calculate the next Tx descriptor entry. */
  1783. entry = np->cur_tx % TX_RING_SIZE;
  1784. np->tx_skbuff[entry] = skb;
  1785. np->tx_dma[entry] = pci_map_single(np->pci_dev,
  1786. skb->data,skb->len, PCI_DMA_TODEVICE);
  1787. np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
  1788. spin_lock_irqsave(&np->lock, flags);
  1789. if (!np->hands_off) {
  1790. np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
  1791. /* StrongARM: Explicitly cache flush np->tx_ring and
  1792. * skb->data,skb->len. */
  1793. wmb();
  1794. np->cur_tx++;
  1795. if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
  1796. netdev_tx_done(dev);
  1797. if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
  1798. netif_stop_queue(dev);
  1799. }
  1800. /* Wake the potentially-idle transmit channel. */
  1801. writel(TxOn, ioaddr + ChipCmd);
  1802. } else {
  1803. dev_kfree_skb_irq(skb);
  1804. np->stats.tx_dropped++;
  1805. }
  1806. spin_unlock_irqrestore(&np->lock, flags);
  1807. dev->trans_start = jiffies;
  1808. if (netif_msg_tx_queued(np)) {
  1809. printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
  1810. dev->name, np->cur_tx, entry);
  1811. }
  1812. return 0;
  1813. }
  1814. static void netdev_tx_done(struct net_device *dev)
  1815. {
  1816. struct netdev_private *np = netdev_priv(dev);
  1817. for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
  1818. int entry = np->dirty_tx % TX_RING_SIZE;
  1819. if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
  1820. break;
  1821. if (netif_msg_tx_done(np))
  1822. printk(KERN_DEBUG
  1823. "%s: tx frame #%d finished, status %#08x.\n",
  1824. dev->name, np->dirty_tx,
  1825. le32_to_cpu(np->tx_ring[entry].cmd_status));
  1826. if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
  1827. np->stats.tx_packets++;
  1828. np->stats.tx_bytes += np->tx_skbuff[entry]->len;
  1829. } else { /* Various Tx errors */
  1830. int tx_status =
  1831. le32_to_cpu(np->tx_ring[entry].cmd_status);
  1832. if (tx_status & (DescTxAbort|DescTxExcColl))
  1833. np->stats.tx_aborted_errors++;
  1834. if (tx_status & DescTxFIFO)
  1835. np->stats.tx_fifo_errors++;
  1836. if (tx_status & DescTxCarrier)
  1837. np->stats.tx_carrier_errors++;
  1838. if (tx_status & DescTxOOWCol)
  1839. np->stats.tx_window_errors++;
  1840. np->stats.tx_errors++;
  1841. }
  1842. pci_unmap_single(np->pci_dev,np->tx_dma[entry],
  1843. np->tx_skbuff[entry]->len,
  1844. PCI_DMA_TODEVICE);
  1845. /* Free the original skb. */
  1846. dev_kfree_skb_irq(np->tx_skbuff[entry]);
  1847. np->tx_skbuff[entry] = NULL;
  1848. }
  1849. if (netif_queue_stopped(dev)
  1850. && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
  1851. /* The ring is no longer full, wake queue. */
  1852. netif_wake_queue(dev);
  1853. }
  1854. }
  1855. /* The interrupt handler doesn't actually handle interrupts itself, it
  1856. * schedules a NAPI poll if there is anything to do. */
  1857. static irqreturn_t intr_handler(int irq, void *dev_instance)
  1858. {
  1859. struct net_device *dev = dev_instance;
  1860. struct netdev_private *np = netdev_priv(dev);
  1861. void __iomem * ioaddr = ns_ioaddr(dev);
  1862. /* Reading IntrStatus automatically acknowledges so don't do
  1863. * that while interrupts are disabled, (for example, while a
  1864. * poll is scheduled). */
  1865. if (np->hands_off || !readl(ioaddr + IntrEnable))
  1866. return IRQ_NONE;
  1867. np->intr_status = readl(ioaddr + IntrStatus);
  1868. if (!np->intr_status)
  1869. return IRQ_NONE;
  1870. if (netif_msg_intr(np))
  1871. printk(KERN_DEBUG
  1872. "%s: Interrupt, status %#08x, mask %#08x.\n",
  1873. dev->name, np->intr_status,
  1874. readl(ioaddr + IntrMask));
  1875. prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]);
  1876. if (netif_rx_schedule_prep(dev)) {
  1877. /* Disable interrupts and register for poll */
  1878. natsemi_irq_disable(dev);
  1879. __netif_rx_schedule(dev);
  1880. } else
  1881. printk(KERN_WARNING
  1882. "%s: Ignoring interrupt, status %#08x, mask %#08x.\n",
  1883. dev->name, np->intr_status,
  1884. readl(ioaddr + IntrMask));
  1885. return IRQ_HANDLED;
  1886. }
  1887. /* This is the NAPI poll routine. As well as the standard RX handling
  1888. * it also handles all other interrupts that the chip might raise.
  1889. */
  1890. static int natsemi_poll(struct net_device *dev, int *budget)
  1891. {
  1892. struct netdev_private *np = netdev_priv(dev);
  1893. void __iomem * ioaddr = ns_ioaddr(dev);
  1894. int work_to_do = min(*budget, dev->quota);
  1895. int work_done = 0;
  1896. do {
  1897. if (netif_msg_intr(np))
  1898. printk(KERN_DEBUG
  1899. "%s: Poll, status %#08x, mask %#08x.\n",
  1900. dev->name, np->intr_status,
  1901. readl(ioaddr + IntrMask));
  1902. /* netdev_rx() may read IntrStatus again if the RX state
  1903. * machine falls over so do it first. */
  1904. if (np->intr_status &
  1905. (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
  1906. IntrRxErr | IntrRxOverrun)) {
  1907. netdev_rx(dev, &work_done, work_to_do);
  1908. }
  1909. if (np->intr_status &
  1910. (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
  1911. spin_lock(&np->lock);
  1912. netdev_tx_done(dev);
  1913. spin_unlock(&np->lock);
  1914. }
  1915. /* Abnormal error summary/uncommon events handlers. */
  1916. if (np->intr_status & IntrAbnormalSummary)
  1917. netdev_error(dev, np->intr_status);
  1918. *budget -= work_done;
  1919. dev->quota -= work_done;
  1920. if (work_done >= work_to_do)
  1921. return 1;
  1922. np->intr_status = readl(ioaddr + IntrStatus);
  1923. } while (np->intr_status);
  1924. netif_rx_complete(dev);
  1925. /* Reenable interrupts providing nothing is trying to shut
  1926. * the chip down. */
  1927. spin_lock(&np->lock);
  1928. if (!np->hands_off && netif_running(dev))
  1929. natsemi_irq_enable(dev);
  1930. spin_unlock(&np->lock);
  1931. return 0;
  1932. }
  1933. /* This routine is logically part of the interrupt handler, but separated
  1934. for clarity and better register allocation. */
  1935. static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do)
  1936. {
  1937. struct netdev_private *np = netdev_priv(dev);
  1938. int entry = np->cur_rx % RX_RING_SIZE;
  1939. int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
  1940. s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
  1941. unsigned int buflen = np->rx_buf_sz;
  1942. void __iomem * ioaddr = ns_ioaddr(dev);
  1943. /* If the driver owns the next entry it's a new packet. Send it up. */
  1944. while (desc_status < 0) { /* e.g. & DescOwn */
  1945. int pkt_len;
  1946. if (netif_msg_rx_status(np))
  1947. printk(KERN_DEBUG
  1948. " netdev_rx() entry %d status was %#08x.\n",
  1949. entry, desc_status);
  1950. if (--boguscnt < 0)
  1951. break;
  1952. if (*work_done >= work_to_do)
  1953. break;
  1954. (*work_done)++;
  1955. pkt_len = (desc_status & DescSizeMask) - 4;
  1956. if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
  1957. if (desc_status & DescMore) {
  1958. unsigned long flags;
  1959. if (netif_msg_rx_err(np))
  1960. printk(KERN_WARNING
  1961. "%s: Oversized(?) Ethernet "
  1962. "frame spanned multiple "
  1963. "buffers, entry %#08x "
  1964. "status %#08x.\n", dev->name,
  1965. np->cur_rx, desc_status);
  1966. np->stats.rx_length_errors++;
  1967. /* The RX state machine has probably
  1968. * locked up beneath us. Follow the
  1969. * reset procedure documented in
  1970. * AN-1287. */
  1971. spin_lock_irqsave(&np->lock, flags);
  1972. reset_rx(dev);
  1973. reinit_rx(dev);
  1974. writel(np->ring_dma, ioaddr + RxRingPtr);
  1975. check_link(dev);
  1976. spin_unlock_irqrestore(&np->lock, flags);
  1977. /* We'll enable RX on exit from this
  1978. * function. */
  1979. break;
  1980. } else {
  1981. /* There was an error. */
  1982. np->stats.rx_errors++;
  1983. if (desc_status & (DescRxAbort|DescRxOver))
  1984. np->stats.rx_over_errors++;
  1985. if (desc_status & (DescRxLong|DescRxRunt))
  1986. np->stats.rx_length_errors++;
  1987. if (desc_status & (DescRxInvalid|DescRxAlign))
  1988. np->stats.rx_frame_errors++;
  1989. if (desc_status & DescRxCRC)
  1990. np->stats.rx_crc_errors++;
  1991. }
  1992. } else if (pkt_len > np->rx_buf_sz) {
  1993. /* if this is the tail of a double buffer
  1994. * packet, we've already counted the error
  1995. * on the first part. Ignore the second half.
  1996. */
  1997. } else {
  1998. struct sk_buff *skb;
  1999. /* Omit CRC size. */
  2000. /* Check if the packet is long enough to accept
  2001. * without copying to a minimally-sized skbuff. */
  2002. if (pkt_len < rx_copybreak
  2003. && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
  2004. skb->dev = dev;
  2005. /* 16 byte align the IP header */
  2006. skb_reserve(skb, RX_OFFSET);
  2007. pci_dma_sync_single_for_cpu(np->pci_dev,
  2008. np->rx_dma[entry],
  2009. buflen,
  2010. PCI_DMA_FROMDEVICE);
  2011. eth_copy_and_sum(skb,
  2012. np->rx_skbuff[entry]->data, pkt_len, 0);
  2013. skb_put(skb, pkt_len);
  2014. pci_dma_sync_single_for_device(np->pci_dev,
  2015. np->rx_dma[entry],
  2016. buflen,
  2017. PCI_DMA_FROMDEVICE);
  2018. } else {
  2019. pci_unmap_single(np->pci_dev, np->rx_dma[entry],
  2020. buflen, PCI_DMA_FROMDEVICE);
  2021. skb_put(skb = np->rx_skbuff[entry], pkt_len);
  2022. np->rx_skbuff[entry] = NULL;
  2023. }
  2024. skb->protocol = eth_type_trans(skb, dev);
  2025. netif_receive_skb(skb);
  2026. dev->last_rx = jiffies;
  2027. np->stats.rx_packets++;
  2028. np->stats.rx_bytes += pkt_len;
  2029. }
  2030. entry = (++np->cur_rx) % RX_RING_SIZE;
  2031. np->rx_head_desc = &np->rx_ring[entry];
  2032. desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
  2033. }
  2034. refill_rx(dev);
  2035. /* Restart Rx engine if stopped. */
  2036. if (np->oom)
  2037. mod_timer(&np->timer, jiffies + 1);
  2038. else
  2039. writel(RxOn, ioaddr + ChipCmd);
  2040. }
  2041. static void netdev_error(struct net_device *dev, int intr_status)
  2042. {
  2043. struct netdev_private *np = netdev_priv(dev);
  2044. void __iomem * ioaddr = ns_ioaddr(dev);
  2045. spin_lock(&np->lock);
  2046. if (intr_status & LinkChange) {
  2047. u16 lpa = mdio_read(dev, MII_LPA);
  2048. if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
  2049. && netif_msg_link(np)) {
  2050. printk(KERN_INFO
  2051. "%s: Autonegotiation advertising"
  2052. " %#04x partner %#04x.\n", dev->name,
  2053. np->advertising, lpa);
  2054. }
  2055. /* read MII int status to clear the flag */
  2056. readw(ioaddr + MIntrStatus);
  2057. check_link(dev);
  2058. }
  2059. if (intr_status & StatsMax) {
  2060. __get_stats(dev);
  2061. }
  2062. if (intr_status & IntrTxUnderrun) {
  2063. if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
  2064. np->tx_config += TX_DRTH_VAL_INC;
  2065. if (netif_msg_tx_err(np))
  2066. printk(KERN_NOTICE
  2067. "%s: increased tx threshold, txcfg %#08x.\n",
  2068. dev->name, np->tx_config);
  2069. } else {
  2070. if (netif_msg_tx_err(np))
  2071. printk(KERN_NOTICE
  2072. "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
  2073. dev->name, np->tx_config);
  2074. }
  2075. writel(np->tx_config, ioaddr + TxConfig);
  2076. }
  2077. if (intr_status & WOLPkt && netif_msg_wol(np)) {
  2078. int wol_status = readl(ioaddr + WOLCmd);
  2079. printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
  2080. dev->name, wol_status);
  2081. }
  2082. if (intr_status & RxStatusFIFOOver) {
  2083. if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
  2084. printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
  2085. dev->name);
  2086. }
  2087. np->stats.rx_fifo_errors++;
  2088. }
  2089. /* Hmmmmm, it's not clear how to recover from PCI faults. */
  2090. if (intr_status & IntrPCIErr) {
  2091. printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
  2092. intr_status & IntrPCIErr);
  2093. np->stats.tx_fifo_errors++;
  2094. np->stats.rx_fifo_errors++;
  2095. }
  2096. spin_unlock(&np->lock);
  2097. }
  2098. static void __get_stats(struct net_device *dev)
  2099. {
  2100. void __iomem * ioaddr = ns_ioaddr(dev);
  2101. struct netdev_private *np = netdev_priv(dev);
  2102. /* The chip only need report frame silently dropped. */
  2103. np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
  2104. np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
  2105. }
  2106. static struct net_device_stats *get_stats(struct net_device *dev)
  2107. {
  2108. struct netdev_private *np = netdev_priv(dev);
  2109. /* The chip only need report frame silently dropped. */
  2110. spin_lock_irq(&np->lock);
  2111. if (netif_running(dev) && !np->hands_off)
  2112. __get_stats(dev);
  2113. spin_unlock_irq(&np->lock);
  2114. return &np->stats;
  2115. }
  2116. #ifdef CONFIG_NET_POLL_CONTROLLER
  2117. static void natsemi_poll_controller(struct net_device *dev)
  2118. {
  2119. disable_irq(dev->irq);
  2120. intr_handler(dev->irq, dev);
  2121. enable_irq(dev->irq);
  2122. }
  2123. #endif
  2124. #define HASH_TABLE 0x200
  2125. static void __set_rx_mode(struct net_device *dev)
  2126. {
  2127. void __iomem * ioaddr = ns_ioaddr(dev);
  2128. struct netdev_private *np = netdev_priv(dev);
  2129. u8 mc_filter[64]; /* Multicast hash filter */
  2130. u32 rx_mode;
  2131. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  2132. rx_mode = RxFilterEnable | AcceptBroadcast
  2133. | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
  2134. } else if ((dev->mc_count > multicast_filter_limit)
  2135. || (dev->flags & IFF_ALLMULTI)) {
  2136. rx_mode = RxFilterEnable | AcceptBroadcast
  2137. | AcceptAllMulticast | AcceptMyPhys;
  2138. } else {
  2139. struct dev_mc_list *mclist;
  2140. int i;
  2141. memset(mc_filter, 0, sizeof(mc_filter));
  2142. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  2143. i++, mclist = mclist->next) {
  2144. int i = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
  2145. mc_filter[i/8] |= (1 << (i & 0x07));
  2146. }
  2147. rx_mode = RxFilterEnable | AcceptBroadcast
  2148. | AcceptMulticast | AcceptMyPhys;
  2149. for (i = 0; i < 64; i += 2) {
  2150. writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
  2151. writel((mc_filter[i + 1] << 8) + mc_filter[i],
  2152. ioaddr + RxFilterData);
  2153. }
  2154. }
  2155. writel(rx_mode, ioaddr + RxFilterAddr);
  2156. np->cur_rx_mode = rx_mode;
  2157. }
  2158. static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
  2159. {
  2160. if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
  2161. return -EINVAL;
  2162. dev->mtu = new_mtu;
  2163. /* synchronized against open : rtnl_lock() held by caller */
  2164. if (netif_running(dev)) {
  2165. struct netdev_private *np = netdev_priv(dev);
  2166. void __iomem * ioaddr = ns_ioaddr(dev);
  2167. disable_irq(dev->irq);
  2168. spin_lock(&np->lock);
  2169. /* stop engines */
  2170. natsemi_stop_rxtx(dev);
  2171. /* drain rx queue */
  2172. drain_rx(dev);
  2173. /* change buffers */
  2174. set_bufsize(dev);
  2175. reinit_rx(dev);
  2176. writel(np->ring_dma, ioaddr + RxRingPtr);
  2177. /* restart engines */
  2178. writel(RxOn | TxOn, ioaddr + ChipCmd);
  2179. spin_unlock(&np->lock);
  2180. enable_irq(dev->irq);
  2181. }
  2182. return 0;
  2183. }
  2184. static void set_rx_mode(struct net_device *dev)
  2185. {
  2186. struct netdev_private *np = netdev_priv(dev);
  2187. spin_lock_irq(&np->lock);
  2188. if (!np->hands_off)
  2189. __set_rx_mode(dev);
  2190. spin_unlock_irq(&np->lock);
  2191. }
  2192. static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  2193. {
  2194. struct netdev_private *np = netdev_priv(dev);
  2195. strncpy(info->driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
  2196. strncpy(info->version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
  2197. strncpy(info->bus_info, pci_name(np->pci_dev), ETHTOOL_BUSINFO_LEN);
  2198. }
  2199. static int get_regs_len(struct net_device *dev)
  2200. {
  2201. return NATSEMI_REGS_SIZE;
  2202. }
  2203. static int get_eeprom_len(struct net_device *dev)
  2204. {
  2205. struct netdev_private *np = netdev_priv(dev);
  2206. return np->eeprom_size;
  2207. }
  2208. static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2209. {
  2210. struct netdev_private *np = netdev_priv(dev);
  2211. spin_lock_irq(&np->lock);
  2212. netdev_get_ecmd(dev, ecmd);
  2213. spin_unlock_irq(&np->lock);
  2214. return 0;
  2215. }
  2216. static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2217. {
  2218. struct netdev_private *np = netdev_priv(dev);
  2219. int res;
  2220. spin_lock_irq(&np->lock);
  2221. res = netdev_set_ecmd(dev, ecmd);
  2222. spin_unlock_irq(&np->lock);
  2223. return res;
  2224. }
  2225. static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2226. {
  2227. struct netdev_private *np = netdev_priv(dev);
  2228. spin_lock_irq(&np->lock);
  2229. netdev_get_wol(dev, &wol->supported, &wol->wolopts);
  2230. netdev_get_sopass(dev, wol->sopass);
  2231. spin_unlock_irq(&np->lock);
  2232. }
  2233. static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2234. {
  2235. struct netdev_private *np = netdev_priv(dev);
  2236. int res;
  2237. spin_lock_irq(&np->lock);
  2238. netdev_set_wol(dev, wol->wolopts);
  2239. res = netdev_set_sopass(dev, wol->sopass);
  2240. spin_unlock_irq(&np->lock);
  2241. return res;
  2242. }
  2243. static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
  2244. {
  2245. struct netdev_private *np = netdev_priv(dev);
  2246. regs->version = NATSEMI_REGS_VER;
  2247. spin_lock_irq(&np->lock);
  2248. netdev_get_regs(dev, buf);
  2249. spin_unlock_irq(&np->lock);
  2250. }
  2251. static u32 get_msglevel(struct net_device *dev)
  2252. {
  2253. struct netdev_private *np = netdev_priv(dev);
  2254. return np->msg_enable;
  2255. }
  2256. static void set_msglevel(struct net_device *dev, u32 val)
  2257. {
  2258. struct netdev_private *np = netdev_priv(dev);
  2259. np->msg_enable = val;
  2260. }
  2261. static int nway_reset(struct net_device *dev)
  2262. {
  2263. int tmp;
  2264. int r = -EINVAL;
  2265. /* if autoneg is off, it's an error */
  2266. tmp = mdio_read(dev, MII_BMCR);
  2267. if (tmp & BMCR_ANENABLE) {
  2268. tmp |= (BMCR_ANRESTART);
  2269. mdio_write(dev, MII_BMCR, tmp);
  2270. r = 0;
  2271. }
  2272. return r;
  2273. }
  2274. static u32 get_link(struct net_device *dev)
  2275. {
  2276. /* LSTATUS is latched low until a read - so read twice */
  2277. mdio_read(dev, MII_BMSR);
  2278. return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
  2279. }
  2280. static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  2281. {
  2282. struct netdev_private *np = netdev_priv(dev);
  2283. u8 *eebuf;
  2284. int res;
  2285. eebuf = kmalloc(np->eeprom_size, GFP_KERNEL);
  2286. if (!eebuf)
  2287. return -ENOMEM;
  2288. eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
  2289. spin_lock_irq(&np->lock);
  2290. res = netdev_get_eeprom(dev, eebuf);
  2291. spin_unlock_irq(&np->lock);
  2292. if (!res)
  2293. memcpy(data, eebuf+eeprom->offset, eeprom->len);
  2294. kfree(eebuf);
  2295. return res;
  2296. }
  2297. static const struct ethtool_ops ethtool_ops = {
  2298. .get_drvinfo = get_drvinfo,
  2299. .get_regs_len = get_regs_len,
  2300. .get_eeprom_len = get_eeprom_len,
  2301. .get_settings = get_settings,
  2302. .set_settings = set_settings,
  2303. .get_wol = get_wol,
  2304. .set_wol = set_wol,
  2305. .get_regs = get_regs,
  2306. .get_msglevel = get_msglevel,
  2307. .set_msglevel = set_msglevel,
  2308. .nway_reset = nway_reset,
  2309. .get_link = get_link,
  2310. .get_eeprom = get_eeprom,
  2311. };
  2312. static int netdev_set_wol(struct net_device *dev, u32 newval)
  2313. {
  2314. struct netdev_private *np = netdev_priv(dev);
  2315. void __iomem * ioaddr = ns_ioaddr(dev);
  2316. u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary;
  2317. /* translate to bitmasks this chip understands */
  2318. if (newval & WAKE_PHY)
  2319. data |= WakePhy;
  2320. if (newval & WAKE_UCAST)
  2321. data |= WakeUnicast;
  2322. if (newval & WAKE_MCAST)
  2323. data |= WakeMulticast;
  2324. if (newval & WAKE_BCAST)
  2325. data |= WakeBroadcast;
  2326. if (newval & WAKE_ARP)
  2327. data |= WakeArp;
  2328. if (newval & WAKE_MAGIC)
  2329. data |= WakeMagic;
  2330. if (np->srr >= SRR_DP83815_D) {
  2331. if (newval & WAKE_MAGICSECURE) {
  2332. data |= WakeMagicSecure;
  2333. }
  2334. }
  2335. writel(data, ioaddr + WOLCmd);
  2336. return 0;
  2337. }
  2338. static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
  2339. {
  2340. struct netdev_private *np = netdev_priv(dev);
  2341. void __iomem * ioaddr = ns_ioaddr(dev);
  2342. u32 regval = readl(ioaddr + WOLCmd);
  2343. *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
  2344. | WAKE_ARP | WAKE_MAGIC);
  2345. if (np->srr >= SRR_DP83815_D) {
  2346. /* SOPASS works on revD and higher */
  2347. *supported |= WAKE_MAGICSECURE;
  2348. }
  2349. *cur = 0;
  2350. /* translate from chip bitmasks */
  2351. if (regval & WakePhy)
  2352. *cur |= WAKE_PHY;
  2353. if (regval & WakeUnicast)
  2354. *cur |= WAKE_UCAST;
  2355. if (regval & WakeMulticast)
  2356. *cur |= WAKE_MCAST;
  2357. if (regval & WakeBroadcast)
  2358. *cur |= WAKE_BCAST;
  2359. if (regval & WakeArp)
  2360. *cur |= WAKE_ARP;
  2361. if (regval & WakeMagic)
  2362. *cur |= WAKE_MAGIC;
  2363. if (regval & WakeMagicSecure) {
  2364. /* this can be on in revC, but it's broken */
  2365. *cur |= WAKE_MAGICSECURE;
  2366. }
  2367. return 0;
  2368. }
  2369. static int netdev_set_sopass(struct net_device *dev, u8 *newval)
  2370. {
  2371. struct netdev_private *np = netdev_priv(dev);
  2372. void __iomem * ioaddr = ns_ioaddr(dev);
  2373. u16 *sval = (u16 *)newval;
  2374. u32 addr;
  2375. if (np->srr < SRR_DP83815_D) {
  2376. return 0;
  2377. }
  2378. /* enable writing to these registers by disabling the RX filter */
  2379. addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
  2380. addr &= ~RxFilterEnable;
  2381. writel(addr, ioaddr + RxFilterAddr);
  2382. /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
  2383. writel(addr | 0xa, ioaddr + RxFilterAddr);
  2384. writew(sval[0], ioaddr + RxFilterData);
  2385. writel(addr | 0xc, ioaddr + RxFilterAddr);
  2386. writew(sval[1], ioaddr + RxFilterData);
  2387. writel(addr | 0xe, ioaddr + RxFilterAddr);
  2388. writew(sval[2], ioaddr + RxFilterData);
  2389. /* re-enable the RX filter */
  2390. writel(addr | RxFilterEnable, ioaddr + RxFilterAddr);
  2391. return 0;
  2392. }
  2393. static int netdev_get_sopass(struct net_device *dev, u8 *data)
  2394. {
  2395. struct netdev_private *np = netdev_priv(dev);
  2396. void __iomem * ioaddr = ns_ioaddr(dev);
  2397. u16 *sval = (u16 *)data;
  2398. u32 addr;
  2399. if (np->srr < SRR_DP83815_D) {
  2400. sval[0] = sval[1] = sval[2] = 0;
  2401. return 0;
  2402. }
  2403. /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
  2404. addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask;
  2405. writel(addr | 0xa, ioaddr + RxFilterAddr);
  2406. sval[0] = readw(ioaddr + RxFilterData);
  2407. writel(addr | 0xc, ioaddr + RxFilterAddr);
  2408. sval[1] = readw(ioaddr + RxFilterData);
  2409. writel(addr | 0xe, ioaddr + RxFilterAddr);
  2410. sval[2] = readw(ioaddr + RxFilterData);
  2411. writel(addr, ioaddr + RxFilterAddr);
  2412. return 0;
  2413. }
  2414. static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
  2415. {
  2416. struct netdev_private *np = netdev_priv(dev);
  2417. u32 tmp;
  2418. ecmd->port = dev->if_port;
  2419. ecmd->speed = np->speed;
  2420. ecmd->duplex = np->duplex;
  2421. ecmd->autoneg = np->autoneg;
  2422. ecmd->advertising = 0;
  2423. if (np->advertising & ADVERTISE_10HALF)
  2424. ecmd->advertising |= ADVERTISED_10baseT_Half;
  2425. if (np->advertising & ADVERTISE_10FULL)
  2426. ecmd->advertising |= ADVERTISED_10baseT_Full;
  2427. if (np->advertising & ADVERTISE_100HALF)
  2428. ecmd->advertising |= ADVERTISED_100baseT_Half;
  2429. if (np->advertising & ADVERTISE_100FULL)
  2430. ecmd->advertising |= ADVERTISED_100baseT_Full;
  2431. ecmd->supported = (SUPPORTED_Autoneg |
  2432. SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
  2433. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  2434. SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
  2435. ecmd->phy_address = np->phy_addr_external;
  2436. /*
  2437. * We intentionally report the phy address of the external
  2438. * phy, even if the internal phy is used. This is necessary
  2439. * to work around a deficiency of the ethtool interface:
  2440. * It's only possible to query the settings of the active
  2441. * port. Therefore
  2442. * # ethtool -s ethX port mii
  2443. * actually sends an ioctl to switch to port mii with the
  2444. * settings that are used for the current active port.
  2445. * If we would report a different phy address in this
  2446. * command, then
  2447. * # ethtool -s ethX port tp;ethtool -s ethX port mii
  2448. * would unintentionally change the phy address.
  2449. *
  2450. * Fortunately the phy address doesn't matter with the
  2451. * internal phy...
  2452. */
  2453. /* set information based on active port type */
  2454. switch (ecmd->port) {
  2455. default:
  2456. case PORT_TP:
  2457. ecmd->advertising |= ADVERTISED_TP;
  2458. ecmd->transceiver = XCVR_INTERNAL;
  2459. break;
  2460. case PORT_MII:
  2461. ecmd->advertising |= ADVERTISED_MII;
  2462. ecmd->transceiver = XCVR_EXTERNAL;
  2463. break;
  2464. case PORT_FIBRE:
  2465. ecmd->advertising |= ADVERTISED_FIBRE;
  2466. ecmd->transceiver = XCVR_EXTERNAL;
  2467. break;
  2468. }
  2469. /* if autonegotiation is on, try to return the active speed/duplex */
  2470. if (ecmd->autoneg == AUTONEG_ENABLE) {
  2471. ecmd->advertising |= ADVERTISED_Autoneg;
  2472. tmp = mii_nway_result(
  2473. np->advertising & mdio_read(dev, MII_LPA));
  2474. if (tmp == LPA_100FULL || tmp == LPA_100HALF)
  2475. ecmd->speed = SPEED_100;
  2476. else
  2477. ecmd->speed = SPEED_10;
  2478. if (tmp == LPA_100FULL || tmp == LPA_10FULL)
  2479. ecmd->duplex = DUPLEX_FULL;
  2480. else
  2481. ecmd->duplex = DUPLEX_HALF;
  2482. }
  2483. /* ignore maxtxpkt, maxrxpkt for now */
  2484. return 0;
  2485. }
  2486. static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
  2487. {
  2488. struct netdev_private *np = netdev_priv(dev);
  2489. if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
  2490. return -EINVAL;
  2491. if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
  2492. return -EINVAL;
  2493. if (ecmd->autoneg == AUTONEG_ENABLE) {
  2494. if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
  2495. ADVERTISED_10baseT_Full |
  2496. ADVERTISED_100baseT_Half |
  2497. ADVERTISED_100baseT_Full)) == 0) {
  2498. return -EINVAL;
  2499. }
  2500. } else if (ecmd->autoneg == AUTONEG_DISABLE) {
  2501. if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
  2502. return -EINVAL;
  2503. if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
  2504. return -EINVAL;
  2505. } else {
  2506. return -EINVAL;
  2507. }
  2508. /*
  2509. * If we're ignoring the PHY then autoneg and the internal
  2510. * transciever are really not going to work so don't let the
  2511. * user select them.
  2512. */
  2513. if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE ||
  2514. ecmd->port == PORT_TP))
  2515. return -EINVAL;
  2516. /*
  2517. * maxtxpkt, maxrxpkt: ignored for now.
  2518. *
  2519. * transceiver:
  2520. * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
  2521. * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
  2522. * selects based on ecmd->port.
  2523. *
  2524. * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
  2525. * phys that are connected to the mii bus. It's used to apply fibre
  2526. * specific updates.
  2527. */
  2528. /* WHEW! now lets bang some bits */
  2529. /* save the parms */
  2530. dev->if_port = ecmd->port;
  2531. np->autoneg = ecmd->autoneg;
  2532. np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
  2533. if (np->autoneg == AUTONEG_ENABLE) {
  2534. /* advertise only what has been requested */
  2535. np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  2536. if (ecmd->advertising & ADVERTISED_10baseT_Half)
  2537. np->advertising |= ADVERTISE_10HALF;
  2538. if (ecmd->advertising & ADVERTISED_10baseT_Full)
  2539. np->advertising |= ADVERTISE_10FULL;
  2540. if (ecmd->advertising & ADVERTISED_100baseT_Half)
  2541. np->advertising |= ADVERTISE_100HALF;
  2542. if (ecmd->advertising & ADVERTISED_100baseT_Full)
  2543. np->advertising |= ADVERTISE_100FULL;
  2544. } else {
  2545. np->speed = ecmd->speed;
  2546. np->duplex = ecmd->duplex;
  2547. /* user overriding the initial full duplex parm? */
  2548. if (np->duplex == DUPLEX_HALF)
  2549. np->full_duplex = 0;
  2550. }
  2551. /* get the right phy enabled */
  2552. if (ecmd->port == PORT_TP)
  2553. switch_port_internal(dev);
  2554. else
  2555. switch_port_external(dev);
  2556. /* set parms and see how this affected our link status */
  2557. init_phy_fixup(dev);
  2558. check_link(dev);
  2559. return 0;
  2560. }
  2561. static int netdev_get_regs(struct net_device *dev, u8 *buf)
  2562. {
  2563. int i;
  2564. int j;
  2565. u32 rfcr;
  2566. u32 *rbuf = (u32 *)buf;
  2567. void __iomem * ioaddr = ns_ioaddr(dev);
  2568. /* read non-mii page 0 of registers */
  2569. for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
  2570. rbuf[i] = readl(ioaddr + i*4);
  2571. }
  2572. /* read current mii registers */
  2573. for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
  2574. rbuf[i] = mdio_read(dev, i & 0x1f);
  2575. /* read only the 'magic' registers from page 1 */
  2576. writew(1, ioaddr + PGSEL);
  2577. rbuf[i++] = readw(ioaddr + PMDCSR);
  2578. rbuf[i++] = readw(ioaddr + TSTDAT);
  2579. rbuf[i++] = readw(ioaddr + DSPCFG);
  2580. rbuf[i++] = readw(ioaddr + SDCFG);
  2581. writew(0, ioaddr + PGSEL);
  2582. /* read RFCR indexed registers */
  2583. rfcr = readl(ioaddr + RxFilterAddr);
  2584. for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
  2585. writel(j*2, ioaddr + RxFilterAddr);
  2586. rbuf[i++] = readw(ioaddr + RxFilterData);
  2587. }
  2588. writel(rfcr, ioaddr + RxFilterAddr);
  2589. /* the interrupt status is clear-on-read - see if we missed any */
  2590. if (rbuf[4] & rbuf[5]) {
  2591. printk(KERN_WARNING
  2592. "%s: shoot, we dropped an interrupt (%#08x)\n",
  2593. dev->name, rbuf[4] & rbuf[5]);
  2594. }
  2595. return 0;
  2596. }
  2597. #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
  2598. | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
  2599. | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
  2600. | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
  2601. | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
  2602. | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
  2603. | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
  2604. | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
  2605. static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
  2606. {
  2607. int i;
  2608. u16 *ebuf = (u16 *)buf;
  2609. void __iomem * ioaddr = ns_ioaddr(dev);
  2610. struct netdev_private *np = netdev_priv(dev);
  2611. /* eeprom_read reads 16 bits, and indexes by 16 bits */
  2612. for (i = 0; i < np->eeprom_size/2; i++) {
  2613. ebuf[i] = eeprom_read(ioaddr, i);
  2614. /* The EEPROM itself stores data bit-swapped, but eeprom_read
  2615. * reads it back "sanely". So we swap it back here in order to
  2616. * present it to userland as it is stored. */
  2617. ebuf[i] = SWAP_BITS(ebuf[i]);
  2618. }
  2619. return 0;
  2620. }
  2621. static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  2622. {
  2623. struct mii_ioctl_data *data = if_mii(rq);
  2624. struct netdev_private *np = netdev_priv(dev);
  2625. switch(cmd) {
  2626. case SIOCGMIIPHY: /* Get address of MII PHY in use. */
  2627. case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
  2628. data->phy_id = np->phy_addr_external;
  2629. /* Fall Through */
  2630. case SIOCGMIIREG: /* Read MII PHY register. */
  2631. case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
  2632. /* The phy_id is not enough to uniquely identify
  2633. * the intended target. Therefore the command is sent to
  2634. * the given mii on the current port.
  2635. */
  2636. if (dev->if_port == PORT_TP) {
  2637. if ((data->phy_id & 0x1f) == np->phy_addr_external)
  2638. data->val_out = mdio_read(dev,
  2639. data->reg_num & 0x1f);
  2640. else
  2641. data->val_out = 0;
  2642. } else {
  2643. move_int_phy(dev, data->phy_id & 0x1f);
  2644. data->val_out = miiport_read(dev, data->phy_id & 0x1f,
  2645. data->reg_num & 0x1f);
  2646. }
  2647. return 0;
  2648. case SIOCSMIIREG: /* Write MII PHY register. */
  2649. case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
  2650. if (!capable(CAP_NET_ADMIN))
  2651. return -EPERM;
  2652. if (dev->if_port == PORT_TP) {
  2653. if ((data->phy_id & 0x1f) == np->phy_addr_external) {
  2654. if ((data->reg_num & 0x1f) == MII_ADVERTISE)
  2655. np->advertising = data->val_in;
  2656. mdio_write(dev, data->reg_num & 0x1f,
  2657. data->val_in);
  2658. }
  2659. } else {
  2660. if ((data->phy_id & 0x1f) == np->phy_addr_external) {
  2661. if ((data->reg_num & 0x1f) == MII_ADVERTISE)
  2662. np->advertising = data->val_in;
  2663. }
  2664. move_int_phy(dev, data->phy_id & 0x1f);
  2665. miiport_write(dev, data->phy_id & 0x1f,
  2666. data->reg_num & 0x1f,
  2667. data->val_in);
  2668. }
  2669. return 0;
  2670. default:
  2671. return -EOPNOTSUPP;
  2672. }
  2673. }
  2674. static void enable_wol_mode(struct net_device *dev, int enable_intr)
  2675. {
  2676. void __iomem * ioaddr = ns_ioaddr(dev);
  2677. struct netdev_private *np = netdev_priv(dev);
  2678. if (netif_msg_wol(np))
  2679. printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
  2680. dev->name);
  2681. /* For WOL we must restart the rx process in silent mode.
  2682. * Write NULL to the RxRingPtr. Only possible if
  2683. * rx process is stopped
  2684. */
  2685. writel(0, ioaddr + RxRingPtr);
  2686. /* read WoL status to clear */
  2687. readl(ioaddr + WOLCmd);
  2688. /* PME on, clear status */
  2689. writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
  2690. /* and restart the rx process */
  2691. writel(RxOn, ioaddr + ChipCmd);
  2692. if (enable_intr) {
  2693. /* enable the WOL interrupt.
  2694. * Could be used to send a netlink message.
  2695. */
  2696. writel(WOLPkt | LinkChange, ioaddr + IntrMask);
  2697. natsemi_irq_enable(dev);
  2698. }
  2699. }
  2700. static int netdev_close(struct net_device *dev)
  2701. {
  2702. void __iomem * ioaddr = ns_ioaddr(dev);
  2703. struct netdev_private *np = netdev_priv(dev);
  2704. if (netif_msg_ifdown(np))
  2705. printk(KERN_DEBUG
  2706. "%s: Shutting down ethercard, status was %#04x.\n",
  2707. dev->name, (int)readl(ioaddr + ChipCmd));
  2708. if (netif_msg_pktdata(np))
  2709. printk(KERN_DEBUG
  2710. "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
  2711. dev->name, np->cur_tx, np->dirty_tx,
  2712. np->cur_rx, np->dirty_rx);
  2713. /*
  2714. * FIXME: what if someone tries to close a device
  2715. * that is suspended?
  2716. * Should we reenable the nic to switch to
  2717. * the final WOL settings?
  2718. */
  2719. del_timer_sync(&np->timer);
  2720. disable_irq(dev->irq);
  2721. spin_lock_irq(&np->lock);
  2722. natsemi_irq_disable(dev);
  2723. np->hands_off = 1;
  2724. spin_unlock_irq(&np->lock);
  2725. enable_irq(dev->irq);
  2726. free_irq(dev->irq, dev);
  2727. /* Interrupt disabled, interrupt handler released,
  2728. * queue stopped, timer deleted, rtnl_lock held
  2729. * All async codepaths that access the driver are disabled.
  2730. */
  2731. spin_lock_irq(&np->lock);
  2732. np->hands_off = 0;
  2733. readl(ioaddr + IntrMask);
  2734. readw(ioaddr + MIntrStatus);
  2735. /* Freeze Stats */
  2736. writel(StatsFreeze, ioaddr + StatsCtrl);
  2737. /* Stop the chip's Tx and Rx processes. */
  2738. natsemi_stop_rxtx(dev);
  2739. __get_stats(dev);
  2740. spin_unlock_irq(&np->lock);
  2741. /* clear the carrier last - an interrupt could reenable it otherwise */
  2742. netif_carrier_off(dev);
  2743. netif_stop_queue(dev);
  2744. dump_ring(dev);
  2745. drain_ring(dev);
  2746. free_ring(dev);
  2747. {
  2748. u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
  2749. if (wol) {
  2750. /* restart the NIC in WOL mode.
  2751. * The nic must be stopped for this.
  2752. */
  2753. enable_wol_mode(dev, 0);
  2754. } else {
  2755. /* Restore PME enable bit unmolested */
  2756. writel(np->SavedClkRun, ioaddr + ClkRun);
  2757. }
  2758. }
  2759. return 0;
  2760. }
  2761. static void __devexit natsemi_remove1 (struct pci_dev *pdev)
  2762. {
  2763. struct net_device *dev = pci_get_drvdata(pdev);
  2764. void __iomem * ioaddr = ns_ioaddr(dev);
  2765. unregister_netdev (dev);
  2766. pci_release_regions (pdev);
  2767. iounmap(ioaddr);
  2768. free_netdev (dev);
  2769. pci_set_drvdata(pdev, NULL);
  2770. }
  2771. #ifdef CONFIG_PM
  2772. /*
  2773. * The ns83815 chip doesn't have explicit RxStop bits.
  2774. * Kicking the Rx or Tx process for a new packet reenables the Rx process
  2775. * of the nic, thus this function must be very careful:
  2776. *
  2777. * suspend/resume synchronization:
  2778. * entry points:
  2779. * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
  2780. * start_tx, tx_timeout
  2781. *
  2782. * No function accesses the hardware without checking np->hands_off.
  2783. * the check occurs under spin_lock_irq(&np->lock);
  2784. * exceptions:
  2785. * * netdev_ioctl: noncritical access.
  2786. * * netdev_open: cannot happen due to the device_detach
  2787. * * netdev_close: doesn't hurt.
  2788. * * netdev_timer: timer stopped by natsemi_suspend.
  2789. * * intr_handler: doesn't acquire the spinlock. suspend calls
  2790. * disable_irq() to enforce synchronization.
  2791. * * natsemi_poll: checks before reenabling interrupts. suspend
  2792. * sets hands_off, disables interrupts and then waits with
  2793. * netif_poll_disable().
  2794. *
  2795. * Interrupts must be disabled, otherwise hands_off can cause irq storms.
  2796. */
  2797. static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state)
  2798. {
  2799. struct net_device *dev = pci_get_drvdata (pdev);
  2800. struct netdev_private *np = netdev_priv(dev);
  2801. void __iomem * ioaddr = ns_ioaddr(dev);
  2802. rtnl_lock();
  2803. if (netif_running (dev)) {
  2804. del_timer_sync(&np->timer);
  2805. disable_irq(dev->irq);
  2806. spin_lock_irq(&np->lock);
  2807. natsemi_irq_disable(dev);
  2808. np->hands_off = 1;
  2809. natsemi_stop_rxtx(dev);
  2810. netif_stop_queue(dev);
  2811. spin_unlock_irq(&np->lock);
  2812. enable_irq(dev->irq);
  2813. netif_poll_disable(dev);
  2814. /* Update the error counts. */
  2815. __get_stats(dev);
  2816. /* pci_power_off(pdev, -1); */
  2817. drain_ring(dev);
  2818. {
  2819. u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
  2820. /* Restore PME enable bit */
  2821. if (wol) {
  2822. /* restart the NIC in WOL mode.
  2823. * The nic must be stopped for this.
  2824. * FIXME: use the WOL interrupt
  2825. */
  2826. enable_wol_mode(dev, 0);
  2827. } else {
  2828. /* Restore PME enable bit unmolested */
  2829. writel(np->SavedClkRun, ioaddr + ClkRun);
  2830. }
  2831. }
  2832. }
  2833. netif_device_detach(dev);
  2834. rtnl_unlock();
  2835. return 0;
  2836. }
  2837. static int natsemi_resume (struct pci_dev *pdev)
  2838. {
  2839. struct net_device *dev = pci_get_drvdata (pdev);
  2840. struct netdev_private *np = netdev_priv(dev);
  2841. rtnl_lock();
  2842. if (netif_device_present(dev))
  2843. goto out;
  2844. if (netif_running(dev)) {
  2845. BUG_ON(!np->hands_off);
  2846. pci_enable_device(pdev);
  2847. /* pci_power_on(pdev); */
  2848. natsemi_reset(dev);
  2849. init_ring(dev);
  2850. disable_irq(dev->irq);
  2851. spin_lock_irq(&np->lock);
  2852. np->hands_off = 0;
  2853. init_registers(dev);
  2854. netif_device_attach(dev);
  2855. spin_unlock_irq(&np->lock);
  2856. enable_irq(dev->irq);
  2857. mod_timer(&np->timer, jiffies + 1*HZ);
  2858. }
  2859. netif_device_attach(dev);
  2860. netif_poll_enable(dev);
  2861. out:
  2862. rtnl_unlock();
  2863. return 0;
  2864. }
  2865. #endif /* CONFIG_PM */
  2866. static struct pci_driver natsemi_driver = {
  2867. .name = DRV_NAME,
  2868. .id_table = natsemi_pci_tbl,
  2869. .probe = natsemi_probe1,
  2870. .remove = __devexit_p(natsemi_remove1),
  2871. #ifdef CONFIG_PM
  2872. .suspend = natsemi_suspend,
  2873. .resume = natsemi_resume,
  2874. #endif
  2875. };
  2876. static int __init natsemi_init_mod (void)
  2877. {
  2878. /* when a module, this is printed whether or not devices are found in probe */
  2879. #ifdef MODULE
  2880. printk(version);
  2881. #endif
  2882. return pci_register_driver(&natsemi_driver);
  2883. }
  2884. static void __exit natsemi_exit_mod (void)
  2885. {
  2886. pci_unregister_driver (&natsemi_driver);
  2887. }
  2888. module_init(natsemi_init_mod);
  2889. module_exit(natsemi_exit_mod);