myri_sbus.h 9.3 KB

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  1. /* myri_sbus.h: Defines for MyriCOM MyriNET SBUS card driver.
  2. *
  3. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  4. */
  5. #ifndef _MYRI_SBUS_H
  6. #define _MYRI_SBUS_H
  7. /* LANAI Registers */
  8. #define LANAI_IPF0 0x00UL /* Context zero state registers.*/
  9. #define LANAI_CUR0 0x04UL
  10. #define LANAI_PREV0 0x08UL
  11. #define LANAI_DATA0 0x0cUL
  12. #define LANAI_DPF0 0x10UL
  13. #define LANAI_IPF1 0x14UL /* Context one state registers. */
  14. #define LANAI_CUR1 0x18UL
  15. #define LANAI_PREV1 0x1cUL
  16. #define LANAI_DATA1 0x20UL
  17. #define LANAI_DPF1 0x24UL
  18. #define LANAI_ISTAT 0x28UL /* Interrupt status. */
  19. #define LANAI_EIMASK 0x2cUL /* External IRQ mask. */
  20. #define LANAI_ITIMER 0x30UL /* IRQ timer. */
  21. #define LANAI_RTC 0x34UL /* Real Time Clock */
  22. #define LANAI_CSUM 0x38UL /* Checksum. */
  23. #define LANAI_DMAXADDR 0x3cUL /* SBUS DMA external address. */
  24. #define LANAI_DMALADDR 0x40UL /* SBUS DMA local address. */
  25. #define LANAI_DMACTR 0x44UL /* SBUS DMA counter. */
  26. #define LANAI_RXDMAPTR 0x48UL /* Receive DMA pointer. */
  27. #define LANAI_RXDMALIM 0x4cUL /* Receive DMA limit. */
  28. #define LANAI_TXDMAPTR 0x50UL /* Transmit DMA pointer. */
  29. #define LANAI_TXDMALIM 0x54UL /* Transmit DMA limit. */
  30. #define LANAI_TXDMALIMT 0x58UL /* Transmit DMA limit w/tail. */
  31. /* 0x5cUL, reserved */
  32. #define LANAI_RBYTE 0x60UL /* Receive byte. */
  33. /* 0x64-->0x6c, reserved */
  34. #define LANAI_RHALF 0x70UL /* Receive half-word. */
  35. /* 0x72UL, reserved */
  36. #define LANAI_RWORD 0x74UL /* Receive word. */
  37. #define LANAI_SALIGN 0x78UL /* Send align. */
  38. #define LANAI_SBYTE 0x7cUL /* SingleSend send-byte. */
  39. #define LANAI_SHALF 0x80UL /* SingleSend send-halfword. */
  40. #define LANAI_SWORD 0x84UL /* SingleSend send-word. */
  41. #define LANAI_SSENDT 0x88UL /* SingleSend special. */
  42. #define LANAI_DMADIR 0x8cUL /* DMA direction. */
  43. #define LANAI_DMASTAT 0x90UL /* DMA status. */
  44. #define LANAI_TIMEO 0x94UL /* Timeout register. */
  45. #define LANAI_MYRINET 0x98UL /* XXX MAGIC myricom thing */
  46. #define LANAI_HWDEBUG 0x9cUL /* Hardware debugging reg. */
  47. #define LANAI_LEDS 0xa0UL /* LED control. */
  48. #define LANAI_VERS 0xa4UL /* Version register. */
  49. #define LANAI_LINKON 0xa8UL /* Link activation reg. */
  50. /* 0xac-->0x104, reserved */
  51. #define LANAI_CVAL 0x108UL /* Clock value register. */
  52. #define LANAI_REG_SIZE 0x10cUL
  53. /* Interrupt status bits. */
  54. #define ISTAT_DEBUG 0x80000000
  55. #define ISTAT_HOST 0x40000000
  56. #define ISTAT_LAN7 0x00800000
  57. #define ISTAT_LAN6 0x00400000
  58. #define ISTAT_LAN5 0x00200000
  59. #define ISTAT_LAN4 0x00100000
  60. #define ISTAT_LAN3 0x00080000
  61. #define ISTAT_LAN2 0x00040000
  62. #define ISTAT_LAN1 0x00020000
  63. #define ISTAT_LAN0 0x00010000
  64. #define ISTAT_WRDY 0x00008000
  65. #define ISTAT_HRDY 0x00004000
  66. #define ISTAT_SRDY 0x00002000
  67. #define ISTAT_LINK 0x00001000
  68. #define ISTAT_FRES 0x00000800
  69. #define ISTAT_NRES 0x00000800
  70. #define ISTAT_WAKE 0x00000400
  71. #define ISTAT_OB2 0x00000200
  72. #define ISTAT_OB1 0x00000100
  73. #define ISTAT_TAIL 0x00000080
  74. #define ISTAT_WDOG 0x00000040
  75. #define ISTAT_TIME 0x00000020
  76. #define ISTAT_DMA 0x00000010
  77. #define ISTAT_SEND 0x00000008
  78. #define ISTAT_BUF 0x00000004
  79. #define ISTAT_RECV 0x00000002
  80. #define ISTAT_BRDY 0x00000001
  81. /* MYRI Registers */
  82. #define MYRI_RESETOFF 0x00UL
  83. #define MYRI_RESETON 0x04UL
  84. #define MYRI_IRQOFF 0x08UL
  85. #define MYRI_IRQON 0x0cUL
  86. #define MYRI_WAKEUPOFF 0x10UL
  87. #define MYRI_WAKEUPON 0x14UL
  88. #define MYRI_IRQREAD 0x18UL
  89. /* 0x1c-->0x3ffc, reserved */
  90. #define MYRI_LOCALMEM 0x4000UL
  91. #define MYRI_REG_SIZE 0x25000UL
  92. /* Shared memory interrupt mask. */
  93. #define SHMEM_IMASK_RX 0x00000002
  94. #define SHMEM_IMASK_TX 0x00000001
  95. /* Just to make things readable. */
  96. #define KERNEL_CHANNEL 0
  97. /* The size of this must be >= 129 bytes. */
  98. struct myri_eeprom {
  99. unsigned int cval;
  100. unsigned short cpuvers;
  101. unsigned char id[6];
  102. unsigned int ramsz;
  103. unsigned char fvers[32];
  104. unsigned char mvers[16];
  105. unsigned short dlval;
  106. unsigned short brd_type;
  107. unsigned short bus_type;
  108. unsigned short prod_code;
  109. unsigned int serial_num;
  110. unsigned short _reserved[24];
  111. unsigned int _unused[2];
  112. };
  113. /* EEPROM bus types, only SBUS is valid in this driver. */
  114. #define BUS_TYPE_SBUS 1
  115. /* EEPROM CPU revisions. */
  116. #define CPUVERS_2_3 0x0203
  117. #define CPUVERS_3_0 0x0300
  118. #define CPUVERS_3_1 0x0301
  119. #define CPUVERS_3_2 0x0302
  120. #define CPUVERS_4_0 0x0400
  121. #define CPUVERS_4_1 0x0401
  122. #define CPUVERS_4_2 0x0402
  123. #define CPUVERS_5_0 0x0500
  124. /* MYRI Control Registers */
  125. #define MYRICTRL_CTRL 0x00UL
  126. #define MYRICTRL_IRQLVL 0x02UL
  127. #define MYRICTRL_REG_SIZE 0x04UL
  128. /* Global control register defines. */
  129. #define CONTROL_ROFF 0x8000 /* Reset OFF. */
  130. #define CONTROL_RON 0x4000 /* Reset ON. */
  131. #define CONTROL_EIRQ 0x2000 /* Enable IRQ's. */
  132. #define CONTROL_DIRQ 0x1000 /* Disable IRQ's. */
  133. #define CONTROL_WON 0x0800 /* Wake-up ON. */
  134. #define MYRI_SCATTER_ENTRIES 8
  135. #define MYRI_GATHER_ENTRIES 16
  136. struct myri_sglist {
  137. u32 addr;
  138. u32 len;
  139. };
  140. struct myri_rxd {
  141. struct myri_sglist myri_scatters[MYRI_SCATTER_ENTRIES]; /* DMA scatter list.*/
  142. u32 csum; /* HW computed checksum. */
  143. u32 ctx;
  144. u32 num_sg; /* Total scatter entries. */
  145. };
  146. struct myri_txd {
  147. struct myri_sglist myri_gathers[MYRI_GATHER_ENTRIES]; /* DMA scatter list. */
  148. u32 num_sg; /* Total scatter entries. */
  149. u16 addr[4]; /* XXX address */
  150. u32 chan;
  151. u32 len; /* Total length of packet. */
  152. u32 csum_off; /* Where data to csum is. */
  153. u32 csum_field; /* Where csum goes in pkt. */
  154. };
  155. #define MYRINET_MTU 8432
  156. #define RX_ALLOC_SIZE 8448
  157. #define MYRI_PAD_LEN 2
  158. #define RX_COPY_THRESHOLD 256
  159. /* These numbers are cast in stone, new firmware is needed if
  160. * you want to change them.
  161. */
  162. #define TX_RING_MAXSIZE 16
  163. #define RX_RING_MAXSIZE 16
  164. #define TX_RING_SIZE 16
  165. #define RX_RING_SIZE 16
  166. /* GRRR... */
  167. static __inline__ int NEXT_RX(int num)
  168. {
  169. /* XXX >=??? */
  170. if(++num > RX_RING_SIZE)
  171. num = 0;
  172. return num;
  173. }
  174. static __inline__ int PREV_RX(int num)
  175. {
  176. if(--num < 0)
  177. num = RX_RING_SIZE;
  178. return num;
  179. }
  180. #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
  181. #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
  182. #define TX_BUFFS_AVAIL(head, tail) \
  183. ((head) <= (tail) ? \
  184. (head) + (TX_RING_SIZE - 1) - (tail) : \
  185. (head) - (tail) - 1)
  186. struct sendq {
  187. u32 tail;
  188. u32 head;
  189. u32 hdebug;
  190. u32 mdebug;
  191. struct myri_txd myri_txd[TX_RING_MAXSIZE];
  192. };
  193. struct recvq {
  194. u32 head;
  195. u32 tail;
  196. u32 hdebug;
  197. u32 mdebug;
  198. struct myri_rxd myri_rxd[RX_RING_MAXSIZE + 1];
  199. };
  200. #define MYRI_MLIST_SIZE 8
  201. struct mclist {
  202. u32 maxlen;
  203. u32 len;
  204. u32 cache;
  205. struct pair {
  206. u8 addr[8];
  207. u32 val;
  208. } mc_pairs[MYRI_MLIST_SIZE];
  209. u8 bcast_addr[8];
  210. };
  211. struct myri_channel {
  212. u32 state; /* State of the channel. */
  213. u32 busy; /* Channel is busy. */
  214. struct sendq sendq; /* Device tx queue. */
  215. struct recvq recvq; /* Device rx queue. */
  216. struct recvq recvqa; /* Device rx queue acked. */
  217. u32 rbytes; /* Receive bytes. */
  218. u32 sbytes; /* Send bytes. */
  219. u32 rmsgs; /* Receive messages. */
  220. u32 smsgs; /* Send messages. */
  221. struct mclist mclist; /* Device multicast list. */
  222. };
  223. /* Values for per-channel state. */
  224. #define STATE_WFH 0 /* Waiting for HOST. */
  225. #define STATE_WFN 1 /* Waiting for NET. */
  226. #define STATE_READY 2 /* Ready. */
  227. struct myri_shmem {
  228. u8 addr[8]; /* Board's address. */
  229. u32 nchan; /* Number of channels. */
  230. u32 burst; /* SBUS dma burst enable. */
  231. u32 shakedown; /* DarkkkkStarrr Crashesss... */
  232. u32 send; /* Send wanted. */
  233. u32 imask; /* Interrupt enable mask. */
  234. u32 mlevel; /* Map level. */
  235. u32 debug[4]; /* Misc. debug areas. */
  236. struct myri_channel channel; /* Only one channel on a host. */
  237. };
  238. struct myri_eth {
  239. /* These are frequently accessed, keep together
  240. * to obtain good cache hit rates.
  241. */
  242. spinlock_t irq_lock;
  243. struct myri_shmem __iomem *shmem; /* Shared data structures. */
  244. void __iomem *cregs; /* Control register space. */
  245. struct recvq __iomem *rqack; /* Where we ack rx's. */
  246. struct recvq __iomem *rq; /* Where we put buffers. */
  247. struct sendq __iomem *sq; /* Where we stuff tx's. */
  248. struct net_device *dev; /* Linux/NET dev struct. */
  249. int tx_old; /* To speed up tx cleaning. */
  250. void __iomem *lregs; /* Quick ptr to LANAI regs. */
  251. struct sk_buff *rx_skbs[RX_RING_SIZE+1];/* RX skb's */
  252. struct sk_buff *tx_skbs[TX_RING_SIZE]; /* TX skb's */
  253. struct net_device_stats enet_stats; /* Interface stats. */
  254. /* These are less frequently accessed. */
  255. void __iomem *regs; /* MyriCOM register space. */
  256. void __iomem *lanai; /* View 2 of register space. */
  257. unsigned int myri_bursts; /* SBUS bursts. */
  258. struct myri_eeprom eeprom; /* Local copy of EEPROM. */
  259. unsigned int reg_size; /* Size of register space. */
  260. unsigned int shmem_base; /* Offset to shared ram. */
  261. struct sbus_dev *myri_sdev; /* Our SBUS device struct. */
  262. };
  263. /* We use this to acquire receive skb's that we can DMA directly into. */
  264. #define ALIGNED_RX_SKB_ADDR(addr) \
  265. ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
  266. static inline struct sk_buff *myri_alloc_skb(unsigned int length, gfp_t gfp_flags)
  267. {
  268. struct sk_buff *skb;
  269. skb = alloc_skb(length + 64, gfp_flags);
  270. if(skb) {
  271. int offset = ALIGNED_RX_SKB_ADDR(skb->data);
  272. if(offset)
  273. skb_reserve(skb, offset);
  274. }
  275. return skb;
  276. }
  277. #endif /* !(_MYRI_SBUS_H) */