myri_sbus.c 32 KB

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  1. /* myri_sbus.c: MyriCOM MyriNET SBUS card driver.
  2. *
  3. * Copyright (C) 1996, 1999, 2006 David S. Miller (davem@davemloft.net)
  4. */
  5. static char version[] =
  6. "myri_sbus.c:v2.0 June 23, 2006 David S. Miller (davem@davemloft.net)\n";
  7. #include <linux/module.h>
  8. #include <linux/errno.h>
  9. #include <linux/kernel.h>
  10. #include <linux/types.h>
  11. #include <linux/fcntl.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/ioport.h>
  14. #include <linux/in.h>
  15. #include <linux/slab.h>
  16. #include <linux/string.h>
  17. #include <linux/delay.h>
  18. #include <linux/init.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/skbuff.h>
  22. #include <linux/bitops.h>
  23. #include <net/dst.h>
  24. #include <net/arp.h>
  25. #include <net/sock.h>
  26. #include <net/ipv6.h>
  27. #include <asm/system.h>
  28. #include <asm/io.h>
  29. #include <asm/dma.h>
  30. #include <asm/byteorder.h>
  31. #include <asm/idprom.h>
  32. #include <asm/sbus.h>
  33. #include <asm/openprom.h>
  34. #include <asm/oplib.h>
  35. #include <asm/auxio.h>
  36. #include <asm/pgtable.h>
  37. #include <asm/irq.h>
  38. #include "myri_sbus.h"
  39. #include "myri_code.h"
  40. /* #define DEBUG_DETECT */
  41. /* #define DEBUG_IRQ */
  42. /* #define DEBUG_TRANSMIT */
  43. /* #define DEBUG_RECEIVE */
  44. /* #define DEBUG_HEADER */
  45. #ifdef DEBUG_DETECT
  46. #define DET(x) printk x
  47. #else
  48. #define DET(x)
  49. #endif
  50. #ifdef DEBUG_IRQ
  51. #define DIRQ(x) printk x
  52. #else
  53. #define DIRQ(x)
  54. #endif
  55. #ifdef DEBUG_TRANSMIT
  56. #define DTX(x) printk x
  57. #else
  58. #define DTX(x)
  59. #endif
  60. #ifdef DEBUG_RECEIVE
  61. #define DRX(x) printk x
  62. #else
  63. #define DRX(x)
  64. #endif
  65. #ifdef DEBUG_HEADER
  66. #define DHDR(x) printk x
  67. #else
  68. #define DHDR(x)
  69. #endif
  70. static void myri_reset_off(void __iomem *lp, void __iomem *cregs)
  71. {
  72. /* Clear IRQ mask. */
  73. sbus_writel(0, lp + LANAI_EIMASK);
  74. /* Turn RESET function off. */
  75. sbus_writel(CONTROL_ROFF, cregs + MYRICTRL_CTRL);
  76. }
  77. static void myri_reset_on(void __iomem *cregs)
  78. {
  79. /* Enable RESET function. */
  80. sbus_writel(CONTROL_RON, cregs + MYRICTRL_CTRL);
  81. /* Disable IRQ's. */
  82. sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL);
  83. }
  84. static void myri_disable_irq(void __iomem *lp, void __iomem *cregs)
  85. {
  86. sbus_writel(CONTROL_DIRQ, cregs + MYRICTRL_CTRL);
  87. sbus_writel(0, lp + LANAI_EIMASK);
  88. sbus_writel(ISTAT_HOST, lp + LANAI_ISTAT);
  89. }
  90. static void myri_enable_irq(void __iomem *lp, void __iomem *cregs)
  91. {
  92. sbus_writel(CONTROL_EIRQ, cregs + MYRICTRL_CTRL);
  93. sbus_writel(ISTAT_HOST, lp + LANAI_EIMASK);
  94. }
  95. static inline void bang_the_chip(struct myri_eth *mp)
  96. {
  97. struct myri_shmem __iomem *shmem = mp->shmem;
  98. void __iomem *cregs = mp->cregs;
  99. sbus_writel(1, &shmem->send);
  100. sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL);
  101. }
  102. static int myri_do_handshake(struct myri_eth *mp)
  103. {
  104. struct myri_shmem __iomem *shmem = mp->shmem;
  105. void __iomem *cregs = mp->cregs;
  106. struct myri_channel __iomem *chan = &shmem->channel;
  107. int tick = 0;
  108. DET(("myri_do_handshake: "));
  109. if (sbus_readl(&chan->state) == STATE_READY) {
  110. DET(("Already STATE_READY, failed.\n"));
  111. return -1; /* We're hosed... */
  112. }
  113. myri_disable_irq(mp->lregs, cregs);
  114. while (tick++ <= 25) {
  115. u32 softstate;
  116. /* Wake it up. */
  117. DET(("shakedown, CONTROL_WON, "));
  118. sbus_writel(1, &shmem->shakedown);
  119. sbus_writel(CONTROL_WON, cregs + MYRICTRL_CTRL);
  120. softstate = sbus_readl(&chan->state);
  121. DET(("chanstate[%08x] ", softstate));
  122. if (softstate == STATE_READY) {
  123. DET(("wakeup successful, "));
  124. break;
  125. }
  126. if (softstate != STATE_WFN) {
  127. DET(("not WFN setting that, "));
  128. sbus_writel(STATE_WFN, &chan->state);
  129. }
  130. udelay(20);
  131. }
  132. myri_enable_irq(mp->lregs, cregs);
  133. if (tick > 25) {
  134. DET(("25 ticks we lose, failure.\n"));
  135. return -1;
  136. }
  137. DET(("success\n"));
  138. return 0;
  139. }
  140. static int __devinit myri_load_lanai(struct myri_eth *mp)
  141. {
  142. struct net_device *dev = mp->dev;
  143. struct myri_shmem __iomem *shmem = mp->shmem;
  144. void __iomem *rptr;
  145. int i;
  146. myri_disable_irq(mp->lregs, mp->cregs);
  147. myri_reset_on(mp->cregs);
  148. rptr = mp->lanai;
  149. for (i = 0; i < mp->eeprom.ramsz; i++)
  150. sbus_writeb(0, rptr + i);
  151. if (mp->eeprom.cpuvers >= CPUVERS_3_0)
  152. sbus_writel(mp->eeprom.cval, mp->lregs + LANAI_CVAL);
  153. /* Load executable code. */
  154. for (i = 0; i < sizeof(lanai4_code); i++)
  155. sbus_writeb(lanai4_code[i], rptr + (lanai4_code_off * 2) + i);
  156. /* Load data segment. */
  157. for (i = 0; i < sizeof(lanai4_data); i++)
  158. sbus_writeb(lanai4_data[i], rptr + (lanai4_data_off * 2) + i);
  159. /* Set device address. */
  160. sbus_writeb(0, &shmem->addr[0]);
  161. sbus_writeb(0, &shmem->addr[1]);
  162. for (i = 0; i < 6; i++)
  163. sbus_writeb(dev->dev_addr[i],
  164. &shmem->addr[i + 2]);
  165. /* Set SBUS bursts and interrupt mask. */
  166. sbus_writel(((mp->myri_bursts & 0xf8) >> 3), &shmem->burst);
  167. sbus_writel(SHMEM_IMASK_RX, &shmem->imask);
  168. /* Release the LANAI. */
  169. myri_disable_irq(mp->lregs, mp->cregs);
  170. myri_reset_off(mp->lregs, mp->cregs);
  171. myri_disable_irq(mp->lregs, mp->cregs);
  172. /* Wait for the reset to complete. */
  173. for (i = 0; i < 5000; i++) {
  174. if (sbus_readl(&shmem->channel.state) != STATE_READY)
  175. break;
  176. else
  177. udelay(10);
  178. }
  179. if (i == 5000)
  180. printk(KERN_ERR "myricom: Chip would not reset after firmware load.\n");
  181. i = myri_do_handshake(mp);
  182. if (i)
  183. printk(KERN_ERR "myricom: Handshake with LANAI failed.\n");
  184. if (mp->eeprom.cpuvers == CPUVERS_4_0)
  185. sbus_writel(0, mp->lregs + LANAI_VERS);
  186. return i;
  187. }
  188. static void myri_clean_rings(struct myri_eth *mp)
  189. {
  190. struct sendq __iomem *sq = mp->sq;
  191. struct recvq __iomem *rq = mp->rq;
  192. int i;
  193. sbus_writel(0, &rq->tail);
  194. sbus_writel(0, &rq->head);
  195. for (i = 0; i < (RX_RING_SIZE+1); i++) {
  196. if (mp->rx_skbs[i] != NULL) {
  197. struct myri_rxd __iomem *rxd = &rq->myri_rxd[i];
  198. u32 dma_addr;
  199. dma_addr = sbus_readl(&rxd->myri_scatters[0].addr);
  200. sbus_unmap_single(mp->myri_sdev, dma_addr, RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE);
  201. dev_kfree_skb(mp->rx_skbs[i]);
  202. mp->rx_skbs[i] = NULL;
  203. }
  204. }
  205. mp->tx_old = 0;
  206. sbus_writel(0, &sq->tail);
  207. sbus_writel(0, &sq->head);
  208. for (i = 0; i < TX_RING_SIZE; i++) {
  209. if (mp->tx_skbs[i] != NULL) {
  210. struct sk_buff *skb = mp->tx_skbs[i];
  211. struct myri_txd __iomem *txd = &sq->myri_txd[i];
  212. u32 dma_addr;
  213. dma_addr = sbus_readl(&txd->myri_gathers[0].addr);
  214. sbus_unmap_single(mp->myri_sdev, dma_addr, (skb->len + 3) & ~3, SBUS_DMA_TODEVICE);
  215. dev_kfree_skb(mp->tx_skbs[i]);
  216. mp->tx_skbs[i] = NULL;
  217. }
  218. }
  219. }
  220. static void myri_init_rings(struct myri_eth *mp, int from_irq)
  221. {
  222. struct recvq __iomem *rq = mp->rq;
  223. struct myri_rxd __iomem *rxd = &rq->myri_rxd[0];
  224. struct net_device *dev = mp->dev;
  225. gfp_t gfp_flags = GFP_KERNEL;
  226. int i;
  227. if (from_irq || in_interrupt())
  228. gfp_flags = GFP_ATOMIC;
  229. myri_clean_rings(mp);
  230. for (i = 0; i < RX_RING_SIZE; i++) {
  231. struct sk_buff *skb = myri_alloc_skb(RX_ALLOC_SIZE, gfp_flags);
  232. u32 dma_addr;
  233. if (!skb)
  234. continue;
  235. mp->rx_skbs[i] = skb;
  236. skb->dev = dev;
  237. skb_put(skb, RX_ALLOC_SIZE);
  238. dma_addr = sbus_map_single(mp->myri_sdev, skb->data, RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE);
  239. sbus_writel(dma_addr, &rxd[i].myri_scatters[0].addr);
  240. sbus_writel(RX_ALLOC_SIZE, &rxd[i].myri_scatters[0].len);
  241. sbus_writel(i, &rxd[i].ctx);
  242. sbus_writel(1, &rxd[i].num_sg);
  243. }
  244. sbus_writel(0, &rq->head);
  245. sbus_writel(RX_RING_SIZE, &rq->tail);
  246. }
  247. static int myri_init(struct myri_eth *mp, int from_irq)
  248. {
  249. myri_init_rings(mp, from_irq);
  250. return 0;
  251. }
  252. static void myri_is_not_so_happy(struct myri_eth *mp)
  253. {
  254. }
  255. #ifdef DEBUG_HEADER
  256. static void dump_ehdr(struct ethhdr *ehdr)
  257. {
  258. printk("ehdr[h_dst(%02x:%02x:%02x:%02x:%02x:%02x)"
  259. "h_source(%02x:%02x:%02x:%02x:%02x:%02x)h_proto(%04x)]\n",
  260. ehdr->h_dest[0], ehdr->h_dest[1], ehdr->h_dest[2],
  261. ehdr->h_dest[3], ehdr->h_dest[4], ehdr->h_dest[4],
  262. ehdr->h_source[0], ehdr->h_source[1], ehdr->h_source[2],
  263. ehdr->h_source[3], ehdr->h_source[4], ehdr->h_source[4],
  264. ehdr->h_proto);
  265. }
  266. static void dump_ehdr_and_myripad(unsigned char *stuff)
  267. {
  268. struct ethhdr *ehdr = (struct ethhdr *) (stuff + 2);
  269. printk("pad[%02x:%02x]", stuff[0], stuff[1]);
  270. printk("ehdr[h_dst(%02x:%02x:%02x:%02x:%02x:%02x)"
  271. "h_source(%02x:%02x:%02x:%02x:%02x:%02x)h_proto(%04x)]\n",
  272. ehdr->h_dest[0], ehdr->h_dest[1], ehdr->h_dest[2],
  273. ehdr->h_dest[3], ehdr->h_dest[4], ehdr->h_dest[4],
  274. ehdr->h_source[0], ehdr->h_source[1], ehdr->h_source[2],
  275. ehdr->h_source[3], ehdr->h_source[4], ehdr->h_source[4],
  276. ehdr->h_proto);
  277. }
  278. #endif
  279. static void myri_tx(struct myri_eth *mp, struct net_device *dev)
  280. {
  281. struct sendq __iomem *sq= mp->sq;
  282. int entry = mp->tx_old;
  283. int limit = sbus_readl(&sq->head);
  284. DTX(("entry[%d] limit[%d] ", entry, limit));
  285. if (entry == limit)
  286. return;
  287. while (entry != limit) {
  288. struct sk_buff *skb = mp->tx_skbs[entry];
  289. u32 dma_addr;
  290. DTX(("SKB[%d] ", entry));
  291. dma_addr = sbus_readl(&sq->myri_txd[entry].myri_gathers[0].addr);
  292. sbus_unmap_single(mp->myri_sdev, dma_addr, skb->len, SBUS_DMA_TODEVICE);
  293. dev_kfree_skb(skb);
  294. mp->tx_skbs[entry] = NULL;
  295. mp->enet_stats.tx_packets++;
  296. entry = NEXT_TX(entry);
  297. }
  298. mp->tx_old = entry;
  299. }
  300. /* Determine the packet's protocol ID. The rule here is that we
  301. * assume 802.3 if the type field is short enough to be a length.
  302. * This is normal practice and works for any 'now in use' protocol.
  303. */
  304. static __be16 myri_type_trans(struct sk_buff *skb, struct net_device *dev)
  305. {
  306. struct ethhdr *eth;
  307. unsigned char *rawp;
  308. skb->mac.raw = (((unsigned char *)skb->data) + MYRI_PAD_LEN);
  309. skb_pull(skb, dev->hard_header_len);
  310. eth = eth_hdr(skb);
  311. #ifdef DEBUG_HEADER
  312. DHDR(("myri_type_trans: "));
  313. dump_ehdr(eth);
  314. #endif
  315. if (*eth->h_dest & 1) {
  316. if (memcmp(eth->h_dest, dev->broadcast, ETH_ALEN)==0)
  317. skb->pkt_type = PACKET_BROADCAST;
  318. else
  319. skb->pkt_type = PACKET_MULTICAST;
  320. } else if (dev->flags & (IFF_PROMISC|IFF_ALLMULTI)) {
  321. if (memcmp(eth->h_dest, dev->dev_addr, ETH_ALEN))
  322. skb->pkt_type = PACKET_OTHERHOST;
  323. }
  324. if (ntohs(eth->h_proto) >= 1536)
  325. return eth->h_proto;
  326. rawp = skb->data;
  327. /* This is a magic hack to spot IPX packets. Older Novell breaks
  328. * the protocol design and runs IPX over 802.3 without an 802.2 LLC
  329. * layer. We look for FFFF which isn't a used 802.2 SSAP/DSAP. This
  330. * won't work for fault tolerant netware but does for the rest.
  331. */
  332. if (*(unsigned short *)rawp == 0xFFFF)
  333. return htons(ETH_P_802_3);
  334. /* Real 802.2 LLC */
  335. return htons(ETH_P_802_2);
  336. }
  337. static void myri_rx(struct myri_eth *mp, struct net_device *dev)
  338. {
  339. struct recvq __iomem *rq = mp->rq;
  340. struct recvq __iomem *rqa = mp->rqack;
  341. int entry = sbus_readl(&rqa->head);
  342. int limit = sbus_readl(&rqa->tail);
  343. int drops;
  344. DRX(("entry[%d] limit[%d] ", entry, limit));
  345. if (entry == limit)
  346. return;
  347. drops = 0;
  348. DRX(("\n"));
  349. while (entry != limit) {
  350. struct myri_rxd __iomem *rxdack = &rqa->myri_rxd[entry];
  351. u32 csum = sbus_readl(&rxdack->csum);
  352. int len = sbus_readl(&rxdack->myri_scatters[0].len);
  353. int index = sbus_readl(&rxdack->ctx);
  354. struct myri_rxd __iomem *rxd = &rq->myri_rxd[sbus_readl(&rq->tail)];
  355. struct sk_buff *skb = mp->rx_skbs[index];
  356. /* Ack it. */
  357. sbus_writel(NEXT_RX(entry), &rqa->head);
  358. /* Check for errors. */
  359. DRX(("rxd[%d]: %p len[%d] csum[%08x] ", entry, rxd, len, csum));
  360. sbus_dma_sync_single_for_cpu(mp->myri_sdev,
  361. sbus_readl(&rxd->myri_scatters[0].addr),
  362. RX_ALLOC_SIZE, SBUS_DMA_FROMDEVICE);
  363. if (len < (ETH_HLEN + MYRI_PAD_LEN) || (skb->data[0] != MYRI_PAD_LEN)) {
  364. DRX(("ERROR["));
  365. mp->enet_stats.rx_errors++;
  366. if (len < (ETH_HLEN + MYRI_PAD_LEN)) {
  367. DRX(("BAD_LENGTH] "));
  368. mp->enet_stats.rx_length_errors++;
  369. } else {
  370. DRX(("NO_PADDING] "));
  371. mp->enet_stats.rx_frame_errors++;
  372. }
  373. /* Return it to the LANAI. */
  374. drop_it:
  375. drops++;
  376. DRX(("DROP "));
  377. mp->enet_stats.rx_dropped++;
  378. sbus_dma_sync_single_for_device(mp->myri_sdev,
  379. sbus_readl(&rxd->myri_scatters[0].addr),
  380. RX_ALLOC_SIZE,
  381. SBUS_DMA_FROMDEVICE);
  382. sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
  383. sbus_writel(index, &rxd->ctx);
  384. sbus_writel(1, &rxd->num_sg);
  385. sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
  386. goto next;
  387. }
  388. DRX(("len[%d] ", len));
  389. if (len > RX_COPY_THRESHOLD) {
  390. struct sk_buff *new_skb;
  391. u32 dma_addr;
  392. DRX(("BIGBUFF "));
  393. new_skb = myri_alloc_skb(RX_ALLOC_SIZE, GFP_ATOMIC);
  394. if (new_skb == NULL) {
  395. DRX(("skb_alloc(FAILED) "));
  396. goto drop_it;
  397. }
  398. sbus_unmap_single(mp->myri_sdev,
  399. sbus_readl(&rxd->myri_scatters[0].addr),
  400. RX_ALLOC_SIZE,
  401. SBUS_DMA_FROMDEVICE);
  402. mp->rx_skbs[index] = new_skb;
  403. new_skb->dev = dev;
  404. skb_put(new_skb, RX_ALLOC_SIZE);
  405. dma_addr = sbus_map_single(mp->myri_sdev,
  406. new_skb->data,
  407. RX_ALLOC_SIZE,
  408. SBUS_DMA_FROMDEVICE);
  409. sbus_writel(dma_addr, &rxd->myri_scatters[0].addr);
  410. sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
  411. sbus_writel(index, &rxd->ctx);
  412. sbus_writel(1, &rxd->num_sg);
  413. sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
  414. /* Trim the original skb for the netif. */
  415. DRX(("trim(%d) ", len));
  416. skb_trim(skb, len);
  417. } else {
  418. struct sk_buff *copy_skb = dev_alloc_skb(len);
  419. DRX(("SMALLBUFF "));
  420. if (copy_skb == NULL) {
  421. DRX(("dev_alloc_skb(FAILED) "));
  422. goto drop_it;
  423. }
  424. /* DMA sync already done above. */
  425. copy_skb->dev = dev;
  426. DRX(("resv_and_put "));
  427. skb_put(copy_skb, len);
  428. memcpy(copy_skb->data, skb->data, len);
  429. /* Reuse original ring buffer. */
  430. DRX(("reuse "));
  431. sbus_dma_sync_single_for_device(mp->myri_sdev,
  432. sbus_readl(&rxd->myri_scatters[0].addr),
  433. RX_ALLOC_SIZE,
  434. SBUS_DMA_FROMDEVICE);
  435. sbus_writel(RX_ALLOC_SIZE, &rxd->myri_scatters[0].len);
  436. sbus_writel(index, &rxd->ctx);
  437. sbus_writel(1, &rxd->num_sg);
  438. sbus_writel(NEXT_RX(sbus_readl(&rq->tail)), &rq->tail);
  439. skb = copy_skb;
  440. }
  441. /* Just like the happy meal we get checksums from this card. */
  442. skb->csum = csum;
  443. skb->ip_summed = CHECKSUM_UNNECESSARY; /* XXX */
  444. skb->protocol = myri_type_trans(skb, dev);
  445. DRX(("prot[%04x] netif_rx ", skb->protocol));
  446. netif_rx(skb);
  447. dev->last_rx = jiffies;
  448. mp->enet_stats.rx_packets++;
  449. mp->enet_stats.rx_bytes += len;
  450. next:
  451. DRX(("NEXT\n"));
  452. entry = NEXT_RX(entry);
  453. }
  454. }
  455. static irqreturn_t myri_interrupt(int irq, void *dev_id)
  456. {
  457. struct net_device *dev = (struct net_device *) dev_id;
  458. struct myri_eth *mp = (struct myri_eth *) dev->priv;
  459. void __iomem *lregs = mp->lregs;
  460. struct myri_channel __iomem *chan = &mp->shmem->channel;
  461. unsigned long flags;
  462. u32 status;
  463. int handled = 0;
  464. spin_lock_irqsave(&mp->irq_lock, flags);
  465. status = sbus_readl(lregs + LANAI_ISTAT);
  466. DIRQ(("myri_interrupt: status[%08x] ", status));
  467. if (status & ISTAT_HOST) {
  468. u32 softstate;
  469. handled = 1;
  470. DIRQ(("IRQ_DISAB "));
  471. myri_disable_irq(lregs, mp->cregs);
  472. softstate = sbus_readl(&chan->state);
  473. DIRQ(("state[%08x] ", softstate));
  474. if (softstate != STATE_READY) {
  475. DIRQ(("myri_not_so_happy "));
  476. myri_is_not_so_happy(mp);
  477. }
  478. DIRQ(("\nmyri_rx: "));
  479. myri_rx(mp, dev);
  480. DIRQ(("\nistat=ISTAT_HOST "));
  481. sbus_writel(ISTAT_HOST, lregs + LANAI_ISTAT);
  482. DIRQ(("IRQ_ENAB "));
  483. myri_enable_irq(lregs, mp->cregs);
  484. }
  485. DIRQ(("\n"));
  486. spin_unlock_irqrestore(&mp->irq_lock, flags);
  487. return IRQ_RETVAL(handled);
  488. }
  489. static int myri_open(struct net_device *dev)
  490. {
  491. struct myri_eth *mp = (struct myri_eth *) dev->priv;
  492. return myri_init(mp, in_interrupt());
  493. }
  494. static int myri_close(struct net_device *dev)
  495. {
  496. struct myri_eth *mp = (struct myri_eth *) dev->priv;
  497. myri_clean_rings(mp);
  498. return 0;
  499. }
  500. static void myri_tx_timeout(struct net_device *dev)
  501. {
  502. struct myri_eth *mp = (struct myri_eth *) dev->priv;
  503. printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
  504. mp->enet_stats.tx_errors++;
  505. myri_init(mp, 0);
  506. netif_wake_queue(dev);
  507. }
  508. static int myri_start_xmit(struct sk_buff *skb, struct net_device *dev)
  509. {
  510. struct myri_eth *mp = (struct myri_eth *) dev->priv;
  511. struct sendq __iomem *sq = mp->sq;
  512. struct myri_txd __iomem *txd;
  513. unsigned long flags;
  514. unsigned int head, tail;
  515. int len, entry;
  516. u32 dma_addr;
  517. DTX(("myri_start_xmit: "));
  518. myri_tx(mp, dev);
  519. netif_stop_queue(dev);
  520. /* This is just to prevent multiple PIO reads for TX_BUFFS_AVAIL. */
  521. head = sbus_readl(&sq->head);
  522. tail = sbus_readl(&sq->tail);
  523. if (!TX_BUFFS_AVAIL(head, tail)) {
  524. DTX(("no buffs available, returning 1\n"));
  525. return 1;
  526. }
  527. spin_lock_irqsave(&mp->irq_lock, flags);
  528. DHDR(("xmit[skbdata(%p)]\n", skb->data));
  529. #ifdef DEBUG_HEADER
  530. dump_ehdr_and_myripad(((unsigned char *) skb->data));
  531. #endif
  532. /* XXX Maybe this can go as well. */
  533. len = skb->len;
  534. if (len & 3) {
  535. DTX(("len&3 "));
  536. len = (len + 4) & (~3);
  537. }
  538. entry = sbus_readl(&sq->tail);
  539. txd = &sq->myri_txd[entry];
  540. mp->tx_skbs[entry] = skb;
  541. /* Must do this before we sbus map it. */
  542. if (skb->data[MYRI_PAD_LEN] & 0x1) {
  543. sbus_writew(0xffff, &txd->addr[0]);
  544. sbus_writew(0xffff, &txd->addr[1]);
  545. sbus_writew(0xffff, &txd->addr[2]);
  546. sbus_writew(0xffff, &txd->addr[3]);
  547. } else {
  548. sbus_writew(0xffff, &txd->addr[0]);
  549. sbus_writew((skb->data[0] << 8) | skb->data[1], &txd->addr[1]);
  550. sbus_writew((skb->data[2] << 8) | skb->data[3], &txd->addr[2]);
  551. sbus_writew((skb->data[4] << 8) | skb->data[5], &txd->addr[3]);
  552. }
  553. dma_addr = sbus_map_single(mp->myri_sdev, skb->data, len, SBUS_DMA_TODEVICE);
  554. sbus_writel(dma_addr, &txd->myri_gathers[0].addr);
  555. sbus_writel(len, &txd->myri_gathers[0].len);
  556. sbus_writel(1, &txd->num_sg);
  557. sbus_writel(KERNEL_CHANNEL, &txd->chan);
  558. sbus_writel(len, &txd->len);
  559. sbus_writel((u32)-1, &txd->csum_off);
  560. sbus_writel(0, &txd->csum_field);
  561. sbus_writel(NEXT_TX(entry), &sq->tail);
  562. DTX(("BangTheChip "));
  563. bang_the_chip(mp);
  564. DTX(("tbusy=0, returning 0\n"));
  565. netif_start_queue(dev);
  566. spin_unlock_irqrestore(&mp->irq_lock, flags);
  567. return 0;
  568. }
  569. /* Create the MyriNet MAC header for an arbitrary protocol layer
  570. *
  571. * saddr=NULL means use device source address
  572. * daddr=NULL means leave destination address (eg unresolved arp)
  573. */
  574. static int myri_header(struct sk_buff *skb, struct net_device *dev, unsigned short type,
  575. void *daddr, void *saddr, unsigned len)
  576. {
  577. struct ethhdr *eth = (struct ethhdr *) skb_push(skb, ETH_HLEN);
  578. unsigned char *pad = (unsigned char *) skb_push(skb, MYRI_PAD_LEN);
  579. #ifdef DEBUG_HEADER
  580. DHDR(("myri_header: pad[%02x,%02x] ", pad[0], pad[1]));
  581. dump_ehdr(eth);
  582. #endif
  583. /* Set the MyriNET padding identifier. */
  584. pad[0] = MYRI_PAD_LEN;
  585. pad[1] = 0xab;
  586. /* Set the protocol type. For a packet of type ETH_P_802_3 we put the length
  587. * in here instead. It is up to the 802.2 layer to carry protocol information.
  588. */
  589. if (type != ETH_P_802_3)
  590. eth->h_proto = htons(type);
  591. else
  592. eth->h_proto = htons(len);
  593. /* Set the source hardware address. */
  594. if (saddr)
  595. memcpy(eth->h_source, saddr, dev->addr_len);
  596. else
  597. memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
  598. /* Anyway, the loopback-device should never use this function... */
  599. if (dev->flags & IFF_LOOPBACK) {
  600. int i;
  601. for (i = 0; i < dev->addr_len; i++)
  602. eth->h_dest[i] = 0;
  603. return(dev->hard_header_len);
  604. }
  605. if (daddr) {
  606. memcpy(eth->h_dest, daddr, dev->addr_len);
  607. return dev->hard_header_len;
  608. }
  609. return -dev->hard_header_len;
  610. }
  611. /* Rebuild the MyriNet MAC header. This is called after an ARP
  612. * (or in future other address resolution) has completed on this
  613. * sk_buff. We now let ARP fill in the other fields.
  614. */
  615. static int myri_rebuild_header(struct sk_buff *skb)
  616. {
  617. unsigned char *pad = (unsigned char *) skb->data;
  618. struct ethhdr *eth = (struct ethhdr *) (pad + MYRI_PAD_LEN);
  619. struct net_device *dev = skb->dev;
  620. #ifdef DEBUG_HEADER
  621. DHDR(("myri_rebuild_header: pad[%02x,%02x] ", pad[0], pad[1]));
  622. dump_ehdr(eth);
  623. #endif
  624. /* Refill MyriNet padding identifiers, this is just being anal. */
  625. pad[0] = MYRI_PAD_LEN;
  626. pad[1] = 0xab;
  627. switch (eth->h_proto)
  628. {
  629. #ifdef CONFIG_INET
  630. case __constant_htons(ETH_P_IP):
  631. return arp_find(eth->h_dest, skb);
  632. #endif
  633. default:
  634. printk(KERN_DEBUG
  635. "%s: unable to resolve type %X addresses.\n",
  636. dev->name, (int)eth->h_proto);
  637. memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
  638. return 0;
  639. break;
  640. }
  641. return 0;
  642. }
  643. int myri_header_cache(struct neighbour *neigh, struct hh_cache *hh)
  644. {
  645. unsigned short type = hh->hh_type;
  646. unsigned char *pad;
  647. struct ethhdr *eth;
  648. struct net_device *dev = neigh->dev;
  649. pad = ((unsigned char *) hh->hh_data) +
  650. HH_DATA_OFF(sizeof(*eth) + MYRI_PAD_LEN);
  651. eth = (struct ethhdr *) (pad + MYRI_PAD_LEN);
  652. if (type == __constant_htons(ETH_P_802_3))
  653. return -1;
  654. /* Refill MyriNet padding identifiers, this is just being anal. */
  655. pad[0] = MYRI_PAD_LEN;
  656. pad[1] = 0xab;
  657. eth->h_proto = type;
  658. memcpy(eth->h_source, dev->dev_addr, dev->addr_len);
  659. memcpy(eth->h_dest, neigh->ha, dev->addr_len);
  660. hh->hh_len = 16;
  661. return 0;
  662. }
  663. /* Called by Address Resolution module to notify changes in address. */
  664. void myri_header_cache_update(struct hh_cache *hh, struct net_device *dev, unsigned char * haddr)
  665. {
  666. memcpy(((u8*)hh->hh_data) + HH_DATA_OFF(sizeof(struct ethhdr)),
  667. haddr, dev->addr_len);
  668. }
  669. static int myri_change_mtu(struct net_device *dev, int new_mtu)
  670. {
  671. if ((new_mtu < (ETH_HLEN + MYRI_PAD_LEN)) || (new_mtu > MYRINET_MTU))
  672. return -EINVAL;
  673. dev->mtu = new_mtu;
  674. return 0;
  675. }
  676. static struct net_device_stats *myri_get_stats(struct net_device *dev)
  677. { return &(((struct myri_eth *)dev->priv)->enet_stats); }
  678. static void myri_set_multicast(struct net_device *dev)
  679. {
  680. /* Do nothing, all MyriCOM nodes transmit multicast frames
  681. * as broadcast packets...
  682. */
  683. }
  684. static inline void set_boardid_from_idprom(struct myri_eth *mp, int num)
  685. {
  686. mp->eeprom.id[0] = 0;
  687. mp->eeprom.id[1] = idprom->id_machtype;
  688. mp->eeprom.id[2] = (idprom->id_sernum >> 16) & 0xff;
  689. mp->eeprom.id[3] = (idprom->id_sernum >> 8) & 0xff;
  690. mp->eeprom.id[4] = (idprom->id_sernum >> 0) & 0xff;
  691. mp->eeprom.id[5] = num;
  692. }
  693. static inline void determine_reg_space_size(struct myri_eth *mp)
  694. {
  695. switch(mp->eeprom.cpuvers) {
  696. case CPUVERS_2_3:
  697. case CPUVERS_3_0:
  698. case CPUVERS_3_1:
  699. case CPUVERS_3_2:
  700. mp->reg_size = (3 * 128 * 1024) + 4096;
  701. break;
  702. case CPUVERS_4_0:
  703. case CPUVERS_4_1:
  704. mp->reg_size = ((4096<<1) + mp->eeprom.ramsz);
  705. break;
  706. case CPUVERS_4_2:
  707. case CPUVERS_5_0:
  708. default:
  709. printk("myricom: AIEEE weird cpu version %04x assuming pre4.0\n",
  710. mp->eeprom.cpuvers);
  711. mp->reg_size = (3 * 128 * 1024) + 4096;
  712. };
  713. }
  714. #ifdef DEBUG_DETECT
  715. static void dump_eeprom(struct myri_eth *mp)
  716. {
  717. printk("EEPROM: clockval[%08x] cpuvers[%04x] "
  718. "id[%02x,%02x,%02x,%02x,%02x,%02x]\n",
  719. mp->eeprom.cval, mp->eeprom.cpuvers,
  720. mp->eeprom.id[0], mp->eeprom.id[1], mp->eeprom.id[2],
  721. mp->eeprom.id[3], mp->eeprom.id[4], mp->eeprom.id[5]);
  722. printk("EEPROM: ramsz[%08x]\n", mp->eeprom.ramsz);
  723. printk("EEPROM: fvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
  724. mp->eeprom.fvers[0], mp->eeprom.fvers[1], mp->eeprom.fvers[2],
  725. mp->eeprom.fvers[3], mp->eeprom.fvers[4], mp->eeprom.fvers[5],
  726. mp->eeprom.fvers[6], mp->eeprom.fvers[7]);
  727. printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
  728. mp->eeprom.fvers[8], mp->eeprom.fvers[9], mp->eeprom.fvers[10],
  729. mp->eeprom.fvers[11], mp->eeprom.fvers[12], mp->eeprom.fvers[13],
  730. mp->eeprom.fvers[14], mp->eeprom.fvers[15]);
  731. printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
  732. mp->eeprom.fvers[16], mp->eeprom.fvers[17], mp->eeprom.fvers[18],
  733. mp->eeprom.fvers[19], mp->eeprom.fvers[20], mp->eeprom.fvers[21],
  734. mp->eeprom.fvers[22], mp->eeprom.fvers[23]);
  735. printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n",
  736. mp->eeprom.fvers[24], mp->eeprom.fvers[25], mp->eeprom.fvers[26],
  737. mp->eeprom.fvers[27], mp->eeprom.fvers[28], mp->eeprom.fvers[29],
  738. mp->eeprom.fvers[30], mp->eeprom.fvers[31]);
  739. printk("EEPROM: mvers[%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x\n",
  740. mp->eeprom.mvers[0], mp->eeprom.mvers[1], mp->eeprom.mvers[2],
  741. mp->eeprom.mvers[3], mp->eeprom.mvers[4], mp->eeprom.mvers[5],
  742. mp->eeprom.mvers[6], mp->eeprom.mvers[7]);
  743. printk("EEPROM: %02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x]\n",
  744. mp->eeprom.mvers[8], mp->eeprom.mvers[9], mp->eeprom.mvers[10],
  745. mp->eeprom.mvers[11], mp->eeprom.mvers[12], mp->eeprom.mvers[13],
  746. mp->eeprom.mvers[14], mp->eeprom.mvers[15]);
  747. printk("EEPROM: dlval[%04x] brd_type[%04x] bus_type[%04x] prod_code[%04x]\n",
  748. mp->eeprom.dlval, mp->eeprom.brd_type, mp->eeprom.bus_type,
  749. mp->eeprom.prod_code);
  750. printk("EEPROM: serial_num[%08x]\n", mp->eeprom.serial_num);
  751. }
  752. #endif
  753. static int __devinit myri_ether_init(struct sbus_dev *sdev)
  754. {
  755. static int num;
  756. static unsigned version_printed;
  757. struct net_device *dev;
  758. struct myri_eth *mp;
  759. unsigned char prop_buf[32];
  760. int i;
  761. DET(("myri_ether_init(%p,%d):\n", sdev, num));
  762. dev = alloc_etherdev(sizeof(struct myri_eth));
  763. if (!dev)
  764. return -ENOMEM;
  765. if (version_printed++ == 0)
  766. printk(version);
  767. SET_MODULE_OWNER(dev);
  768. SET_NETDEV_DEV(dev, &sdev->ofdev.dev);
  769. mp = (struct myri_eth *) dev->priv;
  770. spin_lock_init(&mp->irq_lock);
  771. mp->myri_sdev = sdev;
  772. /* Clean out skb arrays. */
  773. for (i = 0; i < (RX_RING_SIZE + 1); i++)
  774. mp->rx_skbs[i] = NULL;
  775. for (i = 0; i < TX_RING_SIZE; i++)
  776. mp->tx_skbs[i] = NULL;
  777. /* First check for EEPROM information. */
  778. i = prom_getproperty(sdev->prom_node, "myrinet-eeprom-info",
  779. (char *)&mp->eeprom, sizeof(struct myri_eeprom));
  780. DET(("prom_getprop(myrinet-eeprom-info) returns %d\n", i));
  781. if (i == 0 || i == -1) {
  782. /* No eeprom property, must cook up the values ourselves. */
  783. DET(("No EEPROM: "));
  784. mp->eeprom.bus_type = BUS_TYPE_SBUS;
  785. mp->eeprom.cpuvers = prom_getintdefault(sdev->prom_node,"cpu_version",0);
  786. mp->eeprom.cval = prom_getintdefault(sdev->prom_node,"clock_value",0);
  787. mp->eeprom.ramsz = prom_getintdefault(sdev->prom_node,"sram_size",0);
  788. DET(("cpuvers[%d] cval[%d] ramsz[%d]\n", mp->eeprom.cpuvers,
  789. mp->eeprom.cval, mp->eeprom.ramsz));
  790. if (mp->eeprom.cpuvers == 0) {
  791. DET(("EEPROM: cpuvers was zero, setting to %04x\n",CPUVERS_2_3));
  792. mp->eeprom.cpuvers = CPUVERS_2_3;
  793. }
  794. if (mp->eeprom.cpuvers < CPUVERS_3_0) {
  795. DET(("EEPROM: cpuvers < CPUVERS_3_0, clockval set to zero.\n"));
  796. mp->eeprom.cval = 0;
  797. }
  798. if (mp->eeprom.ramsz == 0) {
  799. DET(("EEPROM: ramsz == 0, setting to 128k\n"));
  800. mp->eeprom.ramsz = (128 * 1024);
  801. }
  802. i = prom_getproperty(sdev->prom_node, "myrinet-board-id",
  803. &prop_buf[0], 10);
  804. DET(("EEPROM: prom_getprop(myrinet-board-id) returns %d\n", i));
  805. if ((i != 0) && (i != -1))
  806. memcpy(&mp->eeprom.id[0], &prop_buf[0], 6);
  807. else
  808. set_boardid_from_idprom(mp, num);
  809. i = prom_getproperty(sdev->prom_node, "fpga_version",
  810. &mp->eeprom.fvers[0], 32);
  811. DET(("EEPROM: prom_getprop(fpga_version) returns %d\n", i));
  812. if (i == 0 || i == -1)
  813. memset(&mp->eeprom.fvers[0], 0, 32);
  814. if (mp->eeprom.cpuvers == CPUVERS_4_1) {
  815. DET(("EEPROM: cpuvers CPUVERS_4_1, "));
  816. if (mp->eeprom.ramsz == (128 * 1024)) {
  817. DET(("ramsize 128k, setting to 256k, "));
  818. mp->eeprom.ramsz = (256 * 1024);
  819. }
  820. if ((mp->eeprom.cval==0x40414041)||(mp->eeprom.cval==0x90449044)){
  821. DET(("changing cval from %08x to %08x ",
  822. mp->eeprom.cval, 0x50e450e4));
  823. mp->eeprom.cval = 0x50e450e4;
  824. }
  825. DET(("\n"));
  826. }
  827. }
  828. #ifdef DEBUG_DETECT
  829. dump_eeprom(mp);
  830. #endif
  831. for (i = 0; i < 6; i++)
  832. dev->dev_addr[i] = mp->eeprom.id[i];
  833. determine_reg_space_size(mp);
  834. /* Map in the MyriCOM register/localram set. */
  835. if (mp->eeprom.cpuvers < CPUVERS_4_0) {
  836. /* XXX Makes no sense, if control reg is non-existant this
  837. * XXX driver cannot function at all... maybe pre-4.0 is
  838. * XXX only a valid version for PCI cards? Ask feldy...
  839. */
  840. DET(("Mapping regs for cpuvers < CPUVERS_4_0\n"));
  841. mp->regs = sbus_ioremap(&sdev->resource[0], 0,
  842. mp->reg_size, "MyriCOM Regs");
  843. if (!mp->regs) {
  844. printk("MyriCOM: Cannot map MyriCOM registers.\n");
  845. goto err;
  846. }
  847. mp->lanai = mp->regs + (256 * 1024);
  848. mp->lregs = mp->lanai + (0x10000 * 2);
  849. } else {
  850. DET(("Mapping regs for cpuvers >= CPUVERS_4_0\n"));
  851. mp->cregs = sbus_ioremap(&sdev->resource[0], 0,
  852. PAGE_SIZE, "MyriCOM Control Regs");
  853. mp->lregs = sbus_ioremap(&sdev->resource[0], (256 * 1024),
  854. PAGE_SIZE, "MyriCOM LANAI Regs");
  855. mp->lanai =
  856. sbus_ioremap(&sdev->resource[0], (512 * 1024),
  857. mp->eeprom.ramsz, "MyriCOM SRAM");
  858. }
  859. DET(("Registers mapped: cregs[%p] lregs[%p] lanai[%p]\n",
  860. mp->cregs, mp->lregs, mp->lanai));
  861. if (mp->eeprom.cpuvers >= CPUVERS_4_0)
  862. mp->shmem_base = 0xf000;
  863. else
  864. mp->shmem_base = 0x8000;
  865. DET(("Shared memory base is %04x, ", mp->shmem_base));
  866. mp->shmem = (struct myri_shmem __iomem *)
  867. (mp->lanai + (mp->shmem_base * 2));
  868. DET(("shmem mapped at %p\n", mp->shmem));
  869. mp->rqack = &mp->shmem->channel.recvqa;
  870. mp->rq = &mp->shmem->channel.recvq;
  871. mp->sq = &mp->shmem->channel.sendq;
  872. /* Reset the board. */
  873. DET(("Resetting LANAI\n"));
  874. myri_reset_off(mp->lregs, mp->cregs);
  875. myri_reset_on(mp->cregs);
  876. /* Turn IRQ's off. */
  877. myri_disable_irq(mp->lregs, mp->cregs);
  878. /* Reset once more. */
  879. myri_reset_on(mp->cregs);
  880. /* Get the supported DVMA burst sizes from our SBUS. */
  881. mp->myri_bursts = prom_getintdefault(mp->myri_sdev->bus->prom_node,
  882. "burst-sizes", 0x00);
  883. if (!sbus_can_burst64(sdev))
  884. mp->myri_bursts &= ~(DMA_BURST64);
  885. DET(("MYRI bursts %02x\n", mp->myri_bursts));
  886. /* Encode SBUS interrupt level in second control register. */
  887. i = prom_getint(sdev->prom_node, "interrupts");
  888. if (i == 0)
  889. i = 4;
  890. DET(("prom_getint(interrupts)==%d, irqlvl set to %04x\n",
  891. i, (1 << i)));
  892. sbus_writel((1 << i), mp->cregs + MYRICTRL_IRQLVL);
  893. mp->dev = dev;
  894. dev->open = &myri_open;
  895. dev->stop = &myri_close;
  896. dev->hard_start_xmit = &myri_start_xmit;
  897. dev->tx_timeout = &myri_tx_timeout;
  898. dev->watchdog_timeo = 5*HZ;
  899. dev->get_stats = &myri_get_stats;
  900. dev->set_multicast_list = &myri_set_multicast;
  901. dev->irq = sdev->irqs[0];
  902. /* Register interrupt handler now. */
  903. DET(("Requesting MYRIcom IRQ line.\n"));
  904. if (request_irq(dev->irq, &myri_interrupt,
  905. IRQF_SHARED, "MyriCOM Ethernet", (void *) dev)) {
  906. printk("MyriCOM: Cannot register interrupt handler.\n");
  907. goto err;
  908. }
  909. dev->mtu = MYRINET_MTU;
  910. dev->change_mtu = myri_change_mtu;
  911. dev->hard_header = myri_header;
  912. dev->rebuild_header = myri_rebuild_header;
  913. dev->hard_header_len = (ETH_HLEN + MYRI_PAD_LEN);
  914. dev->hard_header_cache = myri_header_cache;
  915. dev->header_cache_update= myri_header_cache_update;
  916. /* Load code onto the LANai. */
  917. DET(("Loading LANAI firmware\n"));
  918. myri_load_lanai(mp);
  919. if (register_netdev(dev)) {
  920. printk("MyriCOM: Cannot register device.\n");
  921. goto err_free_irq;
  922. }
  923. dev_set_drvdata(&sdev->ofdev.dev, mp);
  924. num++;
  925. printk("%s: MyriCOM MyriNET Ethernet ", dev->name);
  926. for (i = 0; i < 6; i++)
  927. printk("%2.2x%c", dev->dev_addr[i],
  928. i == 5 ? ' ' : ':');
  929. printk("\n");
  930. return 0;
  931. err_free_irq:
  932. free_irq(dev->irq, dev);
  933. err:
  934. /* This will also free the co-allocated 'dev->priv' */
  935. free_netdev(dev);
  936. return -ENODEV;
  937. }
  938. static int __devinit myri_sbus_probe(struct of_device *dev, const struct of_device_id *match)
  939. {
  940. struct sbus_dev *sdev = to_sbus_device(&dev->dev);
  941. return myri_ether_init(sdev);
  942. }
  943. static int __devexit myri_sbus_remove(struct of_device *dev)
  944. {
  945. struct myri_eth *mp = dev_get_drvdata(&dev->dev);
  946. struct net_device *net_dev = mp->dev;
  947. unregister_netdevice(net_dev);
  948. free_irq(net_dev->irq, net_dev);
  949. if (mp->eeprom.cpuvers < CPUVERS_4_0) {
  950. sbus_iounmap(mp->regs, mp->reg_size);
  951. } else {
  952. sbus_iounmap(mp->cregs, PAGE_SIZE);
  953. sbus_iounmap(mp->lregs, (256 * 1024));
  954. sbus_iounmap(mp->lanai, (512 * 1024));
  955. }
  956. free_netdev(net_dev);
  957. dev_set_drvdata(&dev->dev, NULL);
  958. return 0;
  959. }
  960. static struct of_device_id myri_sbus_match[] = {
  961. {
  962. .name = "MYRICOM,mlanai",
  963. },
  964. {
  965. .name = "myri",
  966. },
  967. {},
  968. };
  969. MODULE_DEVICE_TABLE(of, myri_sbus_match);
  970. static struct of_platform_driver myri_sbus_driver = {
  971. .name = "myri",
  972. .match_table = myri_sbus_match,
  973. .probe = myri_sbus_probe,
  974. .remove = __devexit_p(myri_sbus_remove),
  975. };
  976. static int __init myri_sbus_init(void)
  977. {
  978. return of_register_driver(&myri_sbus_driver, &sbus_bus_type);
  979. }
  980. static void __exit myri_sbus_exit(void)
  981. {
  982. of_unregister_driver(&myri_sbus_driver);
  983. }
  984. module_init(myri_sbus_init);
  985. module_exit(myri_sbus_exit);
  986. MODULE_LICENSE("GPL");