mv643xx_eth.h 12 KB

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  1. #ifndef __MV643XX_ETH_H__
  2. #define __MV643XX_ETH_H__
  3. #include <linux/module.h>
  4. #include <linux/kernel.h>
  5. #include <linux/spinlock.h>
  6. #include <linux/workqueue.h>
  7. #include <linux/mii.h>
  8. #include <linux/mv643xx.h>
  9. #include <asm/dma-mapping.h>
  10. /* Checksum offload for Tx works for most packets, but
  11. * fails if previous packet sent did not use hw csum
  12. */
  13. #define MV643XX_CHECKSUM_OFFLOAD_TX
  14. #define MV643XX_NAPI
  15. #define MV643XX_TX_FAST_REFILL
  16. #undef MV643XX_COAL
  17. /*
  18. * Number of RX / TX descriptors on RX / TX rings.
  19. * Note that allocating RX descriptors is done by allocating the RX
  20. * ring AND a preallocated RX buffers (skb's) for each descriptor.
  21. * The TX descriptors only allocates the TX descriptors ring,
  22. * with no pre allocated TX buffers (skb's are allocated by higher layers.
  23. */
  24. /* Default TX ring size is 1000 descriptors */
  25. #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
  26. /* Default RX ring size is 400 descriptors */
  27. #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
  28. #define MV643XX_TX_COAL 100
  29. #ifdef MV643XX_COAL
  30. #define MV643XX_RX_COAL 100
  31. #endif
  32. #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
  33. #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
  34. #else
  35. #define MAX_DESCS_PER_SKB 1
  36. #endif
  37. #define ETH_VLAN_HLEN 4
  38. #define ETH_FCS_LEN 4
  39. #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
  40. #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
  41. ETH_VLAN_HLEN + ETH_FCS_LEN)
  42. #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + dma_get_cache_alignment())
  43. #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
  44. #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
  45. #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
  46. #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
  47. #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
  48. #define ETH_INT_CAUSE_EXT 0x00000002
  49. #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
  50. #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
  51. #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
  52. #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
  53. #define ETH_INT_CAUSE_PHY 0x00010000
  54. #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY)
  55. #define ETH_INT_MASK_ALL 0x00000000
  56. #define ETH_INT_MASK_ALL_EXT 0x00000000
  57. #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
  58. #define PHY_WAIT_MICRO_SECONDS 10
  59. /* Buffer offset from buffer pointer */
  60. #define RX_BUF_OFFSET 0x2
  61. /* Gigabit Ethernet Unit Global Registers */
  62. /* MIB Counters register definitions */
  63. #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
  64. #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
  65. #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
  66. #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
  67. #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
  68. #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
  69. #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
  70. #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
  71. #define ETH_MIB_FRAMES_64_OCTETS 0x20
  72. #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
  73. #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
  74. #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
  75. #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
  76. #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
  77. #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
  78. #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
  79. #define ETH_MIB_GOOD_FRAMES_SENT 0x40
  80. #define ETH_MIB_EXCESSIVE_COLLISION 0x44
  81. #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
  82. #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
  83. #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
  84. #define ETH_MIB_FC_SENT 0x54
  85. #define ETH_MIB_GOOD_FC_RECEIVED 0x58
  86. #define ETH_MIB_BAD_FC_RECEIVED 0x5c
  87. #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
  88. #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
  89. #define ETH_MIB_OVERSIZE_RECEIVED 0x68
  90. #define ETH_MIB_JABBER_RECEIVED 0x6c
  91. #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
  92. #define ETH_MIB_BAD_CRC_EVENT 0x74
  93. #define ETH_MIB_COLLISION 0x78
  94. #define ETH_MIB_LATE_COLLISION 0x7c
  95. /* Port serial status reg (PSR) */
  96. #define ETH_INTERFACE_PCM 0x00000001
  97. #define ETH_LINK_IS_UP 0x00000002
  98. #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
  99. #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
  100. #define ETH_GMII_SPEED_1000 0x00000010
  101. #define ETH_MII_SPEED_100 0x00000020
  102. #define ETH_TX_IN_PROGRESS 0x00000080
  103. #define ETH_BYPASS_ACTIVE 0x00000100
  104. #define ETH_PORT_AT_PARTITION_STATE 0x00000200
  105. #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
  106. /* SMI reg */
  107. #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
  108. #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
  109. #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
  110. #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
  111. /* Interrupt Cause Register Bit Definitions */
  112. /* SDMA command status fields macros */
  113. /* Tx & Rx descriptors status */
  114. #define ETH_ERROR_SUMMARY 0x00000001
  115. /* Tx & Rx descriptors command */
  116. #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
  117. /* Tx descriptors status */
  118. #define ETH_LC_ERROR 0
  119. #define ETH_UR_ERROR 0x00000002
  120. #define ETH_RL_ERROR 0x00000004
  121. #define ETH_LLC_SNAP_FORMAT 0x00000200
  122. /* Rx descriptors status */
  123. #define ETH_OVERRUN_ERROR 0x00000002
  124. #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
  125. #define ETH_RESOURCE_ERROR 0x00000006
  126. #define ETH_VLAN_TAGGED 0x00080000
  127. #define ETH_BPDU_FRAME 0x00100000
  128. #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
  129. #define ETH_OTHER_FRAME_TYPE 0x00400000
  130. #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
  131. #define ETH_FRAME_TYPE_IP_V_4 0x01000000
  132. #define ETH_FRAME_HEADER_OK 0x02000000
  133. #define ETH_RX_LAST_DESC 0x04000000
  134. #define ETH_RX_FIRST_DESC 0x08000000
  135. #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
  136. #define ETH_RX_ENABLE_INTERRUPT 0x20000000
  137. #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
  138. /* Rx descriptors byte count */
  139. #define ETH_FRAME_FRAGMENTED 0x00000004
  140. /* Tx descriptors command */
  141. #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
  142. #define ETH_FRAME_SET_TO_VLAN 0x00008000
  143. #define ETH_UDP_FRAME 0x00010000
  144. #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
  145. #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
  146. #define ETH_ZERO_PADDING 0x00080000
  147. #define ETH_TX_LAST_DESC 0x00100000
  148. #define ETH_TX_FIRST_DESC 0x00200000
  149. #define ETH_GEN_CRC 0x00400000
  150. #define ETH_TX_ENABLE_INTERRUPT 0x00800000
  151. #define ETH_AUTO_MODE 0x40000000
  152. #define ETH_TX_IHL_SHIFT 11
  153. /* typedefs */
  154. typedef enum _eth_func_ret_status {
  155. ETH_OK, /* Returned as expected. */
  156. ETH_ERROR, /* Fundamental error. */
  157. ETH_RETRY, /* Could not process request. Try later.*/
  158. ETH_END_OF_JOB, /* Ring has nothing to process. */
  159. ETH_QUEUE_FULL, /* Ring resource error. */
  160. ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
  161. } ETH_FUNC_RET_STATUS;
  162. typedef enum _eth_target {
  163. ETH_TARGET_DRAM,
  164. ETH_TARGET_DEVICE,
  165. ETH_TARGET_CBS,
  166. ETH_TARGET_PCI0,
  167. ETH_TARGET_PCI1
  168. } ETH_TARGET;
  169. /* These are for big-endian machines. Little endian needs different
  170. * definitions.
  171. */
  172. #if defined(__BIG_ENDIAN)
  173. struct eth_rx_desc {
  174. u16 byte_cnt; /* Descriptor buffer byte count */
  175. u16 buf_size; /* Buffer size */
  176. u32 cmd_sts; /* Descriptor command status */
  177. u32 next_desc_ptr; /* Next descriptor pointer */
  178. u32 buf_ptr; /* Descriptor buffer pointer */
  179. };
  180. struct eth_tx_desc {
  181. u16 byte_cnt; /* buffer byte count */
  182. u16 l4i_chk; /* CPU provided TCP checksum */
  183. u32 cmd_sts; /* Command/status field */
  184. u32 next_desc_ptr; /* Pointer to next descriptor */
  185. u32 buf_ptr; /* pointer to buffer for this descriptor*/
  186. };
  187. #elif defined(__LITTLE_ENDIAN)
  188. struct eth_rx_desc {
  189. u32 cmd_sts; /* Descriptor command status */
  190. u16 buf_size; /* Buffer size */
  191. u16 byte_cnt; /* Descriptor buffer byte count */
  192. u32 buf_ptr; /* Descriptor buffer pointer */
  193. u32 next_desc_ptr; /* Next descriptor pointer */
  194. };
  195. struct eth_tx_desc {
  196. u32 cmd_sts; /* Command/status field */
  197. u16 l4i_chk; /* CPU provided TCP checksum */
  198. u16 byte_cnt; /* buffer byte count */
  199. u32 buf_ptr; /* pointer to buffer for this descriptor*/
  200. u32 next_desc_ptr; /* Pointer to next descriptor */
  201. };
  202. #else
  203. #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
  204. #endif
  205. /* Unified struct for Rx and Tx operations. The user is not required to */
  206. /* be familier with neither Tx nor Rx descriptors. */
  207. struct pkt_info {
  208. unsigned short byte_cnt; /* Descriptor buffer byte count */
  209. unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
  210. unsigned int cmd_sts; /* Descriptor command status */
  211. dma_addr_t buf_ptr; /* Descriptor buffer pointer */
  212. struct sk_buff *return_info; /* User resource return information */
  213. };
  214. /* Ethernet port specific information */
  215. struct mv643xx_mib_counters {
  216. u64 good_octets_received;
  217. u32 bad_octets_received;
  218. u32 internal_mac_transmit_err;
  219. u32 good_frames_received;
  220. u32 bad_frames_received;
  221. u32 broadcast_frames_received;
  222. u32 multicast_frames_received;
  223. u32 frames_64_octets;
  224. u32 frames_65_to_127_octets;
  225. u32 frames_128_to_255_octets;
  226. u32 frames_256_to_511_octets;
  227. u32 frames_512_to_1023_octets;
  228. u32 frames_1024_to_max_octets;
  229. u64 good_octets_sent;
  230. u32 good_frames_sent;
  231. u32 excessive_collision;
  232. u32 multicast_frames_sent;
  233. u32 broadcast_frames_sent;
  234. u32 unrec_mac_control_received;
  235. u32 fc_sent;
  236. u32 good_fc_received;
  237. u32 bad_fc_received;
  238. u32 undersize_received;
  239. u32 fragments_received;
  240. u32 oversize_received;
  241. u32 jabber_received;
  242. u32 mac_receive_error;
  243. u32 bad_crc_event;
  244. u32 collision;
  245. u32 late_collision;
  246. };
  247. struct mv643xx_private {
  248. int port_num; /* User Ethernet port number */
  249. u32 rx_sram_addr; /* Base address of rx sram area */
  250. u32 rx_sram_size; /* Size of rx sram area */
  251. u32 tx_sram_addr; /* Base address of tx sram area */
  252. u32 tx_sram_size; /* Size of tx sram area */
  253. int rx_resource_err; /* Rx ring resource error flag */
  254. /* Tx/Rx rings managment indexes fields. For driver use */
  255. /* Next available and first returning Rx resource */
  256. int rx_curr_desc_q, rx_used_desc_q;
  257. /* Next available and first returning Tx resource */
  258. int tx_curr_desc_q, tx_used_desc_q;
  259. #ifdef MV643XX_TX_FAST_REFILL
  260. u32 tx_clean_threshold;
  261. #endif
  262. struct eth_rx_desc *p_rx_desc_area;
  263. dma_addr_t rx_desc_dma;
  264. int rx_desc_area_size;
  265. struct sk_buff **rx_skb;
  266. struct eth_tx_desc *p_tx_desc_area;
  267. dma_addr_t tx_desc_dma;
  268. int tx_desc_area_size;
  269. struct sk_buff **tx_skb;
  270. struct work_struct tx_timeout_task;
  271. struct net_device_stats stats;
  272. struct mv643xx_mib_counters mib_counters;
  273. spinlock_t lock;
  274. /* Size of Tx Ring per queue */
  275. int tx_ring_size;
  276. /* Number of tx descriptors in use */
  277. int tx_desc_count;
  278. /* Size of Rx Ring per queue */
  279. int rx_ring_size;
  280. /* Number of rx descriptors in use */
  281. int rx_desc_count;
  282. /*
  283. * Used in case RX Ring is empty, which can be caused when
  284. * system does not have resources (skb's)
  285. */
  286. struct timer_list timeout;
  287. u32 rx_int_coal;
  288. u32 tx_int_coal;
  289. struct mii_if_info mii;
  290. };
  291. /* Port operation control routines */
  292. static void eth_port_init(struct mv643xx_private *mp);
  293. static void eth_port_reset(unsigned int eth_port_num);
  294. static void eth_port_start(struct net_device *dev);
  295. /* Port MAC address routines */
  296. static void eth_port_uc_addr_set(unsigned int eth_port_num,
  297. unsigned char *p_addr);
  298. /* PHY and MIB routines */
  299. static void ethernet_phy_reset(unsigned int eth_port_num);
  300. static void eth_port_write_smi_reg(unsigned int eth_port_num,
  301. unsigned int phy_reg, unsigned int value);
  302. static void eth_port_read_smi_reg(unsigned int eth_port_num,
  303. unsigned int phy_reg, unsigned int *value);
  304. static void eth_clear_mib_counters(unsigned int eth_port_num);
  305. /* Port data flow control routines */
  306. static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
  307. struct pkt_info *p_pkt_info);
  308. static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
  309. struct pkt_info *p_pkt_info);
  310. #endif /* __MV643XX_ETH_H__ */