mv643xx_eth.c 81 KB

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  1. /*
  2. * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
  3. * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
  4. *
  5. * Based on the 64360 driver from:
  6. * Copyright (C) 2002 rabeeh@galileo.co.il
  7. *
  8. * Copyright (C) 2003 PMC-Sierra, Inc.,
  9. * written by Manish Lachwani
  10. *
  11. * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
  12. *
  13. * Copyright (C) 2004-2006 MontaVista Software, Inc.
  14. * Dale Farnsworth <dale@farnsworth.org>
  15. *
  16. * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
  17. * <sjhill@realitydiluted.com>
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License
  21. * as published by the Free Software Foundation; either version 2
  22. * of the License, or (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  32. */
  33. #include <linux/init.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/in.h>
  36. #include <linux/ip.h>
  37. #include <linux/tcp.h>
  38. #include <linux/udp.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/bitops.h>
  41. #include <linux/delay.h>
  42. #include <linux/ethtool.h>
  43. #include <linux/platform_device.h>
  44. #include <asm/io.h>
  45. #include <asm/types.h>
  46. #include <asm/pgtable.h>
  47. #include <asm/system.h>
  48. #include <asm/delay.h>
  49. #include "mv643xx_eth.h"
  50. /* Static function declarations */
  51. static void eth_port_uc_addr_get(struct net_device *dev,
  52. unsigned char *MacAddr);
  53. static void eth_port_set_multicast_list(struct net_device *);
  54. static void mv643xx_eth_port_enable_tx(unsigned int port_num,
  55. unsigned int queues);
  56. static void mv643xx_eth_port_enable_rx(unsigned int port_num,
  57. unsigned int queues);
  58. static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
  59. static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
  60. static int mv643xx_eth_open(struct net_device *);
  61. static int mv643xx_eth_stop(struct net_device *);
  62. static int mv643xx_eth_change_mtu(struct net_device *, int);
  63. static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
  64. static void eth_port_init_mac_tables(unsigned int eth_port_num);
  65. #ifdef MV643XX_NAPI
  66. static int mv643xx_poll(struct net_device *dev, int *budget);
  67. #endif
  68. static int ethernet_phy_get(unsigned int eth_port_num);
  69. static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
  70. static int ethernet_phy_detect(unsigned int eth_port_num);
  71. static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
  72. static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
  73. static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
  74. static const struct ethtool_ops mv643xx_ethtool_ops;
  75. static char mv643xx_driver_name[] = "mv643xx_eth";
  76. static char mv643xx_driver_version[] = "1.0";
  77. static void __iomem *mv643xx_eth_shared_base;
  78. /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
  79. static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
  80. static inline u32 mv_read(int offset)
  81. {
  82. void __iomem *reg_base;
  83. reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
  84. return readl(reg_base + offset);
  85. }
  86. static inline void mv_write(int offset, u32 data)
  87. {
  88. void __iomem *reg_base;
  89. reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
  90. writel(data, reg_base + offset);
  91. }
  92. /*
  93. * Changes MTU (maximum transfer unit) of the gigabit ethenret port
  94. *
  95. * Input : pointer to ethernet interface network device structure
  96. * new mtu size
  97. * Output : 0 upon success, -EINVAL upon failure
  98. */
  99. static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
  100. {
  101. if ((new_mtu > 9500) || (new_mtu < 64))
  102. return -EINVAL;
  103. dev->mtu = new_mtu;
  104. /*
  105. * Stop then re-open the interface. This will allocate RX skb's with
  106. * the new MTU.
  107. * There is a possible danger that the open will not successed, due
  108. * to memory is full, which might fail the open function.
  109. */
  110. if (netif_running(dev)) {
  111. mv643xx_eth_stop(dev);
  112. if (mv643xx_eth_open(dev))
  113. printk(KERN_ERR
  114. "%s: Fatal error on opening device\n",
  115. dev->name);
  116. }
  117. return 0;
  118. }
  119. /*
  120. * mv643xx_eth_rx_refill_descs
  121. *
  122. * Fills / refills RX queue on a certain gigabit ethernet port
  123. *
  124. * Input : pointer to ethernet interface network device structure
  125. * Output : N/A
  126. */
  127. static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
  128. {
  129. struct mv643xx_private *mp = netdev_priv(dev);
  130. struct pkt_info pkt_info;
  131. struct sk_buff *skb;
  132. int unaligned;
  133. while (mp->rx_desc_count < mp->rx_ring_size) {
  134. skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
  135. if (!skb)
  136. break;
  137. mp->rx_desc_count++;
  138. unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
  139. if (unaligned)
  140. skb_reserve(skb, dma_get_cache_alignment() - unaligned);
  141. pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
  142. pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
  143. pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
  144. ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
  145. pkt_info.return_info = skb;
  146. if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
  147. printk(KERN_ERR
  148. "%s: Error allocating RX Ring\n", dev->name);
  149. break;
  150. }
  151. skb_reserve(skb, ETH_HW_IP_ALIGN);
  152. }
  153. /*
  154. * If RX ring is empty of SKB, set a timer to try allocating
  155. * again at a later time.
  156. */
  157. if (mp->rx_desc_count == 0) {
  158. printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
  159. mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
  160. add_timer(&mp->timeout);
  161. }
  162. }
  163. /*
  164. * mv643xx_eth_rx_refill_descs_timer_wrapper
  165. *
  166. * Timer routine to wake up RX queue filling task. This function is
  167. * used only in case the RX queue is empty, and all alloc_skb has
  168. * failed (due to out of memory event).
  169. *
  170. * Input : pointer to ethernet interface network device structure
  171. * Output : N/A
  172. */
  173. static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
  174. {
  175. mv643xx_eth_rx_refill_descs((struct net_device *)data);
  176. }
  177. /*
  178. * mv643xx_eth_update_mac_address
  179. *
  180. * Update the MAC address of the port in the address table
  181. *
  182. * Input : pointer to ethernet interface network device structure
  183. * Output : N/A
  184. */
  185. static void mv643xx_eth_update_mac_address(struct net_device *dev)
  186. {
  187. struct mv643xx_private *mp = netdev_priv(dev);
  188. unsigned int port_num = mp->port_num;
  189. eth_port_init_mac_tables(port_num);
  190. eth_port_uc_addr_set(port_num, dev->dev_addr);
  191. }
  192. /*
  193. * mv643xx_eth_set_rx_mode
  194. *
  195. * Change from promiscuos to regular rx mode
  196. *
  197. * Input : pointer to ethernet interface network device structure
  198. * Output : N/A
  199. */
  200. static void mv643xx_eth_set_rx_mode(struct net_device *dev)
  201. {
  202. struct mv643xx_private *mp = netdev_priv(dev);
  203. u32 config_reg;
  204. config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num));
  205. if (dev->flags & IFF_PROMISC)
  206. config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
  207. else
  208. config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
  209. mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg);
  210. eth_port_set_multicast_list(dev);
  211. }
  212. /*
  213. * mv643xx_eth_set_mac_address
  214. *
  215. * Change the interface's mac address.
  216. * No special hardware thing should be done because interface is always
  217. * put in promiscuous mode.
  218. *
  219. * Input : pointer to ethernet interface network device structure and
  220. * a pointer to the designated entry to be added to the cache.
  221. * Output : zero upon success, negative upon failure
  222. */
  223. static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
  224. {
  225. int i;
  226. for (i = 0; i < 6; i++)
  227. /* +2 is for the offset of the HW addr type */
  228. dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
  229. mv643xx_eth_update_mac_address(dev);
  230. return 0;
  231. }
  232. /*
  233. * mv643xx_eth_tx_timeout
  234. *
  235. * Called upon a timeout on transmitting a packet
  236. *
  237. * Input : pointer to ethernet interface network device structure.
  238. * Output : N/A
  239. */
  240. static void mv643xx_eth_tx_timeout(struct net_device *dev)
  241. {
  242. struct mv643xx_private *mp = netdev_priv(dev);
  243. printk(KERN_INFO "%s: TX timeout ", dev->name);
  244. /* Do the reset outside of interrupt context */
  245. schedule_work(&mp->tx_timeout_task);
  246. }
  247. /*
  248. * mv643xx_eth_tx_timeout_task
  249. *
  250. * Actual routine to reset the adapter when a timeout on Tx has occurred
  251. */
  252. static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
  253. {
  254. struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
  255. tx_timeout_task);
  256. struct net_device *dev = mp->mii.dev; /* yuck */
  257. if (!netif_running(dev))
  258. return;
  259. netif_stop_queue(dev);
  260. eth_port_reset(mp->port_num);
  261. eth_port_start(dev);
  262. if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
  263. netif_wake_queue(dev);
  264. }
  265. /**
  266. * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
  267. *
  268. * If force is non-zero, frees uncompleted descriptors as well
  269. */
  270. int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
  271. {
  272. struct mv643xx_private *mp = netdev_priv(dev);
  273. struct eth_tx_desc *desc;
  274. u32 cmd_sts;
  275. struct sk_buff *skb;
  276. unsigned long flags;
  277. int tx_index;
  278. dma_addr_t addr;
  279. int count;
  280. int released = 0;
  281. while (mp->tx_desc_count > 0) {
  282. spin_lock_irqsave(&mp->lock, flags);
  283. /* tx_desc_count might have changed before acquiring the lock */
  284. if (mp->tx_desc_count <= 0) {
  285. spin_unlock_irqrestore(&mp->lock, flags);
  286. return released;
  287. }
  288. tx_index = mp->tx_used_desc_q;
  289. desc = &mp->p_tx_desc_area[tx_index];
  290. cmd_sts = desc->cmd_sts;
  291. if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
  292. spin_unlock_irqrestore(&mp->lock, flags);
  293. return released;
  294. }
  295. mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
  296. mp->tx_desc_count--;
  297. addr = desc->buf_ptr;
  298. count = desc->byte_cnt;
  299. skb = mp->tx_skb[tx_index];
  300. if (skb)
  301. mp->tx_skb[tx_index] = NULL;
  302. if (cmd_sts & ETH_ERROR_SUMMARY) {
  303. printk("%s: Error in TX\n", dev->name);
  304. mp->stats.tx_errors++;
  305. }
  306. spin_unlock_irqrestore(&mp->lock, flags);
  307. if (cmd_sts & ETH_TX_FIRST_DESC)
  308. dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
  309. else
  310. dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
  311. if (skb)
  312. dev_kfree_skb_irq(skb);
  313. released = 1;
  314. }
  315. return released;
  316. }
  317. static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
  318. {
  319. struct mv643xx_private *mp = netdev_priv(dev);
  320. if (mv643xx_eth_free_tx_descs(dev, 0) &&
  321. mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
  322. netif_wake_queue(dev);
  323. }
  324. static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
  325. {
  326. mv643xx_eth_free_tx_descs(dev, 1);
  327. }
  328. /*
  329. * mv643xx_eth_receive
  330. *
  331. * This function is forward packets that are received from the port's
  332. * queues toward kernel core or FastRoute them to another interface.
  333. *
  334. * Input : dev - a pointer to the required interface
  335. * max - maximum number to receive (0 means unlimted)
  336. *
  337. * Output : number of served packets
  338. */
  339. static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
  340. {
  341. struct mv643xx_private *mp = netdev_priv(dev);
  342. struct net_device_stats *stats = &mp->stats;
  343. unsigned int received_packets = 0;
  344. struct sk_buff *skb;
  345. struct pkt_info pkt_info;
  346. while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
  347. dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
  348. DMA_FROM_DEVICE);
  349. mp->rx_desc_count--;
  350. received_packets++;
  351. /*
  352. * Update statistics.
  353. * Note byte count includes 4 byte CRC count
  354. */
  355. stats->rx_packets++;
  356. stats->rx_bytes += pkt_info.byte_cnt;
  357. skb = pkt_info.return_info;
  358. /*
  359. * In case received a packet without first / last bits on OR
  360. * the error summary bit is on, the packets needs to be dropeed.
  361. */
  362. if (((pkt_info.cmd_sts
  363. & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
  364. (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
  365. || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
  366. stats->rx_dropped++;
  367. if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
  368. ETH_RX_LAST_DESC)) !=
  369. (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
  370. if (net_ratelimit())
  371. printk(KERN_ERR
  372. "%s: Received packet spread "
  373. "on multiple descriptors\n",
  374. dev->name);
  375. }
  376. if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
  377. stats->rx_errors++;
  378. dev_kfree_skb_irq(skb);
  379. } else {
  380. /*
  381. * The -4 is for the CRC in the trailer of the
  382. * received packet
  383. */
  384. skb_put(skb, pkt_info.byte_cnt - 4);
  385. skb->dev = dev;
  386. if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
  387. skb->ip_summed = CHECKSUM_UNNECESSARY;
  388. skb->csum = htons(
  389. (pkt_info.cmd_sts & 0x0007fff8) >> 3);
  390. }
  391. skb->protocol = eth_type_trans(skb, dev);
  392. #ifdef MV643XX_NAPI
  393. netif_receive_skb(skb);
  394. #else
  395. netif_rx(skb);
  396. #endif
  397. }
  398. dev->last_rx = jiffies;
  399. }
  400. mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
  401. return received_packets;
  402. }
  403. /* Set the mv643xx port configuration register for the speed/duplex mode. */
  404. static void mv643xx_eth_update_pscr(struct net_device *dev,
  405. struct ethtool_cmd *ecmd)
  406. {
  407. struct mv643xx_private *mp = netdev_priv(dev);
  408. int port_num = mp->port_num;
  409. u32 o_pscr, n_pscr;
  410. unsigned int queues;
  411. o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
  412. n_pscr = o_pscr;
  413. /* clear speed, duplex and rx buffer size fields */
  414. n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 |
  415. MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
  416. MV643XX_ETH_SET_FULL_DUPLEX_MODE |
  417. MV643XX_ETH_MAX_RX_PACKET_MASK);
  418. if (ecmd->duplex == DUPLEX_FULL)
  419. n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE;
  420. if (ecmd->speed == SPEED_1000)
  421. n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
  422. MV643XX_ETH_MAX_RX_PACKET_9700BYTE;
  423. else {
  424. if (ecmd->speed == SPEED_100)
  425. n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100;
  426. n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE;
  427. }
  428. if (n_pscr != o_pscr) {
  429. if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0)
  430. mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
  431. n_pscr);
  432. else {
  433. queues = mv643xx_eth_port_disable_tx(port_num);
  434. o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
  435. mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
  436. o_pscr);
  437. mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
  438. n_pscr);
  439. mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
  440. n_pscr);
  441. if (queues)
  442. mv643xx_eth_port_enable_tx(port_num, queues);
  443. }
  444. }
  445. }
  446. /*
  447. * mv643xx_eth_int_handler
  448. *
  449. * Main interrupt handler for the gigbit ethernet ports
  450. *
  451. * Input : irq - irq number (not used)
  452. * dev_id - a pointer to the required interface's data structure
  453. * regs - not used
  454. * Output : N/A
  455. */
  456. static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
  457. {
  458. struct net_device *dev = (struct net_device *)dev_id;
  459. struct mv643xx_private *mp = netdev_priv(dev);
  460. u32 eth_int_cause, eth_int_cause_ext = 0;
  461. unsigned int port_num = mp->port_num;
  462. /* Read interrupt cause registers */
  463. eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
  464. ETH_INT_UNMASK_ALL;
  465. if (eth_int_cause & ETH_INT_CAUSE_EXT) {
  466. eth_int_cause_ext = mv_read(
  467. MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
  468. ETH_INT_UNMASK_ALL_EXT;
  469. mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),
  470. ~eth_int_cause_ext);
  471. }
  472. /* PHY status changed */
  473. if (eth_int_cause_ext & ETH_INT_CAUSE_PHY) {
  474. struct ethtool_cmd cmd;
  475. if (mii_link_ok(&mp->mii)) {
  476. mii_ethtool_gset(&mp->mii, &cmd);
  477. mv643xx_eth_update_pscr(dev, &cmd);
  478. mv643xx_eth_port_enable_tx(port_num,
  479. ETH_TX_QUEUES_ENABLED);
  480. if (!netif_carrier_ok(dev)) {
  481. netif_carrier_on(dev);
  482. if (mp->tx_ring_size - mp->tx_desc_count >=
  483. MAX_DESCS_PER_SKB)
  484. netif_wake_queue(dev);
  485. }
  486. } else if (netif_carrier_ok(dev)) {
  487. netif_stop_queue(dev);
  488. netif_carrier_off(dev);
  489. }
  490. }
  491. #ifdef MV643XX_NAPI
  492. if (eth_int_cause & ETH_INT_CAUSE_RX) {
  493. /* schedule the NAPI poll routine to maintain port */
  494. mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
  495. ETH_INT_MASK_ALL);
  496. /* wait for previous write to complete */
  497. mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
  498. netif_rx_schedule(dev);
  499. }
  500. #else
  501. if (eth_int_cause & ETH_INT_CAUSE_RX)
  502. mv643xx_eth_receive_queue(dev, INT_MAX);
  503. #endif
  504. if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
  505. mv643xx_eth_free_completed_tx_descs(dev);
  506. /*
  507. * If no real interrupt occured, exit.
  508. * This can happen when using gigE interrupt coalescing mechanism.
  509. */
  510. if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
  511. return IRQ_NONE;
  512. return IRQ_HANDLED;
  513. }
  514. #ifdef MV643XX_COAL
  515. /*
  516. * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
  517. *
  518. * DESCRIPTION:
  519. * This routine sets the RX coalescing interrupt mechanism parameter.
  520. * This parameter is a timeout counter, that counts in 64 t_clk
  521. * chunks ; that when timeout event occurs a maskable interrupt
  522. * occurs.
  523. * The parameter is calculated using the tClk of the MV-643xx chip
  524. * , and the required delay of the interrupt in usec.
  525. *
  526. * INPUT:
  527. * unsigned int eth_port_num Ethernet port number
  528. * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
  529. * unsigned int delay Delay in usec
  530. *
  531. * OUTPUT:
  532. * Interrupt coalescing mechanism value is set in MV-643xx chip.
  533. *
  534. * RETURN:
  535. * The interrupt coalescing value set in the gigE port.
  536. *
  537. */
  538. static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
  539. unsigned int t_clk, unsigned int delay)
  540. {
  541. unsigned int coal = ((t_clk / 1000000) * delay) / 64;
  542. /* Set RX Coalescing mechanism */
  543. mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
  544. ((coal & 0x3fff) << 8) |
  545. (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
  546. & 0xffc000ff));
  547. return coal;
  548. }
  549. #endif
  550. /*
  551. * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
  552. *
  553. * DESCRIPTION:
  554. * This routine sets the TX coalescing interrupt mechanism parameter.
  555. * This parameter is a timeout counter, that counts in 64 t_clk
  556. * chunks ; that when timeout event occurs a maskable interrupt
  557. * occurs.
  558. * The parameter is calculated using the t_cLK frequency of the
  559. * MV-643xx chip and the required delay in the interrupt in uSec
  560. *
  561. * INPUT:
  562. * unsigned int eth_port_num Ethernet port number
  563. * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
  564. * unsigned int delay Delay in uSeconds
  565. *
  566. * OUTPUT:
  567. * Interrupt coalescing mechanism value is set in MV-643xx chip.
  568. *
  569. * RETURN:
  570. * The interrupt coalescing value set in the gigE port.
  571. *
  572. */
  573. static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
  574. unsigned int t_clk, unsigned int delay)
  575. {
  576. unsigned int coal;
  577. coal = ((t_clk / 1000000) * delay) / 64;
  578. /* Set TX Coalescing mechanism */
  579. mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
  580. coal << 4);
  581. return coal;
  582. }
  583. /*
  584. * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
  585. *
  586. * DESCRIPTION:
  587. * This function prepares a Rx chained list of descriptors and packet
  588. * buffers in a form of a ring. The routine must be called after port
  589. * initialization routine and before port start routine.
  590. * The Ethernet SDMA engine uses CPU bus addresses to access the various
  591. * devices in the system (i.e. DRAM). This function uses the ethernet
  592. * struct 'virtual to physical' routine (set by the user) to set the ring
  593. * with physical addresses.
  594. *
  595. * INPUT:
  596. * struct mv643xx_private *mp Ethernet Port Control srtuct.
  597. *
  598. * OUTPUT:
  599. * The routine updates the Ethernet port control struct with information
  600. * regarding the Rx descriptors and buffers.
  601. *
  602. * RETURN:
  603. * None.
  604. */
  605. static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
  606. {
  607. volatile struct eth_rx_desc *p_rx_desc;
  608. int rx_desc_num = mp->rx_ring_size;
  609. int i;
  610. /* initialize the next_desc_ptr links in the Rx descriptors ring */
  611. p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
  612. for (i = 0; i < rx_desc_num; i++) {
  613. p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
  614. ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
  615. }
  616. /* Save Rx desc pointer to driver struct. */
  617. mp->rx_curr_desc_q = 0;
  618. mp->rx_used_desc_q = 0;
  619. mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
  620. }
  621. /*
  622. * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
  623. *
  624. * DESCRIPTION:
  625. * This function prepares a Tx chained list of descriptors and packet
  626. * buffers in a form of a ring. The routine must be called after port
  627. * initialization routine and before port start routine.
  628. * The Ethernet SDMA engine uses CPU bus addresses to access the various
  629. * devices in the system (i.e. DRAM). This function uses the ethernet
  630. * struct 'virtual to physical' routine (set by the user) to set the ring
  631. * with physical addresses.
  632. *
  633. * INPUT:
  634. * struct mv643xx_private *mp Ethernet Port Control srtuct.
  635. *
  636. * OUTPUT:
  637. * The routine updates the Ethernet port control struct with information
  638. * regarding the Tx descriptors and buffers.
  639. *
  640. * RETURN:
  641. * None.
  642. */
  643. static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
  644. {
  645. int tx_desc_num = mp->tx_ring_size;
  646. struct eth_tx_desc *p_tx_desc;
  647. int i;
  648. /* Initialize the next_desc_ptr links in the Tx descriptors ring */
  649. p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
  650. for (i = 0; i < tx_desc_num; i++) {
  651. p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
  652. ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
  653. }
  654. mp->tx_curr_desc_q = 0;
  655. mp->tx_used_desc_q = 0;
  656. mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
  657. }
  658. static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  659. {
  660. struct mv643xx_private *mp = netdev_priv(dev);
  661. int err;
  662. spin_lock_irq(&mp->lock);
  663. err = mii_ethtool_sset(&mp->mii, cmd);
  664. spin_unlock_irq(&mp->lock);
  665. return err;
  666. }
  667. static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  668. {
  669. struct mv643xx_private *mp = netdev_priv(dev);
  670. int err;
  671. spin_lock_irq(&mp->lock);
  672. err = mii_ethtool_gset(&mp->mii, cmd);
  673. spin_unlock_irq(&mp->lock);
  674. /* The PHY may support 1000baseT_Half, but the mv643xx does not */
  675. cmd->supported &= ~SUPPORTED_1000baseT_Half;
  676. cmd->advertising &= ~ADVERTISED_1000baseT_Half;
  677. return err;
  678. }
  679. /*
  680. * mv643xx_eth_open
  681. *
  682. * This function is called when openning the network device. The function
  683. * should initialize all the hardware, initialize cyclic Rx/Tx
  684. * descriptors chain and buffers and allocate an IRQ to the network
  685. * device.
  686. *
  687. * Input : a pointer to the network device structure
  688. *
  689. * Output : zero of success , nonzero if fails.
  690. */
  691. static int mv643xx_eth_open(struct net_device *dev)
  692. {
  693. struct mv643xx_private *mp = netdev_priv(dev);
  694. unsigned int port_num = mp->port_num;
  695. unsigned int size;
  696. int err;
  697. /* Clear any pending ethernet port interrupts */
  698. mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
  699. mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
  700. /* wait for previous write to complete */
  701. mv_read (MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num));
  702. err = request_irq(dev->irq, mv643xx_eth_int_handler,
  703. IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
  704. if (err) {
  705. printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
  706. port_num);
  707. return -EAGAIN;
  708. }
  709. eth_port_init(mp);
  710. memset(&mp->timeout, 0, sizeof(struct timer_list));
  711. mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
  712. mp->timeout.data = (unsigned long)dev;
  713. /* Allocate RX and TX skb rings */
  714. mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
  715. GFP_KERNEL);
  716. if (!mp->rx_skb) {
  717. printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
  718. err = -ENOMEM;
  719. goto out_free_irq;
  720. }
  721. mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
  722. GFP_KERNEL);
  723. if (!mp->tx_skb) {
  724. printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
  725. err = -ENOMEM;
  726. goto out_free_rx_skb;
  727. }
  728. /* Allocate TX ring */
  729. mp->tx_desc_count = 0;
  730. size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
  731. mp->tx_desc_area_size = size;
  732. if (mp->tx_sram_size) {
  733. mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
  734. mp->tx_sram_size);
  735. mp->tx_desc_dma = mp->tx_sram_addr;
  736. } else
  737. mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
  738. &mp->tx_desc_dma,
  739. GFP_KERNEL);
  740. if (!mp->p_tx_desc_area) {
  741. printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
  742. dev->name, size);
  743. err = -ENOMEM;
  744. goto out_free_tx_skb;
  745. }
  746. BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
  747. memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
  748. ether_init_tx_desc_ring(mp);
  749. /* Allocate RX ring */
  750. mp->rx_desc_count = 0;
  751. size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
  752. mp->rx_desc_area_size = size;
  753. if (mp->rx_sram_size) {
  754. mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
  755. mp->rx_sram_size);
  756. mp->rx_desc_dma = mp->rx_sram_addr;
  757. } else
  758. mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
  759. &mp->rx_desc_dma,
  760. GFP_KERNEL);
  761. if (!mp->p_rx_desc_area) {
  762. printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
  763. dev->name, size);
  764. printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
  765. dev->name);
  766. if (mp->rx_sram_size)
  767. iounmap(mp->p_tx_desc_area);
  768. else
  769. dma_free_coherent(NULL, mp->tx_desc_area_size,
  770. mp->p_tx_desc_area, mp->tx_desc_dma);
  771. err = -ENOMEM;
  772. goto out_free_tx_skb;
  773. }
  774. memset((void *)mp->p_rx_desc_area, 0, size);
  775. ether_init_rx_desc_ring(mp);
  776. mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
  777. eth_port_start(dev);
  778. /* Interrupt Coalescing */
  779. #ifdef MV643XX_COAL
  780. mp->rx_int_coal =
  781. eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
  782. #endif
  783. mp->tx_int_coal =
  784. eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
  785. /* Unmask phy and link status changes interrupts */
  786. mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
  787. ETH_INT_UNMASK_ALL_EXT);
  788. /* Unmask RX buffer and TX end interrupt */
  789. mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
  790. return 0;
  791. out_free_tx_skb:
  792. kfree(mp->tx_skb);
  793. out_free_rx_skb:
  794. kfree(mp->rx_skb);
  795. out_free_irq:
  796. free_irq(dev->irq, dev);
  797. return err;
  798. }
  799. static void mv643xx_eth_free_tx_rings(struct net_device *dev)
  800. {
  801. struct mv643xx_private *mp = netdev_priv(dev);
  802. /* Stop Tx Queues */
  803. mv643xx_eth_port_disable_tx(mp->port_num);
  804. /* Free outstanding skb's on TX ring */
  805. mv643xx_eth_free_all_tx_descs(dev);
  806. BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
  807. /* Free TX ring */
  808. if (mp->tx_sram_size)
  809. iounmap(mp->p_tx_desc_area);
  810. else
  811. dma_free_coherent(NULL, mp->tx_desc_area_size,
  812. mp->p_tx_desc_area, mp->tx_desc_dma);
  813. }
  814. static void mv643xx_eth_free_rx_rings(struct net_device *dev)
  815. {
  816. struct mv643xx_private *mp = netdev_priv(dev);
  817. unsigned int port_num = mp->port_num;
  818. int curr;
  819. /* Stop RX Queues */
  820. mv643xx_eth_port_disable_rx(port_num);
  821. /* Free preallocated skb's on RX rings */
  822. for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
  823. if (mp->rx_skb[curr]) {
  824. dev_kfree_skb(mp->rx_skb[curr]);
  825. mp->rx_desc_count--;
  826. }
  827. }
  828. if (mp->rx_desc_count)
  829. printk(KERN_ERR
  830. "%s: Error in freeing Rx Ring. %d skb's still"
  831. " stuck in RX Ring - ignoring them\n", dev->name,
  832. mp->rx_desc_count);
  833. /* Free RX ring */
  834. if (mp->rx_sram_size)
  835. iounmap(mp->p_rx_desc_area);
  836. else
  837. dma_free_coherent(NULL, mp->rx_desc_area_size,
  838. mp->p_rx_desc_area, mp->rx_desc_dma);
  839. }
  840. /*
  841. * mv643xx_eth_stop
  842. *
  843. * This function is used when closing the network device.
  844. * It updates the hardware,
  845. * release all memory that holds buffers and descriptors and release the IRQ.
  846. * Input : a pointer to the device structure
  847. * Output : zero if success , nonzero if fails
  848. */
  849. static int mv643xx_eth_stop(struct net_device *dev)
  850. {
  851. struct mv643xx_private *mp = netdev_priv(dev);
  852. unsigned int port_num = mp->port_num;
  853. /* Mask all interrupts on ethernet port */
  854. mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
  855. /* wait for previous write to complete */
  856. mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
  857. #ifdef MV643XX_NAPI
  858. netif_poll_disable(dev);
  859. #endif
  860. netif_carrier_off(dev);
  861. netif_stop_queue(dev);
  862. eth_port_reset(mp->port_num);
  863. mv643xx_eth_free_tx_rings(dev);
  864. mv643xx_eth_free_rx_rings(dev);
  865. #ifdef MV643XX_NAPI
  866. netif_poll_enable(dev);
  867. #endif
  868. free_irq(dev->irq, dev);
  869. return 0;
  870. }
  871. #ifdef MV643XX_NAPI
  872. /*
  873. * mv643xx_poll
  874. *
  875. * This function is used in case of NAPI
  876. */
  877. static int mv643xx_poll(struct net_device *dev, int *budget)
  878. {
  879. struct mv643xx_private *mp = netdev_priv(dev);
  880. int done = 1, orig_budget, work_done;
  881. unsigned int port_num = mp->port_num;
  882. #ifdef MV643XX_TX_FAST_REFILL
  883. if (++mp->tx_clean_threshold > 5) {
  884. mv643xx_eth_free_completed_tx_descs(dev);
  885. mp->tx_clean_threshold = 0;
  886. }
  887. #endif
  888. if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
  889. != (u32) mp->rx_used_desc_q) {
  890. orig_budget = *budget;
  891. if (orig_budget > dev->quota)
  892. orig_budget = dev->quota;
  893. work_done = mv643xx_eth_receive_queue(dev, orig_budget);
  894. *budget -= work_done;
  895. dev->quota -= work_done;
  896. if (work_done >= orig_budget)
  897. done = 0;
  898. }
  899. if (done) {
  900. netif_rx_complete(dev);
  901. mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
  902. mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
  903. mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
  904. ETH_INT_UNMASK_ALL);
  905. }
  906. return done ? 0 : 1;
  907. }
  908. #endif
  909. /**
  910. * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
  911. *
  912. * Hardware can't handle unaligned fragments smaller than 9 bytes.
  913. * This helper function detects that case.
  914. */
  915. static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
  916. {
  917. unsigned int frag;
  918. skb_frag_t *fragp;
  919. for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
  920. fragp = &skb_shinfo(skb)->frags[frag];
  921. if (fragp->size <= 8 && fragp->page_offset & 0x7)
  922. return 1;
  923. }
  924. return 0;
  925. }
  926. /**
  927. * eth_alloc_tx_desc_index - return the index of the next available tx desc
  928. */
  929. static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
  930. {
  931. int tx_desc_curr;
  932. BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
  933. tx_desc_curr = mp->tx_curr_desc_q;
  934. mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
  935. BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
  936. return tx_desc_curr;
  937. }
  938. /**
  939. * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
  940. *
  941. * Ensure the data for each fragment to be transmitted is mapped properly,
  942. * then fill in descriptors in the tx hw queue.
  943. */
  944. static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
  945. struct sk_buff *skb)
  946. {
  947. int frag;
  948. int tx_index;
  949. struct eth_tx_desc *desc;
  950. for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
  951. skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
  952. tx_index = eth_alloc_tx_desc_index(mp);
  953. desc = &mp->p_tx_desc_area[tx_index];
  954. desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
  955. /* Last Frag enables interrupt and frees the skb */
  956. if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
  957. desc->cmd_sts |= ETH_ZERO_PADDING |
  958. ETH_TX_LAST_DESC |
  959. ETH_TX_ENABLE_INTERRUPT;
  960. mp->tx_skb[tx_index] = skb;
  961. } else
  962. mp->tx_skb[tx_index] = NULL;
  963. desc = &mp->p_tx_desc_area[tx_index];
  964. desc->l4i_chk = 0;
  965. desc->byte_cnt = this_frag->size;
  966. desc->buf_ptr = dma_map_page(NULL, this_frag->page,
  967. this_frag->page_offset,
  968. this_frag->size,
  969. DMA_TO_DEVICE);
  970. }
  971. }
  972. /**
  973. * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
  974. *
  975. * Ensure the data for an skb to be transmitted is mapped properly,
  976. * then fill in descriptors in the tx hw queue and start the hardware.
  977. */
  978. static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
  979. struct sk_buff *skb)
  980. {
  981. int tx_index;
  982. struct eth_tx_desc *desc;
  983. u32 cmd_sts;
  984. int length;
  985. int nr_frags = skb_shinfo(skb)->nr_frags;
  986. cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
  987. tx_index = eth_alloc_tx_desc_index(mp);
  988. desc = &mp->p_tx_desc_area[tx_index];
  989. if (nr_frags) {
  990. eth_tx_fill_frag_descs(mp, skb);
  991. length = skb_headlen(skb);
  992. mp->tx_skb[tx_index] = NULL;
  993. } else {
  994. cmd_sts |= ETH_ZERO_PADDING |
  995. ETH_TX_LAST_DESC |
  996. ETH_TX_ENABLE_INTERRUPT;
  997. length = skb->len;
  998. mp->tx_skb[tx_index] = skb;
  999. }
  1000. desc->byte_cnt = length;
  1001. desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
  1002. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1003. BUG_ON(skb->protocol != ETH_P_IP);
  1004. cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
  1005. ETH_GEN_IP_V_4_CHECKSUM |
  1006. skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
  1007. switch (skb->nh.iph->protocol) {
  1008. case IPPROTO_UDP:
  1009. cmd_sts |= ETH_UDP_FRAME;
  1010. desc->l4i_chk = skb->h.uh->check;
  1011. break;
  1012. case IPPROTO_TCP:
  1013. desc->l4i_chk = skb->h.th->check;
  1014. break;
  1015. default:
  1016. BUG();
  1017. }
  1018. } else {
  1019. /* Errata BTS #50, IHL must be 5 if no HW checksum */
  1020. cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
  1021. desc->l4i_chk = 0;
  1022. }
  1023. /* ensure all other descriptors are written before first cmd_sts */
  1024. wmb();
  1025. desc->cmd_sts = cmd_sts;
  1026. /* ensure all descriptors are written before poking hardware */
  1027. wmb();
  1028. mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
  1029. mp->tx_desc_count += nr_frags + 1;
  1030. }
  1031. /**
  1032. * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
  1033. *
  1034. */
  1035. static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1036. {
  1037. struct mv643xx_private *mp = netdev_priv(dev);
  1038. struct net_device_stats *stats = &mp->stats;
  1039. unsigned long flags;
  1040. BUG_ON(netif_queue_stopped(dev));
  1041. BUG_ON(skb == NULL);
  1042. if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
  1043. printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
  1044. netif_stop_queue(dev);
  1045. return 1;
  1046. }
  1047. if (has_tiny_unaligned_frags(skb)) {
  1048. if (__skb_linearize(skb)) {
  1049. stats->tx_dropped++;
  1050. printk(KERN_DEBUG "%s: failed to linearize tiny "
  1051. "unaligned fragment\n", dev->name);
  1052. return 1;
  1053. }
  1054. }
  1055. spin_lock_irqsave(&mp->lock, flags);
  1056. eth_tx_submit_descs_for_skb(mp, skb);
  1057. stats->tx_bytes = skb->len;
  1058. stats->tx_packets++;
  1059. dev->trans_start = jiffies;
  1060. if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
  1061. netif_stop_queue(dev);
  1062. spin_unlock_irqrestore(&mp->lock, flags);
  1063. return 0; /* success */
  1064. }
  1065. /*
  1066. * mv643xx_eth_get_stats
  1067. *
  1068. * Returns a pointer to the interface statistics.
  1069. *
  1070. * Input : dev - a pointer to the required interface
  1071. *
  1072. * Output : a pointer to the interface's statistics
  1073. */
  1074. static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
  1075. {
  1076. struct mv643xx_private *mp = netdev_priv(dev);
  1077. return &mp->stats;
  1078. }
  1079. #ifdef CONFIG_NET_POLL_CONTROLLER
  1080. static void mv643xx_netpoll(struct net_device *netdev)
  1081. {
  1082. struct mv643xx_private *mp = netdev_priv(netdev);
  1083. int port_num = mp->port_num;
  1084. mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
  1085. /* wait for previous write to complete */
  1086. mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
  1087. mv643xx_eth_int_handler(netdev->irq, netdev);
  1088. mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
  1089. }
  1090. #endif
  1091. static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
  1092. int speed, int duplex,
  1093. struct ethtool_cmd *cmd)
  1094. {
  1095. struct mv643xx_private *mp = netdev_priv(dev);
  1096. memset(cmd, 0, sizeof(*cmd));
  1097. cmd->port = PORT_MII;
  1098. cmd->transceiver = XCVR_INTERNAL;
  1099. cmd->phy_address = phy_address;
  1100. if (speed == 0) {
  1101. cmd->autoneg = AUTONEG_ENABLE;
  1102. /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
  1103. cmd->speed = SPEED_100;
  1104. cmd->advertising = ADVERTISED_10baseT_Half |
  1105. ADVERTISED_10baseT_Full |
  1106. ADVERTISED_100baseT_Half |
  1107. ADVERTISED_100baseT_Full;
  1108. if (mp->mii.supports_gmii)
  1109. cmd->advertising |= ADVERTISED_1000baseT_Full;
  1110. } else {
  1111. cmd->autoneg = AUTONEG_DISABLE;
  1112. cmd->speed = speed;
  1113. cmd->duplex = duplex;
  1114. }
  1115. }
  1116. /*/
  1117. * mv643xx_eth_probe
  1118. *
  1119. * First function called after registering the network device.
  1120. * It's purpose is to initialize the device as an ethernet device,
  1121. * fill the ethernet device structure with pointers * to functions,
  1122. * and set the MAC address of the interface
  1123. *
  1124. * Input : struct device *
  1125. * Output : -ENOMEM if failed , 0 if success
  1126. */
  1127. static int mv643xx_eth_probe(struct platform_device *pdev)
  1128. {
  1129. struct mv643xx_eth_platform_data *pd;
  1130. int port_num;
  1131. struct mv643xx_private *mp;
  1132. struct net_device *dev;
  1133. u8 *p;
  1134. struct resource *res;
  1135. int err;
  1136. struct ethtool_cmd cmd;
  1137. int duplex = DUPLEX_HALF;
  1138. int speed = 0; /* default to auto-negotiation */
  1139. pd = pdev->dev.platform_data;
  1140. if (pd == NULL) {
  1141. printk(KERN_ERR "No mv643xx_eth_platform_data\n");
  1142. return -ENODEV;
  1143. }
  1144. dev = alloc_etherdev(sizeof(struct mv643xx_private));
  1145. if (!dev)
  1146. return -ENOMEM;
  1147. platform_set_drvdata(pdev, dev);
  1148. mp = netdev_priv(dev);
  1149. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1150. BUG_ON(!res);
  1151. dev->irq = res->start;
  1152. dev->open = mv643xx_eth_open;
  1153. dev->stop = mv643xx_eth_stop;
  1154. dev->hard_start_xmit = mv643xx_eth_start_xmit;
  1155. dev->get_stats = mv643xx_eth_get_stats;
  1156. dev->set_mac_address = mv643xx_eth_set_mac_address;
  1157. dev->set_multicast_list = mv643xx_eth_set_rx_mode;
  1158. /* No need to Tx Timeout */
  1159. dev->tx_timeout = mv643xx_eth_tx_timeout;
  1160. #ifdef MV643XX_NAPI
  1161. dev->poll = mv643xx_poll;
  1162. dev->weight = 64;
  1163. #endif
  1164. #ifdef CONFIG_NET_POLL_CONTROLLER
  1165. dev->poll_controller = mv643xx_netpoll;
  1166. #endif
  1167. dev->watchdog_timeo = 2 * HZ;
  1168. dev->tx_queue_len = mp->tx_ring_size;
  1169. dev->base_addr = 0;
  1170. dev->change_mtu = mv643xx_eth_change_mtu;
  1171. dev->do_ioctl = mv643xx_eth_do_ioctl;
  1172. SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
  1173. #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
  1174. #ifdef MAX_SKB_FRAGS
  1175. /*
  1176. * Zero copy can only work if we use Discovery II memory. Else, we will
  1177. * have to map the buffers to ISA memory which is only 16 MB
  1178. */
  1179. dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
  1180. #endif
  1181. #endif
  1182. /* Configure the timeout task */
  1183. INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
  1184. spin_lock_init(&mp->lock);
  1185. port_num = mp->port_num = pd->port_number;
  1186. /* set default config values */
  1187. eth_port_uc_addr_get(dev, dev->dev_addr);
  1188. mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
  1189. mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
  1190. if (is_valid_ether_addr(pd->mac_addr))
  1191. memcpy(dev->dev_addr, pd->mac_addr, 6);
  1192. if (pd->phy_addr || pd->force_phy_addr)
  1193. ethernet_phy_set(port_num, pd->phy_addr);
  1194. if (pd->rx_queue_size)
  1195. mp->rx_ring_size = pd->rx_queue_size;
  1196. if (pd->tx_queue_size)
  1197. mp->tx_ring_size = pd->tx_queue_size;
  1198. if (pd->tx_sram_size) {
  1199. mp->tx_sram_size = pd->tx_sram_size;
  1200. mp->tx_sram_addr = pd->tx_sram_addr;
  1201. }
  1202. if (pd->rx_sram_size) {
  1203. mp->rx_sram_size = pd->rx_sram_size;
  1204. mp->rx_sram_addr = pd->rx_sram_addr;
  1205. }
  1206. duplex = pd->duplex;
  1207. speed = pd->speed;
  1208. /* Hook up MII support for ethtool */
  1209. mp->mii.dev = dev;
  1210. mp->mii.mdio_read = mv643xx_mdio_read;
  1211. mp->mii.mdio_write = mv643xx_mdio_write;
  1212. mp->mii.phy_id = ethernet_phy_get(port_num);
  1213. mp->mii.phy_id_mask = 0x3f;
  1214. mp->mii.reg_num_mask = 0x1f;
  1215. err = ethernet_phy_detect(port_num);
  1216. if (err) {
  1217. pr_debug("MV643xx ethernet port %d: "
  1218. "No PHY detected at addr %d\n",
  1219. port_num, ethernet_phy_get(port_num));
  1220. goto out;
  1221. }
  1222. ethernet_phy_reset(port_num);
  1223. mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
  1224. mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
  1225. mv643xx_eth_update_pscr(dev, &cmd);
  1226. mv643xx_set_settings(dev, &cmd);
  1227. SET_MODULE_OWNER(dev);
  1228. SET_NETDEV_DEV(dev, &pdev->dev);
  1229. err = register_netdev(dev);
  1230. if (err)
  1231. goto out;
  1232. p = dev->dev_addr;
  1233. printk(KERN_NOTICE
  1234. "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
  1235. dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
  1236. if (dev->features & NETIF_F_SG)
  1237. printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
  1238. if (dev->features & NETIF_F_IP_CSUM)
  1239. printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
  1240. dev->name);
  1241. #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
  1242. printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
  1243. #endif
  1244. #ifdef MV643XX_COAL
  1245. printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
  1246. dev->name);
  1247. #endif
  1248. #ifdef MV643XX_NAPI
  1249. printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
  1250. #endif
  1251. if (mp->tx_sram_size > 0)
  1252. printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
  1253. return 0;
  1254. out:
  1255. free_netdev(dev);
  1256. return err;
  1257. }
  1258. static int mv643xx_eth_remove(struct platform_device *pdev)
  1259. {
  1260. struct net_device *dev = platform_get_drvdata(pdev);
  1261. unregister_netdev(dev);
  1262. flush_scheduled_work();
  1263. free_netdev(dev);
  1264. platform_set_drvdata(pdev, NULL);
  1265. return 0;
  1266. }
  1267. static int mv643xx_eth_shared_probe(struct platform_device *pdev)
  1268. {
  1269. struct resource *res;
  1270. printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
  1271. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1272. if (res == NULL)
  1273. return -ENODEV;
  1274. mv643xx_eth_shared_base = ioremap(res->start,
  1275. MV643XX_ETH_SHARED_REGS_SIZE);
  1276. if (mv643xx_eth_shared_base == NULL)
  1277. return -ENOMEM;
  1278. return 0;
  1279. }
  1280. static int mv643xx_eth_shared_remove(struct platform_device *pdev)
  1281. {
  1282. iounmap(mv643xx_eth_shared_base);
  1283. mv643xx_eth_shared_base = NULL;
  1284. return 0;
  1285. }
  1286. static void mv643xx_eth_shutdown(struct platform_device *pdev)
  1287. {
  1288. struct net_device *dev = platform_get_drvdata(pdev);
  1289. struct mv643xx_private *mp = netdev_priv(dev);
  1290. unsigned int port_num = mp->port_num;
  1291. /* Mask all interrupts on ethernet port */
  1292. mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
  1293. mv_read (MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
  1294. eth_port_reset(port_num);
  1295. }
  1296. static struct platform_driver mv643xx_eth_driver = {
  1297. .probe = mv643xx_eth_probe,
  1298. .remove = mv643xx_eth_remove,
  1299. .shutdown = mv643xx_eth_shutdown,
  1300. .driver = {
  1301. .name = MV643XX_ETH_NAME,
  1302. },
  1303. };
  1304. static struct platform_driver mv643xx_eth_shared_driver = {
  1305. .probe = mv643xx_eth_shared_probe,
  1306. .remove = mv643xx_eth_shared_remove,
  1307. .driver = {
  1308. .name = MV643XX_ETH_SHARED_NAME,
  1309. },
  1310. };
  1311. /*
  1312. * mv643xx_init_module
  1313. *
  1314. * Registers the network drivers into the Linux kernel
  1315. *
  1316. * Input : N/A
  1317. *
  1318. * Output : N/A
  1319. */
  1320. static int __init mv643xx_init_module(void)
  1321. {
  1322. int rc;
  1323. rc = platform_driver_register(&mv643xx_eth_shared_driver);
  1324. if (!rc) {
  1325. rc = platform_driver_register(&mv643xx_eth_driver);
  1326. if (rc)
  1327. platform_driver_unregister(&mv643xx_eth_shared_driver);
  1328. }
  1329. return rc;
  1330. }
  1331. /*
  1332. * mv643xx_cleanup_module
  1333. *
  1334. * Registers the network drivers into the Linux kernel
  1335. *
  1336. * Input : N/A
  1337. *
  1338. * Output : N/A
  1339. */
  1340. static void __exit mv643xx_cleanup_module(void)
  1341. {
  1342. platform_driver_unregister(&mv643xx_eth_driver);
  1343. platform_driver_unregister(&mv643xx_eth_shared_driver);
  1344. }
  1345. module_init(mv643xx_init_module);
  1346. module_exit(mv643xx_cleanup_module);
  1347. MODULE_LICENSE("GPL");
  1348. MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
  1349. " and Dale Farnsworth");
  1350. MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
  1351. /*
  1352. * The second part is the low level driver of the gigE ethernet ports.
  1353. */
  1354. /*
  1355. * Marvell's Gigabit Ethernet controller low level driver
  1356. *
  1357. * DESCRIPTION:
  1358. * This file introduce low level API to Marvell's Gigabit Ethernet
  1359. * controller. This Gigabit Ethernet Controller driver API controls
  1360. * 1) Operations (i.e. port init, start, reset etc').
  1361. * 2) Data flow (i.e. port send, receive etc').
  1362. * Each Gigabit Ethernet port is controlled via
  1363. * struct mv643xx_private.
  1364. * This struct includes user configuration information as well as
  1365. * driver internal data needed for its operations.
  1366. *
  1367. * Supported Features:
  1368. * - This low level driver is OS independent. Allocating memory for
  1369. * the descriptor rings and buffers are not within the scope of
  1370. * this driver.
  1371. * - The user is free from Rx/Tx queue managing.
  1372. * - This low level driver introduce functionality API that enable
  1373. * the to operate Marvell's Gigabit Ethernet Controller in a
  1374. * convenient way.
  1375. * - Simple Gigabit Ethernet port operation API.
  1376. * - Simple Gigabit Ethernet port data flow API.
  1377. * - Data flow and operation API support per queue functionality.
  1378. * - Support cached descriptors for better performance.
  1379. * - Enable access to all four DRAM banks and internal SRAM memory
  1380. * spaces.
  1381. * - PHY access and control API.
  1382. * - Port control register configuration API.
  1383. * - Full control over Unicast and Multicast MAC configurations.
  1384. *
  1385. * Operation flow:
  1386. *
  1387. * Initialization phase
  1388. * This phase complete the initialization of the the
  1389. * mv643xx_private struct.
  1390. * User information regarding port configuration has to be set
  1391. * prior to calling the port initialization routine.
  1392. *
  1393. * In this phase any port Tx/Rx activity is halted, MIB counters
  1394. * are cleared, PHY address is set according to user parameter and
  1395. * access to DRAM and internal SRAM memory spaces.
  1396. *
  1397. * Driver ring initialization
  1398. * Allocating memory for the descriptor rings and buffers is not
  1399. * within the scope of this driver. Thus, the user is required to
  1400. * allocate memory for the descriptors ring and buffers. Those
  1401. * memory parameters are used by the Rx and Tx ring initialization
  1402. * routines in order to curve the descriptor linked list in a form
  1403. * of a ring.
  1404. * Note: Pay special attention to alignment issues when using
  1405. * cached descriptors/buffers. In this phase the driver store
  1406. * information in the mv643xx_private struct regarding each queue
  1407. * ring.
  1408. *
  1409. * Driver start
  1410. * This phase prepares the Ethernet port for Rx and Tx activity.
  1411. * It uses the information stored in the mv643xx_private struct to
  1412. * initialize the various port registers.
  1413. *
  1414. * Data flow:
  1415. * All packet references to/from the driver are done using
  1416. * struct pkt_info.
  1417. * This struct is a unified struct used with Rx and Tx operations.
  1418. * This way the user is not required to be familiar with neither
  1419. * Tx nor Rx descriptors structures.
  1420. * The driver's descriptors rings are management by indexes.
  1421. * Those indexes controls the ring resources and used to indicate
  1422. * a SW resource error:
  1423. * 'current'
  1424. * This index points to the current available resource for use. For
  1425. * example in Rx process this index will point to the descriptor
  1426. * that will be passed to the user upon calling the receive
  1427. * routine. In Tx process, this index will point to the descriptor
  1428. * that will be assigned with the user packet info and transmitted.
  1429. * 'used'
  1430. * This index points to the descriptor that need to restore its
  1431. * resources. For example in Rx process, using the Rx buffer return
  1432. * API will attach the buffer returned in packet info to the
  1433. * descriptor pointed by 'used'. In Tx process, using the Tx
  1434. * descriptor return will merely return the user packet info with
  1435. * the command status of the transmitted buffer pointed by the
  1436. * 'used' index. Nevertheless, it is essential to use this routine
  1437. * to update the 'used' index.
  1438. * 'first'
  1439. * This index supports Tx Scatter-Gather. It points to the first
  1440. * descriptor of a packet assembled of multiple buffers. For
  1441. * example when in middle of Such packet we have a Tx resource
  1442. * error the 'curr' index get the value of 'first' to indicate
  1443. * that the ring returned to its state before trying to transmit
  1444. * this packet.
  1445. *
  1446. * Receive operation:
  1447. * The eth_port_receive API set the packet information struct,
  1448. * passed by the caller, with received information from the
  1449. * 'current' SDMA descriptor.
  1450. * It is the user responsibility to return this resource back
  1451. * to the Rx descriptor ring to enable the reuse of this source.
  1452. * Return Rx resource is done using the eth_rx_return_buff API.
  1453. *
  1454. * Prior to calling the initialization routine eth_port_init() the user
  1455. * must set the following fields under mv643xx_private struct:
  1456. * port_num User Ethernet port number.
  1457. * port_config User port configuration value.
  1458. * port_config_extend User port config extend value.
  1459. * port_sdma_config User port SDMA config value.
  1460. * port_serial_control User port serial control value.
  1461. *
  1462. * This driver data flow is done using the struct pkt_info which
  1463. * is a unified struct for Rx and Tx operations:
  1464. *
  1465. * byte_cnt Tx/Rx descriptor buffer byte count.
  1466. * l4i_chk CPU provided TCP Checksum. For Tx operation
  1467. * only.
  1468. * cmd_sts Tx/Rx descriptor command status.
  1469. * buf_ptr Tx/Rx descriptor buffer pointer.
  1470. * return_info Tx/Rx user resource return information.
  1471. */
  1472. /* PHY routines */
  1473. static int ethernet_phy_get(unsigned int eth_port_num);
  1474. static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
  1475. /* Ethernet Port routines */
  1476. static void eth_port_set_filter_table_entry(int table, unsigned char entry);
  1477. /*
  1478. * eth_port_init - Initialize the Ethernet port driver
  1479. *
  1480. * DESCRIPTION:
  1481. * This function prepares the ethernet port to start its activity:
  1482. * 1) Completes the ethernet port driver struct initialization toward port
  1483. * start routine.
  1484. * 2) Resets the device to a quiescent state in case of warm reboot.
  1485. * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
  1486. * 4) Clean MAC tables. The reset status of those tables is unknown.
  1487. * 5) Set PHY address.
  1488. * Note: Call this routine prior to eth_port_start routine and after
  1489. * setting user values in the user fields of Ethernet port control
  1490. * struct.
  1491. *
  1492. * INPUT:
  1493. * struct mv643xx_private *mp Ethernet port control struct
  1494. *
  1495. * OUTPUT:
  1496. * See description.
  1497. *
  1498. * RETURN:
  1499. * None.
  1500. */
  1501. static void eth_port_init(struct mv643xx_private *mp)
  1502. {
  1503. mp->rx_resource_err = 0;
  1504. eth_port_reset(mp->port_num);
  1505. eth_port_init_mac_tables(mp->port_num);
  1506. }
  1507. /*
  1508. * eth_port_start - Start the Ethernet port activity.
  1509. *
  1510. * DESCRIPTION:
  1511. * This routine prepares the Ethernet port for Rx and Tx activity:
  1512. * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
  1513. * has been initialized a descriptor's ring (using
  1514. * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
  1515. * 2. Initialize and enable the Ethernet configuration port by writing to
  1516. * the port's configuration and command registers.
  1517. * 3. Initialize and enable the SDMA by writing to the SDMA's
  1518. * configuration and command registers. After completing these steps,
  1519. * the ethernet port SDMA can starts to perform Rx and Tx activities.
  1520. *
  1521. * Note: Each Rx and Tx queue descriptor's list must be initialized prior
  1522. * to calling this function (use ether_init_tx_desc_ring for Tx queues
  1523. * and ether_init_rx_desc_ring for Rx queues).
  1524. *
  1525. * INPUT:
  1526. * dev - a pointer to the required interface
  1527. *
  1528. * OUTPUT:
  1529. * Ethernet port is ready to receive and transmit.
  1530. *
  1531. * RETURN:
  1532. * None.
  1533. */
  1534. static void eth_port_start(struct net_device *dev)
  1535. {
  1536. struct mv643xx_private *mp = netdev_priv(dev);
  1537. unsigned int port_num = mp->port_num;
  1538. int tx_curr_desc, rx_curr_desc;
  1539. u32 pscr;
  1540. struct ethtool_cmd ethtool_cmd;
  1541. /* Assignment of Tx CTRP of given queue */
  1542. tx_curr_desc = mp->tx_curr_desc_q;
  1543. mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
  1544. (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
  1545. /* Assignment of Rx CRDP of given queue */
  1546. rx_curr_desc = mp->rx_curr_desc_q;
  1547. mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
  1548. (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
  1549. /* Add the assigned Ethernet address to the port's address table */
  1550. eth_port_uc_addr_set(port_num, dev->dev_addr);
  1551. /* Assign port configuration and command. */
  1552. mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num),
  1553. MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE);
  1554. mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
  1555. MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE);
  1556. pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
  1557. pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS);
  1558. mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
  1559. pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
  1560. MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII |
  1561. MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX |
  1562. MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
  1563. MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED;
  1564. mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
  1565. pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE;
  1566. mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
  1567. /* Assign port SDMA configuration */
  1568. mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
  1569. MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE);
  1570. /* Enable port Rx. */
  1571. mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
  1572. /* Disable port bandwidth limits by clearing MTU register */
  1573. mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
  1574. /* save phy settings across reset */
  1575. mv643xx_get_settings(dev, &ethtool_cmd);
  1576. ethernet_phy_reset(mp->port_num);
  1577. mv643xx_set_settings(dev, &ethtool_cmd);
  1578. }
  1579. /*
  1580. * eth_port_uc_addr_set - This function Set the port Unicast address.
  1581. *
  1582. * DESCRIPTION:
  1583. * This function Set the port Ethernet MAC address.
  1584. *
  1585. * INPUT:
  1586. * unsigned int eth_port_num Port number.
  1587. * char * p_addr Address to be set
  1588. *
  1589. * OUTPUT:
  1590. * Set MAC address low and high registers. also calls
  1591. * eth_port_set_filter_table_entry() to set the unicast
  1592. * table with the proper information.
  1593. *
  1594. * RETURN:
  1595. * N/A.
  1596. *
  1597. */
  1598. static void eth_port_uc_addr_set(unsigned int eth_port_num,
  1599. unsigned char *p_addr)
  1600. {
  1601. unsigned int mac_h;
  1602. unsigned int mac_l;
  1603. int table;
  1604. mac_l = (p_addr[4] << 8) | (p_addr[5]);
  1605. mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
  1606. (p_addr[3] << 0);
  1607. mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
  1608. mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
  1609. /* Accept frames of this address */
  1610. table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num);
  1611. eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
  1612. }
  1613. /*
  1614. * eth_port_uc_addr_get - This function retrieves the port Unicast address
  1615. * (MAC address) from the ethernet hw registers.
  1616. *
  1617. * DESCRIPTION:
  1618. * This function retrieves the port Ethernet MAC address.
  1619. *
  1620. * INPUT:
  1621. * unsigned int eth_port_num Port number.
  1622. * char *MacAddr pointer where the MAC address is stored
  1623. *
  1624. * OUTPUT:
  1625. * Copy the MAC address to the location pointed to by MacAddr
  1626. *
  1627. * RETURN:
  1628. * N/A.
  1629. *
  1630. */
  1631. static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
  1632. {
  1633. struct mv643xx_private *mp = netdev_priv(dev);
  1634. unsigned int mac_h;
  1635. unsigned int mac_l;
  1636. mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
  1637. mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
  1638. p_addr[0] = (mac_h >> 24) & 0xff;
  1639. p_addr[1] = (mac_h >> 16) & 0xff;
  1640. p_addr[2] = (mac_h >> 8) & 0xff;
  1641. p_addr[3] = mac_h & 0xff;
  1642. p_addr[4] = (mac_l >> 8) & 0xff;
  1643. p_addr[5] = mac_l & 0xff;
  1644. }
  1645. /*
  1646. * The entries in each table are indexed by a hash of a packet's MAC
  1647. * address. One bit in each entry determines whether the packet is
  1648. * accepted. There are 4 entries (each 8 bits wide) in each register
  1649. * of the table. The bits in each entry are defined as follows:
  1650. * 0 Accept=1, Drop=0
  1651. * 3-1 Queue (ETH_Q0=0)
  1652. * 7-4 Reserved = 0;
  1653. */
  1654. static void eth_port_set_filter_table_entry(int table, unsigned char entry)
  1655. {
  1656. unsigned int table_reg;
  1657. unsigned int tbl_offset;
  1658. unsigned int reg_offset;
  1659. tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
  1660. reg_offset = entry % 4; /* Entry offset within the register */
  1661. /* Set "accepts frame bit" at specified table entry */
  1662. table_reg = mv_read(table + tbl_offset);
  1663. table_reg |= 0x01 << (8 * reg_offset);
  1664. mv_write(table + tbl_offset, table_reg);
  1665. }
  1666. /*
  1667. * eth_port_mc_addr - Multicast address settings.
  1668. *
  1669. * The MV device supports multicast using two tables:
  1670. * 1) Special Multicast Table for MAC addresses of the form
  1671. * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
  1672. * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
  1673. * Table entries in the DA-Filter table.
  1674. * 2) Other Multicast Table for multicast of another type. A CRC-8bit
  1675. * is used as an index to the Other Multicast Table entries in the
  1676. * DA-Filter table. This function calculates the CRC-8bit value.
  1677. * In either case, eth_port_set_filter_table_entry() is then called
  1678. * to set to set the actual table entry.
  1679. */
  1680. static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
  1681. {
  1682. unsigned int mac_h;
  1683. unsigned int mac_l;
  1684. unsigned char crc_result = 0;
  1685. int table;
  1686. int mac_array[48];
  1687. int crc[8];
  1688. int i;
  1689. if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
  1690. (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
  1691. table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
  1692. (eth_port_num);
  1693. eth_port_set_filter_table_entry(table, p_addr[5]);
  1694. return;
  1695. }
  1696. /* Calculate CRC-8 out of the given address */
  1697. mac_h = (p_addr[0] << 8) | (p_addr[1]);
  1698. mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
  1699. (p_addr[4] << 8) | (p_addr[5] << 0);
  1700. for (i = 0; i < 32; i++)
  1701. mac_array[i] = (mac_l >> i) & 0x1;
  1702. for (i = 32; i < 48; i++)
  1703. mac_array[i] = (mac_h >> (i - 32)) & 0x1;
  1704. crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
  1705. mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
  1706. mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
  1707. mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
  1708. mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
  1709. crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
  1710. mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
  1711. mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
  1712. mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
  1713. mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
  1714. mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
  1715. mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
  1716. crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
  1717. mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
  1718. mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
  1719. mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
  1720. mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
  1721. mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
  1722. crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
  1723. mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
  1724. mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
  1725. mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
  1726. mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
  1727. mac_array[3] ^ mac_array[2] ^ mac_array[1];
  1728. crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
  1729. mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
  1730. mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
  1731. mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
  1732. mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
  1733. mac_array[3] ^ mac_array[2];
  1734. crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
  1735. mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
  1736. mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
  1737. mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
  1738. mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
  1739. mac_array[4] ^ mac_array[3];
  1740. crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
  1741. mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
  1742. mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
  1743. mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
  1744. mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
  1745. mac_array[4];
  1746. crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
  1747. mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
  1748. mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
  1749. mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
  1750. mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
  1751. for (i = 0; i < 8; i++)
  1752. crc_result = crc_result | (crc[i] << i);
  1753. table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
  1754. eth_port_set_filter_table_entry(table, crc_result);
  1755. }
  1756. /*
  1757. * Set the entire multicast list based on dev->mc_list.
  1758. */
  1759. static void eth_port_set_multicast_list(struct net_device *dev)
  1760. {
  1761. struct dev_mc_list *mc_list;
  1762. int i;
  1763. int table_index;
  1764. struct mv643xx_private *mp = netdev_priv(dev);
  1765. unsigned int eth_port_num = mp->port_num;
  1766. /* If the device is in promiscuous mode or in all multicast mode,
  1767. * we will fully populate both multicast tables with accept.
  1768. * This is guaranteed to yield a match on all multicast addresses...
  1769. */
  1770. if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
  1771. for (table_index = 0; table_index <= 0xFC; table_index += 4) {
  1772. /* Set all entries in DA filter special multicast
  1773. * table (Ex_dFSMT)
  1774. * Set for ETH_Q0 for now
  1775. * Bits
  1776. * 0 Accept=1, Drop=0
  1777. * 3-1 Queue ETH_Q0=0
  1778. * 7-4 Reserved = 0;
  1779. */
  1780. mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
  1781. /* Set all entries in DA filter other multicast
  1782. * table (Ex_dFOMT)
  1783. * Set for ETH_Q0 for now
  1784. * Bits
  1785. * 0 Accept=1, Drop=0
  1786. * 3-1 Queue ETH_Q0=0
  1787. * 7-4 Reserved = 0;
  1788. */
  1789. mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
  1790. }
  1791. return;
  1792. }
  1793. /* We will clear out multicast tables every time we get the list.
  1794. * Then add the entire new list...
  1795. */
  1796. for (table_index = 0; table_index <= 0xFC; table_index += 4) {
  1797. /* Clear DA filter special multicast table (Ex_dFSMT) */
  1798. mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
  1799. (eth_port_num) + table_index, 0);
  1800. /* Clear DA filter other multicast table (Ex_dFOMT) */
  1801. mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
  1802. (eth_port_num) + table_index, 0);
  1803. }
  1804. /* Get pointer to net_device multicast list and add each one... */
  1805. for (i = 0, mc_list = dev->mc_list;
  1806. (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
  1807. i++, mc_list = mc_list->next)
  1808. if (mc_list->dmi_addrlen == 6)
  1809. eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
  1810. }
  1811. /*
  1812. * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
  1813. *
  1814. * DESCRIPTION:
  1815. * Go through all the DA filter tables (Unicast, Special Multicast &
  1816. * Other Multicast) and set each entry to 0.
  1817. *
  1818. * INPUT:
  1819. * unsigned int eth_port_num Ethernet Port number.
  1820. *
  1821. * OUTPUT:
  1822. * Multicast and Unicast packets are rejected.
  1823. *
  1824. * RETURN:
  1825. * None.
  1826. */
  1827. static void eth_port_init_mac_tables(unsigned int eth_port_num)
  1828. {
  1829. int table_index;
  1830. /* Clear DA filter unicast table (Ex_dFUT) */
  1831. for (table_index = 0; table_index <= 0xC; table_index += 4)
  1832. mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
  1833. (eth_port_num) + table_index, 0);
  1834. for (table_index = 0; table_index <= 0xFC; table_index += 4) {
  1835. /* Clear DA filter special multicast table (Ex_dFSMT) */
  1836. mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
  1837. (eth_port_num) + table_index, 0);
  1838. /* Clear DA filter other multicast table (Ex_dFOMT) */
  1839. mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
  1840. (eth_port_num) + table_index, 0);
  1841. }
  1842. }
  1843. /*
  1844. * eth_clear_mib_counters - Clear all MIB counters
  1845. *
  1846. * DESCRIPTION:
  1847. * This function clears all MIB counters of a specific ethernet port.
  1848. * A read from the MIB counter will reset the counter.
  1849. *
  1850. * INPUT:
  1851. * unsigned int eth_port_num Ethernet Port number.
  1852. *
  1853. * OUTPUT:
  1854. * After reading all MIB counters, the counters resets.
  1855. *
  1856. * RETURN:
  1857. * MIB counter value.
  1858. *
  1859. */
  1860. static void eth_clear_mib_counters(unsigned int eth_port_num)
  1861. {
  1862. int i;
  1863. /* Perform dummy reads from MIB counters */
  1864. for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
  1865. i += 4)
  1866. mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
  1867. }
  1868. static inline u32 read_mib(struct mv643xx_private *mp, int offset)
  1869. {
  1870. return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
  1871. }
  1872. static void eth_update_mib_counters(struct mv643xx_private *mp)
  1873. {
  1874. struct mv643xx_mib_counters *p = &mp->mib_counters;
  1875. int offset;
  1876. p->good_octets_received +=
  1877. read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
  1878. p->good_octets_received +=
  1879. (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
  1880. for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
  1881. offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
  1882. offset += 4)
  1883. *(u32 *)((char *)p + offset) += read_mib(mp, offset);
  1884. p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
  1885. p->good_octets_sent +=
  1886. (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
  1887. for (offset = ETH_MIB_GOOD_FRAMES_SENT;
  1888. offset <= ETH_MIB_LATE_COLLISION;
  1889. offset += 4)
  1890. *(u32 *)((char *)p + offset) += read_mib(mp, offset);
  1891. }
  1892. /*
  1893. * ethernet_phy_detect - Detect whether a phy is present
  1894. *
  1895. * DESCRIPTION:
  1896. * This function tests whether there is a PHY present on
  1897. * the specified port.
  1898. *
  1899. * INPUT:
  1900. * unsigned int eth_port_num Ethernet Port number.
  1901. *
  1902. * OUTPUT:
  1903. * None
  1904. *
  1905. * RETURN:
  1906. * 0 on success
  1907. * -ENODEV on failure
  1908. *
  1909. */
  1910. static int ethernet_phy_detect(unsigned int port_num)
  1911. {
  1912. unsigned int phy_reg_data0;
  1913. int auto_neg;
  1914. eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
  1915. auto_neg = phy_reg_data0 & 0x1000;
  1916. phy_reg_data0 ^= 0x1000; /* invert auto_neg */
  1917. eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
  1918. eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
  1919. if ((phy_reg_data0 & 0x1000) == auto_neg)
  1920. return -ENODEV; /* change didn't take */
  1921. phy_reg_data0 ^= 0x1000;
  1922. eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
  1923. return 0;
  1924. }
  1925. /*
  1926. * ethernet_phy_get - Get the ethernet port PHY address.
  1927. *
  1928. * DESCRIPTION:
  1929. * This routine returns the given ethernet port PHY address.
  1930. *
  1931. * INPUT:
  1932. * unsigned int eth_port_num Ethernet Port number.
  1933. *
  1934. * OUTPUT:
  1935. * None.
  1936. *
  1937. * RETURN:
  1938. * PHY address.
  1939. *
  1940. */
  1941. static int ethernet_phy_get(unsigned int eth_port_num)
  1942. {
  1943. unsigned int reg_data;
  1944. reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
  1945. return ((reg_data >> (5 * eth_port_num)) & 0x1f);
  1946. }
  1947. /*
  1948. * ethernet_phy_set - Set the ethernet port PHY address.
  1949. *
  1950. * DESCRIPTION:
  1951. * This routine sets the given ethernet port PHY address.
  1952. *
  1953. * INPUT:
  1954. * unsigned int eth_port_num Ethernet Port number.
  1955. * int phy_addr PHY address.
  1956. *
  1957. * OUTPUT:
  1958. * None.
  1959. *
  1960. * RETURN:
  1961. * None.
  1962. *
  1963. */
  1964. static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
  1965. {
  1966. u32 reg_data;
  1967. int addr_shift = 5 * eth_port_num;
  1968. reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
  1969. reg_data &= ~(0x1f << addr_shift);
  1970. reg_data |= (phy_addr & 0x1f) << addr_shift;
  1971. mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
  1972. }
  1973. /*
  1974. * ethernet_phy_reset - Reset Ethernet port PHY.
  1975. *
  1976. * DESCRIPTION:
  1977. * This routine utilizes the SMI interface to reset the ethernet port PHY.
  1978. *
  1979. * INPUT:
  1980. * unsigned int eth_port_num Ethernet Port number.
  1981. *
  1982. * OUTPUT:
  1983. * The PHY is reset.
  1984. *
  1985. * RETURN:
  1986. * None.
  1987. *
  1988. */
  1989. static void ethernet_phy_reset(unsigned int eth_port_num)
  1990. {
  1991. unsigned int phy_reg_data;
  1992. /* Reset the PHY */
  1993. eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
  1994. phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
  1995. eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
  1996. /* wait for PHY to come out of reset */
  1997. do {
  1998. udelay(1);
  1999. eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
  2000. } while (phy_reg_data & 0x8000);
  2001. }
  2002. static void mv643xx_eth_port_enable_tx(unsigned int port_num,
  2003. unsigned int queues)
  2004. {
  2005. mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
  2006. }
  2007. static void mv643xx_eth_port_enable_rx(unsigned int port_num,
  2008. unsigned int queues)
  2009. {
  2010. mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
  2011. }
  2012. static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
  2013. {
  2014. u32 queues;
  2015. /* Stop Tx port activity. Check port Tx activity. */
  2016. queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
  2017. & 0xFF;
  2018. if (queues) {
  2019. /* Issue stop command for active queues only */
  2020. mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
  2021. (queues << 8));
  2022. /* Wait for all Tx activity to terminate. */
  2023. /* Check port cause register that all Tx queues are stopped */
  2024. while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
  2025. & 0xFF)
  2026. udelay(PHY_WAIT_MICRO_SECONDS);
  2027. /* Wait for Tx FIFO to empty */
  2028. while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
  2029. ETH_PORT_TX_FIFO_EMPTY)
  2030. udelay(PHY_WAIT_MICRO_SECONDS);
  2031. }
  2032. return queues;
  2033. }
  2034. static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
  2035. {
  2036. u32 queues;
  2037. /* Stop Rx port activity. Check port Rx activity. */
  2038. queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
  2039. & 0xFF;
  2040. if (queues) {
  2041. /* Issue stop command for active queues only */
  2042. mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
  2043. (queues << 8));
  2044. /* Wait for all Rx activity to terminate. */
  2045. /* Check port cause register that all Rx queues are stopped */
  2046. while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
  2047. & 0xFF)
  2048. udelay(PHY_WAIT_MICRO_SECONDS);
  2049. }
  2050. return queues;
  2051. }
  2052. /*
  2053. * eth_port_reset - Reset Ethernet port
  2054. *
  2055. * DESCRIPTION:
  2056. * This routine resets the chip by aborting any SDMA engine activity and
  2057. * clearing the MIB counters. The Receiver and the Transmit unit are in
  2058. * idle state after this command is performed and the port is disabled.
  2059. *
  2060. * INPUT:
  2061. * unsigned int eth_port_num Ethernet Port number.
  2062. *
  2063. * OUTPUT:
  2064. * Channel activity is halted.
  2065. *
  2066. * RETURN:
  2067. * None.
  2068. *
  2069. */
  2070. static void eth_port_reset(unsigned int port_num)
  2071. {
  2072. unsigned int reg_data;
  2073. mv643xx_eth_port_disable_tx(port_num);
  2074. mv643xx_eth_port_disable_rx(port_num);
  2075. /* Clear all MIB counters */
  2076. eth_clear_mib_counters(port_num);
  2077. /* Reset the Enable bit in the Configuration Register */
  2078. reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
  2079. reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE |
  2080. MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
  2081. MV643XX_ETH_FORCE_LINK_PASS);
  2082. mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
  2083. }
  2084. /*
  2085. * eth_port_read_smi_reg - Read PHY registers
  2086. *
  2087. * DESCRIPTION:
  2088. * This routine utilize the SMI interface to interact with the PHY in
  2089. * order to perform PHY register read.
  2090. *
  2091. * INPUT:
  2092. * unsigned int port_num Ethernet Port number.
  2093. * unsigned int phy_reg PHY register address offset.
  2094. * unsigned int *value Register value buffer.
  2095. *
  2096. * OUTPUT:
  2097. * Write the value of a specified PHY register into given buffer.
  2098. *
  2099. * RETURN:
  2100. * false if the PHY is busy or read data is not in valid state.
  2101. * true otherwise.
  2102. *
  2103. */
  2104. static void eth_port_read_smi_reg(unsigned int port_num,
  2105. unsigned int phy_reg, unsigned int *value)
  2106. {
  2107. int phy_addr = ethernet_phy_get(port_num);
  2108. unsigned long flags;
  2109. int i;
  2110. /* the SMI register is a shared resource */
  2111. spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
  2112. /* wait for the SMI register to become available */
  2113. for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
  2114. if (i == PHY_WAIT_ITERATIONS) {
  2115. printk("mv643xx PHY busy timeout, port %d\n", port_num);
  2116. goto out;
  2117. }
  2118. udelay(PHY_WAIT_MICRO_SECONDS);
  2119. }
  2120. mv_write(MV643XX_ETH_SMI_REG,
  2121. (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
  2122. /* now wait for the data to be valid */
  2123. for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
  2124. if (i == PHY_WAIT_ITERATIONS) {
  2125. printk("mv643xx PHY read timeout, port %d\n", port_num);
  2126. goto out;
  2127. }
  2128. udelay(PHY_WAIT_MICRO_SECONDS);
  2129. }
  2130. *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
  2131. out:
  2132. spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
  2133. }
  2134. /*
  2135. * eth_port_write_smi_reg - Write to PHY registers
  2136. *
  2137. * DESCRIPTION:
  2138. * This routine utilize the SMI interface to interact with the PHY in
  2139. * order to perform writes to PHY registers.
  2140. *
  2141. * INPUT:
  2142. * unsigned int eth_port_num Ethernet Port number.
  2143. * unsigned int phy_reg PHY register address offset.
  2144. * unsigned int value Register value.
  2145. *
  2146. * OUTPUT:
  2147. * Write the given value to the specified PHY register.
  2148. *
  2149. * RETURN:
  2150. * false if the PHY is busy.
  2151. * true otherwise.
  2152. *
  2153. */
  2154. static void eth_port_write_smi_reg(unsigned int eth_port_num,
  2155. unsigned int phy_reg, unsigned int value)
  2156. {
  2157. int phy_addr;
  2158. int i;
  2159. unsigned long flags;
  2160. phy_addr = ethernet_phy_get(eth_port_num);
  2161. /* the SMI register is a shared resource */
  2162. spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
  2163. /* wait for the SMI register to become available */
  2164. for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
  2165. if (i == PHY_WAIT_ITERATIONS) {
  2166. printk("mv643xx PHY busy timeout, port %d\n",
  2167. eth_port_num);
  2168. goto out;
  2169. }
  2170. udelay(PHY_WAIT_MICRO_SECONDS);
  2171. }
  2172. mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
  2173. ETH_SMI_OPCODE_WRITE | (value & 0xffff));
  2174. out:
  2175. spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
  2176. }
  2177. /*
  2178. * Wrappers for MII support library.
  2179. */
  2180. static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
  2181. {
  2182. int val;
  2183. struct mv643xx_private *mp = netdev_priv(dev);
  2184. eth_port_read_smi_reg(mp->port_num, location, &val);
  2185. return val;
  2186. }
  2187. static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
  2188. {
  2189. struct mv643xx_private *mp = netdev_priv(dev);
  2190. eth_port_write_smi_reg(mp->port_num, location, val);
  2191. }
  2192. /*
  2193. * eth_port_receive - Get received information from Rx ring.
  2194. *
  2195. * DESCRIPTION:
  2196. * This routine returns the received data to the caller. There is no
  2197. * data copying during routine operation. All information is returned
  2198. * using pointer to packet information struct passed from the caller.
  2199. * If the routine exhausts Rx ring resources then the resource error flag
  2200. * is set.
  2201. *
  2202. * INPUT:
  2203. * struct mv643xx_private *mp Ethernet Port Control srtuct.
  2204. * struct pkt_info *p_pkt_info User packet buffer.
  2205. *
  2206. * OUTPUT:
  2207. * Rx ring current and used indexes are updated.
  2208. *
  2209. * RETURN:
  2210. * ETH_ERROR in case the routine can not access Rx desc ring.
  2211. * ETH_QUEUE_FULL if Rx ring resources are exhausted.
  2212. * ETH_END_OF_JOB if there is no received data.
  2213. * ETH_OK otherwise.
  2214. */
  2215. static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
  2216. struct pkt_info *p_pkt_info)
  2217. {
  2218. int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
  2219. volatile struct eth_rx_desc *p_rx_desc;
  2220. unsigned int command_status;
  2221. unsigned long flags;
  2222. /* Do not process Rx ring in case of Rx ring resource error */
  2223. if (mp->rx_resource_err)
  2224. return ETH_QUEUE_FULL;
  2225. spin_lock_irqsave(&mp->lock, flags);
  2226. /* Get the Rx Desc ring 'curr and 'used' indexes */
  2227. rx_curr_desc = mp->rx_curr_desc_q;
  2228. rx_used_desc = mp->rx_used_desc_q;
  2229. p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
  2230. /* The following parameters are used to save readings from memory */
  2231. command_status = p_rx_desc->cmd_sts;
  2232. rmb();
  2233. /* Nothing to receive... */
  2234. if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
  2235. spin_unlock_irqrestore(&mp->lock, flags);
  2236. return ETH_END_OF_JOB;
  2237. }
  2238. p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
  2239. p_pkt_info->cmd_sts = command_status;
  2240. p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
  2241. p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
  2242. p_pkt_info->l4i_chk = p_rx_desc->buf_size;
  2243. /*
  2244. * Clean the return info field to indicate that the
  2245. * packet has been moved to the upper layers
  2246. */
  2247. mp->rx_skb[rx_curr_desc] = NULL;
  2248. /* Update current index in data structure */
  2249. rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
  2250. mp->rx_curr_desc_q = rx_next_curr_desc;
  2251. /* Rx descriptors exhausted. Set the Rx ring resource error flag */
  2252. if (rx_next_curr_desc == rx_used_desc)
  2253. mp->rx_resource_err = 1;
  2254. spin_unlock_irqrestore(&mp->lock, flags);
  2255. return ETH_OK;
  2256. }
  2257. /*
  2258. * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
  2259. *
  2260. * DESCRIPTION:
  2261. * This routine returns a Rx buffer back to the Rx ring. It retrieves the
  2262. * next 'used' descriptor and attached the returned buffer to it.
  2263. * In case the Rx ring was in "resource error" condition, where there are
  2264. * no available Rx resources, the function resets the resource error flag.
  2265. *
  2266. * INPUT:
  2267. * struct mv643xx_private *mp Ethernet Port Control srtuct.
  2268. * struct pkt_info *p_pkt_info Information on returned buffer.
  2269. *
  2270. * OUTPUT:
  2271. * New available Rx resource in Rx descriptor ring.
  2272. *
  2273. * RETURN:
  2274. * ETH_ERROR in case the routine can not access Rx desc ring.
  2275. * ETH_OK otherwise.
  2276. */
  2277. static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
  2278. struct pkt_info *p_pkt_info)
  2279. {
  2280. int used_rx_desc; /* Where to return Rx resource */
  2281. volatile struct eth_rx_desc *p_used_rx_desc;
  2282. unsigned long flags;
  2283. spin_lock_irqsave(&mp->lock, flags);
  2284. /* Get 'used' Rx descriptor */
  2285. used_rx_desc = mp->rx_used_desc_q;
  2286. p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
  2287. p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
  2288. p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
  2289. mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
  2290. /* Flush the write pipe */
  2291. /* Return the descriptor to DMA ownership */
  2292. wmb();
  2293. p_used_rx_desc->cmd_sts =
  2294. ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
  2295. wmb();
  2296. /* Move the used descriptor pointer to the next descriptor */
  2297. mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
  2298. /* Any Rx return cancels the Rx resource error status */
  2299. mp->rx_resource_err = 0;
  2300. spin_unlock_irqrestore(&mp->lock, flags);
  2301. return ETH_OK;
  2302. }
  2303. /************* Begin ethtool support *************************/
  2304. struct mv643xx_stats {
  2305. char stat_string[ETH_GSTRING_LEN];
  2306. int sizeof_stat;
  2307. int stat_offset;
  2308. };
  2309. #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
  2310. offsetof(struct mv643xx_private, m)
  2311. static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
  2312. { "rx_packets", MV643XX_STAT(stats.rx_packets) },
  2313. { "tx_packets", MV643XX_STAT(stats.tx_packets) },
  2314. { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
  2315. { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
  2316. { "rx_errors", MV643XX_STAT(stats.rx_errors) },
  2317. { "tx_errors", MV643XX_STAT(stats.tx_errors) },
  2318. { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
  2319. { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
  2320. { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
  2321. { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
  2322. { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
  2323. { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
  2324. { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
  2325. { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
  2326. { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
  2327. { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
  2328. { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
  2329. { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
  2330. { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
  2331. { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
  2332. { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
  2333. { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
  2334. { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
  2335. { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
  2336. { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
  2337. { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
  2338. { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
  2339. { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
  2340. { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
  2341. { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
  2342. { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
  2343. { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
  2344. { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
  2345. { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
  2346. { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
  2347. { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
  2348. { "collision", MV643XX_STAT(mib_counters.collision) },
  2349. { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
  2350. };
  2351. #define MV643XX_STATS_LEN \
  2352. sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
  2353. static void mv643xx_get_drvinfo(struct net_device *netdev,
  2354. struct ethtool_drvinfo *drvinfo)
  2355. {
  2356. strncpy(drvinfo->driver, mv643xx_driver_name, 32);
  2357. strncpy(drvinfo->version, mv643xx_driver_version, 32);
  2358. strncpy(drvinfo->fw_version, "N/A", 32);
  2359. strncpy(drvinfo->bus_info, "mv643xx", 32);
  2360. drvinfo->n_stats = MV643XX_STATS_LEN;
  2361. }
  2362. static int mv643xx_get_stats_count(struct net_device *netdev)
  2363. {
  2364. return MV643XX_STATS_LEN;
  2365. }
  2366. static void mv643xx_get_ethtool_stats(struct net_device *netdev,
  2367. struct ethtool_stats *stats, uint64_t *data)
  2368. {
  2369. struct mv643xx_private *mp = netdev->priv;
  2370. int i;
  2371. eth_update_mib_counters(mp);
  2372. for (i = 0; i < MV643XX_STATS_LEN; i++) {
  2373. char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
  2374. data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
  2375. sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
  2376. }
  2377. }
  2378. static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
  2379. uint8_t *data)
  2380. {
  2381. int i;
  2382. switch(stringset) {
  2383. case ETH_SS_STATS:
  2384. for (i=0; i < MV643XX_STATS_LEN; i++) {
  2385. memcpy(data + i * ETH_GSTRING_LEN,
  2386. mv643xx_gstrings_stats[i].stat_string,
  2387. ETH_GSTRING_LEN);
  2388. }
  2389. break;
  2390. }
  2391. }
  2392. static u32 mv643xx_eth_get_link(struct net_device *dev)
  2393. {
  2394. struct mv643xx_private *mp = netdev_priv(dev);
  2395. return mii_link_ok(&mp->mii);
  2396. }
  2397. static int mv643xx_eth_nway_restart(struct net_device *dev)
  2398. {
  2399. struct mv643xx_private *mp = netdev_priv(dev);
  2400. return mii_nway_restart(&mp->mii);
  2401. }
  2402. static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  2403. {
  2404. struct mv643xx_private *mp = netdev_priv(dev);
  2405. return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
  2406. }
  2407. static const struct ethtool_ops mv643xx_ethtool_ops = {
  2408. .get_settings = mv643xx_get_settings,
  2409. .set_settings = mv643xx_set_settings,
  2410. .get_drvinfo = mv643xx_get_drvinfo,
  2411. .get_link = mv643xx_eth_get_link,
  2412. .get_sg = ethtool_op_get_sg,
  2413. .set_sg = ethtool_op_set_sg,
  2414. .get_stats_count = mv643xx_get_stats_count,
  2415. .get_ethtool_stats = mv643xx_get_ethtool_stats,
  2416. .get_strings = mv643xx_get_strings,
  2417. .get_stats_count = mv643xx_get_stats_count,
  2418. .get_ethtool_stats = mv643xx_get_ethtool_stats,
  2419. .nway_reset = mv643xx_eth_nway_restart,
  2420. };
  2421. /************* End ethtool support *************************/