mipsnet.h 3.6 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. */
  6. #ifndef __MIPSNET_H
  7. #define __MIPSNET_H
  8. /*
  9. * Id of this Net device, as seen by the core.
  10. */
  11. #define MIPS_NET_DEV_ID ((uint64_t) \
  12. ((uint64_t)'M'<< 0)| \
  13. ((uint64_t)'I'<< 8)| \
  14. ((uint64_t)'P'<<16)| \
  15. ((uint64_t)'S'<<24)| \
  16. ((uint64_t)'N'<<32)| \
  17. ((uint64_t)'E'<<40)| \
  18. ((uint64_t)'T'<<48)| \
  19. ((uint64_t)'0'<<56))
  20. /*
  21. * Net status/control block as seen by sw in the core.
  22. * (Why not use bit fields? can't be bothered with cross-platform struct
  23. * packing.)
  24. */
  25. typedef struct _net_control_block {
  26. /// dev info for probing
  27. /// reads as MIPSNET%d where %d is some form of version
  28. uint64_t devId; /*0x00 */
  29. /*
  30. * read only busy flag.
  31. * Set and cleared by the Net Device to indicate that an rx or a tx
  32. * is in progress.
  33. */
  34. uint32_t busy; /*0x08 */
  35. /*
  36. * Set by the Net Device.
  37. * The device will set it once data has been received.
  38. * The value is the number of bytes that should be read from
  39. * rxDataBuffer. The value will decrease till 0 until all the data
  40. * from rxDataBuffer has been read.
  41. */
  42. uint32_t rxDataCount; /*0x0c */
  43. #define MIPSNET_MAX_RXTX_DATACOUNT (1<<16)
  44. /*
  45. * Settable from the MIPS core, cleared by the Net Device.
  46. * The core should set the number of bytes it wants to send,
  47. * then it should write those bytes of data to txDataBuffer.
  48. * The device will clear txDataCount has been processed (not necessarily sent).
  49. */
  50. uint32_t txDataCount; /*0x10 */
  51. /*
  52. * Interrupt control
  53. *
  54. * Used to clear the interrupted generated by this dev.
  55. * Write a 1 to clear the interrupt. (except bit31).
  56. *
  57. * Bit0 is set if it was a tx-done interrupt.
  58. * Bit1 is set when new rx-data is available.
  59. * Until this bit is cleared there will be no other RXs.
  60. *
  61. * Bit31 is used for testing, it clears after a read.
  62. * Writing 1 to this bit will cause an interrupt to be generated.
  63. * To clear the test interrupt, write 0 to this register.
  64. */
  65. uint32_t interruptControl; /*0x14 */
  66. #define MIPSNET_INTCTL_TXDONE ((uint32_t)(1<< 0))
  67. #define MIPSNET_INTCTL_RXDONE ((uint32_t)(1<< 1))
  68. #define MIPSNET_INTCTL_TESTBIT ((uint32_t)(1<<31))
  69. #define MIPSNET_INTCTL_ALLSOURCES (MIPSNET_INTCTL_TXDONE|MIPSNET_INTCTL_RXDONE|MIPSNET_INTCTL_TESTBIT)
  70. /*
  71. * Readonly core-specific interrupt info for the device to signal the core.
  72. * The meaning of the contents of this field might change.
  73. */
  74. /*###\todo: the whole memIntf interrupt scheme is messy: the device should have
  75. * no control what so ever of what VPE/register set is being used.
  76. * The MemIntf should only expose interrupt lines, and something in the
  77. * config should be responsible for the line<->core/vpe bindings.
  78. */
  79. uint32_t interruptInfo; /*0x18 */
  80. /*
  81. * This is where the received data is read out.
  82. * There is more data to read until rxDataReady is 0.
  83. * Only 1 byte at this regs offset is used.
  84. */
  85. uint32_t rxDataBuffer; /*0x1c */
  86. /*
  87. * This is where the data to transmit is written.
  88. * Data should be written for the amount specified in the txDataCount register.
  89. * Only 1 byte at this regs offset is used.
  90. */
  91. uint32_t txDataBuffer; /*0x20 */
  92. } MIPS_T_NetControl;
  93. #define MIPSNET_IO_EXTENT 0x40 /* being generous */
  94. #define field_offset(field) ((int)&((MIPS_T_NetControl*)(0))->field)
  95. #endif /* __MIPSNET_H */