meth.h 9.5 KB

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  1. /*
  2. * snull.h -- definitions for the network module
  3. *
  4. * Copyright (C) 2001 Alessandro Rubini and Jonathan Corbet
  5. * Copyright (C) 2001 O'Reilly & Associates
  6. *
  7. * The source code in this file can be freely used, adapted,
  8. * and redistributed in source or binary form, so long as an
  9. * acknowledgment appears in derived source files. The citation
  10. * should list that the code comes from the book "Linux Device
  11. * Drivers" by Alessandro Rubini and Jonathan Corbet, published
  12. * by O'Reilly & Associates. No warranty is attached;
  13. * we cannot take responsibility for errors or fitness for use.
  14. */
  15. /* version dependencies have been confined to a separate file */
  16. /* Tunable parameters */
  17. #define TX_RING_ENTRIES 64 /* 64-512?*/
  18. #define RX_RING_ENTRIES 16 /* Do not change */
  19. /* Internal constants */
  20. #define TX_RING_BUFFER_SIZE (TX_RING_ENTRIES*sizeof(tx_packet))
  21. #define RX_BUFFER_SIZE 1546 /* ethenet packet size */
  22. #define METH_RX_BUFF_SIZE 4096
  23. #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
  24. #define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */
  25. #define RX_BUCKET_SIZE 256
  26. #undef BIT
  27. #define BIT(x) (1UL << (x))
  28. /* For more detailed explanations of what each field menas,
  29. see Nick's great comments to #defines below (or docs, if
  30. you are lucky enough toget hold of them :)*/
  31. /* tx status vector is written over tx command header upon
  32. dma completion. */
  33. typedef struct tx_status_vector {
  34. u64 sent:1; /* always set to 1...*/
  35. u64 pad0:34;/* always set to 0 */
  36. u64 flags:9; /*I'm too lazy to specify each one separately at the moment*/
  37. u64 col_retry_cnt:4; /*collision retry count*/
  38. u64 len:16; /*Transmit length in bytes*/
  39. } tx_status_vector;
  40. /*
  41. * Each packet is 128 bytes long.
  42. * It consists of header, 0-3 concatination
  43. * buffer pointers and up to 120 data bytes.
  44. */
  45. typedef struct tx_packet_hdr {
  46. u64 pad1:36; /*should be filled with 0 */
  47. u64 cat_ptr3_valid:1, /*Concatination pointer valid flags*/
  48. cat_ptr2_valid:1,
  49. cat_ptr1_valid:1;
  50. u64 tx_int_flag:1; /*Generate TX intrrupt when packet has been sent*/
  51. u64 term_dma_flag:1; /*Terminate transmit DMA on transmit abort conditions*/
  52. u64 data_offset:7; /*Starting byte offset in ring data block*/
  53. u64 data_len:16; /*Length of valid data in bytes-1*/
  54. } tx_packet_hdr;
  55. typedef union tx_cat_ptr {
  56. struct {
  57. u64 pad2:16; /* should be 0 */
  58. u64 len:16; /*length of buffer data - 1*/
  59. u64 start_addr:29; /*Physical starting address*/
  60. u64 pad1:3; /* should be zero */
  61. } form;
  62. u64 raw;
  63. } tx_cat_ptr;
  64. typedef struct tx_packet {
  65. union {
  66. tx_packet_hdr header;
  67. tx_status_vector res;
  68. u64 raw;
  69. }header;
  70. union {
  71. tx_cat_ptr cat_buf[3];
  72. char dt[120];
  73. } data;
  74. } tx_packet;
  75. typedef union rx_status_vector {
  76. volatile struct {
  77. u64 pad1:1;/*fill it with ones*/
  78. u64 pad2:15;/*fill with 0*/
  79. u64 ip_chk_sum:16;
  80. u64 seq_num:5;
  81. u64 mac_addr_match:1;
  82. u64 mcast_addr_match:1;
  83. u64 carrier_event_seen:1;
  84. u64 bad_packet:1;
  85. u64 long_event_seen:1;
  86. u64 invalid_preamble:1;
  87. u64 broadcast:1;
  88. u64 multicast:1;
  89. u64 crc_error:1;
  90. u64 huh:1;/*???*/
  91. u64 rx_code_violation:1;
  92. u64 rx_len:16;
  93. } parsed;
  94. volatile u64 raw;
  95. } rx_status_vector;
  96. typedef struct rx_packet {
  97. rx_status_vector status;
  98. u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
  99. u16 pad2;
  100. char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
  101. } rx_packet;
  102. #define TX_INFO_RPTR 0x00FF0000
  103. #define TX_INFO_WPTR 0x000000FF
  104. /* Bits in METH_MAC */
  105. #define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */
  106. #define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
  107. #define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */
  108. /* selects ignored */
  109. #define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */
  110. #define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */
  111. /* Note: when loopback is set this bit becomes collision control. Setting this bit will */
  112. /* cause a collision to be reported. */
  113. /* Bits 5 and 6 are used to determine the the Destination address filter mode */
  114. #define METH_ACCEPT_MY 0 /* 00: Accept PHY address only */
  115. #define METH_ACCEPT_MCAST 0x20 /* 01: Accept physical, broadcast, and multicast filter matches only */
  116. #define METH_ACCEPT_AMCAST 0x40 /* 10: Accept physical, broadcast, and all multicast packets */
  117. #define METH_PROMISC 0x60 /* 11: Promiscious mode */
  118. #define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */
  119. #define METH_MAC_IPG 0x1ffff00
  120. #define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8))
  121. /* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/
  122. /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
  123. /* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns */
  124. /* per increment for 10BaseT */
  125. /* Bits 15 through 21 are used to determine IPGR1 */
  126. /* Bits 22 through 28 are used to determine IPGR2 */
  127. #define METH_REV_SHIFT 29 /* Bits 29 through 31 are used to determine the revision */
  128. /* 000: Inital revision */
  129. /* 001: First revision, Improved TX concatenation */
  130. /* DMA control bits */
  131. #define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */
  132. #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */
  133. #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
  134. #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
  135. #define METH_DMA_RX_EN BIT(15) /* Enable RX */
  136. #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
  137. /* RX FIFO MCL Info bits */
  138. #define METH_RX_FIFO_WPTR(x) (((x)>>16)&0xf)
  139. #define METH_RX_FIFO_RPTR(x) (((x)>>8)&0xf)
  140. #define METH_RX_FIFO_DEPTH(x) ((x)&0x1f)
  141. /* RX status bits */
  142. #define METH_RX_ST_VALID BIT(63)
  143. #define METH_RX_ST_RCV_CODE_VIOLATION BIT(16)
  144. #define METH_RX_ST_DRBL_NBL BIT(17)
  145. #define METH_RX_ST_CRC_ERR BIT(18)
  146. #define METH_RX_ST_MCAST_PKT BIT(19)
  147. #define METH_RX_ST_BCAST_PKT BIT(20)
  148. #define METH_RX_ST_INV_PREAMBLE_CTX BIT(21)
  149. #define METH_RX_ST_LONG_EVT_SEEN BIT(22)
  150. #define METH_RX_ST_BAD_PACKET BIT(23)
  151. #define METH_RX_ST_CARRIER_EVT_SEEN BIT(24)
  152. #define METH_RX_ST_MCAST_FILTER_MATCH BIT(25)
  153. #define METH_RX_ST_PHYS_ADDR_MATCH BIT(26)
  154. #define METH_RX_STATUS_ERRORS \
  155. ( \
  156. METH_RX_ST_RCV_CODE_VIOLATION| \
  157. METH_RX_ST_CRC_ERR| \
  158. METH_RX_ST_INV_PREAMBLE_CTX| \
  159. METH_RX_ST_LONG_EVT_SEEN| \
  160. METH_RX_ST_BAD_PACKET| \
  161. METH_RX_ST_CARRIER_EVT_SEEN \
  162. )
  163. /* Bits in METH_INT */
  164. /* Write _1_ to corresponding bit to clear */
  165. #define METH_INT_TX_EMPTY BIT(0) /* 0: No interrupt pending, 1: The TX ring buffer is empty */
  166. #define METH_INT_TX_PKT BIT(1) /* 0: No interrupt pending */
  167. /* 1: A TX message had the INT request bit set, the packet has been sent. */
  168. #define METH_INT_TX_LINK_FAIL BIT(2) /* 0: No interrupt pending, 1: PHY has reported a link failure */
  169. #define METH_INT_MEM_ERROR BIT(3) /* 0: No interrupt pending */
  170. /* 1: A memory error occurred durring DMA, DMA stopped, Fatal */
  171. #define METH_INT_TX_ABORT BIT(4) /* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */
  172. #define METH_INT_RX_THRESHOLD BIT(5) /* 0: No interrupt pending, 1: Selected receive threshold condition Valid */
  173. #define METH_INT_RX_UNDERFLOW BIT(6) /* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */
  174. #define METH_INT_RX_OVERFLOW BIT(7) /* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */
  175. /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/ /* Bits 8 through 12 alias of RX read-pointer */
  176. #define METH_INT_RX_RPTR_MASK 0x0000F00 /* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/
  177. /* Bits 13 through 15 are always 0. */
  178. #define METH_INT_TX_RPTR_MASK 0x1FF0000 /* Bits 16 through 24 alias of TX read-pointer */
  179. #define METH_INT_RX_SEQ_MASK 0x2E000000 /* Bits 25 through 29 are the starting seq number for the message at the */
  180. /* top of the queue */
  181. #define METH_INT_ERROR (METH_INT_TX_LINK_FAIL| \
  182. METH_INT_MEM_ERROR| \
  183. METH_INT_TX_ABORT| \
  184. METH_INT_RX_OVERFLOW| \
  185. METH_INT_RX_UNDERFLOW)
  186. #define METH_INT_MCAST_HASH BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */
  187. /* TX status bits */
  188. #define METH_TX_ST_DONE BIT(63) /* TX complete */
  189. #define METH_TX_ST_SUCCESS BIT(23) /* Packet was transmitted successfully */
  190. #define METH_TX_ST_TOOLONG BIT(24) /* TX abort due to excessive length */
  191. #define METH_TX_ST_UNDERRUN BIT(25) /* TX abort due to underrun (?) */
  192. #define METH_TX_ST_EXCCOLL BIT(26) /* TX abort due to excess collisions */
  193. #define METH_TX_ST_DEFER BIT(27) /* TX abort due to excess deferals */
  194. #define METH_TX_ST_LATECOLL BIT(28) /* TX abort due to late collision */
  195. /* Tx command header bits */
  196. #define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
  197. /* Phy MDIO interface busy flag */
  198. #define MDIO_BUSY BIT(16)
  199. #define MDIO_DATA_MASK 0xFFFF
  200. /* PHY defines */
  201. #define PHY_QS6612X 0x0181441 /* Quality TX */
  202. #define PHY_ICS1889 0x0015F41 /* ICS FX */
  203. #define PHY_ICS1890 0x0015F42 /* ICS TX */
  204. #define PHY_DP83840 0x20005C0 /* National TX */
  205. #define ADVANCE_RX_PTR(x) x=(x+1)&(RX_RING_ENTRIES-1)