macmace.c 16 KB

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  1. /*
  2. * Driver for the Macintosh 68K onboard MACE controller with PSC
  3. * driven DMA. The MACE driver code is derived from mace.c. The
  4. * Mac68k theory of operation is courtesy of the MacBSD wizards.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Copyright (C) 1996 Paul Mackerras.
  12. * Copyright (C) 1998 Alan Cox <alan@redhat.com>
  13. *
  14. * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/etherdevice.h>
  20. #include <linux/delay.h>
  21. #include <linux/string.h>
  22. #include <linux/crc32.h>
  23. #include <linux/bitrev.h>
  24. #include <asm/io.h>
  25. #include <asm/pgtable.h>
  26. #include <asm/irq.h>
  27. #include <asm/macintosh.h>
  28. #include <asm/macints.h>
  29. #include <asm/mac_psc.h>
  30. #include <asm/page.h>
  31. #include "mace.h"
  32. #define N_TX_RING 1
  33. #define N_RX_RING 8
  34. #define N_RX_PAGES ((N_RX_RING * 0x0800 + PAGE_SIZE - 1) / PAGE_SIZE)
  35. #define TX_TIMEOUT HZ
  36. /* Bits in transmit DMA status */
  37. #define TX_DMA_ERR 0x80
  38. /* The MACE is simply wired down on a Mac68K box */
  39. #define MACE_BASE (void *)(0x50F1C000)
  40. #define MACE_PROM (void *)(0x50F08001)
  41. struct mace_data {
  42. volatile struct mace *mace;
  43. volatile unsigned char *tx_ring;
  44. volatile unsigned char *tx_ring_phys;
  45. volatile unsigned char *rx_ring;
  46. volatile unsigned char *rx_ring_phys;
  47. int dma_intr;
  48. struct net_device_stats stats;
  49. int rx_slot, rx_tail;
  50. int tx_slot, tx_sloti, tx_count;
  51. };
  52. struct mace_frame {
  53. u16 len;
  54. u16 status;
  55. u16 rntpc;
  56. u16 rcvcc;
  57. u32 pad1;
  58. u32 pad2;
  59. u8 data[1];
  60. /* And frame continues.. */
  61. };
  62. #define PRIV_BYTES sizeof(struct mace_data)
  63. extern void psc_debug_dump(void);
  64. static int mace_open(struct net_device *dev);
  65. static int mace_close(struct net_device *dev);
  66. static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
  67. static struct net_device_stats *mace_stats(struct net_device *dev);
  68. static void mace_set_multicast(struct net_device *dev);
  69. static int mace_set_address(struct net_device *dev, void *addr);
  70. static irqreturn_t mace_interrupt(int irq, void *dev_id);
  71. static irqreturn_t mace_dma_intr(int irq, void *dev_id);
  72. static void mace_tx_timeout(struct net_device *dev);
  73. /*
  74. * Load a receive DMA channel with a base address and ring length
  75. */
  76. static void mace_load_rxdma_base(struct net_device *dev, int set)
  77. {
  78. struct mace_data *mp = (struct mace_data *) dev->priv;
  79. psc_write_word(PSC_ENETRD_CMD + set, 0x0100);
  80. psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys);
  81. psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING);
  82. psc_write_word(PSC_ENETRD_CMD + set, 0x9800);
  83. mp->rx_tail = 0;
  84. }
  85. /*
  86. * Reset the receive DMA subsystem
  87. */
  88. static void mace_rxdma_reset(struct net_device *dev)
  89. {
  90. struct mace_data *mp = (struct mace_data *) dev->priv;
  91. volatile struct mace *mace = mp->mace;
  92. u8 maccc = mace->maccc;
  93. mace->maccc = maccc & ~ENRCV;
  94. psc_write_word(PSC_ENETRD_CTL, 0x8800);
  95. mace_load_rxdma_base(dev, 0x00);
  96. psc_write_word(PSC_ENETRD_CTL, 0x0400);
  97. psc_write_word(PSC_ENETRD_CTL, 0x8800);
  98. mace_load_rxdma_base(dev, 0x10);
  99. psc_write_word(PSC_ENETRD_CTL, 0x0400);
  100. mace->maccc = maccc;
  101. mp->rx_slot = 0;
  102. psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800);
  103. psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800);
  104. }
  105. /*
  106. * Reset the transmit DMA subsystem
  107. */
  108. static void mace_txdma_reset(struct net_device *dev)
  109. {
  110. struct mace_data *mp = (struct mace_data *) dev->priv;
  111. volatile struct mace *mace = mp->mace;
  112. u8 maccc;
  113. psc_write_word(PSC_ENETWR_CTL, 0x8800);
  114. maccc = mace->maccc;
  115. mace->maccc = maccc & ~ENXMT;
  116. mp->tx_slot = mp->tx_sloti = 0;
  117. mp->tx_count = N_TX_RING;
  118. psc_write_word(PSC_ENETWR_CTL, 0x0400);
  119. mace->maccc = maccc;
  120. }
  121. /*
  122. * Disable DMA
  123. */
  124. static void mace_dma_off(struct net_device *dev)
  125. {
  126. psc_write_word(PSC_ENETRD_CTL, 0x8800);
  127. psc_write_word(PSC_ENETRD_CTL, 0x1000);
  128. psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100);
  129. psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100);
  130. psc_write_word(PSC_ENETWR_CTL, 0x8800);
  131. psc_write_word(PSC_ENETWR_CTL, 0x1000);
  132. psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100);
  133. psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100);
  134. }
  135. /*
  136. * Not really much of a probe. The hardware table tells us if this
  137. * model of Macintrash has a MACE (AV macintoshes)
  138. */
  139. struct net_device *mace_probe(int unit)
  140. {
  141. int j;
  142. struct mace_data *mp;
  143. unsigned char *addr;
  144. struct net_device *dev;
  145. unsigned char checksum = 0;
  146. static int found = 0;
  147. int err;
  148. if (found || macintosh_config->ether_type != MAC_ETHER_MACE)
  149. return ERR_PTR(-ENODEV);
  150. found = 1; /* prevent 'finding' one on every device probe */
  151. dev = alloc_etherdev(PRIV_BYTES);
  152. if (!dev)
  153. return ERR_PTR(-ENOMEM);
  154. if (unit >= 0)
  155. sprintf(dev->name, "eth%d", unit);
  156. mp = (struct mace_data *) dev->priv;
  157. dev->base_addr = (u32)MACE_BASE;
  158. mp->mace = (volatile struct mace *) MACE_BASE;
  159. dev->irq = IRQ_MAC_MACE;
  160. mp->dma_intr = IRQ_MAC_MACE_DMA;
  161. /*
  162. * The PROM contains 8 bytes which total 0xFF when XOR'd
  163. * together. Due to the usual peculiar apple brain damage
  164. * the bytes are spaced out in a strange boundary and the
  165. * bits are reversed.
  166. */
  167. addr = (void *)MACE_PROM;
  168. for (j = 0; j < 6; ++j) {
  169. u8 v = bitrev8(addr[j<<4]);
  170. checksum ^= v;
  171. dev->dev_addr[j] = v;
  172. }
  173. for (; j < 8; ++j) {
  174. checksum ^= bitrev8(addr[j<<4]);
  175. }
  176. if (checksum != 0xFF) {
  177. free_netdev(dev);
  178. return ERR_PTR(-ENODEV);
  179. }
  180. memset(&mp->stats, 0, sizeof(mp->stats));
  181. dev->open = mace_open;
  182. dev->stop = mace_close;
  183. dev->hard_start_xmit = mace_xmit_start;
  184. dev->tx_timeout = mace_tx_timeout;
  185. dev->watchdog_timeo = TX_TIMEOUT;
  186. dev->get_stats = mace_stats;
  187. dev->set_multicast_list = mace_set_multicast;
  188. dev->set_mac_address = mace_set_address;
  189. printk(KERN_INFO "%s: 68K MACE, hardware address %.2X", dev->name, dev->dev_addr[0]);
  190. for (j = 1 ; j < 6 ; j++) printk(":%.2X", dev->dev_addr[j]);
  191. printk("\n");
  192. err = register_netdev(dev);
  193. if (!err)
  194. return dev;
  195. free_netdev(dev);
  196. return ERR_PTR(err);
  197. }
  198. /*
  199. * Load the address on a mace controller.
  200. */
  201. static int mace_set_address(struct net_device *dev, void *addr)
  202. {
  203. unsigned char *p = addr;
  204. struct mace_data *mp = (struct mace_data *) dev->priv;
  205. volatile struct mace *mb = mp->mace;
  206. int i;
  207. unsigned long flags;
  208. u8 maccc;
  209. local_irq_save(flags);
  210. maccc = mb->maccc;
  211. /* load up the hardware address */
  212. mb->iac = ADDRCHG | PHYADDR;
  213. while ((mb->iac & ADDRCHG) != 0);
  214. for (i = 0; i < 6; ++i) {
  215. mb->padr = dev->dev_addr[i] = p[i];
  216. }
  217. mb->maccc = maccc;
  218. local_irq_restore(flags);
  219. return 0;
  220. }
  221. /*
  222. * Open the Macintosh MACE. Most of this is playing with the DMA
  223. * engine. The ethernet chip is quite friendly.
  224. */
  225. static int mace_open(struct net_device *dev)
  226. {
  227. struct mace_data *mp = (struct mace_data *) dev->priv;
  228. volatile struct mace *mb = mp->mace;
  229. #if 0
  230. int i;
  231. i = 200;
  232. while (--i) {
  233. mb->biucc = SWRST;
  234. if (mb->biucc & SWRST) {
  235. udelay(10);
  236. continue;
  237. }
  238. break;
  239. }
  240. if (!i) {
  241. printk(KERN_ERR "%s: software reset failed!!\n", dev->name);
  242. return -EAGAIN;
  243. }
  244. #endif
  245. mb->biucc = XMTSP_64;
  246. mb->fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | XMTBRST | RCVBRST;
  247. mb->xmtfc = AUTO_PAD_XMIT;
  248. mb->plscc = PORTSEL_AUI;
  249. /* mb->utr = RTRD; */
  250. if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) {
  251. printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq);
  252. return -EAGAIN;
  253. }
  254. if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) {
  255. printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr);
  256. free_irq(dev->irq, dev);
  257. return -EAGAIN;
  258. }
  259. /* Allocate the DMA ring buffers */
  260. mp->rx_ring = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, N_RX_PAGES);
  261. mp->tx_ring = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, 0);
  262. if (mp->tx_ring==NULL || mp->rx_ring==NULL) {
  263. if (mp->rx_ring) free_pages((u32) mp->rx_ring, N_RX_PAGES);
  264. if (mp->tx_ring) free_pages((u32) mp->tx_ring, 0);
  265. free_irq(dev->irq, dev);
  266. free_irq(mp->dma_intr, dev);
  267. printk(KERN_ERR "%s: unable to allocate DMA buffers\n", dev->name);
  268. return -ENOMEM;
  269. }
  270. mp->rx_ring_phys = (unsigned char *) virt_to_bus((void *)mp->rx_ring);
  271. mp->tx_ring_phys = (unsigned char *) virt_to_bus((void *)mp->tx_ring);
  272. /* We want the Rx buffer to be uncached and the Tx buffer to be writethrough */
  273. kernel_set_cachemode((void *)mp->rx_ring, N_RX_PAGES * PAGE_SIZE, IOMAP_NOCACHE_NONSER);
  274. kernel_set_cachemode((void *)mp->tx_ring, PAGE_SIZE, IOMAP_WRITETHROUGH);
  275. mace_dma_off(dev);
  276. /* Not sure what these do */
  277. psc_write_word(PSC_ENETWR_CTL, 0x9000);
  278. psc_write_word(PSC_ENETRD_CTL, 0x9000);
  279. psc_write_word(PSC_ENETWR_CTL, 0x0400);
  280. psc_write_word(PSC_ENETRD_CTL, 0x0400);
  281. #if 0
  282. /* load up the hardware address */
  283. mb->iac = ADDRCHG | PHYADDR;
  284. while ((mb->iac & ADDRCHG) != 0);
  285. for (i = 0; i < 6; ++i)
  286. mb->padr = dev->dev_addr[i];
  287. /* clear the multicast filter */
  288. mb->iac = ADDRCHG | LOGADDR;
  289. while ((mb->iac & ADDRCHG) != 0);
  290. for (i = 0; i < 8; ++i)
  291. mb->ladrf = 0;
  292. mb->plscc = PORTSEL_GPSI + ENPLSIO;
  293. mb->maccc = ENXMT | ENRCV;
  294. mb->imr = RCVINT;
  295. #endif
  296. mace_rxdma_reset(dev);
  297. mace_txdma_reset(dev);
  298. return 0;
  299. }
  300. /*
  301. * Shut down the mace and its interrupt channel
  302. */
  303. static int mace_close(struct net_device *dev)
  304. {
  305. struct mace_data *mp = (struct mace_data *) dev->priv;
  306. volatile struct mace *mb = mp->mace;
  307. mb->maccc = 0; /* disable rx and tx */
  308. mb->imr = 0xFF; /* disable all irqs */
  309. mace_dma_off(dev); /* disable rx and tx dma */
  310. free_irq(dev->irq, dev);
  311. free_irq(IRQ_MAC_MACE_DMA, dev);
  312. free_pages((u32) mp->rx_ring, N_RX_PAGES);
  313. free_pages((u32) mp->tx_ring, 0);
  314. return 0;
  315. }
  316. /*
  317. * Transmit a frame
  318. */
  319. static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
  320. {
  321. struct mace_data *mp = (struct mace_data *) dev->priv;
  322. /* Stop the queue if the buffer is full */
  323. if (!mp->tx_count) {
  324. netif_stop_queue(dev);
  325. return 1;
  326. }
  327. mp->tx_count--;
  328. mp->stats.tx_packets++;
  329. mp->stats.tx_bytes += skb->len;
  330. /* We need to copy into our xmit buffer to take care of alignment and caching issues */
  331. memcpy((void *) mp->tx_ring, skb->data, skb->len);
  332. /* load the Tx DMA and fire it off */
  333. psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys);
  334. psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len);
  335. psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);
  336. mp->tx_slot ^= 0x10;
  337. dev_kfree_skb(skb);
  338. return 0;
  339. }
  340. static struct net_device_stats *mace_stats(struct net_device *dev)
  341. {
  342. struct mace_data *p = (struct mace_data *) dev->priv;
  343. return &p->stats;
  344. }
  345. static void mace_set_multicast(struct net_device *dev)
  346. {
  347. struct mace_data *mp = (struct mace_data *) dev->priv;
  348. volatile struct mace *mb = mp->mace;
  349. int i, j;
  350. u32 crc;
  351. u8 maccc;
  352. maccc = mb->maccc;
  353. mb->maccc &= ~PROM;
  354. if (dev->flags & IFF_PROMISC) {
  355. mb->maccc |= PROM;
  356. } else {
  357. unsigned char multicast_filter[8];
  358. struct dev_mc_list *dmi = dev->mc_list;
  359. if (dev->flags & IFF_ALLMULTI) {
  360. for (i = 0; i < 8; i++) {
  361. multicast_filter[i] = 0xFF;
  362. }
  363. } else {
  364. for (i = 0; i < 8; i++)
  365. multicast_filter[i] = 0;
  366. for (i = 0; i < dev->mc_count; i++) {
  367. crc = ether_crc_le(6, dmi->dmi_addr);
  368. j = crc >> 26; /* bit number in multicast_filter */
  369. multicast_filter[j >> 3] |= 1 << (j & 7);
  370. dmi = dmi->next;
  371. }
  372. }
  373. mb->iac = ADDRCHG | LOGADDR;
  374. while (mb->iac & ADDRCHG);
  375. for (i = 0; i < 8; ++i) {
  376. mb->ladrf = multicast_filter[i];
  377. }
  378. }
  379. mb->maccc = maccc;
  380. }
  381. /*
  382. * Miscellaneous interrupts are handled here. We may end up
  383. * having to bash the chip on the head for bad errors
  384. */
  385. static void mace_handle_misc_intrs(struct mace_data *mp, int intr)
  386. {
  387. volatile struct mace *mb = mp->mace;
  388. static int mace_babbles, mace_jabbers;
  389. if (intr & MPCO) {
  390. mp->stats.rx_missed_errors += 256;
  391. }
  392. mp->stats.rx_missed_errors += mb->mpc; /* reading clears it */
  393. if (intr & RNTPCO) {
  394. mp->stats.rx_length_errors += 256;
  395. }
  396. mp->stats.rx_length_errors += mb->rntpc; /* reading clears it */
  397. if (intr & CERR) {
  398. ++mp->stats.tx_heartbeat_errors;
  399. }
  400. if (intr & BABBLE) {
  401. if (mace_babbles++ < 4) {
  402. printk(KERN_DEBUG "mace: babbling transmitter\n");
  403. }
  404. }
  405. if (intr & JABBER) {
  406. if (mace_jabbers++ < 4) {
  407. printk(KERN_DEBUG "mace: jabbering transceiver\n");
  408. }
  409. }
  410. }
  411. /*
  412. * A transmit error has occurred. (We kick the transmit side from
  413. * the DMA completion)
  414. */
  415. static void mace_xmit_error(struct net_device *dev)
  416. {
  417. struct mace_data *mp = (struct mace_data *) dev->priv;
  418. volatile struct mace *mb = mp->mace;
  419. u8 xmtfs, xmtrc;
  420. xmtfs = mb->xmtfs;
  421. xmtrc = mb->xmtrc;
  422. if (xmtfs & XMTSV) {
  423. if (xmtfs & UFLO) {
  424. printk("%s: DMA underrun.\n", dev->name);
  425. mp->stats.tx_errors++;
  426. mp->stats.tx_fifo_errors++;
  427. mace_txdma_reset(dev);
  428. }
  429. if (xmtfs & RTRY) {
  430. mp->stats.collisions++;
  431. }
  432. }
  433. }
  434. /*
  435. * A receive interrupt occurred.
  436. */
  437. static void mace_recv_interrupt(struct net_device *dev)
  438. {
  439. /* struct mace_data *mp = (struct mace_data *) dev->priv; */
  440. // volatile struct mace *mb = mp->mace;
  441. }
  442. /*
  443. * Process the chip interrupt
  444. */
  445. static irqreturn_t mace_interrupt(int irq, void *dev_id)
  446. {
  447. struct net_device *dev = (struct net_device *) dev_id;
  448. struct mace_data *mp = (struct mace_data *) dev->priv;
  449. volatile struct mace *mb = mp->mace;
  450. u8 ir;
  451. ir = mb->ir;
  452. mace_handle_misc_intrs(mp, ir);
  453. if (ir & XMTINT) {
  454. mace_xmit_error(dev);
  455. }
  456. if (ir & RCVINT) {
  457. mace_recv_interrupt(dev);
  458. }
  459. return IRQ_HANDLED;
  460. }
  461. static void mace_tx_timeout(struct net_device *dev)
  462. {
  463. /* struct mace_data *mp = (struct mace_data *) dev->priv; */
  464. // volatile struct mace *mb = mp->mace;
  465. }
  466. /*
  467. * Handle a newly arrived frame
  468. */
  469. static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf)
  470. {
  471. struct mace_data *mp = (struct mace_data *) dev->priv;
  472. struct sk_buff *skb;
  473. if (mf->status & RS_OFLO) {
  474. printk("%s: fifo overflow.\n", dev->name);
  475. mp->stats.rx_errors++;
  476. mp->stats.rx_fifo_errors++;
  477. }
  478. if (mf->status&(RS_CLSN|RS_FRAMERR|RS_FCSERR))
  479. mp->stats.rx_errors++;
  480. if (mf->status&RS_CLSN) {
  481. mp->stats.collisions++;
  482. }
  483. if (mf->status&RS_FRAMERR) {
  484. mp->stats.rx_frame_errors++;
  485. }
  486. if (mf->status&RS_FCSERR) {
  487. mp->stats.rx_crc_errors++;
  488. }
  489. skb = dev_alloc_skb(mf->len+2);
  490. if (!skb) {
  491. mp->stats.rx_dropped++;
  492. return;
  493. }
  494. skb_reserve(skb,2);
  495. memcpy(skb_put(skb, mf->len), mf->data, mf->len);
  496. skb->dev = dev;
  497. skb->protocol = eth_type_trans(skb, dev);
  498. netif_rx(skb);
  499. dev->last_rx = jiffies;
  500. mp->stats.rx_packets++;
  501. mp->stats.rx_bytes += mf->len;
  502. }
  503. /*
  504. * The PSC has passed us a DMA interrupt event.
  505. */
  506. static irqreturn_t mace_dma_intr(int irq, void *dev_id)
  507. {
  508. struct net_device *dev = (struct net_device *) dev_id;
  509. struct mace_data *mp = (struct mace_data *) dev->priv;
  510. int left, head;
  511. u16 status;
  512. u32 baka;
  513. /* Not sure what this does */
  514. while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY));
  515. if (!(baka & 0x60000000)) return IRQ_NONE;
  516. /*
  517. * Process the read queue
  518. */
  519. status = psc_read_word(PSC_ENETRD_CTL);
  520. if (status & 0x2000) {
  521. mace_rxdma_reset(dev);
  522. } else if (status & 0x0100) {
  523. psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);
  524. left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot);
  525. head = N_RX_RING - left;
  526. /* Loop through the ring buffer and process new packages */
  527. while (mp->rx_tail < head) {
  528. mace_dma_rx_frame(dev, (struct mace_frame *) (mp->rx_ring + (mp->rx_tail * 0x0800)));
  529. mp->rx_tail++;
  530. }
  531. /* If we're out of buffers in this ring then switch to */
  532. /* the other set, otherwise just reactivate this one. */
  533. if (!left) {
  534. mace_load_rxdma_base(dev, mp->rx_slot);
  535. mp->rx_slot ^= 0x10;
  536. } else {
  537. psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);
  538. }
  539. }
  540. /*
  541. * Process the write queue
  542. */
  543. status = psc_read_word(PSC_ENETWR_CTL);
  544. if (status & 0x2000) {
  545. mace_txdma_reset(dev);
  546. } else if (status & 0x0100) {
  547. psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);
  548. mp->tx_sloti ^= 0x10;
  549. mp->tx_count++;
  550. netif_wake_queue(dev);
  551. }
  552. return IRQ_HANDLED;
  553. }
  554. MODULE_LICENSE("GPL");