mace.h 7.0 KB

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  1. /*
  2. * mace.h - definitions for the registers in the Am79C940 MACE
  3. * (Medium Access Control for Ethernet) controller.
  4. *
  5. * Copyright (C) 1996 Paul Mackerras.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #define REG(x) volatile unsigned char x; char x ## _pad[15]
  13. struct mace {
  14. REG(rcvfifo); /* receive FIFO */
  15. REG(xmtfifo); /* transmit FIFO */
  16. REG(xmtfc); /* transmit frame control */
  17. REG(xmtfs); /* transmit frame status */
  18. REG(xmtrc); /* transmit retry count */
  19. REG(rcvfc); /* receive frame control */
  20. REG(rcvfs); /* receive frame status (4 bytes) */
  21. REG(fifofc); /* FIFO frame count */
  22. REG(ir); /* interrupt register */
  23. REG(imr); /* interrupt mask register */
  24. REG(pr); /* poll register */
  25. REG(biucc); /* bus interface unit config control */
  26. REG(fifocc); /* FIFO configuration control */
  27. REG(maccc); /* medium access control config control */
  28. REG(plscc); /* phys layer signalling config control */
  29. REG(phycc); /* physical configuration control */
  30. REG(chipid_lo); /* chip ID, lsb */
  31. REG(chipid_hi); /* chip ID, msb */
  32. REG(iac); /* internal address config */
  33. REG(reg19);
  34. REG(ladrf); /* logical address filter (8 bytes) */
  35. REG(padr); /* physical address (6 bytes) */
  36. REG(reg22);
  37. REG(reg23);
  38. REG(mpc); /* missed packet count (clears when read) */
  39. REG(reg25);
  40. REG(rntpc); /* runt packet count (clears when read) */
  41. REG(rcvcc); /* recv collision count (clears when read) */
  42. REG(reg28);
  43. REG(utr); /* user test reg */
  44. REG(reg30);
  45. REG(reg31);
  46. };
  47. /* Bits in XMTFC */
  48. #define DRTRY 0x80 /* don't retry transmission after collision */
  49. #define DXMTFCS 0x08 /* don't append FCS to transmitted frame */
  50. #define AUTO_PAD_XMIT 0x01 /* auto-pad short packets on transmission */
  51. /* Bits in XMTFS: only valid when XMTSV is set in PR and XMTFS */
  52. #define XMTSV 0x80 /* transmit status (i.e. XMTFS) valid */
  53. #define UFLO 0x40 /* underflow - xmit fifo ran dry */
  54. #define LCOL 0x20 /* late collision (transmission aborted) */
  55. #define MORE 0x10 /* 2 or more retries needed to xmit frame */
  56. #define ONE 0x08 /* 1 retry needed to xmit frame */
  57. #define DEFER 0x04 /* MACE had to defer xmission (enet busy) */
  58. #define LCAR 0x02 /* loss of carrier (transmission aborted) */
  59. #define RTRY 0x01 /* too many retries (transmission aborted) */
  60. /* Bits in XMTRC: only valid when XMTSV is set in PR (and XMTFS) */
  61. #define EXDEF 0x80 /* had to defer for excessive time */
  62. #define RETRY_MASK 0x0f /* number of retries (0 - 15) */
  63. /* Bits in RCVFC */
  64. #define LLRCV 0x08 /* low latency receive: early DMA request */
  65. #define M_RBAR 0x04 /* sets function of EAM/R pin */
  66. #define AUTO_STRIP_RCV 0x01 /* auto-strip short LLC frames on recv */
  67. /*
  68. * Bits in RCVFS. After a frame is received, four bytes of status
  69. * are automatically read from this register and appended to the frame
  70. * data in memory. These are:
  71. * Byte 0 and 1: message byte count and frame status
  72. * Byte 2: runt packet count
  73. * Byte 3: receive collision count
  74. */
  75. #define RS_OFLO 0x8000 /* receive FIFO overflowed */
  76. #define RS_CLSN 0x4000 /* received frame suffered (late) collision */
  77. #define RS_FRAMERR 0x2000 /* framing error flag */
  78. #define RS_FCSERR 0x1000 /* frame had FCS error */
  79. #define RS_COUNT 0x0fff /* mask for byte count field */
  80. /* Bits (fields) in FIFOFC */
  81. #define RCVFC_SH 4 /* receive frame count in FIFO */
  82. #define RCVFC_MASK 0x0f
  83. #define XMTFC_SH 0 /* transmit frame count in FIFO */
  84. #define XMTFC_MASK 0x0f
  85. /*
  86. * Bits in IR and IMR. The IR clears itself when read.
  87. * Setting a bit in the IMR will disable the corresponding interrupt.
  88. */
  89. #define JABBER 0x80 /* jabber error - 10baseT xmission too long */
  90. #define BABBLE 0x40 /* babble - xmitter xmitting for too long */
  91. #define CERR 0x20 /* collision err - no SQE test (heartbeat) */
  92. #define RCVCCO 0x10 /* RCVCC overflow */
  93. #define RNTPCO 0x08 /* RNTPC overflow */
  94. #define MPCO 0x04 /* MPC overflow */
  95. #define RCVINT 0x02 /* receive interrupt */
  96. #define XMTINT 0x01 /* transmitter interrupt */
  97. /* Bits in PR */
  98. #define XMTSV 0x80 /* XMTFS valid (same as in XMTFS) */
  99. #define TDTREQ 0x40 /* set when xmit fifo is requesting data */
  100. #define RDTREQ 0x20 /* set when recv fifo requests data xfer */
  101. /* Bits in BIUCC */
  102. #define BSWP 0x40 /* byte swap, i.e. big-endian bus */
  103. #define XMTSP_4 0x00 /* start xmitting when 4 bytes in FIFO */
  104. #define XMTSP_16 0x10 /* start xmitting when 16 bytes in FIFO */
  105. #define XMTSP_64 0x20 /* start xmitting when 64 bytes in FIFO */
  106. #define XMTSP_112 0x30 /* start xmitting when 112 bytes in FIFO */
  107. #define SWRST 0x01 /* software reset */
  108. /* Bits in FIFOCC */
  109. #define XMTFW_8 0x00 /* xmit fifo watermark = 8 words free */
  110. #define XMTFW_16 0x40 /* 16 words free */
  111. #define XMTFW_32 0x80 /* 32 words free */
  112. #define RCVFW_16 0x00 /* recv fifo watermark = 16 bytes avail */
  113. #define RCVFW_32 0x10 /* 32 bytes avail */
  114. #define RCVFW_64 0x20 /* 64 bytes avail */
  115. #define XMTFWU 0x08 /* xmit fifo watermark update enable */
  116. #define RCVFWU 0x04 /* recv fifo watermark update enable */
  117. #define XMTBRST 0x02 /* enable transmit burst mode */
  118. #define RCVBRST 0x01 /* enable receive burst mode */
  119. /* Bits in MACCC */
  120. #define PROM 0x80 /* promiscuous mode */
  121. #define DXMT2PD 0x40 /* disable xmit two-part deferral algorithm */
  122. #define EMBA 0x20 /* enable modified backoff algorithm */
  123. #define DRCVPA 0x08 /* disable receiving physical address */
  124. #define DRCVBC 0x04 /* disable receiving broadcasts */
  125. #define ENXMT 0x02 /* enable transmitter */
  126. #define ENRCV 0x01 /* enable receiver */
  127. /* Bits in PLSCC */
  128. #define XMTSEL 0x08 /* select DO+/DO- state when idle */
  129. #define PORTSEL_AUI 0x00 /* select AUI port */
  130. #define PORTSEL_10T 0x02 /* select 10Base-T port */
  131. #define PORTSEL_DAI 0x04 /* select DAI port */
  132. #define PORTSEL_GPSI 0x06 /* select GPSI port */
  133. #define ENPLSIO 0x01 /* enable optional PLS I/O pins */
  134. /* Bits in PHYCC */
  135. #define LNKFL 0x80 /* reports 10Base-T link failure */
  136. #define DLNKTST 0x40 /* disable 10Base-T link test */
  137. #define REVPOL 0x20 /* 10Base-T receiver polarity reversed */
  138. #define DAPC 0x10 /* disable auto receiver polarity correction */
  139. #define LRT 0x08 /* low receive threshold for long links */
  140. #define ASEL 0x04 /* auto-select AUI or 10Base-T port */
  141. #define RWAKE 0x02 /* remote wake function */
  142. #define AWAKE 0x01 /* auto wake function */
  143. /* Bits in IAC */
  144. #define ADDRCHG 0x80 /* request address change */
  145. #define PHYADDR 0x04 /* access physical address */
  146. #define LOGADDR 0x02 /* access multicast filter */
  147. /* Bits in UTR */
  148. #define RTRE 0x80 /* reserved test register enable. DON'T SET. */
  149. #define RTRD 0x40 /* reserved test register disable. Sticky */
  150. #define RPAC 0x20 /* accept runt packets */
  151. #define FCOLL 0x10 /* force collision */
  152. #define RCVFCSE 0x08 /* receive FCS enable */
  153. #define LOOP_NONE 0x00 /* no loopback */
  154. #define LOOP_EXT 0x02 /* external loopback */
  155. #define LOOP_INT 0x04 /* internal loopback, excludes MENDEC */
  156. #define LOOP_MENDEC 0x06 /* internal loopback, includes MENDEC */