mace.c 28 KB

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  1. /*
  2. * Network device driver for the MACE ethernet controller on
  3. * Apple Powermacs. Assumes it's under a DBDMA controller.
  4. *
  5. * Copyright (C) 1996 Paul Mackerras.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/kernel.h>
  9. #include <linux/netdevice.h>
  10. #include <linux/etherdevice.h>
  11. #include <linux/delay.h>
  12. #include <linux/string.h>
  13. #include <linux/timer.h>
  14. #include <linux/init.h>
  15. #include <linux/crc32.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/bitrev.h>
  18. #include <asm/prom.h>
  19. #include <asm/dbdma.h>
  20. #include <asm/io.h>
  21. #include <asm/pgtable.h>
  22. #include <asm/macio.h>
  23. #include "mace.h"
  24. static int port_aaui = -1;
  25. #define N_RX_RING 8
  26. #define N_TX_RING 6
  27. #define MAX_TX_ACTIVE 1
  28. #define NCMDS_TX 1 /* dma commands per element in tx ring */
  29. #define RX_BUFLEN (ETH_FRAME_LEN + 8)
  30. #define TX_TIMEOUT HZ /* 1 second */
  31. /* Chip rev needs workaround on HW & multicast addr change */
  32. #define BROKEN_ADDRCHG_REV 0x0941
  33. /* Bits in transmit DMA status */
  34. #define TX_DMA_ERR 0x80
  35. struct mace_data {
  36. volatile struct mace __iomem *mace;
  37. volatile struct dbdma_regs __iomem *tx_dma;
  38. int tx_dma_intr;
  39. volatile struct dbdma_regs __iomem *rx_dma;
  40. int rx_dma_intr;
  41. volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
  42. volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
  43. struct sk_buff *rx_bufs[N_RX_RING];
  44. int rx_fill;
  45. int rx_empty;
  46. struct sk_buff *tx_bufs[N_TX_RING];
  47. int tx_fill;
  48. int tx_empty;
  49. unsigned char maccc;
  50. unsigned char tx_fullup;
  51. unsigned char tx_active;
  52. unsigned char tx_bad_runt;
  53. struct net_device_stats stats;
  54. struct timer_list tx_timeout;
  55. int timeout_active;
  56. int port_aaui;
  57. int chipid;
  58. struct macio_dev *mdev;
  59. spinlock_t lock;
  60. };
  61. /*
  62. * Number of bytes of private data per MACE: allow enough for
  63. * the rx and tx dma commands plus a branch dma command each,
  64. * and another 16 bytes to allow us to align the dma command
  65. * buffers on a 16 byte boundary.
  66. */
  67. #define PRIV_BYTES (sizeof(struct mace_data) \
  68. + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
  69. static int mace_open(struct net_device *dev);
  70. static int mace_close(struct net_device *dev);
  71. static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
  72. static struct net_device_stats *mace_stats(struct net_device *dev);
  73. static void mace_set_multicast(struct net_device *dev);
  74. static void mace_reset(struct net_device *dev);
  75. static int mace_set_address(struct net_device *dev, void *addr);
  76. static irqreturn_t mace_interrupt(int irq, void *dev_id);
  77. static irqreturn_t mace_txdma_intr(int irq, void *dev_id);
  78. static irqreturn_t mace_rxdma_intr(int irq, void *dev_id);
  79. static void mace_set_timeout(struct net_device *dev);
  80. static void mace_tx_timeout(unsigned long data);
  81. static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma);
  82. static inline void mace_clean_rings(struct mace_data *mp);
  83. static void __mace_set_address(struct net_device *dev, void *addr);
  84. /*
  85. * If we can't get a skbuff when we need it, we use this area for DMA.
  86. */
  87. static unsigned char *dummy_buf;
  88. static int __devinit mace_probe(struct macio_dev *mdev, const struct of_device_id *match)
  89. {
  90. struct device_node *mace = macio_get_of_node(mdev);
  91. struct net_device *dev;
  92. struct mace_data *mp;
  93. const unsigned char *addr;
  94. int j, rev, rc = -EBUSY;
  95. if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
  96. printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n",
  97. mace->full_name);
  98. return -ENODEV;
  99. }
  100. addr = get_property(mace, "mac-address", NULL);
  101. if (addr == NULL) {
  102. addr = get_property(mace, "local-mac-address", NULL);
  103. if (addr == NULL) {
  104. printk(KERN_ERR "Can't get mac-address for MACE %s\n",
  105. mace->full_name);
  106. return -ENODEV;
  107. }
  108. }
  109. /*
  110. * lazy allocate the driver-wide dummy buffer. (Note that we
  111. * never have more than one MACE in the system anyway)
  112. */
  113. if (dummy_buf == NULL) {
  114. dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
  115. if (dummy_buf == NULL) {
  116. printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n");
  117. return -ENOMEM;
  118. }
  119. }
  120. if (macio_request_resources(mdev, "mace")) {
  121. printk(KERN_ERR "MACE: can't request IO resources !\n");
  122. return -EBUSY;
  123. }
  124. dev = alloc_etherdev(PRIV_BYTES);
  125. if (!dev) {
  126. printk(KERN_ERR "MACE: can't allocate ethernet device !\n");
  127. rc = -ENOMEM;
  128. goto err_release;
  129. }
  130. SET_MODULE_OWNER(dev);
  131. SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
  132. mp = dev->priv;
  133. mp->mdev = mdev;
  134. macio_set_drvdata(mdev, dev);
  135. dev->base_addr = macio_resource_start(mdev, 0);
  136. mp->mace = ioremap(dev->base_addr, 0x1000);
  137. if (mp->mace == NULL) {
  138. printk(KERN_ERR "MACE: can't map IO resources !\n");
  139. rc = -ENOMEM;
  140. goto err_free;
  141. }
  142. dev->irq = macio_irq(mdev, 0);
  143. rev = addr[0] == 0 && addr[1] == 0xA0;
  144. for (j = 0; j < 6; ++j) {
  145. dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
  146. }
  147. mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
  148. in_8(&mp->mace->chipid_lo);
  149. mp = (struct mace_data *) dev->priv;
  150. mp->maccc = ENXMT | ENRCV;
  151. mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
  152. if (mp->tx_dma == NULL) {
  153. printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
  154. rc = -ENOMEM;
  155. goto err_unmap_io;
  156. }
  157. mp->tx_dma_intr = macio_irq(mdev, 1);
  158. mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000);
  159. if (mp->rx_dma == NULL) {
  160. printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
  161. rc = -ENOMEM;
  162. goto err_unmap_tx_dma;
  163. }
  164. mp->rx_dma_intr = macio_irq(mdev, 2);
  165. mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
  166. mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
  167. memset(&mp->stats, 0, sizeof(mp->stats));
  168. memset((char *) mp->tx_cmds, 0,
  169. (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
  170. init_timer(&mp->tx_timeout);
  171. spin_lock_init(&mp->lock);
  172. mp->timeout_active = 0;
  173. if (port_aaui >= 0)
  174. mp->port_aaui = port_aaui;
  175. else {
  176. /* Apple Network Server uses the AAUI port */
  177. if (machine_is_compatible("AAPL,ShinerESB"))
  178. mp->port_aaui = 1;
  179. else {
  180. #ifdef CONFIG_MACE_AAUI_PORT
  181. mp->port_aaui = 1;
  182. #else
  183. mp->port_aaui = 0;
  184. #endif
  185. }
  186. }
  187. dev->open = mace_open;
  188. dev->stop = mace_close;
  189. dev->hard_start_xmit = mace_xmit_start;
  190. dev->get_stats = mace_stats;
  191. dev->set_multicast_list = mace_set_multicast;
  192. dev->set_mac_address = mace_set_address;
  193. /*
  194. * Most of what is below could be moved to mace_open()
  195. */
  196. mace_reset(dev);
  197. rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
  198. if (rc) {
  199. printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
  200. goto err_unmap_rx_dma;
  201. }
  202. rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
  203. if (rc) {
  204. printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr);
  205. goto err_free_irq;
  206. }
  207. rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
  208. if (rc) {
  209. printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr);
  210. goto err_free_tx_irq;
  211. }
  212. rc = register_netdev(dev);
  213. if (rc) {
  214. printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
  215. goto err_free_rx_irq;
  216. }
  217. printk(KERN_INFO "%s: MACE at", dev->name);
  218. for (j = 0; j < 6; ++j) {
  219. printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
  220. }
  221. printk(", chip revision %d.%d\n", mp->chipid >> 8, mp->chipid & 0xff);
  222. return 0;
  223. err_free_rx_irq:
  224. free_irq(macio_irq(mdev, 2), dev);
  225. err_free_tx_irq:
  226. free_irq(macio_irq(mdev, 1), dev);
  227. err_free_irq:
  228. free_irq(macio_irq(mdev, 0), dev);
  229. err_unmap_rx_dma:
  230. iounmap(mp->rx_dma);
  231. err_unmap_tx_dma:
  232. iounmap(mp->tx_dma);
  233. err_unmap_io:
  234. iounmap(mp->mace);
  235. err_free:
  236. free_netdev(dev);
  237. err_release:
  238. macio_release_resources(mdev);
  239. return rc;
  240. }
  241. static int __devexit mace_remove(struct macio_dev *mdev)
  242. {
  243. struct net_device *dev = macio_get_drvdata(mdev);
  244. struct mace_data *mp;
  245. BUG_ON(dev == NULL);
  246. macio_set_drvdata(mdev, NULL);
  247. mp = dev->priv;
  248. unregister_netdev(dev);
  249. free_irq(dev->irq, dev);
  250. free_irq(mp->tx_dma_intr, dev);
  251. free_irq(mp->rx_dma_intr, dev);
  252. iounmap(mp->rx_dma);
  253. iounmap(mp->tx_dma);
  254. iounmap(mp->mace);
  255. free_netdev(dev);
  256. macio_release_resources(mdev);
  257. return 0;
  258. }
  259. static void dbdma_reset(volatile struct dbdma_regs __iomem *dma)
  260. {
  261. int i;
  262. out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
  263. /*
  264. * Yes this looks peculiar, but apparently it needs to be this
  265. * way on some machines.
  266. */
  267. for (i = 200; i > 0; --i)
  268. if (ld_le32(&dma->control) & RUN)
  269. udelay(1);
  270. }
  271. static void mace_reset(struct net_device *dev)
  272. {
  273. struct mace_data *mp = (struct mace_data *) dev->priv;
  274. volatile struct mace __iomem *mb = mp->mace;
  275. int i;
  276. /* soft-reset the chip */
  277. i = 200;
  278. while (--i) {
  279. out_8(&mb->biucc, SWRST);
  280. if (in_8(&mb->biucc) & SWRST) {
  281. udelay(10);
  282. continue;
  283. }
  284. break;
  285. }
  286. if (!i) {
  287. printk(KERN_ERR "mace: cannot reset chip!\n");
  288. return;
  289. }
  290. out_8(&mb->imr, 0xff); /* disable all intrs for now */
  291. i = in_8(&mb->ir);
  292. out_8(&mb->maccc, 0); /* turn off tx, rx */
  293. out_8(&mb->biucc, XMTSP_64);
  294. out_8(&mb->utr, RTRD);
  295. out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
  296. out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
  297. out_8(&mb->rcvfc, 0);
  298. /* load up the hardware address */
  299. __mace_set_address(dev, dev->dev_addr);
  300. /* clear the multicast filter */
  301. if (mp->chipid == BROKEN_ADDRCHG_REV)
  302. out_8(&mb->iac, LOGADDR);
  303. else {
  304. out_8(&mb->iac, ADDRCHG | LOGADDR);
  305. while ((in_8(&mb->iac) & ADDRCHG) != 0)
  306. ;
  307. }
  308. for (i = 0; i < 8; ++i)
  309. out_8(&mb->ladrf, 0);
  310. /* done changing address */
  311. if (mp->chipid != BROKEN_ADDRCHG_REV)
  312. out_8(&mb->iac, 0);
  313. if (mp->port_aaui)
  314. out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
  315. else
  316. out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
  317. }
  318. static void __mace_set_address(struct net_device *dev, void *addr)
  319. {
  320. struct mace_data *mp = (struct mace_data *) dev->priv;
  321. volatile struct mace __iomem *mb = mp->mace;
  322. unsigned char *p = addr;
  323. int i;
  324. /* load up the hardware address */
  325. if (mp->chipid == BROKEN_ADDRCHG_REV)
  326. out_8(&mb->iac, PHYADDR);
  327. else {
  328. out_8(&mb->iac, ADDRCHG | PHYADDR);
  329. while ((in_8(&mb->iac) & ADDRCHG) != 0)
  330. ;
  331. }
  332. for (i = 0; i < 6; ++i)
  333. out_8(&mb->padr, dev->dev_addr[i] = p[i]);
  334. if (mp->chipid != BROKEN_ADDRCHG_REV)
  335. out_8(&mb->iac, 0);
  336. }
  337. static int mace_set_address(struct net_device *dev, void *addr)
  338. {
  339. struct mace_data *mp = (struct mace_data *) dev->priv;
  340. volatile struct mace __iomem *mb = mp->mace;
  341. unsigned long flags;
  342. spin_lock_irqsave(&mp->lock, flags);
  343. __mace_set_address(dev, addr);
  344. /* note: setting ADDRCHG clears ENRCV */
  345. out_8(&mb->maccc, mp->maccc);
  346. spin_unlock_irqrestore(&mp->lock, flags);
  347. return 0;
  348. }
  349. static inline void mace_clean_rings(struct mace_data *mp)
  350. {
  351. int i;
  352. /* free some skb's */
  353. for (i = 0; i < N_RX_RING; ++i) {
  354. if (mp->rx_bufs[i] != 0) {
  355. dev_kfree_skb(mp->rx_bufs[i]);
  356. mp->rx_bufs[i] = NULL;
  357. }
  358. }
  359. for (i = mp->tx_empty; i != mp->tx_fill; ) {
  360. dev_kfree_skb(mp->tx_bufs[i]);
  361. if (++i >= N_TX_RING)
  362. i = 0;
  363. }
  364. }
  365. static int mace_open(struct net_device *dev)
  366. {
  367. struct mace_data *mp = (struct mace_data *) dev->priv;
  368. volatile struct mace __iomem *mb = mp->mace;
  369. volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
  370. volatile struct dbdma_regs __iomem *td = mp->tx_dma;
  371. volatile struct dbdma_cmd *cp;
  372. int i;
  373. struct sk_buff *skb;
  374. unsigned char *data;
  375. /* reset the chip */
  376. mace_reset(dev);
  377. /* initialize list of sk_buffs for receiving and set up recv dma */
  378. mace_clean_rings(mp);
  379. memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
  380. cp = mp->rx_cmds;
  381. for (i = 0; i < N_RX_RING - 1; ++i) {
  382. skb = dev_alloc_skb(RX_BUFLEN + 2);
  383. if (skb == 0) {
  384. data = dummy_buf;
  385. } else {
  386. skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */
  387. data = skb->data;
  388. }
  389. mp->rx_bufs[i] = skb;
  390. st_le16(&cp->req_count, RX_BUFLEN);
  391. st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
  392. st_le32(&cp->phy_addr, virt_to_bus(data));
  393. cp->xfer_status = 0;
  394. ++cp;
  395. }
  396. mp->rx_bufs[i] = NULL;
  397. st_le16(&cp->command, DBDMA_STOP);
  398. mp->rx_fill = i;
  399. mp->rx_empty = 0;
  400. /* Put a branch back to the beginning of the receive command list */
  401. ++cp;
  402. st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
  403. st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds));
  404. /* start rx dma */
  405. out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
  406. out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
  407. out_le32(&rd->control, (RUN << 16) | RUN);
  408. /* put a branch at the end of the tx command list */
  409. cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
  410. st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
  411. st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds));
  412. /* reset tx dma */
  413. out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
  414. out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
  415. mp->tx_fill = 0;
  416. mp->tx_empty = 0;
  417. mp->tx_fullup = 0;
  418. mp->tx_active = 0;
  419. mp->tx_bad_runt = 0;
  420. /* turn it on! */
  421. out_8(&mb->maccc, mp->maccc);
  422. /* enable all interrupts except receive interrupts */
  423. out_8(&mb->imr, RCVINT);
  424. return 0;
  425. }
  426. static int mace_close(struct net_device *dev)
  427. {
  428. struct mace_data *mp = (struct mace_data *) dev->priv;
  429. volatile struct mace __iomem *mb = mp->mace;
  430. volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
  431. volatile struct dbdma_regs __iomem *td = mp->tx_dma;
  432. /* disable rx and tx */
  433. out_8(&mb->maccc, 0);
  434. out_8(&mb->imr, 0xff); /* disable all intrs */
  435. /* disable rx and tx dma */
  436. st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
  437. st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
  438. mace_clean_rings(mp);
  439. return 0;
  440. }
  441. static inline void mace_set_timeout(struct net_device *dev)
  442. {
  443. struct mace_data *mp = (struct mace_data *) dev->priv;
  444. if (mp->timeout_active)
  445. del_timer(&mp->tx_timeout);
  446. mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
  447. mp->tx_timeout.function = mace_tx_timeout;
  448. mp->tx_timeout.data = (unsigned long) dev;
  449. add_timer(&mp->tx_timeout);
  450. mp->timeout_active = 1;
  451. }
  452. static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
  453. {
  454. struct mace_data *mp = (struct mace_data *) dev->priv;
  455. volatile struct dbdma_regs __iomem *td = mp->tx_dma;
  456. volatile struct dbdma_cmd *cp, *np;
  457. unsigned long flags;
  458. int fill, next, len;
  459. /* see if there's a free slot in the tx ring */
  460. spin_lock_irqsave(&mp->lock, flags);
  461. fill = mp->tx_fill;
  462. next = fill + 1;
  463. if (next >= N_TX_RING)
  464. next = 0;
  465. if (next == mp->tx_empty) {
  466. netif_stop_queue(dev);
  467. mp->tx_fullup = 1;
  468. spin_unlock_irqrestore(&mp->lock, flags);
  469. return 1; /* can't take it at the moment */
  470. }
  471. spin_unlock_irqrestore(&mp->lock, flags);
  472. /* partially fill in the dma command block */
  473. len = skb->len;
  474. if (len > ETH_FRAME_LEN) {
  475. printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
  476. len = ETH_FRAME_LEN;
  477. }
  478. mp->tx_bufs[fill] = skb;
  479. cp = mp->tx_cmds + NCMDS_TX * fill;
  480. st_le16(&cp->req_count, len);
  481. st_le32(&cp->phy_addr, virt_to_bus(skb->data));
  482. np = mp->tx_cmds + NCMDS_TX * next;
  483. out_le16(&np->command, DBDMA_STOP);
  484. /* poke the tx dma channel */
  485. spin_lock_irqsave(&mp->lock, flags);
  486. mp->tx_fill = next;
  487. if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
  488. out_le16(&cp->xfer_status, 0);
  489. out_le16(&cp->command, OUTPUT_LAST);
  490. out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
  491. ++mp->tx_active;
  492. mace_set_timeout(dev);
  493. }
  494. if (++next >= N_TX_RING)
  495. next = 0;
  496. if (next == mp->tx_empty)
  497. netif_stop_queue(dev);
  498. spin_unlock_irqrestore(&mp->lock, flags);
  499. return 0;
  500. }
  501. static struct net_device_stats *mace_stats(struct net_device *dev)
  502. {
  503. struct mace_data *p = (struct mace_data *) dev->priv;
  504. return &p->stats;
  505. }
  506. static void mace_set_multicast(struct net_device *dev)
  507. {
  508. struct mace_data *mp = (struct mace_data *) dev->priv;
  509. volatile struct mace __iomem *mb = mp->mace;
  510. int i, j;
  511. u32 crc;
  512. unsigned long flags;
  513. spin_lock_irqsave(&mp->lock, flags);
  514. mp->maccc &= ~PROM;
  515. if (dev->flags & IFF_PROMISC) {
  516. mp->maccc |= PROM;
  517. } else {
  518. unsigned char multicast_filter[8];
  519. struct dev_mc_list *dmi = dev->mc_list;
  520. if (dev->flags & IFF_ALLMULTI) {
  521. for (i = 0; i < 8; i++)
  522. multicast_filter[i] = 0xff;
  523. } else {
  524. for (i = 0; i < 8; i++)
  525. multicast_filter[i] = 0;
  526. for (i = 0; i < dev->mc_count; i++) {
  527. crc = ether_crc_le(6, dmi->dmi_addr);
  528. j = crc >> 26; /* bit number in multicast_filter */
  529. multicast_filter[j >> 3] |= 1 << (j & 7);
  530. dmi = dmi->next;
  531. }
  532. }
  533. #if 0
  534. printk("Multicast filter :");
  535. for (i = 0; i < 8; i++)
  536. printk("%02x ", multicast_filter[i]);
  537. printk("\n");
  538. #endif
  539. if (mp->chipid == BROKEN_ADDRCHG_REV)
  540. out_8(&mb->iac, LOGADDR);
  541. else {
  542. out_8(&mb->iac, ADDRCHG | LOGADDR);
  543. while ((in_8(&mb->iac) & ADDRCHG) != 0)
  544. ;
  545. }
  546. for (i = 0; i < 8; ++i)
  547. out_8(&mb->ladrf, multicast_filter[i]);
  548. if (mp->chipid != BROKEN_ADDRCHG_REV)
  549. out_8(&mb->iac, 0);
  550. }
  551. /* reset maccc */
  552. out_8(&mb->maccc, mp->maccc);
  553. spin_unlock_irqrestore(&mp->lock, flags);
  554. }
  555. static void mace_handle_misc_intrs(struct mace_data *mp, int intr)
  556. {
  557. volatile struct mace __iomem *mb = mp->mace;
  558. static int mace_babbles, mace_jabbers;
  559. if (intr & MPCO)
  560. mp->stats.rx_missed_errors += 256;
  561. mp->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */
  562. if (intr & RNTPCO)
  563. mp->stats.rx_length_errors += 256;
  564. mp->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
  565. if (intr & CERR)
  566. ++mp->stats.tx_heartbeat_errors;
  567. if (intr & BABBLE)
  568. if (mace_babbles++ < 4)
  569. printk(KERN_DEBUG "mace: babbling transmitter\n");
  570. if (intr & JABBER)
  571. if (mace_jabbers++ < 4)
  572. printk(KERN_DEBUG "mace: jabbering transceiver\n");
  573. }
  574. static irqreturn_t mace_interrupt(int irq, void *dev_id)
  575. {
  576. struct net_device *dev = (struct net_device *) dev_id;
  577. struct mace_data *mp = (struct mace_data *) dev->priv;
  578. volatile struct mace __iomem *mb = mp->mace;
  579. volatile struct dbdma_regs __iomem *td = mp->tx_dma;
  580. volatile struct dbdma_cmd *cp;
  581. int intr, fs, i, stat, x;
  582. int xcount, dstat;
  583. unsigned long flags;
  584. /* static int mace_last_fs, mace_last_xcount; */
  585. spin_lock_irqsave(&mp->lock, flags);
  586. intr = in_8(&mb->ir); /* read interrupt register */
  587. in_8(&mb->xmtrc); /* get retries */
  588. mace_handle_misc_intrs(mp, intr);
  589. i = mp->tx_empty;
  590. while (in_8(&mb->pr) & XMTSV) {
  591. del_timer(&mp->tx_timeout);
  592. mp->timeout_active = 0;
  593. /*
  594. * Clear any interrupt indication associated with this status
  595. * word. This appears to unlatch any error indication from
  596. * the DMA controller.
  597. */
  598. intr = in_8(&mb->ir);
  599. if (intr != 0)
  600. mace_handle_misc_intrs(mp, intr);
  601. if (mp->tx_bad_runt) {
  602. fs = in_8(&mb->xmtfs);
  603. mp->tx_bad_runt = 0;
  604. out_8(&mb->xmtfc, AUTO_PAD_XMIT);
  605. continue;
  606. }
  607. dstat = ld_le32(&td->status);
  608. /* stop DMA controller */
  609. out_le32(&td->control, RUN << 16);
  610. /*
  611. * xcount is the number of complete frames which have been
  612. * written to the fifo but for which status has not been read.
  613. */
  614. xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
  615. if (xcount == 0 || (dstat & DEAD)) {
  616. /*
  617. * If a packet was aborted before the DMA controller has
  618. * finished transferring it, it seems that there are 2 bytes
  619. * which are stuck in some buffer somewhere. These will get
  620. * transmitted as soon as we read the frame status (which
  621. * reenables the transmit data transfer request). Turning
  622. * off the DMA controller and/or resetting the MACE doesn't
  623. * help. So we disable auto-padding and FCS transmission
  624. * so the two bytes will only be a runt packet which should
  625. * be ignored by other stations.
  626. */
  627. out_8(&mb->xmtfc, DXMTFCS);
  628. }
  629. fs = in_8(&mb->xmtfs);
  630. if ((fs & XMTSV) == 0) {
  631. printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
  632. fs, xcount, dstat);
  633. mace_reset(dev);
  634. /*
  635. * XXX mace likes to hang the machine after a xmtfs error.
  636. * This is hard to reproduce, reseting *may* help
  637. */
  638. }
  639. cp = mp->tx_cmds + NCMDS_TX * i;
  640. stat = ld_le16(&cp->xfer_status);
  641. if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
  642. /*
  643. * Check whether there were in fact 2 bytes written to
  644. * the transmit FIFO.
  645. */
  646. udelay(1);
  647. x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
  648. if (x != 0) {
  649. /* there were two bytes with an end-of-packet indication */
  650. mp->tx_bad_runt = 1;
  651. mace_set_timeout(dev);
  652. } else {
  653. /*
  654. * Either there weren't the two bytes buffered up, or they
  655. * didn't have an end-of-packet indication.
  656. * We flush the transmit FIFO just in case (by setting the
  657. * XMTFWU bit with the transmitter disabled).
  658. */
  659. out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
  660. out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
  661. udelay(1);
  662. out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
  663. out_8(&mb->xmtfc, AUTO_PAD_XMIT);
  664. }
  665. }
  666. /* dma should have finished */
  667. if (i == mp->tx_fill) {
  668. printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
  669. fs, xcount, dstat);
  670. continue;
  671. }
  672. /* Update stats */
  673. if (fs & (UFLO|LCOL|LCAR|RTRY)) {
  674. ++mp->stats.tx_errors;
  675. if (fs & LCAR)
  676. ++mp->stats.tx_carrier_errors;
  677. if (fs & (UFLO|LCOL|RTRY))
  678. ++mp->stats.tx_aborted_errors;
  679. } else {
  680. mp->stats.tx_bytes += mp->tx_bufs[i]->len;
  681. ++mp->stats.tx_packets;
  682. }
  683. dev_kfree_skb_irq(mp->tx_bufs[i]);
  684. --mp->tx_active;
  685. if (++i >= N_TX_RING)
  686. i = 0;
  687. #if 0
  688. mace_last_fs = fs;
  689. mace_last_xcount = xcount;
  690. #endif
  691. }
  692. if (i != mp->tx_empty) {
  693. mp->tx_fullup = 0;
  694. netif_wake_queue(dev);
  695. }
  696. mp->tx_empty = i;
  697. i += mp->tx_active;
  698. if (i >= N_TX_RING)
  699. i -= N_TX_RING;
  700. if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
  701. do {
  702. /* set up the next one */
  703. cp = mp->tx_cmds + NCMDS_TX * i;
  704. out_le16(&cp->xfer_status, 0);
  705. out_le16(&cp->command, OUTPUT_LAST);
  706. ++mp->tx_active;
  707. if (++i >= N_TX_RING)
  708. i = 0;
  709. } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
  710. out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
  711. mace_set_timeout(dev);
  712. }
  713. spin_unlock_irqrestore(&mp->lock, flags);
  714. return IRQ_HANDLED;
  715. }
  716. static void mace_tx_timeout(unsigned long data)
  717. {
  718. struct net_device *dev = (struct net_device *) data;
  719. struct mace_data *mp = (struct mace_data *) dev->priv;
  720. volatile struct mace __iomem *mb = mp->mace;
  721. volatile struct dbdma_regs __iomem *td = mp->tx_dma;
  722. volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
  723. volatile struct dbdma_cmd *cp;
  724. unsigned long flags;
  725. int i;
  726. spin_lock_irqsave(&mp->lock, flags);
  727. mp->timeout_active = 0;
  728. if (mp->tx_active == 0 && !mp->tx_bad_runt)
  729. goto out;
  730. /* update various counters */
  731. mace_handle_misc_intrs(mp, in_8(&mb->ir));
  732. cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
  733. /* turn off both tx and rx and reset the chip */
  734. out_8(&mb->maccc, 0);
  735. printk(KERN_ERR "mace: transmit timeout - resetting\n");
  736. dbdma_reset(td);
  737. mace_reset(dev);
  738. /* restart rx dma */
  739. cp = bus_to_virt(ld_le32(&rd->cmdptr));
  740. dbdma_reset(rd);
  741. out_le16(&cp->xfer_status, 0);
  742. out_le32(&rd->cmdptr, virt_to_bus(cp));
  743. out_le32(&rd->control, (RUN << 16) | RUN);
  744. /* fix up the transmit side */
  745. i = mp->tx_empty;
  746. mp->tx_active = 0;
  747. ++mp->stats.tx_errors;
  748. if (mp->tx_bad_runt) {
  749. mp->tx_bad_runt = 0;
  750. } else if (i != mp->tx_fill) {
  751. dev_kfree_skb(mp->tx_bufs[i]);
  752. if (++i >= N_TX_RING)
  753. i = 0;
  754. mp->tx_empty = i;
  755. }
  756. mp->tx_fullup = 0;
  757. netif_wake_queue(dev);
  758. if (i != mp->tx_fill) {
  759. cp = mp->tx_cmds + NCMDS_TX * i;
  760. out_le16(&cp->xfer_status, 0);
  761. out_le16(&cp->command, OUTPUT_LAST);
  762. out_le32(&td->cmdptr, virt_to_bus(cp));
  763. out_le32(&td->control, (RUN << 16) | RUN);
  764. ++mp->tx_active;
  765. mace_set_timeout(dev);
  766. }
  767. /* turn it back on */
  768. out_8(&mb->imr, RCVINT);
  769. out_8(&mb->maccc, mp->maccc);
  770. out:
  771. spin_unlock_irqrestore(&mp->lock, flags);
  772. }
  773. static irqreturn_t mace_txdma_intr(int irq, void *dev_id)
  774. {
  775. return IRQ_HANDLED;
  776. }
  777. static irqreturn_t mace_rxdma_intr(int irq, void *dev_id)
  778. {
  779. struct net_device *dev = (struct net_device *) dev_id;
  780. struct mace_data *mp = (struct mace_data *) dev->priv;
  781. volatile struct dbdma_regs __iomem *rd = mp->rx_dma;
  782. volatile struct dbdma_cmd *cp, *np;
  783. int i, nb, stat, next;
  784. struct sk_buff *skb;
  785. unsigned frame_status;
  786. static int mace_lost_status;
  787. unsigned char *data;
  788. unsigned long flags;
  789. spin_lock_irqsave(&mp->lock, flags);
  790. for (i = mp->rx_empty; i != mp->rx_fill; ) {
  791. cp = mp->rx_cmds + i;
  792. stat = ld_le16(&cp->xfer_status);
  793. if ((stat & ACTIVE) == 0) {
  794. next = i + 1;
  795. if (next >= N_RX_RING)
  796. next = 0;
  797. np = mp->rx_cmds + next;
  798. if (next != mp->rx_fill
  799. && (ld_le16(&np->xfer_status) & ACTIVE) != 0) {
  800. printk(KERN_DEBUG "mace: lost a status word\n");
  801. ++mace_lost_status;
  802. } else
  803. break;
  804. }
  805. nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count);
  806. out_le16(&cp->command, DBDMA_STOP);
  807. /* got a packet, have a look at it */
  808. skb = mp->rx_bufs[i];
  809. if (skb == 0) {
  810. ++mp->stats.rx_dropped;
  811. } else if (nb > 8) {
  812. data = skb->data;
  813. frame_status = (data[nb-3] << 8) + data[nb-4];
  814. if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
  815. ++mp->stats.rx_errors;
  816. if (frame_status & RS_OFLO)
  817. ++mp->stats.rx_over_errors;
  818. if (frame_status & RS_FRAMERR)
  819. ++mp->stats.rx_frame_errors;
  820. if (frame_status & RS_FCSERR)
  821. ++mp->stats.rx_crc_errors;
  822. } else {
  823. /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
  824. * FCS on frames with 802.3 headers. This means that Ethernet
  825. * frames have 8 extra octets at the end, while 802.3 frames
  826. * have only 4. We need to correctly account for this. */
  827. if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
  828. nb -= 4;
  829. else /* Ethernet header; mace includes FCS */
  830. nb -= 8;
  831. skb_put(skb, nb);
  832. skb->dev = dev;
  833. skb->protocol = eth_type_trans(skb, dev);
  834. mp->stats.rx_bytes += skb->len;
  835. netif_rx(skb);
  836. dev->last_rx = jiffies;
  837. mp->rx_bufs[i] = NULL;
  838. ++mp->stats.rx_packets;
  839. }
  840. } else {
  841. ++mp->stats.rx_errors;
  842. ++mp->stats.rx_length_errors;
  843. }
  844. /* advance to next */
  845. if (++i >= N_RX_RING)
  846. i = 0;
  847. }
  848. mp->rx_empty = i;
  849. i = mp->rx_fill;
  850. for (;;) {
  851. next = i + 1;
  852. if (next >= N_RX_RING)
  853. next = 0;
  854. if (next == mp->rx_empty)
  855. break;
  856. cp = mp->rx_cmds + i;
  857. skb = mp->rx_bufs[i];
  858. if (skb == 0) {
  859. skb = dev_alloc_skb(RX_BUFLEN + 2);
  860. if (skb != 0) {
  861. skb_reserve(skb, 2);
  862. mp->rx_bufs[i] = skb;
  863. }
  864. }
  865. st_le16(&cp->req_count, RX_BUFLEN);
  866. data = skb? skb->data: dummy_buf;
  867. st_le32(&cp->phy_addr, virt_to_bus(data));
  868. out_le16(&cp->xfer_status, 0);
  869. out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
  870. #if 0
  871. if ((ld_le32(&rd->status) & ACTIVE) != 0) {
  872. out_le32(&rd->control, (PAUSE << 16) | PAUSE);
  873. while ((in_le32(&rd->status) & ACTIVE) != 0)
  874. ;
  875. }
  876. #endif
  877. i = next;
  878. }
  879. if (i != mp->rx_fill) {
  880. out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
  881. mp->rx_fill = i;
  882. }
  883. spin_unlock_irqrestore(&mp->lock, flags);
  884. return IRQ_HANDLED;
  885. }
  886. static struct of_device_id mace_match[] =
  887. {
  888. {
  889. .name = "mace",
  890. },
  891. {},
  892. };
  893. MODULE_DEVICE_TABLE (of, mace_match);
  894. static struct macio_driver mace_driver =
  895. {
  896. .name = "mace",
  897. .match_table = mace_match,
  898. .probe = mace_probe,
  899. .remove = mace_remove,
  900. };
  901. static int __init mace_init(void)
  902. {
  903. return macio_register_driver(&mace_driver);
  904. }
  905. static void __exit mace_cleanup(void)
  906. {
  907. macio_unregister_driver(&mace_driver);
  908. kfree(dummy_buf);
  909. dummy_buf = NULL;
  910. }
  911. MODULE_AUTHOR("Paul Mackerras");
  912. MODULE_DESCRIPTION("PowerMac MACE driver.");
  913. module_param(port_aaui, int, 0);
  914. MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
  915. MODULE_LICENSE("GPL");
  916. module_init(mace_init);
  917. module_exit(mace_cleanup);