macb.c 28 KB

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  1. /*
  2. * Atmel MACB Ethernet Controller driver
  3. *
  4. * Copyright (C) 2004-2006 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/slab.h>
  16. #include <linux/init.h>
  17. #include <linux/netdevice.h>
  18. #include <linux/etherdevice.h>
  19. #include <linux/mii.h>
  20. #include <linux/mutex.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/ethtool.h>
  23. #include <linux/platform_device.h>
  24. #include <asm/arch/board.h>
  25. #include "macb.h"
  26. #define RX_BUFFER_SIZE 128
  27. #define RX_RING_SIZE 512
  28. #define RX_RING_BYTES (sizeof(struct dma_desc) * RX_RING_SIZE)
  29. /* Make the IP header word-aligned (the ethernet header is 14 bytes) */
  30. #define RX_OFFSET 2
  31. #define TX_RING_SIZE 128
  32. #define DEF_TX_RING_PENDING (TX_RING_SIZE - 1)
  33. #define TX_RING_BYTES (sizeof(struct dma_desc) * TX_RING_SIZE)
  34. #define TX_RING_GAP(bp) \
  35. (TX_RING_SIZE - (bp)->tx_pending)
  36. #define TX_BUFFS_AVAIL(bp) \
  37. (((bp)->tx_tail <= (bp)->tx_head) ? \
  38. (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head : \
  39. (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
  40. #define NEXT_TX(n) (((n) + 1) & (TX_RING_SIZE - 1))
  41. #define NEXT_RX(n) (((n) + 1) & (RX_RING_SIZE - 1))
  42. /* minimum number of free TX descriptors before waking up TX process */
  43. #define MACB_TX_WAKEUP_THRESH (TX_RING_SIZE / 4)
  44. #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
  45. | MACB_BIT(ISR_ROVR))
  46. static void __macb_set_hwaddr(struct macb *bp)
  47. {
  48. u32 bottom;
  49. u16 top;
  50. bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
  51. macb_writel(bp, SA1B, bottom);
  52. top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
  53. macb_writel(bp, SA1T, top);
  54. }
  55. static void __init macb_get_hwaddr(struct macb *bp)
  56. {
  57. u32 bottom;
  58. u16 top;
  59. u8 addr[6];
  60. bottom = macb_readl(bp, SA1B);
  61. top = macb_readl(bp, SA1T);
  62. addr[0] = bottom & 0xff;
  63. addr[1] = (bottom >> 8) & 0xff;
  64. addr[2] = (bottom >> 16) & 0xff;
  65. addr[3] = (bottom >> 24) & 0xff;
  66. addr[4] = top & 0xff;
  67. addr[5] = (top >> 8) & 0xff;
  68. if (is_valid_ether_addr(addr))
  69. memcpy(bp->dev->dev_addr, addr, sizeof(addr));
  70. }
  71. static void macb_enable_mdio(struct macb *bp)
  72. {
  73. unsigned long flags;
  74. u32 reg;
  75. spin_lock_irqsave(&bp->lock, flags);
  76. reg = macb_readl(bp, NCR);
  77. reg |= MACB_BIT(MPE);
  78. macb_writel(bp, NCR, reg);
  79. macb_writel(bp, IER, MACB_BIT(MFD));
  80. spin_unlock_irqrestore(&bp->lock, flags);
  81. }
  82. static void macb_disable_mdio(struct macb *bp)
  83. {
  84. unsigned long flags;
  85. u32 reg;
  86. spin_lock_irqsave(&bp->lock, flags);
  87. reg = macb_readl(bp, NCR);
  88. reg &= ~MACB_BIT(MPE);
  89. macb_writel(bp, NCR, reg);
  90. macb_writel(bp, IDR, MACB_BIT(MFD));
  91. spin_unlock_irqrestore(&bp->lock, flags);
  92. }
  93. static int macb_mdio_read(struct net_device *dev, int phy_id, int location)
  94. {
  95. struct macb *bp = netdev_priv(dev);
  96. int value;
  97. mutex_lock(&bp->mdio_mutex);
  98. macb_enable_mdio(bp);
  99. macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
  100. | MACB_BF(RW, MACB_MAN_READ)
  101. | MACB_BF(PHYA, phy_id)
  102. | MACB_BF(REGA, location)
  103. | MACB_BF(CODE, MACB_MAN_CODE)));
  104. wait_for_completion(&bp->mdio_complete);
  105. value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
  106. macb_disable_mdio(bp);
  107. mutex_unlock(&bp->mdio_mutex);
  108. return value;
  109. }
  110. static void macb_mdio_write(struct net_device *dev, int phy_id,
  111. int location, int val)
  112. {
  113. struct macb *bp = netdev_priv(dev);
  114. dev_dbg(&bp->pdev->dev, "mdio_write %02x:%02x <- %04x\n",
  115. phy_id, location, val);
  116. mutex_lock(&bp->mdio_mutex);
  117. macb_enable_mdio(bp);
  118. macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
  119. | MACB_BF(RW, MACB_MAN_WRITE)
  120. | MACB_BF(PHYA, phy_id)
  121. | MACB_BF(REGA, location)
  122. | MACB_BF(CODE, MACB_MAN_CODE)
  123. | MACB_BF(DATA, val)));
  124. wait_for_completion(&bp->mdio_complete);
  125. macb_disable_mdio(bp);
  126. mutex_unlock(&bp->mdio_mutex);
  127. }
  128. static int macb_phy_probe(struct macb *bp)
  129. {
  130. int phy_address;
  131. u16 phyid1, phyid2;
  132. for (phy_address = 0; phy_address < 32; phy_address++) {
  133. phyid1 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID1);
  134. phyid2 = macb_mdio_read(bp->dev, phy_address, MII_PHYSID2);
  135. if (phyid1 != 0xffff && phyid1 != 0x0000
  136. && phyid2 != 0xffff && phyid2 != 0x0000)
  137. break;
  138. }
  139. if (phy_address == 32)
  140. return -ENODEV;
  141. dev_info(&bp->pdev->dev,
  142. "detected PHY at address %d (ID %04x:%04x)\n",
  143. phy_address, phyid1, phyid2);
  144. bp->mii.phy_id = phy_address;
  145. return 0;
  146. }
  147. static void macb_set_media(struct macb *bp, int media)
  148. {
  149. u32 reg;
  150. spin_lock_irq(&bp->lock);
  151. reg = macb_readl(bp, NCFGR);
  152. reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
  153. if (media & (ADVERTISE_100HALF | ADVERTISE_100FULL))
  154. reg |= MACB_BIT(SPD);
  155. if (media & ADVERTISE_FULL)
  156. reg |= MACB_BIT(FD);
  157. macb_writel(bp, NCFGR, reg);
  158. spin_unlock_irq(&bp->lock);
  159. }
  160. static void macb_check_media(struct macb *bp, int ok_to_print, int init_media)
  161. {
  162. struct mii_if_info *mii = &bp->mii;
  163. unsigned int old_carrier, new_carrier;
  164. int advertise, lpa, media, duplex;
  165. /* if forced media, go no further */
  166. if (mii->force_media)
  167. return;
  168. /* check current and old link status */
  169. old_carrier = netif_carrier_ok(mii->dev) ? 1 : 0;
  170. new_carrier = (unsigned int) mii_link_ok(mii);
  171. /* if carrier state did not change, assume nothing else did */
  172. if (!init_media && old_carrier == new_carrier)
  173. return;
  174. /* no carrier, nothing much to do */
  175. if (!new_carrier) {
  176. netif_carrier_off(mii->dev);
  177. printk(KERN_INFO "%s: link down\n", mii->dev->name);
  178. return;
  179. }
  180. /*
  181. * we have carrier, see who's on the other end
  182. */
  183. netif_carrier_on(mii->dev);
  184. /* get MII advertise and LPA values */
  185. if (!init_media && mii->advertising) {
  186. advertise = mii->advertising;
  187. } else {
  188. advertise = mii->mdio_read(mii->dev, mii->phy_id, MII_ADVERTISE);
  189. mii->advertising = advertise;
  190. }
  191. lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
  192. /* figure out media and duplex from advertise and LPA values */
  193. media = mii_nway_result(lpa & advertise);
  194. duplex = (media & ADVERTISE_FULL) ? 1 : 0;
  195. if (ok_to_print)
  196. printk(KERN_INFO "%s: link up, %sMbps, %s-duplex, lpa 0x%04X\n",
  197. mii->dev->name,
  198. media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? "100" : "10",
  199. duplex ? "full" : "half", lpa);
  200. mii->full_duplex = duplex;
  201. /* Let the MAC know about the new link state */
  202. macb_set_media(bp, media);
  203. }
  204. static void macb_update_stats(struct macb *bp)
  205. {
  206. u32 __iomem *reg = bp->regs + MACB_PFR;
  207. u32 *p = &bp->hw_stats.rx_pause_frames;
  208. u32 *end = &bp->hw_stats.tx_pause_frames + 1;
  209. WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
  210. for(; p < end; p++, reg++)
  211. *p += __raw_readl(reg);
  212. }
  213. static void macb_periodic_task(struct work_struct *work)
  214. {
  215. struct macb *bp = container_of(work, struct macb, periodic_task.work);
  216. macb_update_stats(bp);
  217. macb_check_media(bp, 1, 0);
  218. schedule_delayed_work(&bp->periodic_task, HZ);
  219. }
  220. static void macb_tx(struct macb *bp)
  221. {
  222. unsigned int tail;
  223. unsigned int head;
  224. u32 status;
  225. status = macb_readl(bp, TSR);
  226. macb_writel(bp, TSR, status);
  227. dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
  228. (unsigned long)status);
  229. if (status & MACB_BIT(UND)) {
  230. printk(KERN_ERR "%s: TX underrun, resetting buffers\n",
  231. bp->dev->name);
  232. bp->tx_head = bp->tx_tail = 0;
  233. }
  234. if (!(status & MACB_BIT(COMP)))
  235. /*
  236. * This may happen when a buffer becomes complete
  237. * between reading the ISR and scanning the
  238. * descriptors. Nothing to worry about.
  239. */
  240. return;
  241. head = bp->tx_head;
  242. for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
  243. struct ring_info *rp = &bp->tx_skb[tail];
  244. struct sk_buff *skb = rp->skb;
  245. u32 bufstat;
  246. BUG_ON(skb == NULL);
  247. rmb();
  248. bufstat = bp->tx_ring[tail].ctrl;
  249. if (!(bufstat & MACB_BIT(TX_USED)))
  250. break;
  251. dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
  252. tail, skb->data);
  253. dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
  254. DMA_TO_DEVICE);
  255. bp->stats.tx_packets++;
  256. bp->stats.tx_bytes += skb->len;
  257. rp->skb = NULL;
  258. dev_kfree_skb_irq(skb);
  259. }
  260. bp->tx_tail = tail;
  261. if (netif_queue_stopped(bp->dev) &&
  262. TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
  263. netif_wake_queue(bp->dev);
  264. }
  265. static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
  266. unsigned int last_frag)
  267. {
  268. unsigned int len;
  269. unsigned int frag;
  270. unsigned int offset = 0;
  271. struct sk_buff *skb;
  272. len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
  273. dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
  274. first_frag, last_frag, len);
  275. skb = dev_alloc_skb(len + RX_OFFSET);
  276. if (!skb) {
  277. bp->stats.rx_dropped++;
  278. for (frag = first_frag; ; frag = NEXT_RX(frag)) {
  279. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  280. if (frag == last_frag)
  281. break;
  282. }
  283. wmb();
  284. return 1;
  285. }
  286. skb_reserve(skb, RX_OFFSET);
  287. skb->dev = bp->dev;
  288. skb->ip_summed = CHECKSUM_NONE;
  289. skb_put(skb, len);
  290. for (frag = first_frag; ; frag = NEXT_RX(frag)) {
  291. unsigned int frag_len = RX_BUFFER_SIZE;
  292. if (offset + frag_len > len) {
  293. BUG_ON(frag != last_frag);
  294. frag_len = len - offset;
  295. }
  296. memcpy(skb->data + offset,
  297. bp->rx_buffers + (RX_BUFFER_SIZE * frag),
  298. frag_len);
  299. offset += RX_BUFFER_SIZE;
  300. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  301. wmb();
  302. if (frag == last_frag)
  303. break;
  304. }
  305. skb->protocol = eth_type_trans(skb, bp->dev);
  306. bp->stats.rx_packets++;
  307. bp->stats.rx_bytes += len;
  308. bp->dev->last_rx = jiffies;
  309. dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
  310. skb->len, skb->csum);
  311. netif_receive_skb(skb);
  312. return 0;
  313. }
  314. /* Mark DMA descriptors from begin up to and not including end as unused */
  315. static void discard_partial_frame(struct macb *bp, unsigned int begin,
  316. unsigned int end)
  317. {
  318. unsigned int frag;
  319. for (frag = begin; frag != end; frag = NEXT_RX(frag))
  320. bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
  321. wmb();
  322. /*
  323. * When this happens, the hardware stats registers for
  324. * whatever caused this is updated, so we don't have to record
  325. * anything.
  326. */
  327. }
  328. static int macb_rx(struct macb *bp, int budget)
  329. {
  330. int received = 0;
  331. unsigned int tail = bp->rx_tail;
  332. int first_frag = -1;
  333. for (; budget > 0; tail = NEXT_RX(tail)) {
  334. u32 addr, ctrl;
  335. rmb();
  336. addr = bp->rx_ring[tail].addr;
  337. ctrl = bp->rx_ring[tail].ctrl;
  338. if (!(addr & MACB_BIT(RX_USED)))
  339. break;
  340. if (ctrl & MACB_BIT(RX_SOF)) {
  341. if (first_frag != -1)
  342. discard_partial_frame(bp, first_frag, tail);
  343. first_frag = tail;
  344. }
  345. if (ctrl & MACB_BIT(RX_EOF)) {
  346. int dropped;
  347. BUG_ON(first_frag == -1);
  348. dropped = macb_rx_frame(bp, first_frag, tail);
  349. first_frag = -1;
  350. if (!dropped) {
  351. received++;
  352. budget--;
  353. }
  354. }
  355. }
  356. if (first_frag != -1)
  357. bp->rx_tail = first_frag;
  358. else
  359. bp->rx_tail = tail;
  360. return received;
  361. }
  362. static int macb_poll(struct net_device *dev, int *budget)
  363. {
  364. struct macb *bp = netdev_priv(dev);
  365. int orig_budget, work_done, retval = 0;
  366. u32 status;
  367. status = macb_readl(bp, RSR);
  368. macb_writel(bp, RSR, status);
  369. if (!status) {
  370. /*
  371. * This may happen if an interrupt was pending before
  372. * this function was called last time, and no packets
  373. * have been received since.
  374. */
  375. netif_rx_complete(dev);
  376. goto out;
  377. }
  378. dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
  379. (unsigned long)status, *budget);
  380. if (!(status & MACB_BIT(REC))) {
  381. dev_warn(&bp->pdev->dev,
  382. "No RX buffers complete, status = %02lx\n",
  383. (unsigned long)status);
  384. netif_rx_complete(dev);
  385. goto out;
  386. }
  387. orig_budget = *budget;
  388. if (orig_budget > dev->quota)
  389. orig_budget = dev->quota;
  390. work_done = macb_rx(bp, orig_budget);
  391. if (work_done < orig_budget) {
  392. netif_rx_complete(dev);
  393. retval = 0;
  394. } else {
  395. retval = 1;
  396. }
  397. /*
  398. * We've done what we can to clean the buffers. Make sure we
  399. * get notified when new packets arrive.
  400. */
  401. out:
  402. macb_writel(bp, IER, MACB_RX_INT_FLAGS);
  403. /* TODO: Handle errors */
  404. return retval;
  405. }
  406. static irqreturn_t macb_interrupt(int irq, void *dev_id)
  407. {
  408. struct net_device *dev = dev_id;
  409. struct macb *bp = netdev_priv(dev);
  410. u32 status;
  411. status = macb_readl(bp, ISR);
  412. if (unlikely(!status))
  413. return IRQ_NONE;
  414. spin_lock(&bp->lock);
  415. while (status) {
  416. if (status & MACB_BIT(MFD))
  417. complete(&bp->mdio_complete);
  418. /* close possible race with dev_close */
  419. if (unlikely(!netif_running(dev))) {
  420. macb_writel(bp, IDR, ~0UL);
  421. break;
  422. }
  423. if (status & MACB_RX_INT_FLAGS) {
  424. if (netif_rx_schedule_prep(dev)) {
  425. /*
  426. * There's no point taking any more interrupts
  427. * until we have processed the buffers
  428. */
  429. macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
  430. dev_dbg(&bp->pdev->dev, "scheduling RX softirq\n");
  431. __netif_rx_schedule(dev);
  432. }
  433. }
  434. if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND)))
  435. macb_tx(bp);
  436. /*
  437. * Link change detection isn't possible with RMII, so we'll
  438. * add that if/when we get our hands on a full-blown MII PHY.
  439. */
  440. if (status & MACB_BIT(HRESP)) {
  441. /*
  442. * TODO: Reset the hardware, and maybe move the printk
  443. * to a lower-priority context as well (work queue?)
  444. */
  445. printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
  446. dev->name);
  447. }
  448. status = macb_readl(bp, ISR);
  449. }
  450. spin_unlock(&bp->lock);
  451. return IRQ_HANDLED;
  452. }
  453. static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
  454. {
  455. struct macb *bp = netdev_priv(dev);
  456. dma_addr_t mapping;
  457. unsigned int len, entry;
  458. u32 ctrl;
  459. #ifdef DEBUG
  460. int i;
  461. dev_dbg(&bp->pdev->dev,
  462. "start_xmit: len %u head %p data %p tail %p end %p\n",
  463. skb->len, skb->head, skb->data, skb->tail, skb->end);
  464. dev_dbg(&bp->pdev->dev,
  465. "data:");
  466. for (i = 0; i < 16; i++)
  467. printk(" %02x", (unsigned int)skb->data[i]);
  468. printk("\n");
  469. #endif
  470. len = skb->len;
  471. spin_lock_irq(&bp->lock);
  472. /* This is a hard error, log it. */
  473. if (TX_BUFFS_AVAIL(bp) < 1) {
  474. netif_stop_queue(dev);
  475. spin_unlock_irq(&bp->lock);
  476. dev_err(&bp->pdev->dev,
  477. "BUG! Tx Ring full when queue awake!\n");
  478. dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
  479. bp->tx_head, bp->tx_tail);
  480. return 1;
  481. }
  482. entry = bp->tx_head;
  483. dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
  484. mapping = dma_map_single(&bp->pdev->dev, skb->data,
  485. len, DMA_TO_DEVICE);
  486. bp->tx_skb[entry].skb = skb;
  487. bp->tx_skb[entry].mapping = mapping;
  488. dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
  489. skb->data, (unsigned long)mapping);
  490. ctrl = MACB_BF(TX_FRMLEN, len);
  491. ctrl |= MACB_BIT(TX_LAST);
  492. if (entry == (TX_RING_SIZE - 1))
  493. ctrl |= MACB_BIT(TX_WRAP);
  494. bp->tx_ring[entry].addr = mapping;
  495. bp->tx_ring[entry].ctrl = ctrl;
  496. wmb();
  497. entry = NEXT_TX(entry);
  498. bp->tx_head = entry;
  499. macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
  500. if (TX_BUFFS_AVAIL(bp) < 1)
  501. netif_stop_queue(dev);
  502. spin_unlock_irq(&bp->lock);
  503. dev->trans_start = jiffies;
  504. return 0;
  505. }
  506. static void macb_free_consistent(struct macb *bp)
  507. {
  508. if (bp->tx_skb) {
  509. kfree(bp->tx_skb);
  510. bp->tx_skb = NULL;
  511. }
  512. if (bp->rx_ring) {
  513. dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
  514. bp->rx_ring, bp->rx_ring_dma);
  515. bp->rx_ring = NULL;
  516. }
  517. if (bp->tx_ring) {
  518. dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
  519. bp->tx_ring, bp->tx_ring_dma);
  520. bp->tx_ring = NULL;
  521. }
  522. if (bp->rx_buffers) {
  523. dma_free_coherent(&bp->pdev->dev,
  524. RX_RING_SIZE * RX_BUFFER_SIZE,
  525. bp->rx_buffers, bp->rx_buffers_dma);
  526. bp->rx_buffers = NULL;
  527. }
  528. }
  529. static int macb_alloc_consistent(struct macb *bp)
  530. {
  531. int size;
  532. size = TX_RING_SIZE * sizeof(struct ring_info);
  533. bp->tx_skb = kmalloc(size, GFP_KERNEL);
  534. if (!bp->tx_skb)
  535. goto out_err;
  536. size = RX_RING_BYTES;
  537. bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
  538. &bp->rx_ring_dma, GFP_KERNEL);
  539. if (!bp->rx_ring)
  540. goto out_err;
  541. dev_dbg(&bp->pdev->dev,
  542. "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
  543. size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
  544. size = TX_RING_BYTES;
  545. bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
  546. &bp->tx_ring_dma, GFP_KERNEL);
  547. if (!bp->tx_ring)
  548. goto out_err;
  549. dev_dbg(&bp->pdev->dev,
  550. "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
  551. size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
  552. size = RX_RING_SIZE * RX_BUFFER_SIZE;
  553. bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
  554. &bp->rx_buffers_dma, GFP_KERNEL);
  555. if (!bp->rx_buffers)
  556. goto out_err;
  557. dev_dbg(&bp->pdev->dev,
  558. "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
  559. size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
  560. return 0;
  561. out_err:
  562. macb_free_consistent(bp);
  563. return -ENOMEM;
  564. }
  565. static void macb_init_rings(struct macb *bp)
  566. {
  567. int i;
  568. dma_addr_t addr;
  569. addr = bp->rx_buffers_dma;
  570. for (i = 0; i < RX_RING_SIZE; i++) {
  571. bp->rx_ring[i].addr = addr;
  572. bp->rx_ring[i].ctrl = 0;
  573. addr += RX_BUFFER_SIZE;
  574. }
  575. bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
  576. for (i = 0; i < TX_RING_SIZE; i++) {
  577. bp->tx_ring[i].addr = 0;
  578. bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
  579. }
  580. bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
  581. bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
  582. }
  583. static void macb_reset_hw(struct macb *bp)
  584. {
  585. /* Make sure we have the write buffer for ourselves */
  586. wmb();
  587. /*
  588. * Disable RX and TX (XXX: Should we halt the transmission
  589. * more gracefully?)
  590. */
  591. macb_writel(bp, NCR, 0);
  592. /* Clear the stats registers (XXX: Update stats first?) */
  593. macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
  594. /* Clear all status flags */
  595. macb_writel(bp, TSR, ~0UL);
  596. macb_writel(bp, RSR, ~0UL);
  597. /* Disable all interrupts */
  598. macb_writel(bp, IDR, ~0UL);
  599. macb_readl(bp, ISR);
  600. }
  601. static void macb_init_hw(struct macb *bp)
  602. {
  603. u32 config;
  604. macb_reset_hw(bp);
  605. __macb_set_hwaddr(bp);
  606. config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
  607. config |= MACB_BIT(PAE); /* PAuse Enable */
  608. config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
  609. if (bp->dev->flags & IFF_PROMISC)
  610. config |= MACB_BIT(CAF); /* Copy All Frames */
  611. if (!(bp->dev->flags & IFF_BROADCAST))
  612. config |= MACB_BIT(NBC); /* No BroadCast */
  613. macb_writel(bp, NCFGR, config);
  614. /* Initialize TX and RX buffers */
  615. macb_writel(bp, RBQP, bp->rx_ring_dma);
  616. macb_writel(bp, TBQP, bp->tx_ring_dma);
  617. /* Enable TX and RX */
  618. macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE));
  619. /* Enable interrupts */
  620. macb_writel(bp, IER, (MACB_BIT(RCOMP)
  621. | MACB_BIT(RXUBR)
  622. | MACB_BIT(ISR_TUND)
  623. | MACB_BIT(ISR_RLE)
  624. | MACB_BIT(TXERR)
  625. | MACB_BIT(TCOMP)
  626. | MACB_BIT(ISR_ROVR)
  627. | MACB_BIT(HRESP)));
  628. }
  629. static void macb_init_phy(struct net_device *dev)
  630. {
  631. struct macb *bp = netdev_priv(dev);
  632. /* Set some reasonable default settings */
  633. macb_mdio_write(dev, bp->mii.phy_id, MII_ADVERTISE,
  634. ADVERTISE_CSMA | ADVERTISE_ALL);
  635. macb_mdio_write(dev, bp->mii.phy_id, MII_BMCR,
  636. (BMCR_SPEED100 | BMCR_ANENABLE
  637. | BMCR_ANRESTART | BMCR_FULLDPLX));
  638. }
  639. static int macb_open(struct net_device *dev)
  640. {
  641. struct macb *bp = netdev_priv(dev);
  642. int err;
  643. dev_dbg(&bp->pdev->dev, "open\n");
  644. if (!is_valid_ether_addr(dev->dev_addr))
  645. return -EADDRNOTAVAIL;
  646. err = macb_alloc_consistent(bp);
  647. if (err) {
  648. printk(KERN_ERR
  649. "%s: Unable to allocate DMA memory (error %d)\n",
  650. dev->name, err);
  651. return err;
  652. }
  653. macb_init_rings(bp);
  654. macb_init_hw(bp);
  655. macb_init_phy(dev);
  656. macb_check_media(bp, 1, 1);
  657. netif_start_queue(dev);
  658. schedule_delayed_work(&bp->periodic_task, HZ);
  659. return 0;
  660. }
  661. static int macb_close(struct net_device *dev)
  662. {
  663. struct macb *bp = netdev_priv(dev);
  664. unsigned long flags;
  665. cancel_rearming_delayed_work(&bp->periodic_task);
  666. netif_stop_queue(dev);
  667. spin_lock_irqsave(&bp->lock, flags);
  668. macb_reset_hw(bp);
  669. netif_carrier_off(dev);
  670. spin_unlock_irqrestore(&bp->lock, flags);
  671. macb_free_consistent(bp);
  672. return 0;
  673. }
  674. static struct net_device_stats *macb_get_stats(struct net_device *dev)
  675. {
  676. struct macb *bp = netdev_priv(dev);
  677. struct net_device_stats *nstat = &bp->stats;
  678. struct macb_stats *hwstat = &bp->hw_stats;
  679. /* Convert HW stats into netdevice stats */
  680. nstat->rx_errors = (hwstat->rx_fcs_errors +
  681. hwstat->rx_align_errors +
  682. hwstat->rx_resource_errors +
  683. hwstat->rx_overruns +
  684. hwstat->rx_oversize_pkts +
  685. hwstat->rx_jabbers +
  686. hwstat->rx_undersize_pkts +
  687. hwstat->sqe_test_errors +
  688. hwstat->rx_length_mismatch);
  689. nstat->tx_errors = (hwstat->tx_late_cols +
  690. hwstat->tx_excessive_cols +
  691. hwstat->tx_underruns +
  692. hwstat->tx_carrier_errors);
  693. nstat->collisions = (hwstat->tx_single_cols +
  694. hwstat->tx_multiple_cols +
  695. hwstat->tx_excessive_cols);
  696. nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
  697. hwstat->rx_jabbers +
  698. hwstat->rx_undersize_pkts +
  699. hwstat->rx_length_mismatch);
  700. nstat->rx_over_errors = hwstat->rx_resource_errors;
  701. nstat->rx_crc_errors = hwstat->rx_fcs_errors;
  702. nstat->rx_frame_errors = hwstat->rx_align_errors;
  703. nstat->rx_fifo_errors = hwstat->rx_overruns;
  704. /* XXX: What does "missed" mean? */
  705. nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
  706. nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
  707. nstat->tx_fifo_errors = hwstat->tx_underruns;
  708. /* Don't know about heartbeat or window errors... */
  709. return nstat;
  710. }
  711. static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  712. {
  713. struct macb *bp = netdev_priv(dev);
  714. return mii_ethtool_gset(&bp->mii, cmd);
  715. }
  716. static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  717. {
  718. struct macb *bp = netdev_priv(dev);
  719. return mii_ethtool_sset(&bp->mii, cmd);
  720. }
  721. static void macb_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  722. {
  723. struct macb *bp = netdev_priv(dev);
  724. strcpy(info->driver, bp->pdev->dev.driver->name);
  725. strcpy(info->version, "$Revision: 1.1.1.1 $");
  726. strcpy(info->bus_info, bp->pdev->dev.bus_id);
  727. }
  728. static int macb_nway_reset(struct net_device *dev)
  729. {
  730. struct macb *bp = netdev_priv(dev);
  731. return mii_nway_restart(&bp->mii);
  732. }
  733. static struct ethtool_ops macb_ethtool_ops = {
  734. .get_settings = macb_get_settings,
  735. .set_settings = macb_set_settings,
  736. .get_drvinfo = macb_get_drvinfo,
  737. .nway_reset = macb_nway_reset,
  738. .get_link = ethtool_op_get_link,
  739. };
  740. static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  741. {
  742. struct macb *bp = netdev_priv(dev);
  743. if (!netif_running(dev))
  744. return -EINVAL;
  745. return generic_mii_ioctl(&bp->mii, if_mii(rq), cmd, NULL);
  746. }
  747. static ssize_t macb_mii_show(const struct device *_dev, char *buf,
  748. unsigned long addr)
  749. {
  750. struct net_device *dev = to_net_dev(_dev);
  751. struct macb *bp = netdev_priv(dev);
  752. ssize_t ret = -EINVAL;
  753. if (netif_running(dev)) {
  754. int value;
  755. value = macb_mdio_read(dev, bp->mii.phy_id, addr);
  756. ret = sprintf(buf, "0x%04x\n", (uint16_t)value);
  757. }
  758. return ret;
  759. }
  760. #define MII_ENTRY(name, addr) \
  761. static ssize_t show_##name(struct device *_dev, \
  762. struct device_attribute *attr, \
  763. char *buf) \
  764. { \
  765. return macb_mii_show(_dev, buf, addr); \
  766. } \
  767. static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
  768. MII_ENTRY(bmcr, MII_BMCR);
  769. MII_ENTRY(bmsr, MII_BMSR);
  770. MII_ENTRY(physid1, MII_PHYSID1);
  771. MII_ENTRY(physid2, MII_PHYSID2);
  772. MII_ENTRY(advertise, MII_ADVERTISE);
  773. MII_ENTRY(lpa, MII_LPA);
  774. MII_ENTRY(expansion, MII_EXPANSION);
  775. static struct attribute *macb_mii_attrs[] = {
  776. &dev_attr_bmcr.attr,
  777. &dev_attr_bmsr.attr,
  778. &dev_attr_physid1.attr,
  779. &dev_attr_physid2.attr,
  780. &dev_attr_advertise.attr,
  781. &dev_attr_lpa.attr,
  782. &dev_attr_expansion.attr,
  783. NULL,
  784. };
  785. static struct attribute_group macb_mii_group = {
  786. .name = "mii",
  787. .attrs = macb_mii_attrs,
  788. };
  789. static void macb_unregister_sysfs(struct net_device *net)
  790. {
  791. struct device *_dev = &net->dev;
  792. sysfs_remove_group(&_dev->kobj, &macb_mii_group);
  793. }
  794. static int macb_register_sysfs(struct net_device *net)
  795. {
  796. struct device *_dev = &net->dev;
  797. int ret;
  798. ret = sysfs_create_group(&_dev->kobj, &macb_mii_group);
  799. if (ret)
  800. printk(KERN_WARNING
  801. "%s: sysfs mii attribute registration failed: %d\n",
  802. net->name, ret);
  803. return ret;
  804. }
  805. static int __devinit macb_probe(struct platform_device *pdev)
  806. {
  807. struct eth_platform_data *pdata;
  808. struct resource *regs;
  809. struct net_device *dev;
  810. struct macb *bp;
  811. unsigned long pclk_hz;
  812. u32 config;
  813. int err = -ENXIO;
  814. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  815. if (!regs) {
  816. dev_err(&pdev->dev, "no mmio resource defined\n");
  817. goto err_out;
  818. }
  819. err = -ENOMEM;
  820. dev = alloc_etherdev(sizeof(*bp));
  821. if (!dev) {
  822. dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
  823. goto err_out;
  824. }
  825. SET_MODULE_OWNER(dev);
  826. SET_NETDEV_DEV(dev, &pdev->dev);
  827. /* TODO: Actually, we have some interesting features... */
  828. dev->features |= 0;
  829. bp = netdev_priv(dev);
  830. bp->pdev = pdev;
  831. bp->dev = dev;
  832. spin_lock_init(&bp->lock);
  833. #if defined(CONFIG_ARCH_AT91)
  834. bp->pclk = clk_get(&pdev->dev, "macb_clk");
  835. if (IS_ERR(bp->pclk)) {
  836. dev_err(&pdev->dev, "failed to get macb_clk\n");
  837. goto err_out_free_dev;
  838. }
  839. clk_enable(bp->pclk);
  840. #else
  841. bp->pclk = clk_get(&pdev->dev, "pclk");
  842. if (IS_ERR(bp->pclk)) {
  843. dev_err(&pdev->dev, "failed to get pclk\n");
  844. goto err_out_free_dev;
  845. }
  846. bp->hclk = clk_get(&pdev->dev, "hclk");
  847. if (IS_ERR(bp->hclk)) {
  848. dev_err(&pdev->dev, "failed to get hclk\n");
  849. goto err_out_put_pclk;
  850. }
  851. clk_enable(bp->pclk);
  852. clk_enable(bp->hclk);
  853. #endif
  854. bp->regs = ioremap(regs->start, regs->end - regs->start + 1);
  855. if (!bp->regs) {
  856. dev_err(&pdev->dev, "failed to map registers, aborting.\n");
  857. err = -ENOMEM;
  858. goto err_out_disable_clocks;
  859. }
  860. dev->irq = platform_get_irq(pdev, 0);
  861. err = request_irq(dev->irq, macb_interrupt, IRQF_SAMPLE_RANDOM,
  862. dev->name, dev);
  863. if (err) {
  864. printk(KERN_ERR
  865. "%s: Unable to request IRQ %d (error %d)\n",
  866. dev->name, dev->irq, err);
  867. goto err_out_iounmap;
  868. }
  869. dev->open = macb_open;
  870. dev->stop = macb_close;
  871. dev->hard_start_xmit = macb_start_xmit;
  872. dev->get_stats = macb_get_stats;
  873. dev->do_ioctl = macb_ioctl;
  874. dev->poll = macb_poll;
  875. dev->weight = 64;
  876. dev->ethtool_ops = &macb_ethtool_ops;
  877. dev->base_addr = regs->start;
  878. INIT_DELAYED_WORK(&bp->periodic_task, macb_periodic_task);
  879. mutex_init(&bp->mdio_mutex);
  880. init_completion(&bp->mdio_complete);
  881. /* Set MII management clock divider */
  882. pclk_hz = clk_get_rate(bp->pclk);
  883. if (pclk_hz <= 20000000)
  884. config = MACB_BF(CLK, MACB_CLK_DIV8);
  885. else if (pclk_hz <= 40000000)
  886. config = MACB_BF(CLK, MACB_CLK_DIV16);
  887. else if (pclk_hz <= 80000000)
  888. config = MACB_BF(CLK, MACB_CLK_DIV32);
  889. else
  890. config = MACB_BF(CLK, MACB_CLK_DIV64);
  891. macb_writel(bp, NCFGR, config);
  892. bp->mii.dev = dev;
  893. bp->mii.mdio_read = macb_mdio_read;
  894. bp->mii.mdio_write = macb_mdio_write;
  895. bp->mii.phy_id_mask = 0x1f;
  896. bp->mii.reg_num_mask = 0x1f;
  897. macb_get_hwaddr(bp);
  898. err = macb_phy_probe(bp);
  899. if (err) {
  900. dev_err(&pdev->dev, "Failed to detect PHY, aborting.\n");
  901. goto err_out_free_irq;
  902. }
  903. pdata = pdev->dev.platform_data;
  904. if (pdata && pdata->is_rmii)
  905. #if defined(CONFIG_ARCH_AT91)
  906. macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
  907. #else
  908. macb_writel(bp, USRIO, 0);
  909. #endif
  910. else
  911. #if defined(CONFIG_ARCH_AT91)
  912. macb_writel(bp, USRIO, MACB_BIT(CLKEN));
  913. #else
  914. macb_writel(bp, USRIO, MACB_BIT(MII));
  915. #endif
  916. bp->tx_pending = DEF_TX_RING_PENDING;
  917. err = register_netdev(dev);
  918. if (err) {
  919. dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
  920. goto err_out_free_irq;
  921. }
  922. platform_set_drvdata(pdev, dev);
  923. macb_register_sysfs(dev);
  924. printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d "
  925. "(%02x:%02x:%02x:%02x:%02x:%02x)\n",
  926. dev->name, dev->base_addr, dev->irq,
  927. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  928. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  929. return 0;
  930. err_out_free_irq:
  931. free_irq(dev->irq, dev);
  932. err_out_iounmap:
  933. iounmap(bp->regs);
  934. err_out_disable_clocks:
  935. #ifndef CONFIG_ARCH_AT91
  936. clk_disable(bp->hclk);
  937. clk_put(bp->hclk);
  938. #endif
  939. clk_disable(bp->pclk);
  940. err_out_put_pclk:
  941. clk_put(bp->pclk);
  942. err_out_free_dev:
  943. free_netdev(dev);
  944. err_out:
  945. platform_set_drvdata(pdev, NULL);
  946. return err;
  947. }
  948. static int __devexit macb_remove(struct platform_device *pdev)
  949. {
  950. struct net_device *dev;
  951. struct macb *bp;
  952. dev = platform_get_drvdata(pdev);
  953. if (dev) {
  954. bp = netdev_priv(dev);
  955. macb_unregister_sysfs(dev);
  956. unregister_netdev(dev);
  957. free_irq(dev->irq, dev);
  958. iounmap(bp->regs);
  959. #ifndef CONFIG_ARCH_AT91
  960. clk_disable(bp->hclk);
  961. clk_put(bp->hclk);
  962. #endif
  963. clk_disable(bp->pclk);
  964. clk_put(bp->pclk);
  965. free_netdev(dev);
  966. platform_set_drvdata(pdev, NULL);
  967. }
  968. return 0;
  969. }
  970. static struct platform_driver macb_driver = {
  971. .probe = macb_probe,
  972. .remove = __devexit_p(macb_remove),
  973. .driver = {
  974. .name = "macb",
  975. },
  976. };
  977. static int __init macb_init(void)
  978. {
  979. return platform_driver_register(&macb_driver);
  980. }
  981. static void __exit macb_exit(void)
  982. {
  983. platform_driver_unregister(&macb_driver);
  984. }
  985. module_init(macb_init);
  986. module_exit(macb_exit);
  987. MODULE_LICENSE("GPL");
  988. MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
  989. MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");