ioc3-eth.c 43 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
  7. *
  8. * Copyright (C) 1999, 2000, 2001, 2003 Ralf Baechle
  9. * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
  10. *
  11. * References:
  12. * o IOC3 ASIC specification 4.51, 1996-04-18
  13. * o IEEE 802.3 specification, 2000 edition
  14. * o DP38840A Specification, National Semiconductor, March 1997
  15. *
  16. * To do:
  17. *
  18. * o Handle allocation failures in ioc3_alloc_skb() more gracefully.
  19. * o Handle allocation failures in ioc3_init_rings().
  20. * o Use prefetching for large packets. What is a good lower limit for
  21. * prefetching?
  22. * o We're probably allocating a bit too much memory.
  23. * o Use hardware checksums.
  24. * o Convert to using a IOC3 meta driver.
  25. * o Which PHYs might possibly be attached to the IOC3 in real live,
  26. * which workarounds are required for them? Do we ever have Lucent's?
  27. * o For the 2.5 branch kill the mii-tool ioctls.
  28. */
  29. #define IOC3_NAME "ioc3-eth"
  30. #define IOC3_VERSION "2.6.3-4"
  31. #include <linux/init.h>
  32. #include <linux/delay.h>
  33. #include <linux/kernel.h>
  34. #include <linux/mm.h>
  35. #include <linux/errno.h>
  36. #include <linux/module.h>
  37. #include <linux/pci.h>
  38. #include <linux/crc32.h>
  39. #include <linux/mii.h>
  40. #include <linux/in.h>
  41. #include <linux/ip.h>
  42. #include <linux/tcp.h>
  43. #include <linux/udp.h>
  44. #include <linux/dma-mapping.h>
  45. #ifdef CONFIG_SERIAL_8250
  46. #include <linux/serial_core.h>
  47. #include <linux/serial_8250.h>
  48. #endif
  49. #include <linux/netdevice.h>
  50. #include <linux/etherdevice.h>
  51. #include <linux/ethtool.h>
  52. #include <linux/skbuff.h>
  53. #include <net/ip.h>
  54. #include <asm/byteorder.h>
  55. #include <asm/io.h>
  56. #include <asm/pgtable.h>
  57. #include <asm/uaccess.h>
  58. #include <asm/sn/types.h>
  59. #include <asm/sn/sn0/addrs.h>
  60. #include <asm/sn/sn0/hubni.h>
  61. #include <asm/sn/sn0/hubio.h>
  62. #include <asm/sn/klconfig.h>
  63. #include <asm/sn/ioc3.h>
  64. #include <asm/sn/sn0/ip27.h>
  65. #include <asm/pci/bridge.h>
  66. /*
  67. * 64 RX buffers. This is tunable in the range of 16 <= x < 512. The
  68. * value must be a power of two.
  69. */
  70. #define RX_BUFFS 64
  71. #define ETCSR_FD ((17<<ETCSR_IPGR2_SHIFT) | (11<<ETCSR_IPGR1_SHIFT) | 21)
  72. #define ETCSR_HD ((21<<ETCSR_IPGR2_SHIFT) | (21<<ETCSR_IPGR1_SHIFT) | 21)
  73. /* Private per NIC data of the driver. */
  74. struct ioc3_private {
  75. struct ioc3 *regs;
  76. unsigned long *rxr; /* pointer to receiver ring */
  77. struct ioc3_etxd *txr;
  78. struct sk_buff *rx_skbs[512];
  79. struct sk_buff *tx_skbs[128];
  80. struct net_device_stats stats;
  81. int rx_ci; /* RX consumer index */
  82. int rx_pi; /* RX producer index */
  83. int tx_ci; /* TX consumer index */
  84. int tx_pi; /* TX producer index */
  85. int txqlen;
  86. u32 emcr, ehar_h, ehar_l;
  87. spinlock_t ioc3_lock;
  88. struct mii_if_info mii;
  89. struct pci_dev *pdev;
  90. /* Members used by autonegotiation */
  91. struct timer_list ioc3_timer;
  92. };
  93. static inline struct net_device *priv_netdev(struct ioc3_private *dev)
  94. {
  95. return (void *)dev - ((sizeof(struct net_device) + 31) & ~31);
  96. }
  97. static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  98. static void ioc3_set_multicast_list(struct net_device *dev);
  99. static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
  100. static void ioc3_timeout(struct net_device *dev);
  101. static inline unsigned int ioc3_hash(const unsigned char *addr);
  102. static inline void ioc3_stop(struct ioc3_private *ip);
  103. static void ioc3_init(struct net_device *dev);
  104. static const char ioc3_str[] = "IOC3 Ethernet";
  105. static const struct ethtool_ops ioc3_ethtool_ops;
  106. /* We use this to acquire receive skb's that we can DMA directly into. */
  107. #define IOC3_CACHELINE 128UL
  108. static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
  109. {
  110. return (~addr + 1) & (IOC3_CACHELINE - 1UL);
  111. }
  112. static inline struct sk_buff * ioc3_alloc_skb(unsigned long length,
  113. unsigned int gfp_mask)
  114. {
  115. struct sk_buff *skb;
  116. skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);
  117. if (likely(skb)) {
  118. int offset = aligned_rx_skb_addr((unsigned long) skb->data);
  119. if (offset)
  120. skb_reserve(skb, offset);
  121. }
  122. return skb;
  123. }
  124. static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
  125. {
  126. #ifdef CONFIG_SGI_IP27
  127. vdev <<= 57; /* Shift to PCI64_ATTR_VIRTUAL */
  128. return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
  129. ((unsigned long)ptr & TO_PHYS_MASK);
  130. #else
  131. return virt_to_bus(ptr);
  132. #endif
  133. }
  134. /* BEWARE: The IOC3 documentation documents the size of rx buffers as
  135. 1644 while it's actually 1664. This one was nasty to track down ... */
  136. #define RX_OFFSET 10
  137. #define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
  138. /* DMA barrier to separate cached and uncached accesses. */
  139. #define BARRIER() \
  140. __asm__("sync" ::: "memory")
  141. #define IOC3_SIZE 0x100000
  142. /*
  143. * IOC3 is a big endian device
  144. *
  145. * Unorthodox but makes the users of these macros more readable - the pointer
  146. * to the IOC3's memory mapped registers is expected as struct ioc3 * ioc3
  147. * in the environment.
  148. */
  149. #define ioc3_r_mcr() be32_to_cpu(ioc3->mcr)
  150. #define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0)
  151. #define ioc3_w_gpcr_s(v) do { ioc3->gpcr_s = cpu_to_be32(v); } while (0)
  152. #define ioc3_r_emcr() be32_to_cpu(ioc3->emcr)
  153. #define ioc3_w_emcr(v) do { ioc3->emcr = cpu_to_be32(v); } while (0)
  154. #define ioc3_r_eisr() be32_to_cpu(ioc3->eisr)
  155. #define ioc3_w_eisr(v) do { ioc3->eisr = cpu_to_be32(v); } while (0)
  156. #define ioc3_r_eier() be32_to_cpu(ioc3->eier)
  157. #define ioc3_w_eier(v) do { ioc3->eier = cpu_to_be32(v); } while (0)
  158. #define ioc3_r_ercsr() be32_to_cpu(ioc3->ercsr)
  159. #define ioc3_w_ercsr(v) do { ioc3->ercsr = cpu_to_be32(v); } while (0)
  160. #define ioc3_r_erbr_h() be32_to_cpu(ioc3->erbr_h)
  161. #define ioc3_w_erbr_h(v) do { ioc3->erbr_h = cpu_to_be32(v); } while (0)
  162. #define ioc3_r_erbr_l() be32_to_cpu(ioc3->erbr_l)
  163. #define ioc3_w_erbr_l(v) do { ioc3->erbr_l = cpu_to_be32(v); } while (0)
  164. #define ioc3_r_erbar() be32_to_cpu(ioc3->erbar)
  165. #define ioc3_w_erbar(v) do { ioc3->erbar = cpu_to_be32(v); } while (0)
  166. #define ioc3_r_ercir() be32_to_cpu(ioc3->ercir)
  167. #define ioc3_w_ercir(v) do { ioc3->ercir = cpu_to_be32(v); } while (0)
  168. #define ioc3_r_erpir() be32_to_cpu(ioc3->erpir)
  169. #define ioc3_w_erpir(v) do { ioc3->erpir = cpu_to_be32(v); } while (0)
  170. #define ioc3_r_ertr() be32_to_cpu(ioc3->ertr)
  171. #define ioc3_w_ertr(v) do { ioc3->ertr = cpu_to_be32(v); } while (0)
  172. #define ioc3_r_etcsr() be32_to_cpu(ioc3->etcsr)
  173. #define ioc3_w_etcsr(v) do { ioc3->etcsr = cpu_to_be32(v); } while (0)
  174. #define ioc3_r_ersr() be32_to_cpu(ioc3->ersr)
  175. #define ioc3_w_ersr(v) do { ioc3->ersr = cpu_to_be32(v); } while (0)
  176. #define ioc3_r_etcdc() be32_to_cpu(ioc3->etcdc)
  177. #define ioc3_w_etcdc(v) do { ioc3->etcdc = cpu_to_be32(v); } while (0)
  178. #define ioc3_r_ebir() be32_to_cpu(ioc3->ebir)
  179. #define ioc3_w_ebir(v) do { ioc3->ebir = cpu_to_be32(v); } while (0)
  180. #define ioc3_r_etbr_h() be32_to_cpu(ioc3->etbr_h)
  181. #define ioc3_w_etbr_h(v) do { ioc3->etbr_h = cpu_to_be32(v); } while (0)
  182. #define ioc3_r_etbr_l() be32_to_cpu(ioc3->etbr_l)
  183. #define ioc3_w_etbr_l(v) do { ioc3->etbr_l = cpu_to_be32(v); } while (0)
  184. #define ioc3_r_etcir() be32_to_cpu(ioc3->etcir)
  185. #define ioc3_w_etcir(v) do { ioc3->etcir = cpu_to_be32(v); } while (0)
  186. #define ioc3_r_etpir() be32_to_cpu(ioc3->etpir)
  187. #define ioc3_w_etpir(v) do { ioc3->etpir = cpu_to_be32(v); } while (0)
  188. #define ioc3_r_emar_h() be32_to_cpu(ioc3->emar_h)
  189. #define ioc3_w_emar_h(v) do { ioc3->emar_h = cpu_to_be32(v); } while (0)
  190. #define ioc3_r_emar_l() be32_to_cpu(ioc3->emar_l)
  191. #define ioc3_w_emar_l(v) do { ioc3->emar_l = cpu_to_be32(v); } while (0)
  192. #define ioc3_r_ehar_h() be32_to_cpu(ioc3->ehar_h)
  193. #define ioc3_w_ehar_h(v) do { ioc3->ehar_h = cpu_to_be32(v); } while (0)
  194. #define ioc3_r_ehar_l() be32_to_cpu(ioc3->ehar_l)
  195. #define ioc3_w_ehar_l(v) do { ioc3->ehar_l = cpu_to_be32(v); } while (0)
  196. #define ioc3_r_micr() be32_to_cpu(ioc3->micr)
  197. #define ioc3_w_micr(v) do { ioc3->micr = cpu_to_be32(v); } while (0)
  198. #define ioc3_r_midr_r() be32_to_cpu(ioc3->midr_r)
  199. #define ioc3_w_midr_r(v) do { ioc3->midr_r = cpu_to_be32(v); } while (0)
  200. #define ioc3_r_midr_w() be32_to_cpu(ioc3->midr_w)
  201. #define ioc3_w_midr_w(v) do { ioc3->midr_w = cpu_to_be32(v); } while (0)
  202. static inline u32 mcr_pack(u32 pulse, u32 sample)
  203. {
  204. return (pulse << 10) | (sample << 2);
  205. }
  206. static int nic_wait(struct ioc3 *ioc3)
  207. {
  208. u32 mcr;
  209. do {
  210. mcr = ioc3_r_mcr();
  211. } while (!(mcr & 2));
  212. return mcr & 1;
  213. }
  214. static int nic_reset(struct ioc3 *ioc3)
  215. {
  216. int presence;
  217. ioc3_w_mcr(mcr_pack(500, 65));
  218. presence = nic_wait(ioc3);
  219. ioc3_w_mcr(mcr_pack(0, 500));
  220. nic_wait(ioc3);
  221. return presence;
  222. }
  223. static inline int nic_read_bit(struct ioc3 *ioc3)
  224. {
  225. int result;
  226. ioc3_w_mcr(mcr_pack(6, 13));
  227. result = nic_wait(ioc3);
  228. ioc3_w_mcr(mcr_pack(0, 100));
  229. nic_wait(ioc3);
  230. return result;
  231. }
  232. static inline void nic_write_bit(struct ioc3 *ioc3, int bit)
  233. {
  234. if (bit)
  235. ioc3_w_mcr(mcr_pack(6, 110));
  236. else
  237. ioc3_w_mcr(mcr_pack(80, 30));
  238. nic_wait(ioc3);
  239. }
  240. /*
  241. * Read a byte from an iButton device
  242. */
  243. static u32 nic_read_byte(struct ioc3 *ioc3)
  244. {
  245. u32 result = 0;
  246. int i;
  247. for (i = 0; i < 8; i++)
  248. result = (result >> 1) | (nic_read_bit(ioc3) << 7);
  249. return result;
  250. }
  251. /*
  252. * Write a byte to an iButton device
  253. */
  254. static void nic_write_byte(struct ioc3 *ioc3, int byte)
  255. {
  256. int i, bit;
  257. for (i = 8; i; i--) {
  258. bit = byte & 1;
  259. byte >>= 1;
  260. nic_write_bit(ioc3, bit);
  261. }
  262. }
  263. static u64 nic_find(struct ioc3 *ioc3, int *last)
  264. {
  265. int a, b, index, disc;
  266. u64 address = 0;
  267. nic_reset(ioc3);
  268. /* Search ROM. */
  269. nic_write_byte(ioc3, 0xf0);
  270. /* Algorithm from ``Book of iButton Standards''. */
  271. for (index = 0, disc = 0; index < 64; index++) {
  272. a = nic_read_bit(ioc3);
  273. b = nic_read_bit(ioc3);
  274. if (a && b) {
  275. printk("NIC search failed (not fatal).\n");
  276. *last = 0;
  277. return 0;
  278. }
  279. if (!a && !b) {
  280. if (index == *last) {
  281. address |= 1UL << index;
  282. } else if (index > *last) {
  283. address &= ~(1UL << index);
  284. disc = index;
  285. } else if ((address & (1UL << index)) == 0)
  286. disc = index;
  287. nic_write_bit(ioc3, address & (1UL << index));
  288. continue;
  289. } else {
  290. if (a)
  291. address |= 1UL << index;
  292. else
  293. address &= ~(1UL << index);
  294. nic_write_bit(ioc3, a);
  295. continue;
  296. }
  297. }
  298. *last = disc;
  299. return address;
  300. }
  301. static int nic_init(struct ioc3 *ioc3)
  302. {
  303. const char *type;
  304. u8 crc;
  305. u8 serial[6];
  306. int save = 0, i;
  307. type = "unknown";
  308. while (1) {
  309. u64 reg;
  310. reg = nic_find(ioc3, &save);
  311. switch (reg & 0xff) {
  312. case 0x91:
  313. type = "DS1981U";
  314. break;
  315. default:
  316. if (save == 0) {
  317. /* Let the caller try again. */
  318. return -1;
  319. }
  320. continue;
  321. }
  322. nic_reset(ioc3);
  323. /* Match ROM. */
  324. nic_write_byte(ioc3, 0x55);
  325. for (i = 0; i < 8; i++)
  326. nic_write_byte(ioc3, (reg >> (i << 3)) & 0xff);
  327. reg >>= 8; /* Shift out type. */
  328. for (i = 0; i < 6; i++) {
  329. serial[i] = reg & 0xff;
  330. reg >>= 8;
  331. }
  332. crc = reg & 0xff;
  333. break;
  334. }
  335. printk("Found %s NIC", type);
  336. if (type != "unknown") {
  337. printk (" registration number %02x:%02x:%02x:%02x:%02x:%02x,"
  338. " CRC %02x", serial[0], serial[1], serial[2],
  339. serial[3], serial[4], serial[5], crc);
  340. }
  341. printk(".\n");
  342. return 0;
  343. }
  344. /*
  345. * Read the NIC (Number-In-a-Can) device used to store the MAC address on
  346. * SN0 / SN00 nodeboards and PCI cards.
  347. */
  348. static void ioc3_get_eaddr_nic(struct ioc3_private *ip)
  349. {
  350. struct ioc3 *ioc3 = ip->regs;
  351. u8 nic[14];
  352. int tries = 2; /* There may be some problem with the battery? */
  353. int i;
  354. ioc3_w_gpcr_s(1 << 21);
  355. while (tries--) {
  356. if (!nic_init(ioc3))
  357. break;
  358. udelay(500);
  359. }
  360. if (tries < 0) {
  361. printk("Failed to read MAC address\n");
  362. return;
  363. }
  364. /* Read Memory. */
  365. nic_write_byte(ioc3, 0xf0);
  366. nic_write_byte(ioc3, 0x00);
  367. nic_write_byte(ioc3, 0x00);
  368. for (i = 13; i >= 0; i--)
  369. nic[i] = nic_read_byte(ioc3);
  370. for (i = 2; i < 8; i++)
  371. priv_netdev(ip)->dev_addr[i - 2] = nic[i];
  372. }
  373. /*
  374. * Ok, this is hosed by design. It's necessary to know what machine the
  375. * NIC is in in order to know how to read the NIC address. We also have
  376. * to know if it's a PCI card or a NIC in on the node board ...
  377. */
  378. static void ioc3_get_eaddr(struct ioc3_private *ip)
  379. {
  380. int i;
  381. ioc3_get_eaddr_nic(ip);
  382. printk("Ethernet address is ");
  383. for (i = 0; i < 6; i++) {
  384. printk("%02x", priv_netdev(ip)->dev_addr[i]);
  385. if (i < 5)
  386. printk(":");
  387. }
  388. printk(".\n");
  389. }
  390. static void __ioc3_set_mac_address(struct net_device *dev)
  391. {
  392. struct ioc3_private *ip = netdev_priv(dev);
  393. struct ioc3 *ioc3 = ip->regs;
  394. ioc3_w_emar_h((dev->dev_addr[5] << 8) | dev->dev_addr[4]);
  395. ioc3_w_emar_l((dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) |
  396. (dev->dev_addr[1] << 8) | dev->dev_addr[0]);
  397. }
  398. static int ioc3_set_mac_address(struct net_device *dev, void *addr)
  399. {
  400. struct ioc3_private *ip = netdev_priv(dev);
  401. struct sockaddr *sa = addr;
  402. memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
  403. spin_lock_irq(&ip->ioc3_lock);
  404. __ioc3_set_mac_address(dev);
  405. spin_unlock_irq(&ip->ioc3_lock);
  406. return 0;
  407. }
  408. /*
  409. * Caller must hold the ioc3_lock ever for MII readers. This is also
  410. * used to protect the transmitter side but it's low contention.
  411. */
  412. static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
  413. {
  414. struct ioc3_private *ip = netdev_priv(dev);
  415. struct ioc3 *ioc3 = ip->regs;
  416. while (ioc3_r_micr() & MICR_BUSY);
  417. ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG);
  418. while (ioc3_r_micr() & MICR_BUSY);
  419. return ioc3_r_midr_r() & MIDR_DATA_MASK;
  420. }
  421. static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
  422. {
  423. struct ioc3_private *ip = netdev_priv(dev);
  424. struct ioc3 *ioc3 = ip->regs;
  425. while (ioc3_r_micr() & MICR_BUSY);
  426. ioc3_w_midr_w(data);
  427. ioc3_w_micr((phy << MICR_PHYADDR_SHIFT) | reg);
  428. while (ioc3_r_micr() & MICR_BUSY);
  429. }
  430. static int ioc3_mii_init(struct ioc3_private *ip);
  431. static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
  432. {
  433. struct ioc3_private *ip = netdev_priv(dev);
  434. struct ioc3 *ioc3 = ip->regs;
  435. ip->stats.collisions += (ioc3_r_etcdc() & ETCDC_COLLCNT_MASK);
  436. return &ip->stats;
  437. }
  438. #ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
  439. static void ioc3_tcpudp_checksum(struct sk_buff *skb, uint32_t hwsum, int len)
  440. {
  441. struct ethhdr *eh = eth_hdr(skb);
  442. uint32_t csum, ehsum;
  443. unsigned int proto;
  444. struct iphdr *ih;
  445. uint16_t *ew;
  446. unsigned char *cp;
  447. /*
  448. * Did hardware handle the checksum at all? The cases we can handle
  449. * are:
  450. *
  451. * - TCP and UDP checksums of IPv4 only.
  452. * - IPv6 would be doable but we keep that for later ...
  453. * - Only unfragmented packets. Did somebody already tell you
  454. * fragmentation is evil?
  455. * - don't care about packet size. Worst case when processing a
  456. * malformed packet we'll try to access the packet at ip header +
  457. * 64 bytes which is still inside the skb. Even in the unlikely
  458. * case where the checksum is right the higher layers will still
  459. * drop the packet as appropriate.
  460. */
  461. if (eh->h_proto != ntohs(ETH_P_IP))
  462. return;
  463. ih = (struct iphdr *) ((char *)eh + ETH_HLEN);
  464. if (ih->frag_off & htons(IP_MF | IP_OFFSET))
  465. return;
  466. proto = ih->protocol;
  467. if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
  468. return;
  469. /* Same as tx - compute csum of pseudo header */
  470. csum = hwsum +
  471. (ih->tot_len - (ih->ihl << 2)) +
  472. htons((uint16_t)ih->protocol) +
  473. (ih->saddr >> 16) + (ih->saddr & 0xffff) +
  474. (ih->daddr >> 16) + (ih->daddr & 0xffff);
  475. /* Sum up ethernet dest addr, src addr and protocol */
  476. ew = (uint16_t *) eh;
  477. ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
  478. ehsum = (ehsum & 0xffff) + (ehsum >> 16);
  479. ehsum = (ehsum & 0xffff) + (ehsum >> 16);
  480. csum += 0xffff ^ ehsum;
  481. /* In the next step we also subtract the 1's complement
  482. checksum of the trailing ethernet CRC. */
  483. cp = (char *)eh + len; /* points at trailing CRC */
  484. if (len & 1) {
  485. csum += 0xffff ^ (uint16_t) ((cp[1] << 8) | cp[0]);
  486. csum += 0xffff ^ (uint16_t) ((cp[3] << 8) | cp[2]);
  487. } else {
  488. csum += 0xffff ^ (uint16_t) ((cp[0] << 8) | cp[1]);
  489. csum += 0xffff ^ (uint16_t) ((cp[2] << 8) | cp[3]);
  490. }
  491. csum = (csum & 0xffff) + (csum >> 16);
  492. csum = (csum & 0xffff) + (csum >> 16);
  493. if (csum == 0xffff)
  494. skb->ip_summed = CHECKSUM_UNNECESSARY;
  495. }
  496. #endif /* CONFIG_SGI_IOC3_ETH_HW_RX_CSUM */
  497. static inline void ioc3_rx(struct ioc3_private *ip)
  498. {
  499. struct sk_buff *skb, *new_skb;
  500. struct ioc3 *ioc3 = ip->regs;
  501. int rx_entry, n_entry, len;
  502. struct ioc3_erxbuf *rxb;
  503. unsigned long *rxr;
  504. u32 w0, err;
  505. rxr = (unsigned long *) ip->rxr; /* Ring base */
  506. rx_entry = ip->rx_ci; /* RX consume index */
  507. n_entry = ip->rx_pi;
  508. skb = ip->rx_skbs[rx_entry];
  509. rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
  510. w0 = be32_to_cpu(rxb->w0);
  511. while (w0 & ERXBUF_V) {
  512. err = be32_to_cpu(rxb->err); /* It's valid ... */
  513. if (err & ERXBUF_GOODPKT) {
  514. len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
  515. skb_trim(skb, len);
  516. skb->protocol = eth_type_trans(skb, priv_netdev(ip));
  517. new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
  518. if (!new_skb) {
  519. /* Ouch, drop packet and just recycle packet
  520. to keep the ring filled. */
  521. ip->stats.rx_dropped++;
  522. new_skb = skb;
  523. goto next;
  524. }
  525. #ifdef CONFIG_SGI_IOC3_ETH_HW_RX_CSUM
  526. ioc3_tcpudp_checksum(skb, w0 & ERXBUF_IPCKSUM_MASK,len);
  527. #endif
  528. netif_rx(skb);
  529. ip->rx_skbs[rx_entry] = NULL; /* Poison */
  530. new_skb->dev = priv_netdev(ip);
  531. /* Because we reserve afterwards. */
  532. skb_put(new_skb, (1664 + RX_OFFSET));
  533. rxb = (struct ioc3_erxbuf *) new_skb->data;
  534. skb_reserve(new_skb, RX_OFFSET);
  535. priv_netdev(ip)->last_rx = jiffies;
  536. ip->stats.rx_packets++; /* Statistics */
  537. ip->stats.rx_bytes += len;
  538. } else {
  539. /* The frame is invalid and the skb never
  540. reached the network layer so we can just
  541. recycle it. */
  542. new_skb = skb;
  543. ip->stats.rx_errors++;
  544. }
  545. if (err & ERXBUF_CRCERR) /* Statistics */
  546. ip->stats.rx_crc_errors++;
  547. if (err & ERXBUF_FRAMERR)
  548. ip->stats.rx_frame_errors++;
  549. next:
  550. ip->rx_skbs[n_entry] = new_skb;
  551. rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1));
  552. rxb->w0 = 0; /* Clear valid flag */
  553. n_entry = (n_entry + 1) & 511; /* Update erpir */
  554. /* Now go on to the next ring entry. */
  555. rx_entry = (rx_entry + 1) & 511;
  556. skb = ip->rx_skbs[rx_entry];
  557. rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
  558. w0 = be32_to_cpu(rxb->w0);
  559. }
  560. ioc3_w_erpir((n_entry << 3) | ERPIR_ARM);
  561. ip->rx_pi = n_entry;
  562. ip->rx_ci = rx_entry;
  563. }
  564. static inline void ioc3_tx(struct ioc3_private *ip)
  565. {
  566. unsigned long packets, bytes;
  567. struct ioc3 *ioc3 = ip->regs;
  568. int tx_entry, o_entry;
  569. struct sk_buff *skb;
  570. u32 etcir;
  571. spin_lock(&ip->ioc3_lock);
  572. etcir = ioc3_r_etcir();
  573. tx_entry = (etcir >> 7) & 127;
  574. o_entry = ip->tx_ci;
  575. packets = 0;
  576. bytes = 0;
  577. while (o_entry != tx_entry) {
  578. packets++;
  579. skb = ip->tx_skbs[o_entry];
  580. bytes += skb->len;
  581. dev_kfree_skb_irq(skb);
  582. ip->tx_skbs[o_entry] = NULL;
  583. o_entry = (o_entry + 1) & 127; /* Next */
  584. etcir = ioc3_r_etcir(); /* More pkts sent? */
  585. tx_entry = (etcir >> 7) & 127;
  586. }
  587. ip->stats.tx_packets += packets;
  588. ip->stats.tx_bytes += bytes;
  589. ip->txqlen -= packets;
  590. if (ip->txqlen < 128)
  591. netif_wake_queue(priv_netdev(ip));
  592. ip->tx_ci = o_entry;
  593. spin_unlock(&ip->ioc3_lock);
  594. }
  595. /*
  596. * Deal with fatal IOC3 errors. This condition might be caused by a hard or
  597. * software problems, so we should try to recover
  598. * more gracefully if this ever happens. In theory we might be flooded
  599. * with such error interrupts if something really goes wrong, so we might
  600. * also consider to take the interface down.
  601. */
  602. static void ioc3_error(struct ioc3_private *ip, u32 eisr)
  603. {
  604. struct net_device *dev = priv_netdev(ip);
  605. unsigned char *iface = dev->name;
  606. spin_lock(&ip->ioc3_lock);
  607. if (eisr & EISR_RXOFLO)
  608. printk(KERN_ERR "%s: RX overflow.\n", iface);
  609. if (eisr & EISR_RXBUFOFLO)
  610. printk(KERN_ERR "%s: RX buffer overflow.\n", iface);
  611. if (eisr & EISR_RXMEMERR)
  612. printk(KERN_ERR "%s: RX PCI error.\n", iface);
  613. if (eisr & EISR_RXPARERR)
  614. printk(KERN_ERR "%s: RX SSRAM parity error.\n", iface);
  615. if (eisr & EISR_TXBUFUFLO)
  616. printk(KERN_ERR "%s: TX buffer underflow.\n", iface);
  617. if (eisr & EISR_TXMEMERR)
  618. printk(KERN_ERR "%s: TX PCI error.\n", iface);
  619. ioc3_stop(ip);
  620. ioc3_init(dev);
  621. ioc3_mii_init(ip);
  622. netif_wake_queue(dev);
  623. spin_unlock(&ip->ioc3_lock);
  624. }
  625. /* The interrupt handler does all of the Rx thread work and cleans up
  626. after the Tx thread. */
  627. static irqreturn_t ioc3_interrupt(int irq, void *_dev)
  628. {
  629. struct net_device *dev = (struct net_device *)_dev;
  630. struct ioc3_private *ip = netdev_priv(dev);
  631. struct ioc3 *ioc3 = ip->regs;
  632. const u32 enabled = EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
  633. EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
  634. EISR_TXEXPLICIT | EISR_TXMEMERR;
  635. u32 eisr;
  636. eisr = ioc3_r_eisr() & enabled;
  637. ioc3_w_eisr(eisr);
  638. (void) ioc3_r_eisr(); /* Flush */
  639. if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
  640. EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
  641. ioc3_error(ip, eisr);
  642. if (eisr & EISR_RXTIMERINT)
  643. ioc3_rx(ip);
  644. if (eisr & EISR_TXEXPLICIT)
  645. ioc3_tx(ip);
  646. return IRQ_HANDLED;
  647. }
  648. static inline void ioc3_setup_duplex(struct ioc3_private *ip)
  649. {
  650. struct ioc3 *ioc3 = ip->regs;
  651. if (ip->mii.full_duplex) {
  652. ioc3_w_etcsr(ETCSR_FD);
  653. ip->emcr |= EMCR_DUPLEX;
  654. } else {
  655. ioc3_w_etcsr(ETCSR_HD);
  656. ip->emcr &= ~EMCR_DUPLEX;
  657. }
  658. ioc3_w_emcr(ip->emcr);
  659. }
  660. static void ioc3_timer(unsigned long data)
  661. {
  662. struct ioc3_private *ip = (struct ioc3_private *) data;
  663. /* Print the link status if it has changed */
  664. mii_check_media(&ip->mii, 1, 0);
  665. ioc3_setup_duplex(ip);
  666. ip->ioc3_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2s */
  667. add_timer(&ip->ioc3_timer);
  668. }
  669. /*
  670. * Try to find a PHY. There is no apparent relation between the MII addresses
  671. * in the SGI documentation and what we find in reality, so we simply probe
  672. * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
  673. * onboard IOC3s has the special oddity that probing doesn't seem to find it
  674. * yet the interface seems to work fine, so if probing fails we for now will
  675. * simply default to PHY 31 instead of bailing out.
  676. */
  677. static int ioc3_mii_init(struct ioc3_private *ip)
  678. {
  679. struct net_device *dev = priv_netdev(ip);
  680. int i, found = 0, res = 0;
  681. int ioc3_phy_workaround = 1;
  682. u16 word;
  683. for (i = 0; i < 32; i++) {
  684. word = ioc3_mdio_read(dev, i, MII_PHYSID1);
  685. if (word != 0xffff && word != 0x0000) {
  686. found = 1;
  687. break; /* Found a PHY */
  688. }
  689. }
  690. if (!found) {
  691. if (ioc3_phy_workaround)
  692. i = 31;
  693. else {
  694. ip->mii.phy_id = -1;
  695. res = -ENODEV;
  696. goto out;
  697. }
  698. }
  699. ip->mii.phy_id = i;
  700. out:
  701. return res;
  702. }
  703. static void ioc3_mii_start(struct ioc3_private *ip)
  704. {
  705. ip->ioc3_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
  706. ip->ioc3_timer.data = (unsigned long) ip;
  707. ip->ioc3_timer.function = &ioc3_timer;
  708. add_timer(&ip->ioc3_timer);
  709. }
  710. static inline void ioc3_clean_rx_ring(struct ioc3_private *ip)
  711. {
  712. struct sk_buff *skb;
  713. int i;
  714. for (i = ip->rx_ci; i & 15; i++) {
  715. ip->rx_skbs[ip->rx_pi] = ip->rx_skbs[ip->rx_ci];
  716. ip->rxr[ip->rx_pi++] = ip->rxr[ip->rx_ci++];
  717. }
  718. ip->rx_pi &= 511;
  719. ip->rx_ci &= 511;
  720. for (i = ip->rx_ci; i != ip->rx_pi; i = (i+1) & 511) {
  721. struct ioc3_erxbuf *rxb;
  722. skb = ip->rx_skbs[i];
  723. rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
  724. rxb->w0 = 0;
  725. }
  726. }
  727. static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
  728. {
  729. struct sk_buff *skb;
  730. int i;
  731. for (i=0; i < 128; i++) {
  732. skb = ip->tx_skbs[i];
  733. if (skb) {
  734. ip->tx_skbs[i] = NULL;
  735. dev_kfree_skb_any(skb);
  736. }
  737. ip->txr[i].cmd = 0;
  738. }
  739. ip->tx_pi = 0;
  740. ip->tx_ci = 0;
  741. }
  742. static void ioc3_free_rings(struct ioc3_private *ip)
  743. {
  744. struct sk_buff *skb;
  745. int rx_entry, n_entry;
  746. if (ip->txr) {
  747. ioc3_clean_tx_ring(ip);
  748. free_pages((unsigned long)ip->txr, 2);
  749. ip->txr = NULL;
  750. }
  751. if (ip->rxr) {
  752. n_entry = ip->rx_ci;
  753. rx_entry = ip->rx_pi;
  754. while (n_entry != rx_entry) {
  755. skb = ip->rx_skbs[n_entry];
  756. if (skb)
  757. dev_kfree_skb_any(skb);
  758. n_entry = (n_entry + 1) & 511;
  759. }
  760. free_page((unsigned long)ip->rxr);
  761. ip->rxr = NULL;
  762. }
  763. }
  764. static void ioc3_alloc_rings(struct net_device *dev)
  765. {
  766. struct ioc3_private *ip = netdev_priv(dev);
  767. struct ioc3_erxbuf *rxb;
  768. unsigned long *rxr;
  769. int i;
  770. if (ip->rxr == NULL) {
  771. /* Allocate and initialize rx ring. 4kb = 512 entries */
  772. ip->rxr = (unsigned long *) get_zeroed_page(GFP_ATOMIC);
  773. rxr = (unsigned long *) ip->rxr;
  774. if (!rxr)
  775. printk("ioc3_alloc_rings(): get_zeroed_page() failed!\n");
  776. /* Now the rx buffers. The RX ring may be larger but
  777. we only allocate 16 buffers for now. Need to tune
  778. this for performance and memory later. */
  779. for (i = 0; i < RX_BUFFS; i++) {
  780. struct sk_buff *skb;
  781. skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
  782. if (!skb) {
  783. show_free_areas();
  784. continue;
  785. }
  786. ip->rx_skbs[i] = skb;
  787. skb->dev = dev;
  788. /* Because we reserve afterwards. */
  789. skb_put(skb, (1664 + RX_OFFSET));
  790. rxb = (struct ioc3_erxbuf *) skb->data;
  791. rxr[i] = cpu_to_be64(ioc3_map(rxb, 1));
  792. skb_reserve(skb, RX_OFFSET);
  793. }
  794. ip->rx_ci = 0;
  795. ip->rx_pi = RX_BUFFS;
  796. }
  797. if (ip->txr == NULL) {
  798. /* Allocate and initialize tx rings. 16kb = 128 bufs. */
  799. ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);
  800. if (!ip->txr)
  801. printk("ioc3_alloc_rings(): __get_free_pages() failed!\n");
  802. ip->tx_pi = 0;
  803. ip->tx_ci = 0;
  804. }
  805. }
  806. static void ioc3_init_rings(struct net_device *dev)
  807. {
  808. struct ioc3_private *ip = netdev_priv(dev);
  809. struct ioc3 *ioc3 = ip->regs;
  810. unsigned long ring;
  811. ioc3_free_rings(ip);
  812. ioc3_alloc_rings(dev);
  813. ioc3_clean_rx_ring(ip);
  814. ioc3_clean_tx_ring(ip);
  815. /* Now the rx ring base, consume & produce registers. */
  816. ring = ioc3_map(ip->rxr, 0);
  817. ioc3_w_erbr_h(ring >> 32);
  818. ioc3_w_erbr_l(ring & 0xffffffff);
  819. ioc3_w_ercir(ip->rx_ci << 3);
  820. ioc3_w_erpir((ip->rx_pi << 3) | ERPIR_ARM);
  821. ring = ioc3_map(ip->txr, 0);
  822. ip->txqlen = 0; /* nothing queued */
  823. /* Now the tx ring base, consume & produce registers. */
  824. ioc3_w_etbr_h(ring >> 32);
  825. ioc3_w_etbr_l(ring & 0xffffffff);
  826. ioc3_w_etpir(ip->tx_pi << 7);
  827. ioc3_w_etcir(ip->tx_ci << 7);
  828. (void) ioc3_r_etcir(); /* Flush */
  829. }
  830. static inline void ioc3_ssram_disc(struct ioc3_private *ip)
  831. {
  832. struct ioc3 *ioc3 = ip->regs;
  833. volatile u32 *ssram0 = &ioc3->ssram[0x0000];
  834. volatile u32 *ssram1 = &ioc3->ssram[0x4000];
  835. unsigned int pattern = 0x5555;
  836. /* Assume the larger size SSRAM and enable parity checking */
  837. ioc3_w_emcr(ioc3_r_emcr() | (EMCR_BUFSIZ | EMCR_RAMPAR));
  838. *ssram0 = pattern;
  839. *ssram1 = ~pattern & IOC3_SSRAM_DM;
  840. if ((*ssram0 & IOC3_SSRAM_DM) != pattern ||
  841. (*ssram1 & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
  842. /* set ssram size to 64 KB */
  843. ip->emcr = EMCR_RAMPAR;
  844. ioc3_w_emcr(ioc3_r_emcr() & ~EMCR_BUFSIZ);
  845. } else
  846. ip->emcr = EMCR_BUFSIZ | EMCR_RAMPAR;
  847. }
  848. static void ioc3_init(struct net_device *dev)
  849. {
  850. struct ioc3_private *ip = netdev_priv(dev);
  851. struct ioc3 *ioc3 = ip->regs;
  852. del_timer_sync(&ip->ioc3_timer); /* Kill if running */
  853. ioc3_w_emcr(EMCR_RST); /* Reset */
  854. (void) ioc3_r_emcr(); /* Flush WB */
  855. udelay(4); /* Give it time ... */
  856. ioc3_w_emcr(0);
  857. (void) ioc3_r_emcr();
  858. /* Misc registers */
  859. #ifdef CONFIG_SGI_IP27
  860. ioc3_w_erbar(PCI64_ATTR_BAR >> 32); /* Barrier on last store */
  861. #else
  862. ioc3_w_erbar(0); /* Let PCI API get it right */
  863. #endif
  864. (void) ioc3_r_etcdc(); /* Clear on read */
  865. ioc3_w_ercsr(15); /* RX low watermark */
  866. ioc3_w_ertr(0); /* Interrupt immediately */
  867. __ioc3_set_mac_address(dev);
  868. ioc3_w_ehar_h(ip->ehar_h);
  869. ioc3_w_ehar_l(ip->ehar_l);
  870. ioc3_w_ersr(42); /* XXX should be random */
  871. ioc3_init_rings(dev);
  872. ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
  873. EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
  874. ioc3_w_emcr(ip->emcr);
  875. ioc3_w_eier(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
  876. EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
  877. EISR_TXEXPLICIT | EISR_TXMEMERR);
  878. (void) ioc3_r_eier();
  879. }
  880. static inline void ioc3_stop(struct ioc3_private *ip)
  881. {
  882. struct ioc3 *ioc3 = ip->regs;
  883. ioc3_w_emcr(0); /* Shutup */
  884. ioc3_w_eier(0); /* Disable interrupts */
  885. (void) ioc3_r_eier(); /* Flush */
  886. }
  887. static int ioc3_open(struct net_device *dev)
  888. {
  889. struct ioc3_private *ip = netdev_priv(dev);
  890. if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {
  891. printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
  892. return -EAGAIN;
  893. }
  894. ip->ehar_h = 0;
  895. ip->ehar_l = 0;
  896. ioc3_init(dev);
  897. ioc3_mii_start(ip);
  898. netif_start_queue(dev);
  899. return 0;
  900. }
  901. static int ioc3_close(struct net_device *dev)
  902. {
  903. struct ioc3_private *ip = netdev_priv(dev);
  904. del_timer_sync(&ip->ioc3_timer);
  905. netif_stop_queue(dev);
  906. ioc3_stop(ip);
  907. free_irq(dev->irq, dev);
  908. ioc3_free_rings(ip);
  909. return 0;
  910. }
  911. /*
  912. * MENET cards have four IOC3 chips, which are attached to two sets of
  913. * PCI slot resources each: the primary connections are on slots
  914. * 0..3 and the secondaries are on 4..7
  915. *
  916. * All four ethernets are brought out to connectors; six serial ports
  917. * (a pair from each of the first three IOC3s) are brought out to
  918. * MiniDINs; all other subdevices are left swinging in the wind, leave
  919. * them disabled.
  920. */
  921. static inline int ioc3_is_menet(struct pci_dev *pdev)
  922. {
  923. struct pci_dev *dev;
  924. return pdev->bus->parent == NULL
  925. && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(0, 0)))
  926. && dev->vendor == PCI_VENDOR_ID_SGI
  927. && dev->device == PCI_DEVICE_ID_SGI_IOC3
  928. && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(1, 0)))
  929. && dev->vendor == PCI_VENDOR_ID_SGI
  930. && dev->device == PCI_DEVICE_ID_SGI_IOC3
  931. && (dev = pci_find_slot(pdev->bus->number, PCI_DEVFN(2, 0)))
  932. && dev->vendor == PCI_VENDOR_ID_SGI
  933. && dev->device == PCI_DEVICE_ID_SGI_IOC3;
  934. }
  935. #ifdef CONFIG_SERIAL_8250
  936. /*
  937. * Note about serial ports and consoles:
  938. * For console output, everyone uses the IOC3 UARTA (offset 0x178)
  939. * connected to the master node (look in ip27_setup_console() and
  940. * ip27prom_console_write()).
  941. *
  942. * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
  943. * addresses on a partitioned machine. Since we currently use the ioc3
  944. * serial ports, we use dynamic serial port discovery that the serial.c
  945. * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
  946. * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
  947. * than UARTB's, although UARTA on o200s has traditionally been known as
  948. * port 0. So, we just use one serial port from each ioc3 (since the
  949. * serial driver adds addresses to get to higher ports).
  950. *
  951. * The first one to do a register_console becomes the preferred console
  952. * (if there is no kernel command line console= directive). /dev/console
  953. * (ie 5, 1) is then "aliased" into the device number returned by the
  954. * "device" routine referred to in this console structure
  955. * (ip27prom_console_dev).
  956. *
  957. * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
  958. * around ioc3 oddities in this respect.
  959. *
  960. * The IOC3 serials use a 22MHz clock rate with an additional divider by 3.
  961. */
  962. static void __devinit ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
  963. {
  964. struct uart_port port;
  965. /*
  966. * We need to recognice and treat the fourth MENET serial as it
  967. * does not have an SuperIO chip attached to it, therefore attempting
  968. * to access it will result in bus errors. We call something an
  969. * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
  970. * in it. This is paranoid but we want to avoid blowing up on a
  971. * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
  972. * not paranoid enough ...
  973. */
  974. if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
  975. return;
  976. /*
  977. * Register to interrupt zero because we share the interrupt with
  978. * the serial driver which we don't properly support yet.
  979. *
  980. * Can't use UPF_IOREMAP as the whole of IOC3 resources have already
  981. * been registered.
  982. */
  983. memset(&port, 0, sizeof(port));
  984. port.irq = 0;
  985. port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
  986. port.iotype = UPIO_MEM;
  987. port.regshift = 0;
  988. port.uartclk = 22000000 / 3;
  989. port.membase = (unsigned char *) &ioc3->sregs.uarta;
  990. serial8250_register_port(&port);
  991. port.membase = (unsigned char *) &ioc3->sregs.uartb;
  992. serial8250_register_port(&port);
  993. }
  994. #endif
  995. static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  996. {
  997. unsigned int sw_physid1, sw_physid2;
  998. struct net_device *dev = NULL;
  999. struct ioc3_private *ip;
  1000. struct ioc3 *ioc3;
  1001. unsigned long ioc3_base, ioc3_size;
  1002. u32 vendor, model, rev;
  1003. int err, pci_using_dac;
  1004. /* Configure DMA attributes. */
  1005. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  1006. if (!err) {
  1007. pci_using_dac = 1;
  1008. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  1009. if (err < 0) {
  1010. printk(KERN_ERR "%s: Unable to obtain 64 bit DMA "
  1011. "for consistent allocations\n", pci_name(pdev));
  1012. goto out;
  1013. }
  1014. } else {
  1015. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  1016. if (err) {
  1017. printk(KERN_ERR "%s: No usable DMA configuration, "
  1018. "aborting.\n", pci_name(pdev));
  1019. goto out;
  1020. }
  1021. pci_using_dac = 0;
  1022. }
  1023. if (pci_enable_device(pdev))
  1024. return -ENODEV;
  1025. dev = alloc_etherdev(sizeof(struct ioc3_private));
  1026. if (!dev) {
  1027. err = -ENOMEM;
  1028. goto out_disable;
  1029. }
  1030. if (pci_using_dac)
  1031. dev->features |= NETIF_F_HIGHDMA;
  1032. err = pci_request_regions(pdev, "ioc3");
  1033. if (err)
  1034. goto out_free;
  1035. SET_MODULE_OWNER(dev);
  1036. SET_NETDEV_DEV(dev, &pdev->dev);
  1037. ip = netdev_priv(dev);
  1038. dev->irq = pdev->irq;
  1039. ioc3_base = pci_resource_start(pdev, 0);
  1040. ioc3_size = pci_resource_len(pdev, 0);
  1041. ioc3 = (struct ioc3 *) ioremap(ioc3_base, ioc3_size);
  1042. if (!ioc3) {
  1043. printk(KERN_CRIT "ioc3eth(%s): ioremap failed, goodbye.\n",
  1044. pci_name(pdev));
  1045. err = -ENOMEM;
  1046. goto out_res;
  1047. }
  1048. ip->regs = ioc3;
  1049. #ifdef CONFIG_SERIAL_8250
  1050. ioc3_serial_probe(pdev, ioc3);
  1051. #endif
  1052. spin_lock_init(&ip->ioc3_lock);
  1053. init_timer(&ip->ioc3_timer);
  1054. ioc3_stop(ip);
  1055. ioc3_init(dev);
  1056. ip->pdev = pdev;
  1057. ip->mii.phy_id_mask = 0x1f;
  1058. ip->mii.reg_num_mask = 0x1f;
  1059. ip->mii.dev = dev;
  1060. ip->mii.mdio_read = ioc3_mdio_read;
  1061. ip->mii.mdio_write = ioc3_mdio_write;
  1062. ioc3_mii_init(ip);
  1063. if (ip->mii.phy_id == -1) {
  1064. printk(KERN_CRIT "ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
  1065. pci_name(pdev));
  1066. err = -ENODEV;
  1067. goto out_stop;
  1068. }
  1069. ioc3_mii_start(ip);
  1070. ioc3_ssram_disc(ip);
  1071. ioc3_get_eaddr(ip);
  1072. /* The IOC3-specific entries in the device structure. */
  1073. dev->open = ioc3_open;
  1074. dev->hard_start_xmit = ioc3_start_xmit;
  1075. dev->tx_timeout = ioc3_timeout;
  1076. dev->watchdog_timeo = 5 * HZ;
  1077. dev->stop = ioc3_close;
  1078. dev->get_stats = ioc3_get_stats;
  1079. dev->do_ioctl = ioc3_ioctl;
  1080. dev->set_multicast_list = ioc3_set_multicast_list;
  1081. dev->set_mac_address = ioc3_set_mac_address;
  1082. dev->ethtool_ops = &ioc3_ethtool_ops;
  1083. #ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
  1084. dev->features = NETIF_F_IP_CSUM;
  1085. #endif
  1086. sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
  1087. sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
  1088. err = register_netdev(dev);
  1089. if (err)
  1090. goto out_stop;
  1091. mii_check_media(&ip->mii, 1, 1);
  1092. ioc3_setup_duplex(ip);
  1093. vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
  1094. model = (sw_physid2 >> 4) & 0x3f;
  1095. rev = sw_physid2 & 0xf;
  1096. printk(KERN_INFO "%s: Using PHY %d, vendor 0x%x, model %d, "
  1097. "rev %d.\n", dev->name, ip->mii.phy_id, vendor, model, rev);
  1098. printk(KERN_INFO "%s: IOC3 SSRAM has %d kbyte.\n", dev->name,
  1099. ip->emcr & EMCR_BUFSIZ ? 128 : 64);
  1100. return 0;
  1101. out_stop:
  1102. ioc3_stop(ip);
  1103. del_timer_sync(&ip->ioc3_timer);
  1104. ioc3_free_rings(ip);
  1105. out_res:
  1106. pci_release_regions(pdev);
  1107. out_free:
  1108. free_netdev(dev);
  1109. out_disable:
  1110. /*
  1111. * We should call pci_disable_device(pdev); here if the IOC3 wasn't
  1112. * such a weird device ...
  1113. */
  1114. out:
  1115. return err;
  1116. }
  1117. static void __devexit ioc3_remove_one (struct pci_dev *pdev)
  1118. {
  1119. struct net_device *dev = pci_get_drvdata(pdev);
  1120. struct ioc3_private *ip = netdev_priv(dev);
  1121. struct ioc3 *ioc3 = ip->regs;
  1122. unregister_netdev(dev);
  1123. del_timer_sync(&ip->ioc3_timer);
  1124. iounmap(ioc3);
  1125. pci_release_regions(pdev);
  1126. free_netdev(dev);
  1127. /*
  1128. * We should call pci_disable_device(pdev); here if the IOC3 wasn't
  1129. * such a weird device ...
  1130. */
  1131. }
  1132. static struct pci_device_id ioc3_pci_tbl[] = {
  1133. { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
  1134. { 0 }
  1135. };
  1136. MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
  1137. static struct pci_driver ioc3_driver = {
  1138. .name = "ioc3-eth",
  1139. .id_table = ioc3_pci_tbl,
  1140. .probe = ioc3_probe,
  1141. .remove = __devexit_p(ioc3_remove_one),
  1142. };
  1143. static int __init ioc3_init_module(void)
  1144. {
  1145. return pci_register_driver(&ioc3_driver);
  1146. }
  1147. static void __exit ioc3_cleanup_module(void)
  1148. {
  1149. pci_unregister_driver(&ioc3_driver);
  1150. }
  1151. static int ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1152. {
  1153. unsigned long data;
  1154. struct ioc3_private *ip = netdev_priv(dev);
  1155. struct ioc3 *ioc3 = ip->regs;
  1156. unsigned int len;
  1157. struct ioc3_etxd *desc;
  1158. uint32_t w0 = 0;
  1159. int produce;
  1160. #ifdef CONFIG_SGI_IOC3_ETH_HW_TX_CSUM
  1161. /*
  1162. * IOC3 has a fairly simple minded checksumming hardware which simply
  1163. * adds up the 1's complement checksum for the entire packet and
  1164. * inserts it at an offset which can be specified in the descriptor
  1165. * into the transmit packet. This means we have to compensate for the
  1166. * MAC header which should not be summed and the TCP/UDP pseudo headers
  1167. * manually.
  1168. */
  1169. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1170. int proto = ntohs(skb->nh.iph->protocol);
  1171. unsigned int csoff;
  1172. struct iphdr *ih = skb->nh.iph;
  1173. uint32_t csum, ehsum;
  1174. uint16_t *eh;
  1175. /* The MAC header. skb->mac seem the logic approach
  1176. to find the MAC header - except it's a NULL pointer ... */
  1177. eh = (uint16_t *) skb->data;
  1178. /* Sum up dest addr, src addr and protocol */
  1179. ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
  1180. /* Fold ehsum. can't use csum_fold which negates also ... */
  1181. ehsum = (ehsum & 0xffff) + (ehsum >> 16);
  1182. ehsum = (ehsum & 0xffff) + (ehsum >> 16);
  1183. /* Skip IP header; it's sum is always zero and was
  1184. already filled in by ip_output.c */
  1185. csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
  1186. ih->tot_len - (ih->ihl << 2),
  1187. proto, 0xffff ^ ehsum);
  1188. csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
  1189. csum = (csum & 0xffff) + (csum >> 16);
  1190. csoff = ETH_HLEN + (ih->ihl << 2);
  1191. if (proto == IPPROTO_UDP) {
  1192. csoff += offsetof(struct udphdr, check);
  1193. skb->h.uh->check = csum;
  1194. }
  1195. if (proto == IPPROTO_TCP) {
  1196. csoff += offsetof(struct tcphdr, check);
  1197. skb->h.th->check = csum;
  1198. }
  1199. w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
  1200. }
  1201. #endif /* CONFIG_SGI_IOC3_ETH_HW_TX_CSUM */
  1202. spin_lock_irq(&ip->ioc3_lock);
  1203. data = (unsigned long) skb->data;
  1204. len = skb->len;
  1205. produce = ip->tx_pi;
  1206. desc = &ip->txr[produce];
  1207. if (len <= 104) {
  1208. /* Short packet, let's copy it directly into the ring. */
  1209. memcpy(desc->data, skb->data, skb->len);
  1210. if (len < ETH_ZLEN) {
  1211. /* Very short packet, pad with zeros at the end. */
  1212. memset(desc->data + len, 0, ETH_ZLEN - len);
  1213. len = ETH_ZLEN;
  1214. }
  1215. desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
  1216. desc->bufcnt = cpu_to_be32(len);
  1217. } else if ((data ^ (data + len - 1)) & 0x4000) {
  1218. unsigned long b2 = (data | 0x3fffUL) + 1UL;
  1219. unsigned long s1 = b2 - data;
  1220. unsigned long s2 = data + len - b2;
  1221. desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
  1222. ETXD_B1V | ETXD_B2V | w0);
  1223. desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
  1224. (s2 << ETXD_B2CNT_SHIFT));
  1225. desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
  1226. desc->p2 = cpu_to_be64(ioc3_map((void *) b2, 1));
  1227. } else {
  1228. /* Normal sized packet that doesn't cross a page boundary. */
  1229. desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
  1230. desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
  1231. desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
  1232. }
  1233. BARRIER();
  1234. dev->trans_start = jiffies;
  1235. ip->tx_skbs[produce] = skb; /* Remember skb */
  1236. produce = (produce + 1) & 127;
  1237. ip->tx_pi = produce;
  1238. ioc3_w_etpir(produce << 7); /* Fire ... */
  1239. ip->txqlen++;
  1240. if (ip->txqlen >= 127)
  1241. netif_stop_queue(dev);
  1242. spin_unlock_irq(&ip->ioc3_lock);
  1243. return 0;
  1244. }
  1245. static void ioc3_timeout(struct net_device *dev)
  1246. {
  1247. struct ioc3_private *ip = netdev_priv(dev);
  1248. printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
  1249. spin_lock_irq(&ip->ioc3_lock);
  1250. ioc3_stop(ip);
  1251. ioc3_init(dev);
  1252. ioc3_mii_init(ip);
  1253. ioc3_mii_start(ip);
  1254. spin_unlock_irq(&ip->ioc3_lock);
  1255. netif_wake_queue(dev);
  1256. }
  1257. /*
  1258. * Given a multicast ethernet address, this routine calculates the
  1259. * address's bit index in the logical address filter mask
  1260. */
  1261. static inline unsigned int ioc3_hash(const unsigned char *addr)
  1262. {
  1263. unsigned int temp = 0;
  1264. u32 crc;
  1265. int bits;
  1266. crc = ether_crc_le(ETH_ALEN, addr);
  1267. crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
  1268. for (bits = 6; --bits >= 0; ) {
  1269. temp <<= 1;
  1270. temp |= (crc & 0x1);
  1271. crc >>= 1;
  1272. }
  1273. return temp;
  1274. }
  1275. static void ioc3_get_drvinfo (struct net_device *dev,
  1276. struct ethtool_drvinfo *info)
  1277. {
  1278. struct ioc3_private *ip = netdev_priv(dev);
  1279. strcpy (info->driver, IOC3_NAME);
  1280. strcpy (info->version, IOC3_VERSION);
  1281. strcpy (info->bus_info, pci_name(ip->pdev));
  1282. }
  1283. static int ioc3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1284. {
  1285. struct ioc3_private *ip = netdev_priv(dev);
  1286. int rc;
  1287. spin_lock_irq(&ip->ioc3_lock);
  1288. rc = mii_ethtool_gset(&ip->mii, cmd);
  1289. spin_unlock_irq(&ip->ioc3_lock);
  1290. return rc;
  1291. }
  1292. static int ioc3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1293. {
  1294. struct ioc3_private *ip = netdev_priv(dev);
  1295. int rc;
  1296. spin_lock_irq(&ip->ioc3_lock);
  1297. rc = mii_ethtool_sset(&ip->mii, cmd);
  1298. spin_unlock_irq(&ip->ioc3_lock);
  1299. return rc;
  1300. }
  1301. static int ioc3_nway_reset(struct net_device *dev)
  1302. {
  1303. struct ioc3_private *ip = netdev_priv(dev);
  1304. int rc;
  1305. spin_lock_irq(&ip->ioc3_lock);
  1306. rc = mii_nway_restart(&ip->mii);
  1307. spin_unlock_irq(&ip->ioc3_lock);
  1308. return rc;
  1309. }
  1310. static u32 ioc3_get_link(struct net_device *dev)
  1311. {
  1312. struct ioc3_private *ip = netdev_priv(dev);
  1313. int rc;
  1314. spin_lock_irq(&ip->ioc3_lock);
  1315. rc = mii_link_ok(&ip->mii);
  1316. spin_unlock_irq(&ip->ioc3_lock);
  1317. return rc;
  1318. }
  1319. static const struct ethtool_ops ioc3_ethtool_ops = {
  1320. .get_drvinfo = ioc3_get_drvinfo,
  1321. .get_settings = ioc3_get_settings,
  1322. .set_settings = ioc3_set_settings,
  1323. .nway_reset = ioc3_nway_reset,
  1324. .get_link = ioc3_get_link,
  1325. };
  1326. static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1327. {
  1328. struct ioc3_private *ip = netdev_priv(dev);
  1329. int rc;
  1330. spin_lock_irq(&ip->ioc3_lock);
  1331. rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
  1332. spin_unlock_irq(&ip->ioc3_lock);
  1333. return rc;
  1334. }
  1335. static void ioc3_set_multicast_list(struct net_device *dev)
  1336. {
  1337. struct dev_mc_list *dmi = dev->mc_list;
  1338. struct ioc3_private *ip = netdev_priv(dev);
  1339. struct ioc3 *ioc3 = ip->regs;
  1340. u64 ehar = 0;
  1341. int i;
  1342. netif_stop_queue(dev); /* Lock out others. */
  1343. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  1344. ip->emcr |= EMCR_PROMISC;
  1345. ioc3_w_emcr(ip->emcr);
  1346. (void) ioc3_r_emcr();
  1347. } else {
  1348. ip->emcr &= ~EMCR_PROMISC;
  1349. ioc3_w_emcr(ip->emcr); /* Clear promiscuous. */
  1350. (void) ioc3_r_emcr();
  1351. if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
  1352. /* Too many for hashing to make sense or we want all
  1353. multicast packets anyway, so skip computing all the
  1354. hashes and just accept all packets. */
  1355. ip->ehar_h = 0xffffffff;
  1356. ip->ehar_l = 0xffffffff;
  1357. } else {
  1358. for (i = 0; i < dev->mc_count; i++) {
  1359. char *addr = dmi->dmi_addr;
  1360. dmi = dmi->next;
  1361. if (!(*addr & 1))
  1362. continue;
  1363. ehar |= (1UL << ioc3_hash(addr));
  1364. }
  1365. ip->ehar_h = ehar >> 32;
  1366. ip->ehar_l = ehar & 0xffffffff;
  1367. }
  1368. ioc3_w_ehar_h(ip->ehar_h);
  1369. ioc3_w_ehar_l(ip->ehar_l);
  1370. }
  1371. netif_wake_queue(dev); /* Let us get going again. */
  1372. }
  1373. MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
  1374. MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
  1375. MODULE_LICENSE("GPL");
  1376. module_init(ioc3_init_module);
  1377. module_exit(ioc3_cleanup_module);