ibmlana.h 12 KB

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  1. #ifndef _IBM_LANA_INCLUDE_
  2. #define _IBM_LANA_INCLUDE_
  3. #ifdef _IBM_LANA_DRIVER_
  4. /* maximum packet size */
  5. #define PKTSIZE 1524
  6. /* number of transmit buffers */
  7. #define TXBUFCNT 4
  8. /* Adapter ID's */
  9. #define IBM_LANA_ID 0xffe0
  10. /* media enumeration - defined in a way that it fits onto the LAN/A's
  11. POS registers... */
  12. typedef enum {
  13. Media_10BaseT, Media_10Base5,
  14. Media_Unknown, Media_10Base2, Media_Count
  15. } ibmlana_medium;
  16. /* private structure */
  17. typedef struct {
  18. unsigned int slot; /* MCA-Slot-# */
  19. struct net_device_stats stat; /* packet statistics */
  20. int realirq; /* memorizes actual IRQ, even when
  21. currently not allocated */
  22. ibmlana_medium medium; /* physical cannector */
  23. u32 tdastart, txbufstart, /* addresses */
  24. rrastart, rxbufstart, rdastart, rxbufcnt, txusedcnt;
  25. int nextrxdescr, /* next rx descriptor to be used */
  26. lastrxdescr, /* last free rx descriptor */
  27. nexttxdescr, /* last tx descriptor to be used */
  28. currtxdescr, /* tx descriptor currently tx'ed */
  29. txused[TXBUFCNT]; /* busy flags */
  30. void __iomem *base;
  31. spinlock_t lock;
  32. } ibmlana_priv;
  33. /* this card uses quite a lot of I/O ports...luckily the MCA bus decodes
  34. a full 64K I/O range... */
  35. #define IBM_LANA_IORANGE 0xa0
  36. /* Command Register: */
  37. #define SONIC_CMDREG 0x00
  38. #define CMDREG_HTX 0x0001 /* halt transmission */
  39. #define CMDREG_TXP 0x0002 /* start transmission */
  40. #define CMDREG_RXDIS 0x0004 /* disable receiver */
  41. #define CMDREG_RXEN 0x0008 /* enable receiver */
  42. #define CMDREG_STP 0x0010 /* stop timer */
  43. #define CMDREG_ST 0x0020 /* start timer */
  44. #define CMDREG_RST 0x0080 /* software reset */
  45. #define CMDREG_RRRA 0x0100 /* force SONIC to read first RRA */
  46. #define CMDREG_LCAM 0x0200 /* force SONIC to read CAM descrs */
  47. /* Data Configuration Register */
  48. #define SONIC_DCREG 0x02
  49. #define DCREG_EXBUS 0x8000 /* Extended Bus Mode */
  50. #define DCREG_LBR 0x2000 /* Latched Bus Retry */
  51. #define DCREG_PO1 0x1000 /* Programmable Outputs */
  52. #define DCREG_PO0 0x0800
  53. #define DCREG_SBUS 0x0400 /* Synchronous Bus Mode */
  54. #define DCREG_USR1 0x0200 /* User Definable Pins */
  55. #define DCREG_USR0 0x0100
  56. #define DCREG_WC0 0x0000 /* 0..3 Wait States */
  57. #define DCREG_WC1 0x0040
  58. #define DCREG_WC2 0x0080
  59. #define DCREG_WC3 0x00c0
  60. #define DCREG_DW16 0x0000 /* 16 bit Bus Mode */
  61. #define DCREG_DW32 0x0020 /* 32 bit Bus Mode */
  62. #define DCREG_BMS 0x0010 /* Block Mode Select */
  63. #define DCREG_RFT4 0x0000 /* 4/8/16/24 bytes RX Threshold */
  64. #define DCREG_RFT8 0x0004
  65. #define DCREG_RFT16 0x0008
  66. #define DCREG_RFT24 0x000c
  67. #define DCREG_TFT8 0x0000 /* 8/16/24/28 bytes TX Threshold */
  68. #define DCREG_TFT16 0x0001
  69. #define DCREG_TFT24 0x0002
  70. #define DCREG_TFT28 0x0003
  71. /* Receive Control Register */
  72. #define SONIC_RCREG 0x04
  73. #define RCREG_ERR 0x8000 /* accept damaged and collided pkts */
  74. #define RCREG_RNT 0x4000 /* accept packets that are < 64 */
  75. #define RCREG_BRD 0x2000 /* accept broadcasts */
  76. #define RCREG_PRO 0x1000 /* promiscous mode */
  77. #define RCREG_AMC 0x0800 /* accept all multicasts */
  78. #define RCREG_LB_NONE 0x0000 /* no loopback */
  79. #define RCREG_LB_MAC 0x0200 /* MAC loopback */
  80. #define RCREG_LB_ENDEC 0x0400 /* ENDEC loopback */
  81. #define RCREG_LB_XVR 0x0600 /* Transceiver loopback */
  82. #define RCREG_MC 0x0100 /* Multicast received */
  83. #define RCREG_BC 0x0080 /* Broadcast received */
  84. #define RCREG_LPKT 0x0040 /* last packet in RBA */
  85. #define RCREG_CRS 0x0020 /* carrier sense present */
  86. #define RCREG_COL 0x0010 /* recv'd packet with collision */
  87. #define RCREG_CRCR 0x0008 /* recv'd packet with CRC error */
  88. #define RCREG_FAER 0x0004 /* recv'd packet with inv. framing */
  89. #define RCREG_LBK 0x0002 /* recv'd loopback packet */
  90. #define RCREG_PRX 0x0001 /* recv'd packet is OK */
  91. /* Transmit Control Register */
  92. #define SONIC_TCREG 0x06
  93. #define TCREG_PINT 0x8000 /* generate interrupt after TDA read */
  94. #define TCREG_POWC 0x4000 /* timer start out of window detect */
  95. #define TCREG_CRCI 0x2000 /* inhibit CRC generation */
  96. #define TCREG_EXDIS 0x1000 /* disable excessive deferral timer */
  97. #define TCREG_EXD 0x0400 /* excessive deferral occurred */
  98. #define TCREG_DEF 0x0200 /* single deferral occurred */
  99. #define TCREG_NCRS 0x0100 /* no carrier detected */
  100. #define TCREG_CRSL 0x0080 /* carrier lost */
  101. #define TCREG_EXC 0x0040 /* excessive collisions occurred */
  102. #define TCREG_OWC 0x0020 /* out of window collision occurred */
  103. #define TCREG_PMB 0x0008 /* packet monitored bad */
  104. #define TCREG_FU 0x0004 /* FIFO underrun */
  105. #define TCREG_BCM 0x0002 /* byte count mismatch of fragments */
  106. #define TCREG_PTX 0x0001 /* packet transmitted OK */
  107. /* Interrupt Mask Register */
  108. #define SONIC_IMREG 0x08
  109. #define IMREG_BREN 0x4000 /* interrupt when bus retry occurred */
  110. #define IMREG_HBLEN 0x2000 /* interrupt when heartbeat lost */
  111. #define IMREG_LCDEN 0x1000 /* interrupt when CAM loaded */
  112. #define IMREG_PINTEN 0x0800 /* interrupt when PINT in TDA set */
  113. #define IMREG_PRXEN 0x0400 /* interrupt when packet received */
  114. #define IMREG_PTXEN 0x0200 /* interrupt when packet was sent */
  115. #define IMREG_TXEREN 0x0100 /* interrupt when send failed */
  116. #define IMREG_TCEN 0x0080 /* interrupt when timer completed */
  117. #define IMREG_RDEEN 0x0040 /* interrupt when RDA exhausted */
  118. #define IMREG_RBEEN 0x0020 /* interrupt when RBA exhausted */
  119. #define IMREG_RBAEEN 0x0010 /* interrupt when RBA too short */
  120. #define IMREG_CRCEN 0x0008 /* interrupt when CRC counter rolls */
  121. #define IMREG_FAEEN 0x0004 /* interrupt when FAE counter rolls */
  122. #define IMREG_MPEN 0x0002 /* interrupt when MP counter rolls */
  123. #define IMREG_RFOEN 0x0001 /* interrupt when Rx FIFO overflows */
  124. /* Interrupt Status Register */
  125. #define SONIC_ISREG 0x0a
  126. #define ISREG_BR 0x4000 /* bus retry occurred */
  127. #define ISREG_HBL 0x2000 /* heartbeat lost */
  128. #define ISREG_LCD 0x1000 /* CAM loaded */
  129. #define ISREG_PINT 0x0800 /* PINT in TDA set */
  130. #define ISREG_PKTRX 0x0400 /* packet received */
  131. #define ISREG_TXDN 0x0200 /* packet was sent */
  132. #define ISREG_TXER 0x0100 /* send failed */
  133. #define ISREG_TC 0x0080 /* timer completed */
  134. #define ISREG_RDE 0x0040 /* RDA exhausted */
  135. #define ISREG_RBE 0x0020 /* RBA exhausted */
  136. #define ISREG_RBAE 0x0010 /* RBA too short for received frame */
  137. #define ISREG_CRC 0x0008 /* CRC counter rolls over */
  138. #define ISREG_FAE 0x0004 /* FAE counter rolls over */
  139. #define ISREG_MP 0x0002 /* MP counter rolls over */
  140. #define ISREG_RFO 0x0001 /* Rx FIFO overflows */
  141. #define SONIC_UTDA 0x0c /* current transmit descr address */
  142. #define SONIC_CTDA 0x0e
  143. #define SONIC_URDA 0x1a /* current receive descr address */
  144. #define SONIC_CRDA 0x1c
  145. #define SONIC_CRBA0 0x1e /* current receive buffer address */
  146. #define SONIC_CRBA1 0x20
  147. #define SONIC_RBWC0 0x22 /* word count in receive buffer */
  148. #define SONIC_RBWC1 0x24
  149. #define SONIC_EOBC 0x26 /* minimum space to be free in RBA */
  150. #define SONIC_URRA 0x28 /* upper address of CDA & Recv Area */
  151. #define SONIC_RSA 0x2a /* start of receive resource area */
  152. #define SONIC_REA 0x2c /* end of receive resource area */
  153. #define SONIC_RRP 0x2e /* resource read pointer */
  154. #define SONIC_RWP 0x30 /* resource write pointer */
  155. #define SONIC_CAMEPTR 0x42 /* CAM entry pointer */
  156. #define SONIC_CAMADDR2 0x44 /* CAM address ports */
  157. #define SONIC_CAMADDR1 0x46
  158. #define SONIC_CAMADDR0 0x48
  159. #define SONIC_CAMPTR 0x4c /* lower address of CDA */
  160. #define SONIC_CAMCNT 0x4e /* # of CAM descriptors to load */
  161. /* Data Configuration Register 2 */
  162. #define SONIC_DCREG2 0x7e
  163. #define DCREG2_EXPO3 0x8000 /* extended programmable outputs */
  164. #define DCREG2_EXPO2 0x4000
  165. #define DCREG2_EXPO1 0x2000
  166. #define DCREG2_EXPO0 0x1000
  167. #define DCREG2_HD 0x0800 /* heartbeat disable */
  168. #define DCREG2_JD 0x0200 /* jabber timer disable */
  169. #define DCREG2_AUTO 0x0100 /* enable AUI/TP auto selection */
  170. #define DCREG2_XWRAP 0x0040 /* TP transceiver loopback */
  171. #define DCREG2_PH 0x0010 /* HOLD request timing */
  172. #define DCREG2_PCM 0x0004 /* packet compress when matched */
  173. #define DCREG2_PCNM 0x0002 /* packet compress when not matched */
  174. #define DCREG2_RJCM 0x0001 /* inverse packet match via CAM */
  175. /* Board Control Register: Enable RAM, Interrupts... */
  176. #define BCMREG 0x80
  177. #define BCMREG_RAMEN 0x80 /* switch over to RAM */
  178. #define BCMREG_IPEND 0x40 /* interrupt pending ? */
  179. #define BCMREG_RESET 0x08 /* reset board */
  180. #define BCMREG_16BIT 0x04 /* adapter in 16-bit slot */
  181. #define BCMREG_RAMWIN 0x02 /* enable RAM window */
  182. #define BCMREG_IEN 0x01 /* interrupt enable */
  183. /* MAC Address PROM */
  184. #define MACADDRPROM 0x92
  185. /* structure of a CAM entry */
  186. typedef struct {
  187. u32 index; /* pointer into CAM area */
  188. u32 addr0; /* address part (bits 0..15 used) */
  189. u32 addr1;
  190. u32 addr2;
  191. } camentry_t;
  192. /* structure of a receive resource */
  193. typedef struct {
  194. u32 startlo; /* start address (bits 0..15 used) */
  195. u32 starthi;
  196. u32 cntlo; /* size in 16-bit quantities */
  197. u32 cnthi;
  198. } rra_t;
  199. /* structure of a receive descriptor */
  200. typedef struct {
  201. u32 status; /* packet status */
  202. u32 length; /* length in bytes */
  203. u32 startlo; /* start address */
  204. u32 starthi;
  205. u32 seqno; /* frame sequence */
  206. u32 link; /* pointer to next descriptor */
  207. /* bit 0 = EOL */
  208. u32 inuse; /* !=0 --> free for SONIC to write */
  209. } rda_t;
  210. /* structure of a transmit descriptor */
  211. typedef struct {
  212. u32 status; /* transmit status */
  213. u32 config; /* value for TCR */
  214. u32 length; /* total length */
  215. u32 fragcount; /* number of fragments */
  216. u32 startlo; /* start address of fragment */
  217. u32 starthi;
  218. u32 fraglength; /* length of this fragment */
  219. /* more address/length triplets may */
  220. /* follow here */
  221. u32 link; /* pointer to next descriptor */
  222. /* bit 0 = EOL */
  223. } tda_t;
  224. #endif /* _IBM_LANA_DRIVER_ */
  225. #endif /* _IBM_LANA_INCLUDE_ */