gianfar.h 25 KB

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  1. /*
  2. * drivers/net/gianfar.h
  3. *
  4. * Gianfar Ethernet Driver
  5. * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
  6. * Based on 8260_io/fcc_enet.c
  7. *
  8. * Author: Andy Fleming
  9. * Maintainer: Kumar Gala
  10. *
  11. * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. *
  18. * Still left to do:
  19. * -Add support for module parameters
  20. * -Add patch for ethtool phys id
  21. */
  22. #ifndef __GIANFAR_H
  23. #define __GIANFAR_H
  24. #include <linux/kernel.h>
  25. #include <linux/sched.h>
  26. #include <linux/string.h>
  27. #include <linux/errno.h>
  28. #include <linux/slab.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/init.h>
  31. #include <linux/delay.h>
  32. #include <linux/netdevice.h>
  33. #include <linux/etherdevice.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/spinlock.h>
  36. #include <linux/mm.h>
  37. #include <linux/mii.h>
  38. #include <linux/phy.h>
  39. #include <asm/io.h>
  40. #include <asm/irq.h>
  41. #include <asm/uaccess.h>
  42. #include <linux/module.h>
  43. #include <linux/crc32.h>
  44. #include <linux/workqueue.h>
  45. #include <linux/ethtool.h>
  46. #include <linux/netdevice.h>
  47. #include <linux/fsl_devices.h>
  48. #include "gianfar_mii.h"
  49. /* The maximum number of packets to be handled in one call of gfar_poll */
  50. #define GFAR_DEV_WEIGHT 64
  51. /* Length for FCB */
  52. #define GMAC_FCB_LEN 8
  53. /* Default padding amount */
  54. #define DEFAULT_PADDING 2
  55. /* Number of bytes to align the rx bufs to */
  56. #define RXBUF_ALIGNMENT 64
  57. /* The number of bytes which composes a unit for the purpose of
  58. * allocating data buffers. ie-for any given MTU, the data buffer
  59. * will be the next highest multiple of 512 bytes. */
  60. #define INCREMENTAL_BUFFER_SIZE 512
  61. #define MAC_ADDR_LEN 6
  62. #define PHY_INIT_TIMEOUT 100000
  63. #define GFAR_PHY_CHANGE_TIME 2
  64. #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
  65. #define DRV_NAME "gfar-enet"
  66. extern const char gfar_driver_name[];
  67. extern const char gfar_driver_version[];
  68. /* These need to be powers of 2 for this driver */
  69. #ifdef CONFIG_GFAR_NAPI
  70. #define DEFAULT_TX_RING_SIZE 256
  71. #define DEFAULT_RX_RING_SIZE 256
  72. #else
  73. #define DEFAULT_TX_RING_SIZE 64
  74. #define DEFAULT_RX_RING_SIZE 64
  75. #endif
  76. #define GFAR_RX_MAX_RING_SIZE 256
  77. #define GFAR_TX_MAX_RING_SIZE 256
  78. #define GFAR_MAX_FIFO_THRESHOLD 511
  79. #define GFAR_MAX_FIFO_STARVE 511
  80. #define GFAR_MAX_FIFO_STARVE_OFF 511
  81. #define DEFAULT_RX_BUFFER_SIZE 1536
  82. #define TX_RING_MOD_MASK(size) (size-1)
  83. #define RX_RING_MOD_MASK(size) (size-1)
  84. #define JUMBO_BUFFER_SIZE 9728
  85. #define JUMBO_FRAME_SIZE 9600
  86. #define DEFAULT_FIFO_TX_THR 0x100
  87. #define DEFAULT_FIFO_TX_STARVE 0x40
  88. #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
  89. #define DEFAULT_BD_STASH 1
  90. #define DEFAULT_STASH_LENGTH 64
  91. #define DEFAULT_STASH_INDEX 0
  92. /* The number of Exact Match registers */
  93. #define GFAR_EM_NUM 15
  94. /* Latency of interface clock in nanoseconds */
  95. /* Interface clock latency , in this case, means the
  96. * time described by a value of 1 in the interrupt
  97. * coalescing registers' time fields. Since those fields
  98. * refer to the time it takes for 64 clocks to pass, the
  99. * latencies are as such:
  100. * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
  101. * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
  102. * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
  103. */
  104. #define GFAR_GBIT_TIME 512
  105. #define GFAR_100_TIME 2560
  106. #define GFAR_10_TIME 25600
  107. #define DEFAULT_TX_COALESCE 1
  108. #define DEFAULT_TXCOUNT 16
  109. #define DEFAULT_TXTIME 4
  110. #define DEFAULT_RX_COALESCE 1
  111. #define DEFAULT_RXCOUNT 16
  112. #define DEFAULT_RXTIME 4
  113. #define TBIPA_VALUE 0x1f
  114. #define MIIMCFG_INIT_VALUE 0x00000007
  115. #define MIIMCFG_RESET 0x80000000
  116. #define MIIMIND_BUSY 0x00000001
  117. /* MAC register bits */
  118. #define MACCFG1_SOFT_RESET 0x80000000
  119. #define MACCFG1_RESET_RX_MC 0x00080000
  120. #define MACCFG1_RESET_TX_MC 0x00040000
  121. #define MACCFG1_RESET_RX_FUN 0x00020000
  122. #define MACCFG1_RESET_TX_FUN 0x00010000
  123. #define MACCFG1_LOOPBACK 0x00000100
  124. #define MACCFG1_RX_FLOW 0x00000020
  125. #define MACCFG1_TX_FLOW 0x00000010
  126. #define MACCFG1_SYNCD_RX_EN 0x00000008
  127. #define MACCFG1_RX_EN 0x00000004
  128. #define MACCFG1_SYNCD_TX_EN 0x00000002
  129. #define MACCFG1_TX_EN 0x00000001
  130. #define MACCFG2_INIT_SETTINGS 0x00007205
  131. #define MACCFG2_FULL_DUPLEX 0x00000001
  132. #define MACCFG2_IF 0x00000300
  133. #define MACCFG2_MII 0x00000100
  134. #define MACCFG2_GMII 0x00000200
  135. #define MACCFG2_HUGEFRAME 0x00000020
  136. #define MACCFG2_LENGTHCHECK 0x00000010
  137. #define ECNTRL_INIT_SETTINGS 0x00001000
  138. #define ECNTRL_TBI_MODE 0x00000020
  139. #define ECNTRL_REDUCED_MODE 0x00000010
  140. #define ECNTRL_R100 0x00000008
  141. #define ECNTRL_REDUCED_MII_MODE 0x00000004
  142. #define ECNTRL_SGMII_MODE 0x00000002
  143. #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
  144. #define MINFLR_INIT_SETTINGS 0x00000040
  145. /* Init to do tx snooping for buffers and descriptors */
  146. #define DMACTRL_INIT_SETTINGS 0x000000c3
  147. #define DMACTRL_GRS 0x00000010
  148. #define DMACTRL_GTS 0x00000008
  149. #define TSTAT_CLEAR_THALT 0x80000000
  150. /* Interrupt coalescing macros */
  151. #define IC_ICEN 0x80000000
  152. #define IC_ICFT_MASK 0x1fe00000
  153. #define IC_ICFT_SHIFT 21
  154. #define mk_ic_icft(x) \
  155. (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
  156. #define IC_ICTT_MASK 0x0000ffff
  157. #define mk_ic_ictt(x) (x&IC_ICTT_MASK)
  158. #define mk_ic_value(count, time) (IC_ICEN | \
  159. mk_ic_icft(count) | \
  160. mk_ic_ictt(time))
  161. #define RCTRL_PAL_MASK 0x001f0000
  162. #define RCTRL_VLEX 0x00002000
  163. #define RCTRL_FILREN 0x00001000
  164. #define RCTRL_GHTX 0x00000400
  165. #define RCTRL_IPCSEN 0x00000200
  166. #define RCTRL_TUCSEN 0x00000100
  167. #define RCTRL_PRSDEP_MASK 0x000000c0
  168. #define RCTRL_PRSDEP_INIT 0x000000c0
  169. #define RCTRL_PROM 0x00000008
  170. #define RCTRL_EMEN 0x00000002
  171. #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN \
  172. | RCTRL_TUCSEN | RCTRL_PRSDEP_INIT)
  173. #define RCTRL_EXTHASH (RCTRL_GHTX)
  174. #define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
  175. #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
  176. #define RSTAT_CLEAR_RHALT 0x00800000
  177. #define TCTRL_IPCSEN 0x00004000
  178. #define TCTRL_TUCSEN 0x00002000
  179. #define TCTRL_VLINS 0x00001000
  180. #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
  181. #define IEVENT_INIT_CLEAR 0xffffffff
  182. #define IEVENT_BABR 0x80000000
  183. #define IEVENT_RXC 0x40000000
  184. #define IEVENT_BSY 0x20000000
  185. #define IEVENT_EBERR 0x10000000
  186. #define IEVENT_MSRO 0x04000000
  187. #define IEVENT_GTSC 0x02000000
  188. #define IEVENT_BABT 0x01000000
  189. #define IEVENT_TXC 0x00800000
  190. #define IEVENT_TXE 0x00400000
  191. #define IEVENT_TXB 0x00200000
  192. #define IEVENT_TXF 0x00100000
  193. #define IEVENT_LC 0x00040000
  194. #define IEVENT_CRL 0x00020000
  195. #define IEVENT_XFUN 0x00010000
  196. #define IEVENT_RXB0 0x00008000
  197. #define IEVENT_GRSC 0x00000100
  198. #define IEVENT_RXF0 0x00000080
  199. #define IEVENT_FIR 0x00000008
  200. #define IEVENT_FIQ 0x00000004
  201. #define IEVENT_DPE 0x00000002
  202. #define IEVENT_PERR 0x00000001
  203. #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0)
  204. #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
  205. #define IEVENT_ERR_MASK \
  206. (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
  207. IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
  208. | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR)
  209. #define IMASK_INIT_CLEAR 0x00000000
  210. #define IMASK_BABR 0x80000000
  211. #define IMASK_RXC 0x40000000
  212. #define IMASK_BSY 0x20000000
  213. #define IMASK_EBERR 0x10000000
  214. #define IMASK_MSRO 0x04000000
  215. #define IMASK_GRSC 0x02000000
  216. #define IMASK_BABT 0x01000000
  217. #define IMASK_TXC 0x00800000
  218. #define IMASK_TXEEN 0x00400000
  219. #define IMASK_TXBEN 0x00200000
  220. #define IMASK_TXFEN 0x00100000
  221. #define IMASK_LC 0x00040000
  222. #define IMASK_CRL 0x00020000
  223. #define IMASK_XFUN 0x00010000
  224. #define IMASK_RXB0 0x00008000
  225. #define IMASK_GTSC 0x00000100
  226. #define IMASK_RXFEN0 0x00000080
  227. #define IMASK_FIR 0x00000008
  228. #define IMASK_FIQ 0x00000004
  229. #define IMASK_DPE 0x00000002
  230. #define IMASK_PERR 0x00000001
  231. #define IMASK_RX_DISABLED ~(IMASK_RXFEN0 | IMASK_BSY)
  232. #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
  233. IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
  234. IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
  235. | IMASK_PERR)
  236. /* Fifo management */
  237. #define FIFO_TX_THR_MASK 0x01ff
  238. #define FIFO_TX_STARVE_MASK 0x01ff
  239. #define FIFO_TX_STARVE_OFF_MASK 0x01ff
  240. /* Attribute fields */
  241. /* This enables rx snooping for buffers and descriptors */
  242. #define ATTR_BDSTASH 0x00000800
  243. #define ATTR_BUFSTASH 0x00004000
  244. #define ATTR_SNOOPING 0x000000c0
  245. #define ATTR_INIT_SETTINGS ATTR_SNOOPING
  246. #define ATTRELI_INIT_SETTINGS 0x0
  247. #define ATTRELI_EL_MASK 0x3fff0000
  248. #define ATTRELI_EL(x) (x << 16)
  249. #define ATTRELI_EI_MASK 0x00003fff
  250. #define ATTRELI_EI(x) (x)
  251. /* TxBD status field bits */
  252. #define TXBD_READY 0x8000
  253. #define TXBD_PADCRC 0x4000
  254. #define TXBD_WRAP 0x2000
  255. #define TXBD_INTERRUPT 0x1000
  256. #define TXBD_LAST 0x0800
  257. #define TXBD_CRC 0x0400
  258. #define TXBD_DEF 0x0200
  259. #define TXBD_HUGEFRAME 0x0080
  260. #define TXBD_LATECOLLISION 0x0080
  261. #define TXBD_RETRYLIMIT 0x0040
  262. #define TXBD_RETRYCOUNTMASK 0x003c
  263. #define TXBD_UNDERRUN 0x0002
  264. #define TXBD_TOE 0x0002
  265. /* Tx FCB param bits */
  266. #define TXFCB_VLN 0x80
  267. #define TXFCB_IP 0x40
  268. #define TXFCB_IP6 0x20
  269. #define TXFCB_TUP 0x10
  270. #define TXFCB_UDP 0x08
  271. #define TXFCB_CIP 0x04
  272. #define TXFCB_CTU 0x02
  273. #define TXFCB_NPH 0x01
  274. #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
  275. /* RxBD status field bits */
  276. #define RXBD_EMPTY 0x8000
  277. #define RXBD_RO1 0x4000
  278. #define RXBD_WRAP 0x2000
  279. #define RXBD_INTERRUPT 0x1000
  280. #define RXBD_LAST 0x0800
  281. #define RXBD_FIRST 0x0400
  282. #define RXBD_MISS 0x0100
  283. #define RXBD_BROADCAST 0x0080
  284. #define RXBD_MULTICAST 0x0040
  285. #define RXBD_LARGE 0x0020
  286. #define RXBD_NONOCTET 0x0010
  287. #define RXBD_SHORT 0x0008
  288. #define RXBD_CRCERR 0x0004
  289. #define RXBD_OVERRUN 0x0002
  290. #define RXBD_TRUNCATED 0x0001
  291. #define RXBD_STATS 0x01ff
  292. /* Rx FCB status field bits */
  293. #define RXFCB_VLN 0x8000
  294. #define RXFCB_IP 0x4000
  295. #define RXFCB_IP6 0x2000
  296. #define RXFCB_TUP 0x1000
  297. #define RXFCB_CIP 0x0800
  298. #define RXFCB_CTU 0x0400
  299. #define RXFCB_EIP 0x0200
  300. #define RXFCB_ETU 0x0100
  301. #define RXFCB_CSUM_MASK 0x0f00
  302. #define RXFCB_PERR_MASK 0x000c
  303. #define RXFCB_PERR_BADL3 0x0008
  304. struct txbd8
  305. {
  306. u16 status; /* Status Fields */
  307. u16 length; /* Buffer length */
  308. u32 bufPtr; /* Buffer Pointer */
  309. };
  310. struct txfcb {
  311. u8 flags;
  312. u8 reserved;
  313. u8 l4os; /* Level 4 Header Offset */
  314. u8 l3os; /* Level 3 Header Offset */
  315. u16 phcs; /* Pseudo-header Checksum */
  316. u16 vlctl; /* VLAN control word */
  317. };
  318. struct rxbd8
  319. {
  320. u16 status; /* Status Fields */
  321. u16 length; /* Buffer Length */
  322. u32 bufPtr; /* Buffer Pointer */
  323. };
  324. struct rxfcb {
  325. u16 flags;
  326. u8 rq; /* Receive Queue index */
  327. u8 pro; /* Layer 4 Protocol */
  328. u16 reserved;
  329. u16 vlctl; /* VLAN control word */
  330. };
  331. struct rmon_mib
  332. {
  333. u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
  334. u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
  335. u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
  336. u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
  337. u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
  338. u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
  339. u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
  340. u32 rbyt; /* 0x.69c - Receive Byte Counter */
  341. u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
  342. u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
  343. u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
  344. u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
  345. u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
  346. u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
  347. u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
  348. u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
  349. u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
  350. u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
  351. u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
  352. u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
  353. u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
  354. u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
  355. u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
  356. u32 rdrp; /* 0x.6dc - Receive Drop Counter */
  357. u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
  358. u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
  359. u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
  360. u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
  361. u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
  362. u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
  363. u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
  364. u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
  365. u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
  366. u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
  367. u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
  368. u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
  369. u8 res1[4];
  370. u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
  371. u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
  372. u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
  373. u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
  374. u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
  375. u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
  376. u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
  377. u32 car1; /* 0x.730 - Carry Register One */
  378. u32 car2; /* 0x.734 - Carry Register Two */
  379. u32 cam1; /* 0x.738 - Carry Mask Register One */
  380. u32 cam2; /* 0x.73c - Carry Mask Register Two */
  381. };
  382. struct gfar_extra_stats {
  383. u64 kernel_dropped;
  384. u64 rx_large;
  385. u64 rx_short;
  386. u64 rx_nonoctet;
  387. u64 rx_crcerr;
  388. u64 rx_overrun;
  389. u64 rx_bsy;
  390. u64 rx_babr;
  391. u64 rx_trunc;
  392. u64 eberr;
  393. u64 tx_babt;
  394. u64 tx_underrun;
  395. u64 rx_skbmissing;
  396. u64 tx_timeout;
  397. };
  398. #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
  399. #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
  400. /* Number of stats in the stats structure (ignore car and cam regs)*/
  401. #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
  402. #define GFAR_INFOSTR_LEN 32
  403. struct gfar_stats {
  404. u64 extra[GFAR_EXTRA_STATS_LEN];
  405. u64 rmon[GFAR_RMON_LEN];
  406. };
  407. struct gfar {
  408. u32 tsec_id; /* 0x.000 - Controller ID register */
  409. u8 res1[12];
  410. u32 ievent; /* 0x.010 - Interrupt Event Register */
  411. u32 imask; /* 0x.014 - Interrupt Mask Register */
  412. u32 edis; /* 0x.018 - Error Disabled Register */
  413. u8 res2[4];
  414. u32 ecntrl; /* 0x.020 - Ethernet Control Register */
  415. u32 minflr; /* 0x.024 - Minimum Frame Length Register */
  416. u32 ptv; /* 0x.028 - Pause Time Value Register */
  417. u32 dmactrl; /* 0x.02c - DMA Control Register */
  418. u32 tbipa; /* 0x.030 - TBI PHY Address Register */
  419. u8 res3[88];
  420. u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
  421. u8 res4[8];
  422. u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
  423. u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
  424. u8 res5[4];
  425. u32 fifo_rx_pause; /* 0x.0a4 - FIFO receive pause threshold register */
  426. u32 fifo_rx_alarm; /* 0x.0a8 - FIFO receive alarm threshold register */
  427. u8 res6[84];
  428. u32 tctrl; /* 0x.100 - Transmit Control Register */
  429. u32 tstat; /* 0x.104 - Transmit Status Register */
  430. u32 dfvlan; /* 0x.108 - Default VLAN Control word */
  431. u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
  432. u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
  433. u32 tqueue; /* 0x.114 - Transmit queue control register */
  434. u8 res7[40];
  435. u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
  436. u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
  437. u8 res8[52];
  438. u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
  439. u8 res9a[4];
  440. u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
  441. u8 res9b[4];
  442. u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
  443. u8 res9c[4];
  444. u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
  445. u8 res9d[4];
  446. u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
  447. u8 res9e[4];
  448. u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
  449. u8 res9f[4];
  450. u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
  451. u8 res9g[4];
  452. u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
  453. u8 res9h[4];
  454. u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
  455. u8 res9[64];
  456. u32 tbaseh; /* 0x.200 - TxBD base address high */
  457. u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
  458. u8 res10a[4];
  459. u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
  460. u8 res10b[4];
  461. u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
  462. u8 res10c[4];
  463. u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
  464. u8 res10d[4];
  465. u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
  466. u8 res10e[4];
  467. u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
  468. u8 res10f[4];
  469. u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
  470. u8 res10g[4];
  471. u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
  472. u8 res10[192];
  473. u32 rctrl; /* 0x.300 - Receive Control Register */
  474. u32 rstat; /* 0x.304 - Receive Status Register */
  475. u8 res12[8];
  476. u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
  477. u32 rqueue; /* 0x.314 - Receive queue control register */
  478. u8 res13[24];
  479. u32 rbifx; /* 0x.330 - Receive bit field extract control register */
  480. u32 rqfar; /* 0x.334 - Receive queue filing table address register */
  481. u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
  482. u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
  483. u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
  484. u8 res14[56];
  485. u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
  486. u8 res15a[4];
  487. u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
  488. u8 res15b[4];
  489. u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
  490. u8 res15c[4];
  491. u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
  492. u8 res15d[4];
  493. u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
  494. u8 res15e[4];
  495. u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
  496. u8 res15f[4];
  497. u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
  498. u8 res15g[4];
  499. u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
  500. u8 res15h[4];
  501. u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
  502. u8 res16[64];
  503. u32 rbaseh; /* 0x.400 - RxBD base address high */
  504. u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
  505. u8 res17a[4];
  506. u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
  507. u8 res17b[4];
  508. u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
  509. u8 res17c[4];
  510. u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
  511. u8 res17d[4];
  512. u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
  513. u8 res17e[4];
  514. u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
  515. u8 res17f[4];
  516. u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
  517. u8 res17g[4];
  518. u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
  519. u8 res17[192];
  520. u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
  521. u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
  522. u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
  523. u32 hafdup; /* 0x.50c - Half Duplex Register */
  524. u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
  525. u8 res18[12];
  526. u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
  527. u8 res19[4];
  528. u32 ifstat; /* 0x.53c - Interface Status Register */
  529. u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
  530. u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
  531. u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
  532. u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
  533. u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
  534. u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
  535. u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
  536. u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
  537. u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
  538. u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
  539. u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
  540. u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
  541. u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
  542. u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
  543. u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
  544. u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
  545. u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
  546. u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
  547. u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
  548. u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
  549. u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
  550. u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
  551. u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
  552. u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
  553. u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
  554. u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
  555. u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
  556. u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
  557. u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
  558. u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
  559. u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
  560. u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
  561. u8 res20[192];
  562. struct rmon_mib rmon; /* 0x.680-0x.73c */
  563. u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
  564. u8 res21[188];
  565. u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
  566. u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
  567. u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
  568. u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
  569. u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
  570. u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
  571. u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
  572. u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
  573. u8 res22[96];
  574. u32 gaddr0; /* 0x.880 - Group address register 0 */
  575. u32 gaddr1; /* 0x.884 - Group address register 1 */
  576. u32 gaddr2; /* 0x.888 - Group address register 2 */
  577. u32 gaddr3; /* 0x.88c - Group address register 3 */
  578. u32 gaddr4; /* 0x.890 - Group address register 4 */
  579. u32 gaddr5; /* 0x.894 - Group address register 5 */
  580. u32 gaddr6; /* 0x.898 - Group address register 6 */
  581. u32 gaddr7; /* 0x.89c - Group address register 7 */
  582. u8 res23a[352];
  583. u32 fifocfg; /* 0x.a00 - FIFO interface config register */
  584. u8 res23b[252];
  585. u8 res23c[248];
  586. u32 attr; /* 0x.bf8 - Attributes Register */
  587. u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
  588. u8 res24[1024];
  589. };
  590. /* Struct stolen almost completely (and shamelessly) from the FCC enet source
  591. * (Ok, that's not so true anymore, but there is a family resemblence)
  592. * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
  593. * and tx_bd_base always point to the currently available buffer.
  594. * The dirty_tx tracks the current buffer that is being sent by the
  595. * controller. The cur_tx and dirty_tx are equal under both completely
  596. * empty and completely full conditions. The empty/ready indicator in
  597. * the buffer descriptor determines the actual condition.
  598. */
  599. struct gfar_private {
  600. /* Fields controlled by TX lock */
  601. spinlock_t txlock;
  602. /* Pointer to the array of skbuffs */
  603. struct sk_buff ** tx_skbuff;
  604. /* next free skb in the array */
  605. u16 skb_curtx;
  606. /* First skb in line to be transmitted */
  607. u16 skb_dirtytx;
  608. /* Configuration info for the coalescing features */
  609. unsigned char txcoalescing;
  610. unsigned short txcount;
  611. unsigned short txtime;
  612. /* Buffer descriptor pointers */
  613. struct txbd8 *tx_bd_base; /* First tx buffer descriptor */
  614. struct txbd8 *cur_tx; /* Next free ring entry */
  615. struct txbd8 *dirty_tx; /* First buffer in line
  616. to be transmitted */
  617. unsigned int tx_ring_size;
  618. /* RX Locked fields */
  619. spinlock_t rxlock;
  620. /* skb array and index */
  621. struct sk_buff ** rx_skbuff;
  622. u16 skb_currx;
  623. /* RX Coalescing values */
  624. unsigned char rxcoalescing;
  625. unsigned short rxcount;
  626. unsigned short rxtime;
  627. struct rxbd8 *rx_bd_base; /* First Rx buffers */
  628. struct rxbd8 *cur_rx; /* Next free rx ring entry */
  629. /* RX parameters */
  630. unsigned int rx_ring_size;
  631. unsigned int rx_buffer_size;
  632. unsigned int rx_stash_size;
  633. unsigned int rx_stash_index;
  634. struct vlan_group *vlgrp;
  635. /* Unprotected fields */
  636. /* Pointer to the GFAR memory mapped Registers */
  637. struct gfar __iomem *regs;
  638. /* Hash registers and their width */
  639. u32 __iomem *hash_regs[16];
  640. int hash_width;
  641. /* global parameters */
  642. unsigned int fifo_threshold;
  643. unsigned int fifo_starve;
  644. unsigned int fifo_starve_off;
  645. unsigned char vlan_enable:1,
  646. rx_csum_enable:1,
  647. extended_hash:1,
  648. bd_stash_en:1;
  649. unsigned short padding;
  650. unsigned int interruptTransmit;
  651. unsigned int interruptReceive;
  652. unsigned int interruptError;
  653. /* info structure initialized by platform code */
  654. struct gianfar_platform_data *einfo;
  655. /* PHY stuff */
  656. struct phy_device *phydev;
  657. struct mii_bus *mii_bus;
  658. int oldspeed;
  659. int oldduplex;
  660. int oldlink;
  661. uint32_t msg_enable;
  662. /* Network Statistics */
  663. struct net_device_stats stats;
  664. struct gfar_extra_stats extra_stats;
  665. };
  666. static inline u32 gfar_read(volatile unsigned __iomem *addr)
  667. {
  668. u32 val;
  669. val = in_be32(addr);
  670. return val;
  671. }
  672. static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
  673. {
  674. out_be32(addr, val);
  675. }
  676. extern irqreturn_t gfar_receive(int irq, void *dev_id);
  677. extern int startup_gfar(struct net_device *dev);
  678. extern void stop_gfar(struct net_device *dev);
  679. extern void gfar_halt(struct net_device *dev);
  680. extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
  681. int enable, u32 regnum, u32 read);
  682. void gfar_init_sysfs(struct net_device *dev);
  683. #endif /* __GIANFAR_H */