gianfar.c 52 KB

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  1. /*
  2. * drivers/net/gianfar.c
  3. *
  4. * Gianfar Ethernet Driver
  5. * This driver is designed for the non-CPM ethernet controllers
  6. * on the 85xx and 83xx family of integrated processors
  7. * Based on 8260_io/fcc_enet.c
  8. *
  9. * Author: Andy Fleming
  10. * Maintainer: Kumar Gala
  11. *
  12. * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
  13. * Copyright (c) 2007 MontaVista Software, Inc.
  14. *
  15. * This program is free software; you can redistribute it and/or modify it
  16. * under the terms of the GNU General Public License as published by the
  17. * Free Software Foundation; either version 2 of the License, or (at your
  18. * option) any later version.
  19. *
  20. * Gianfar: AKA Lambda Draconis, "Dragon"
  21. * RA 11 31 24.2
  22. * Dec +69 19 52
  23. * V 3.84
  24. * B-V +1.62
  25. *
  26. * Theory of operation
  27. *
  28. * The driver is initialized through platform_device. Structures which
  29. * define the configuration needed by the board are defined in a
  30. * board structure in arch/ppc/platforms (though I do not
  31. * discount the possibility that other architectures could one
  32. * day be supported.
  33. *
  34. * The Gianfar Ethernet Controller uses a ring of buffer
  35. * descriptors. The beginning is indicated by a register
  36. * pointing to the physical address of the start of the ring.
  37. * The end is determined by a "wrap" bit being set in the
  38. * last descriptor of the ring.
  39. *
  40. * When a packet is received, the RXF bit in the
  41. * IEVENT register is set, triggering an interrupt when the
  42. * corresponding bit in the IMASK register is also set (if
  43. * interrupt coalescing is active, then the interrupt may not
  44. * happen immediately, but will wait until either a set number
  45. * of frames or amount of time have passed). In NAPI, the
  46. * interrupt handler will signal there is work to be done, and
  47. * exit. Without NAPI, the packet(s) will be handled
  48. * immediately. Both methods will start at the last known empty
  49. * descriptor, and process every subsequent descriptor until there
  50. * are none left with data (NAPI will stop after a set number of
  51. * packets to give time to other tasks, but will eventually
  52. * process all the packets). The data arrives inside a
  53. * pre-allocated skb, and so after the skb is passed up to the
  54. * stack, a new skb must be allocated, and the address field in
  55. * the buffer descriptor must be updated to indicate this new
  56. * skb.
  57. *
  58. * When the kernel requests that a packet be transmitted, the
  59. * driver starts where it left off last time, and points the
  60. * descriptor at the buffer which was passed in. The driver
  61. * then informs the DMA engine that there are packets ready to
  62. * be transmitted. Once the controller is finished transmitting
  63. * the packet, an interrupt may be triggered (under the same
  64. * conditions as for reception, but depending on the TXF bit).
  65. * The driver then cleans up the buffer.
  66. */
  67. #include <linux/kernel.h>
  68. #include <linux/string.h>
  69. #include <linux/errno.h>
  70. #include <linux/unistd.h>
  71. #include <linux/slab.h>
  72. #include <linux/interrupt.h>
  73. #include <linux/init.h>
  74. #include <linux/delay.h>
  75. #include <linux/netdevice.h>
  76. #include <linux/etherdevice.h>
  77. #include <linux/skbuff.h>
  78. #include <linux/if_vlan.h>
  79. #include <linux/spinlock.h>
  80. #include <linux/mm.h>
  81. #include <linux/platform_device.h>
  82. #include <linux/ip.h>
  83. #include <linux/tcp.h>
  84. #include <linux/udp.h>
  85. #include <linux/in.h>
  86. #include <asm/io.h>
  87. #include <asm/irq.h>
  88. #include <asm/uaccess.h>
  89. #include <linux/module.h>
  90. #include <linux/dma-mapping.h>
  91. #include <linux/crc32.h>
  92. #include <linux/mii.h>
  93. #include <linux/phy.h>
  94. #include "gianfar.h"
  95. #include "gianfar_mii.h"
  96. #define TX_TIMEOUT (1*HZ)
  97. #define SKB_ALLOC_TIMEOUT 1000000
  98. #undef BRIEF_GFAR_ERRORS
  99. #undef VERBOSE_GFAR_ERRORS
  100. #ifdef CONFIG_GFAR_NAPI
  101. #define RECEIVE(x) netif_receive_skb(x)
  102. #else
  103. #define RECEIVE(x) netif_rx(x)
  104. #endif
  105. const char gfar_driver_name[] = "Gianfar Ethernet";
  106. const char gfar_driver_version[] = "1.3";
  107. static int gfar_enet_open(struct net_device *dev);
  108. static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
  109. static void gfar_timeout(struct net_device *dev);
  110. static int gfar_close(struct net_device *dev);
  111. struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
  112. static struct net_device_stats *gfar_get_stats(struct net_device *dev);
  113. static int gfar_set_mac_address(struct net_device *dev);
  114. static int gfar_change_mtu(struct net_device *dev, int new_mtu);
  115. static irqreturn_t gfar_error(int irq, void *dev_id);
  116. static irqreturn_t gfar_transmit(int irq, void *dev_id);
  117. static irqreturn_t gfar_interrupt(int irq, void *dev_id);
  118. static void adjust_link(struct net_device *dev);
  119. static void init_registers(struct net_device *dev);
  120. static int init_phy(struct net_device *dev);
  121. static int gfar_probe(struct platform_device *pdev);
  122. static int gfar_remove(struct platform_device *pdev);
  123. static void free_skb_resources(struct gfar_private *priv);
  124. static void gfar_set_multi(struct net_device *dev);
  125. static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
  126. #ifdef CONFIG_GFAR_NAPI
  127. static int gfar_poll(struct net_device *dev, int *budget);
  128. #endif
  129. #ifdef CONFIG_NET_POLL_CONTROLLER
  130. static void gfar_netpoll(struct net_device *dev);
  131. #endif
  132. int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
  133. static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
  134. static void gfar_vlan_rx_register(struct net_device *netdev,
  135. struct vlan_group *grp);
  136. static void gfar_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
  137. void gfar_halt(struct net_device *dev);
  138. void gfar_start(struct net_device *dev);
  139. static void gfar_clear_exact_match(struct net_device *dev);
  140. static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
  141. extern const struct ethtool_ops gfar_ethtool_ops;
  142. MODULE_AUTHOR("Freescale Semiconductor, Inc");
  143. MODULE_DESCRIPTION("Gianfar Ethernet Driver");
  144. MODULE_LICENSE("GPL");
  145. /* Returns 1 if incoming frames use an FCB */
  146. static inline int gfar_uses_fcb(struct gfar_private *priv)
  147. {
  148. return (priv->vlan_enable || priv->rx_csum_enable);
  149. }
  150. /* Set up the ethernet device structure, private data,
  151. * and anything else we need before we start */
  152. static int gfar_probe(struct platform_device *pdev)
  153. {
  154. u32 tempval;
  155. struct net_device *dev = NULL;
  156. struct gfar_private *priv = NULL;
  157. struct gianfar_platform_data *einfo;
  158. struct resource *r;
  159. int idx;
  160. int err = 0;
  161. einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
  162. if (NULL == einfo) {
  163. printk(KERN_ERR "gfar %d: Missing additional data!\n",
  164. pdev->id);
  165. return -ENODEV;
  166. }
  167. /* Create an ethernet device instance */
  168. dev = alloc_etherdev(sizeof (*priv));
  169. if (NULL == dev)
  170. return -ENOMEM;
  171. priv = netdev_priv(dev);
  172. /* Set the info in the priv to the current info */
  173. priv->einfo = einfo;
  174. /* fill out IRQ fields */
  175. if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  176. priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
  177. priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
  178. priv->interruptError = platform_get_irq_byname(pdev, "error");
  179. if (priv->interruptTransmit < 0 || priv->interruptReceive < 0 || priv->interruptError < 0)
  180. goto regs_fail;
  181. } else {
  182. priv->interruptTransmit = platform_get_irq(pdev, 0);
  183. if (priv->interruptTransmit < 0)
  184. goto regs_fail;
  185. }
  186. /* get a pointer to the register memory */
  187. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  188. priv->regs = ioremap(r->start, sizeof (struct gfar));
  189. if (NULL == priv->regs) {
  190. err = -ENOMEM;
  191. goto regs_fail;
  192. }
  193. spin_lock_init(&priv->txlock);
  194. spin_lock_init(&priv->rxlock);
  195. platform_set_drvdata(pdev, dev);
  196. /* Stop the DMA engine now, in case it was running before */
  197. /* (The firmware could have used it, and left it running). */
  198. /* To do this, we write Graceful Receive Stop and Graceful */
  199. /* Transmit Stop, and then wait until the corresponding bits */
  200. /* in IEVENT indicate the stops have completed. */
  201. tempval = gfar_read(&priv->regs->dmactrl);
  202. tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
  203. gfar_write(&priv->regs->dmactrl, tempval);
  204. tempval = gfar_read(&priv->regs->dmactrl);
  205. tempval |= (DMACTRL_GRS | DMACTRL_GTS);
  206. gfar_write(&priv->regs->dmactrl, tempval);
  207. while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
  208. cpu_relax();
  209. /* Reset MAC layer */
  210. gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  211. tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
  212. gfar_write(&priv->regs->maccfg1, tempval);
  213. /* Initialize MACCFG2. */
  214. gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
  215. /* Initialize ECNTRL */
  216. gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
  217. /* Copy the station address into the dev structure, */
  218. memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
  219. /* Set the dev->base_addr to the gfar reg region */
  220. dev->base_addr = (unsigned long) (priv->regs);
  221. SET_MODULE_OWNER(dev);
  222. SET_NETDEV_DEV(dev, &pdev->dev);
  223. /* Fill in the dev structure */
  224. dev->open = gfar_enet_open;
  225. dev->hard_start_xmit = gfar_start_xmit;
  226. dev->tx_timeout = gfar_timeout;
  227. dev->watchdog_timeo = TX_TIMEOUT;
  228. #ifdef CONFIG_GFAR_NAPI
  229. dev->poll = gfar_poll;
  230. dev->weight = GFAR_DEV_WEIGHT;
  231. #endif
  232. #ifdef CONFIG_NET_POLL_CONTROLLER
  233. dev->poll_controller = gfar_netpoll;
  234. #endif
  235. dev->stop = gfar_close;
  236. dev->get_stats = gfar_get_stats;
  237. dev->change_mtu = gfar_change_mtu;
  238. dev->mtu = 1500;
  239. dev->set_multicast_list = gfar_set_multi;
  240. dev->ethtool_ops = &gfar_ethtool_ops;
  241. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
  242. priv->rx_csum_enable = 1;
  243. dev->features |= NETIF_F_IP_CSUM;
  244. } else
  245. priv->rx_csum_enable = 0;
  246. priv->vlgrp = NULL;
  247. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
  248. dev->vlan_rx_register = gfar_vlan_rx_register;
  249. dev->vlan_rx_kill_vid = gfar_vlan_rx_kill_vid;
  250. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  251. priv->vlan_enable = 1;
  252. }
  253. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
  254. priv->extended_hash = 1;
  255. priv->hash_width = 9;
  256. priv->hash_regs[0] = &priv->regs->igaddr0;
  257. priv->hash_regs[1] = &priv->regs->igaddr1;
  258. priv->hash_regs[2] = &priv->regs->igaddr2;
  259. priv->hash_regs[3] = &priv->regs->igaddr3;
  260. priv->hash_regs[4] = &priv->regs->igaddr4;
  261. priv->hash_regs[5] = &priv->regs->igaddr5;
  262. priv->hash_regs[6] = &priv->regs->igaddr6;
  263. priv->hash_regs[7] = &priv->regs->igaddr7;
  264. priv->hash_regs[8] = &priv->regs->gaddr0;
  265. priv->hash_regs[9] = &priv->regs->gaddr1;
  266. priv->hash_regs[10] = &priv->regs->gaddr2;
  267. priv->hash_regs[11] = &priv->regs->gaddr3;
  268. priv->hash_regs[12] = &priv->regs->gaddr4;
  269. priv->hash_regs[13] = &priv->regs->gaddr5;
  270. priv->hash_regs[14] = &priv->regs->gaddr6;
  271. priv->hash_regs[15] = &priv->regs->gaddr7;
  272. } else {
  273. priv->extended_hash = 0;
  274. priv->hash_width = 8;
  275. priv->hash_regs[0] = &priv->regs->gaddr0;
  276. priv->hash_regs[1] = &priv->regs->gaddr1;
  277. priv->hash_regs[2] = &priv->regs->gaddr2;
  278. priv->hash_regs[3] = &priv->regs->gaddr3;
  279. priv->hash_regs[4] = &priv->regs->gaddr4;
  280. priv->hash_regs[5] = &priv->regs->gaddr5;
  281. priv->hash_regs[6] = &priv->regs->gaddr6;
  282. priv->hash_regs[7] = &priv->regs->gaddr7;
  283. }
  284. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
  285. priv->padding = DEFAULT_PADDING;
  286. else
  287. priv->padding = 0;
  288. if (dev->features & NETIF_F_IP_CSUM)
  289. dev->hard_header_len += GMAC_FCB_LEN;
  290. priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
  291. priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
  292. priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
  293. priv->txcoalescing = DEFAULT_TX_COALESCE;
  294. priv->txcount = DEFAULT_TXCOUNT;
  295. priv->txtime = DEFAULT_TXTIME;
  296. priv->rxcoalescing = DEFAULT_RX_COALESCE;
  297. priv->rxcount = DEFAULT_RXCOUNT;
  298. priv->rxtime = DEFAULT_RXTIME;
  299. /* Enable most messages by default */
  300. priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  301. err = register_netdev(dev);
  302. if (err) {
  303. printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
  304. dev->name);
  305. goto register_fail;
  306. }
  307. /* Create all the sysfs files */
  308. gfar_init_sysfs(dev);
  309. /* Print out the device info */
  310. printk(KERN_INFO DEVICE_NAME, dev->name);
  311. for (idx = 0; idx < 6; idx++)
  312. printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
  313. printk("\n");
  314. /* Even more device info helps when determining which kernel */
  315. /* provided which set of benchmarks. */
  316. #ifdef CONFIG_GFAR_NAPI
  317. printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
  318. #else
  319. printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
  320. #endif
  321. printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
  322. dev->name, priv->rx_ring_size, priv->tx_ring_size);
  323. return 0;
  324. register_fail:
  325. iounmap(priv->regs);
  326. regs_fail:
  327. free_netdev(dev);
  328. return err;
  329. }
  330. static int gfar_remove(struct platform_device *pdev)
  331. {
  332. struct net_device *dev = platform_get_drvdata(pdev);
  333. struct gfar_private *priv = netdev_priv(dev);
  334. platform_set_drvdata(pdev, NULL);
  335. iounmap(priv->regs);
  336. free_netdev(dev);
  337. return 0;
  338. }
  339. /* Reads the controller's registers to determine what interface
  340. * connects it to the PHY.
  341. */
  342. static phy_interface_t gfar_get_interface(struct net_device *dev)
  343. {
  344. struct gfar_private *priv = netdev_priv(dev);
  345. u32 ecntrl = gfar_read(&priv->regs->ecntrl);
  346. if (ecntrl & ECNTRL_SGMII_MODE)
  347. return PHY_INTERFACE_MODE_SGMII;
  348. if (ecntrl & ECNTRL_TBI_MODE) {
  349. if (ecntrl & ECNTRL_REDUCED_MODE)
  350. return PHY_INTERFACE_MODE_RTBI;
  351. else
  352. return PHY_INTERFACE_MODE_TBI;
  353. }
  354. if (ecntrl & ECNTRL_REDUCED_MODE) {
  355. if (ecntrl & ECNTRL_REDUCED_MII_MODE)
  356. return PHY_INTERFACE_MODE_RMII;
  357. else
  358. return PHY_INTERFACE_MODE_RGMII;
  359. }
  360. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
  361. return PHY_INTERFACE_MODE_GMII;
  362. return PHY_INTERFACE_MODE_MII;
  363. }
  364. /* Initializes driver's PHY state, and attaches to the PHY.
  365. * Returns 0 on success.
  366. */
  367. static int init_phy(struct net_device *dev)
  368. {
  369. struct gfar_private *priv = netdev_priv(dev);
  370. uint gigabit_support =
  371. priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
  372. SUPPORTED_1000baseT_Full : 0;
  373. struct phy_device *phydev;
  374. char phy_id[BUS_ID_SIZE];
  375. phy_interface_t interface;
  376. priv->oldlink = 0;
  377. priv->oldspeed = 0;
  378. priv->oldduplex = -1;
  379. snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
  380. interface = gfar_get_interface(dev);
  381. phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
  382. if (IS_ERR(phydev)) {
  383. printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
  384. return PTR_ERR(phydev);
  385. }
  386. /* Remove any features not supported by the controller */
  387. phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
  388. phydev->advertising = phydev->supported;
  389. priv->phydev = phydev;
  390. return 0;
  391. }
  392. static void init_registers(struct net_device *dev)
  393. {
  394. struct gfar_private *priv = netdev_priv(dev);
  395. /* Clear IEVENT */
  396. gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
  397. /* Initialize IMASK */
  398. gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
  399. /* Init hash registers to zero */
  400. gfar_write(&priv->regs->igaddr0, 0);
  401. gfar_write(&priv->regs->igaddr1, 0);
  402. gfar_write(&priv->regs->igaddr2, 0);
  403. gfar_write(&priv->regs->igaddr3, 0);
  404. gfar_write(&priv->regs->igaddr4, 0);
  405. gfar_write(&priv->regs->igaddr5, 0);
  406. gfar_write(&priv->regs->igaddr6, 0);
  407. gfar_write(&priv->regs->igaddr7, 0);
  408. gfar_write(&priv->regs->gaddr0, 0);
  409. gfar_write(&priv->regs->gaddr1, 0);
  410. gfar_write(&priv->regs->gaddr2, 0);
  411. gfar_write(&priv->regs->gaddr3, 0);
  412. gfar_write(&priv->regs->gaddr4, 0);
  413. gfar_write(&priv->regs->gaddr5, 0);
  414. gfar_write(&priv->regs->gaddr6, 0);
  415. gfar_write(&priv->regs->gaddr7, 0);
  416. /* Zero out the rmon mib registers if it has them */
  417. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
  418. memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
  419. /* Mask off the CAM interrupts */
  420. gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
  421. gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
  422. }
  423. /* Initialize the max receive buffer length */
  424. gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
  425. /* Initialize the Minimum Frame Length Register */
  426. gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
  427. /* Assign the TBI an address which won't conflict with the PHYs */
  428. gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
  429. }
  430. /* Halt the receive and transmit queues */
  431. void gfar_halt(struct net_device *dev)
  432. {
  433. struct gfar_private *priv = netdev_priv(dev);
  434. struct gfar __iomem *regs = priv->regs;
  435. u32 tempval;
  436. /* Mask all interrupts */
  437. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  438. /* Clear all interrupts */
  439. gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
  440. /* Stop the DMA, and wait for it to stop */
  441. tempval = gfar_read(&priv->regs->dmactrl);
  442. if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
  443. != (DMACTRL_GRS | DMACTRL_GTS)) {
  444. tempval |= (DMACTRL_GRS | DMACTRL_GTS);
  445. gfar_write(&priv->regs->dmactrl, tempval);
  446. while (!(gfar_read(&priv->regs->ievent) &
  447. (IEVENT_GRSC | IEVENT_GTSC)))
  448. cpu_relax();
  449. }
  450. /* Disable Rx and Tx */
  451. tempval = gfar_read(&regs->maccfg1);
  452. tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
  453. gfar_write(&regs->maccfg1, tempval);
  454. }
  455. void stop_gfar(struct net_device *dev)
  456. {
  457. struct gfar_private *priv = netdev_priv(dev);
  458. struct gfar __iomem *regs = priv->regs;
  459. unsigned long flags;
  460. phy_stop(priv->phydev);
  461. /* Lock it down */
  462. spin_lock_irqsave(&priv->txlock, flags);
  463. spin_lock(&priv->rxlock);
  464. gfar_halt(dev);
  465. spin_unlock(&priv->rxlock);
  466. spin_unlock_irqrestore(&priv->txlock, flags);
  467. /* Free the IRQs */
  468. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  469. free_irq(priv->interruptError, dev);
  470. free_irq(priv->interruptTransmit, dev);
  471. free_irq(priv->interruptReceive, dev);
  472. } else {
  473. free_irq(priv->interruptTransmit, dev);
  474. }
  475. free_skb_resources(priv);
  476. dma_free_coherent(NULL,
  477. sizeof(struct txbd8)*priv->tx_ring_size
  478. + sizeof(struct rxbd8)*priv->rx_ring_size,
  479. priv->tx_bd_base,
  480. gfar_read(&regs->tbase0));
  481. }
  482. /* If there are any tx skbs or rx skbs still around, free them.
  483. * Then free tx_skbuff and rx_skbuff */
  484. static void free_skb_resources(struct gfar_private *priv)
  485. {
  486. struct rxbd8 *rxbdp;
  487. struct txbd8 *txbdp;
  488. int i;
  489. /* Go through all the buffer descriptors and free their data buffers */
  490. txbdp = priv->tx_bd_base;
  491. for (i = 0; i < priv->tx_ring_size; i++) {
  492. if (priv->tx_skbuff[i]) {
  493. dma_unmap_single(NULL, txbdp->bufPtr,
  494. txbdp->length,
  495. DMA_TO_DEVICE);
  496. dev_kfree_skb_any(priv->tx_skbuff[i]);
  497. priv->tx_skbuff[i] = NULL;
  498. }
  499. }
  500. kfree(priv->tx_skbuff);
  501. rxbdp = priv->rx_bd_base;
  502. /* rx_skbuff is not guaranteed to be allocated, so only
  503. * free it and its contents if it is allocated */
  504. if(priv->rx_skbuff != NULL) {
  505. for (i = 0; i < priv->rx_ring_size; i++) {
  506. if (priv->rx_skbuff[i]) {
  507. dma_unmap_single(NULL, rxbdp->bufPtr,
  508. priv->rx_buffer_size,
  509. DMA_FROM_DEVICE);
  510. dev_kfree_skb_any(priv->rx_skbuff[i]);
  511. priv->rx_skbuff[i] = NULL;
  512. }
  513. rxbdp->status = 0;
  514. rxbdp->length = 0;
  515. rxbdp->bufPtr = 0;
  516. rxbdp++;
  517. }
  518. kfree(priv->rx_skbuff);
  519. }
  520. }
  521. void gfar_start(struct net_device *dev)
  522. {
  523. struct gfar_private *priv = netdev_priv(dev);
  524. struct gfar __iomem *regs = priv->regs;
  525. u32 tempval;
  526. /* Enable Rx and Tx in MACCFG1 */
  527. tempval = gfar_read(&regs->maccfg1);
  528. tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
  529. gfar_write(&regs->maccfg1, tempval);
  530. /* Initialize DMACTRL to have WWR and WOP */
  531. tempval = gfar_read(&priv->regs->dmactrl);
  532. tempval |= DMACTRL_INIT_SETTINGS;
  533. gfar_write(&priv->regs->dmactrl, tempval);
  534. /* Make sure we aren't stopped */
  535. tempval = gfar_read(&priv->regs->dmactrl);
  536. tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
  537. gfar_write(&priv->regs->dmactrl, tempval);
  538. /* Clear THLT/RHLT, so that the DMA starts polling now */
  539. gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
  540. gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
  541. /* Unmask the interrupts we look for */
  542. gfar_write(&regs->imask, IMASK_DEFAULT);
  543. }
  544. /* Bring the controller up and running */
  545. int startup_gfar(struct net_device *dev)
  546. {
  547. struct txbd8 *txbdp;
  548. struct rxbd8 *rxbdp;
  549. dma_addr_t addr;
  550. unsigned long vaddr;
  551. int i;
  552. struct gfar_private *priv = netdev_priv(dev);
  553. struct gfar __iomem *regs = priv->regs;
  554. int err = 0;
  555. u32 rctrl = 0;
  556. u32 attrs = 0;
  557. gfar_write(&regs->imask, IMASK_INIT_CLEAR);
  558. /* Allocate memory for the buffer descriptors */
  559. vaddr = (unsigned long) dma_alloc_coherent(NULL,
  560. sizeof (struct txbd8) * priv->tx_ring_size +
  561. sizeof (struct rxbd8) * priv->rx_ring_size,
  562. &addr, GFP_KERNEL);
  563. if (vaddr == 0) {
  564. if (netif_msg_ifup(priv))
  565. printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
  566. dev->name);
  567. return -ENOMEM;
  568. }
  569. priv->tx_bd_base = (struct txbd8 *) vaddr;
  570. /* enet DMA only understands physical addresses */
  571. gfar_write(&regs->tbase0, addr);
  572. /* Start the rx descriptor ring where the tx ring leaves off */
  573. addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
  574. vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
  575. priv->rx_bd_base = (struct rxbd8 *) vaddr;
  576. gfar_write(&regs->rbase0, addr);
  577. /* Setup the skbuff rings */
  578. priv->tx_skbuff =
  579. (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
  580. priv->tx_ring_size, GFP_KERNEL);
  581. if (NULL == priv->tx_skbuff) {
  582. if (netif_msg_ifup(priv))
  583. printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
  584. dev->name);
  585. err = -ENOMEM;
  586. goto tx_skb_fail;
  587. }
  588. for (i = 0; i < priv->tx_ring_size; i++)
  589. priv->tx_skbuff[i] = NULL;
  590. priv->rx_skbuff =
  591. (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
  592. priv->rx_ring_size, GFP_KERNEL);
  593. if (NULL == priv->rx_skbuff) {
  594. if (netif_msg_ifup(priv))
  595. printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
  596. dev->name);
  597. err = -ENOMEM;
  598. goto rx_skb_fail;
  599. }
  600. for (i = 0; i < priv->rx_ring_size; i++)
  601. priv->rx_skbuff[i] = NULL;
  602. /* Initialize some variables in our dev structure */
  603. priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
  604. priv->cur_rx = priv->rx_bd_base;
  605. priv->skb_curtx = priv->skb_dirtytx = 0;
  606. priv->skb_currx = 0;
  607. /* Initialize Transmit Descriptor Ring */
  608. txbdp = priv->tx_bd_base;
  609. for (i = 0; i < priv->tx_ring_size; i++) {
  610. txbdp->status = 0;
  611. txbdp->length = 0;
  612. txbdp->bufPtr = 0;
  613. txbdp++;
  614. }
  615. /* Set the last descriptor in the ring to indicate wrap */
  616. txbdp--;
  617. txbdp->status |= TXBD_WRAP;
  618. rxbdp = priv->rx_bd_base;
  619. for (i = 0; i < priv->rx_ring_size; i++) {
  620. struct sk_buff *skb = NULL;
  621. rxbdp->status = 0;
  622. skb = gfar_new_skb(dev, rxbdp);
  623. priv->rx_skbuff[i] = skb;
  624. rxbdp++;
  625. }
  626. /* Set the last descriptor in the ring to wrap */
  627. rxbdp--;
  628. rxbdp->status |= RXBD_WRAP;
  629. /* If the device has multiple interrupts, register for
  630. * them. Otherwise, only register for the one */
  631. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  632. /* Install our interrupt handlers for Error,
  633. * Transmit, and Receive */
  634. if (request_irq(priv->interruptError, gfar_error,
  635. 0, "enet_error", dev) < 0) {
  636. if (netif_msg_intr(priv))
  637. printk(KERN_ERR "%s: Can't get IRQ %d\n",
  638. dev->name, priv->interruptError);
  639. err = -1;
  640. goto err_irq_fail;
  641. }
  642. if (request_irq(priv->interruptTransmit, gfar_transmit,
  643. 0, "enet_tx", dev) < 0) {
  644. if (netif_msg_intr(priv))
  645. printk(KERN_ERR "%s: Can't get IRQ %d\n",
  646. dev->name, priv->interruptTransmit);
  647. err = -1;
  648. goto tx_irq_fail;
  649. }
  650. if (request_irq(priv->interruptReceive, gfar_receive,
  651. 0, "enet_rx", dev) < 0) {
  652. if (netif_msg_intr(priv))
  653. printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
  654. dev->name, priv->interruptReceive);
  655. err = -1;
  656. goto rx_irq_fail;
  657. }
  658. } else {
  659. if (request_irq(priv->interruptTransmit, gfar_interrupt,
  660. 0, "gfar_interrupt", dev) < 0) {
  661. if (netif_msg_intr(priv))
  662. printk(KERN_ERR "%s: Can't get IRQ %d\n",
  663. dev->name, priv->interruptError);
  664. err = -1;
  665. goto err_irq_fail;
  666. }
  667. }
  668. phy_start(priv->phydev);
  669. /* Configure the coalescing support */
  670. if (priv->txcoalescing)
  671. gfar_write(&regs->txic,
  672. mk_ic_value(priv->txcount, priv->txtime));
  673. else
  674. gfar_write(&regs->txic, 0);
  675. if (priv->rxcoalescing)
  676. gfar_write(&regs->rxic,
  677. mk_ic_value(priv->rxcount, priv->rxtime));
  678. else
  679. gfar_write(&regs->rxic, 0);
  680. if (priv->rx_csum_enable)
  681. rctrl |= RCTRL_CHECKSUMMING;
  682. if (priv->extended_hash) {
  683. rctrl |= RCTRL_EXTHASH;
  684. gfar_clear_exact_match(dev);
  685. rctrl |= RCTRL_EMEN;
  686. }
  687. if (priv->vlan_enable)
  688. rctrl |= RCTRL_VLAN;
  689. if (priv->padding) {
  690. rctrl &= ~RCTRL_PAL_MASK;
  691. rctrl |= RCTRL_PADDING(priv->padding);
  692. }
  693. /* Init rctrl based on our settings */
  694. gfar_write(&priv->regs->rctrl, rctrl);
  695. if (dev->features & NETIF_F_IP_CSUM)
  696. gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
  697. /* Set the extraction length and index */
  698. attrs = ATTRELI_EL(priv->rx_stash_size) |
  699. ATTRELI_EI(priv->rx_stash_index);
  700. gfar_write(&priv->regs->attreli, attrs);
  701. /* Start with defaults, and add stashing or locking
  702. * depending on the approprate variables */
  703. attrs = ATTR_INIT_SETTINGS;
  704. if (priv->bd_stash_en)
  705. attrs |= ATTR_BDSTASH;
  706. if (priv->rx_stash_size != 0)
  707. attrs |= ATTR_BUFSTASH;
  708. gfar_write(&priv->regs->attr, attrs);
  709. gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
  710. gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
  711. gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
  712. /* Start the controller */
  713. gfar_start(dev);
  714. return 0;
  715. rx_irq_fail:
  716. free_irq(priv->interruptTransmit, dev);
  717. tx_irq_fail:
  718. free_irq(priv->interruptError, dev);
  719. err_irq_fail:
  720. rx_skb_fail:
  721. free_skb_resources(priv);
  722. tx_skb_fail:
  723. dma_free_coherent(NULL,
  724. sizeof(struct txbd8)*priv->tx_ring_size
  725. + sizeof(struct rxbd8)*priv->rx_ring_size,
  726. priv->tx_bd_base,
  727. gfar_read(&regs->tbase0));
  728. return err;
  729. }
  730. /* Called when something needs to use the ethernet device */
  731. /* Returns 0 for success. */
  732. static int gfar_enet_open(struct net_device *dev)
  733. {
  734. int err;
  735. /* Initialize a bunch of registers */
  736. init_registers(dev);
  737. gfar_set_mac_address(dev);
  738. err = init_phy(dev);
  739. if(err)
  740. return err;
  741. err = startup_gfar(dev);
  742. netif_start_queue(dev);
  743. return err;
  744. }
  745. static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
  746. {
  747. struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
  748. memset(fcb, 0, GMAC_FCB_LEN);
  749. return fcb;
  750. }
  751. static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
  752. {
  753. u8 flags = 0;
  754. /* If we're here, it's a IP packet with a TCP or UDP
  755. * payload. We set it to checksum, using a pseudo-header
  756. * we provide
  757. */
  758. flags = TXFCB_DEFAULT;
  759. /* Tell the controller what the protocol is */
  760. /* And provide the already calculated phcs */
  761. if (skb->nh.iph->protocol == IPPROTO_UDP) {
  762. flags |= TXFCB_UDP;
  763. fcb->phcs = skb->h.uh->check;
  764. } else
  765. fcb->phcs = skb->h.th->check;
  766. /* l3os is the distance between the start of the
  767. * frame (skb->data) and the start of the IP hdr.
  768. * l4os is the distance between the start of the
  769. * l3 hdr and the l4 hdr */
  770. fcb->l3os = (u16)(skb->nh.raw - skb->data - GMAC_FCB_LEN);
  771. fcb->l4os = (u16)(skb->h.raw - skb->nh.raw);
  772. fcb->flags = flags;
  773. }
  774. void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
  775. {
  776. fcb->flags |= TXFCB_VLN;
  777. fcb->vlctl = vlan_tx_tag_get(skb);
  778. }
  779. /* This is called by the kernel when a frame is ready for transmission. */
  780. /* It is pointed to by the dev->hard_start_xmit function pointer */
  781. static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
  782. {
  783. struct gfar_private *priv = netdev_priv(dev);
  784. struct txfcb *fcb = NULL;
  785. struct txbd8 *txbdp;
  786. u16 status;
  787. unsigned long flags;
  788. /* Update transmit stats */
  789. priv->stats.tx_bytes += skb->len;
  790. /* Lock priv now */
  791. spin_lock_irqsave(&priv->txlock, flags);
  792. /* Point at the first free tx descriptor */
  793. txbdp = priv->cur_tx;
  794. /* Clear all but the WRAP status flags */
  795. status = txbdp->status & TXBD_WRAP;
  796. /* Set up checksumming */
  797. if (likely((dev->features & NETIF_F_IP_CSUM)
  798. && (CHECKSUM_PARTIAL == skb->ip_summed))) {
  799. fcb = gfar_add_fcb(skb, txbdp);
  800. status |= TXBD_TOE;
  801. gfar_tx_checksum(skb, fcb);
  802. }
  803. if (priv->vlan_enable &&
  804. unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
  805. if (unlikely(NULL == fcb)) {
  806. fcb = gfar_add_fcb(skb, txbdp);
  807. status |= TXBD_TOE;
  808. }
  809. gfar_tx_vlan(skb, fcb);
  810. }
  811. /* Set buffer length and pointer */
  812. txbdp->length = skb->len;
  813. txbdp->bufPtr = dma_map_single(NULL, skb->data,
  814. skb->len, DMA_TO_DEVICE);
  815. /* Save the skb pointer so we can free it later */
  816. priv->tx_skbuff[priv->skb_curtx] = skb;
  817. /* Update the current skb pointer (wrapping if this was the last) */
  818. priv->skb_curtx =
  819. (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
  820. /* Flag the BD as interrupt-causing */
  821. status |= TXBD_INTERRUPT;
  822. /* Flag the BD as ready to go, last in frame, and */
  823. /* in need of CRC */
  824. status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
  825. dev->trans_start = jiffies;
  826. txbdp->status = status;
  827. /* If this was the last BD in the ring, the next one */
  828. /* is at the beginning of the ring */
  829. if (txbdp->status & TXBD_WRAP)
  830. txbdp = priv->tx_bd_base;
  831. else
  832. txbdp++;
  833. /* If the next BD still needs to be cleaned up, then the bds
  834. are full. We need to tell the kernel to stop sending us stuff. */
  835. if (txbdp == priv->dirty_tx) {
  836. netif_stop_queue(dev);
  837. priv->stats.tx_fifo_errors++;
  838. }
  839. /* Update the current txbd to the next one */
  840. priv->cur_tx = txbdp;
  841. /* Tell the DMA to go go go */
  842. gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
  843. /* Unlock priv */
  844. spin_unlock_irqrestore(&priv->txlock, flags);
  845. return 0;
  846. }
  847. /* Stops the kernel queue, and halts the controller */
  848. static int gfar_close(struct net_device *dev)
  849. {
  850. struct gfar_private *priv = netdev_priv(dev);
  851. stop_gfar(dev);
  852. /* Disconnect from the PHY */
  853. phy_disconnect(priv->phydev);
  854. priv->phydev = NULL;
  855. netif_stop_queue(dev);
  856. return 0;
  857. }
  858. /* returns a net_device_stats structure pointer */
  859. static struct net_device_stats * gfar_get_stats(struct net_device *dev)
  860. {
  861. struct gfar_private *priv = netdev_priv(dev);
  862. return &(priv->stats);
  863. }
  864. /* Changes the mac address if the controller is not running. */
  865. int gfar_set_mac_address(struct net_device *dev)
  866. {
  867. gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
  868. return 0;
  869. }
  870. /* Enables and disables VLAN insertion/extraction */
  871. static void gfar_vlan_rx_register(struct net_device *dev,
  872. struct vlan_group *grp)
  873. {
  874. struct gfar_private *priv = netdev_priv(dev);
  875. unsigned long flags;
  876. u32 tempval;
  877. spin_lock_irqsave(&priv->rxlock, flags);
  878. priv->vlgrp = grp;
  879. if (grp) {
  880. /* Enable VLAN tag insertion */
  881. tempval = gfar_read(&priv->regs->tctrl);
  882. tempval |= TCTRL_VLINS;
  883. gfar_write(&priv->regs->tctrl, tempval);
  884. /* Enable VLAN tag extraction */
  885. tempval = gfar_read(&priv->regs->rctrl);
  886. tempval |= RCTRL_VLEX;
  887. gfar_write(&priv->regs->rctrl, tempval);
  888. } else {
  889. /* Disable VLAN tag insertion */
  890. tempval = gfar_read(&priv->regs->tctrl);
  891. tempval &= ~TCTRL_VLINS;
  892. gfar_write(&priv->regs->tctrl, tempval);
  893. /* Disable VLAN tag extraction */
  894. tempval = gfar_read(&priv->regs->rctrl);
  895. tempval &= ~RCTRL_VLEX;
  896. gfar_write(&priv->regs->rctrl, tempval);
  897. }
  898. spin_unlock_irqrestore(&priv->rxlock, flags);
  899. }
  900. static void gfar_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
  901. {
  902. struct gfar_private *priv = netdev_priv(dev);
  903. unsigned long flags;
  904. spin_lock_irqsave(&priv->rxlock, flags);
  905. vlan_group_set_device(priv->vlgrp, vid, NULL);
  906. spin_unlock_irqrestore(&priv->rxlock, flags);
  907. }
  908. static int gfar_change_mtu(struct net_device *dev, int new_mtu)
  909. {
  910. int tempsize, tempval;
  911. struct gfar_private *priv = netdev_priv(dev);
  912. int oldsize = priv->rx_buffer_size;
  913. int frame_size = new_mtu + ETH_HLEN;
  914. if (priv->vlan_enable)
  915. frame_size += VLAN_ETH_HLEN;
  916. if (gfar_uses_fcb(priv))
  917. frame_size += GMAC_FCB_LEN;
  918. frame_size += priv->padding;
  919. if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
  920. if (netif_msg_drv(priv))
  921. printk(KERN_ERR "%s: Invalid MTU setting\n",
  922. dev->name);
  923. return -EINVAL;
  924. }
  925. tempsize =
  926. (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
  927. INCREMENTAL_BUFFER_SIZE;
  928. /* Only stop and start the controller if it isn't already
  929. * stopped, and we changed something */
  930. if ((oldsize != tempsize) && (dev->flags & IFF_UP))
  931. stop_gfar(dev);
  932. priv->rx_buffer_size = tempsize;
  933. dev->mtu = new_mtu;
  934. gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
  935. gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
  936. /* If the mtu is larger than the max size for standard
  937. * ethernet frames (ie, a jumbo frame), then set maccfg2
  938. * to allow huge frames, and to check the length */
  939. tempval = gfar_read(&priv->regs->maccfg2);
  940. if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
  941. tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
  942. else
  943. tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
  944. gfar_write(&priv->regs->maccfg2, tempval);
  945. if ((oldsize != tempsize) && (dev->flags & IFF_UP))
  946. startup_gfar(dev);
  947. return 0;
  948. }
  949. /* gfar_timeout gets called when a packet has not been
  950. * transmitted after a set amount of time.
  951. * For now, assume that clearing out all the structures, and
  952. * starting over will fix the problem. */
  953. static void gfar_timeout(struct net_device *dev)
  954. {
  955. struct gfar_private *priv = netdev_priv(dev);
  956. priv->stats.tx_errors++;
  957. if (dev->flags & IFF_UP) {
  958. stop_gfar(dev);
  959. startup_gfar(dev);
  960. }
  961. netif_schedule(dev);
  962. }
  963. /* Interrupt Handler for Transmit complete */
  964. static irqreturn_t gfar_transmit(int irq, void *dev_id)
  965. {
  966. struct net_device *dev = (struct net_device *) dev_id;
  967. struct gfar_private *priv = netdev_priv(dev);
  968. struct txbd8 *bdp;
  969. /* Clear IEVENT */
  970. gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
  971. /* Lock priv */
  972. spin_lock(&priv->txlock);
  973. bdp = priv->dirty_tx;
  974. while ((bdp->status & TXBD_READY) == 0) {
  975. /* If dirty_tx and cur_tx are the same, then either the */
  976. /* ring is empty or full now (it could only be full in the beginning, */
  977. /* obviously). If it is empty, we are done. */
  978. if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
  979. break;
  980. priv->stats.tx_packets++;
  981. /* Deferred means some collisions occurred during transmit, */
  982. /* but we eventually sent the packet. */
  983. if (bdp->status & TXBD_DEF)
  984. priv->stats.collisions++;
  985. /* Free the sk buffer associated with this TxBD */
  986. dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
  987. priv->tx_skbuff[priv->skb_dirtytx] = NULL;
  988. priv->skb_dirtytx =
  989. (priv->skb_dirtytx +
  990. 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
  991. /* update bdp to point at next bd in the ring (wrapping if necessary) */
  992. if (bdp->status & TXBD_WRAP)
  993. bdp = priv->tx_bd_base;
  994. else
  995. bdp++;
  996. /* Move dirty_tx to be the next bd */
  997. priv->dirty_tx = bdp;
  998. /* We freed a buffer, so now we can restart transmission */
  999. if (netif_queue_stopped(dev))
  1000. netif_wake_queue(dev);
  1001. } /* while ((bdp->status & TXBD_READY) == 0) */
  1002. /* If we are coalescing the interrupts, reset the timer */
  1003. /* Otherwise, clear it */
  1004. if (priv->txcoalescing)
  1005. gfar_write(&priv->regs->txic,
  1006. mk_ic_value(priv->txcount, priv->txtime));
  1007. else
  1008. gfar_write(&priv->regs->txic, 0);
  1009. spin_unlock(&priv->txlock);
  1010. return IRQ_HANDLED;
  1011. }
  1012. struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
  1013. {
  1014. unsigned int alignamount;
  1015. struct gfar_private *priv = netdev_priv(dev);
  1016. struct sk_buff *skb = NULL;
  1017. unsigned int timeout = SKB_ALLOC_TIMEOUT;
  1018. /* We have to allocate the skb, so keep trying till we succeed */
  1019. while ((!skb) && timeout--)
  1020. skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
  1021. if (NULL == skb)
  1022. return NULL;
  1023. alignamount = RXBUF_ALIGNMENT -
  1024. (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1));
  1025. /* We need the data buffer to be aligned properly. We will reserve
  1026. * as many bytes as needed to align the data properly
  1027. */
  1028. skb_reserve(skb, alignamount);
  1029. skb->dev = dev;
  1030. bdp->bufPtr = dma_map_single(NULL, skb->data,
  1031. priv->rx_buffer_size, DMA_FROM_DEVICE);
  1032. bdp->length = 0;
  1033. /* Mark the buffer empty */
  1034. bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
  1035. return skb;
  1036. }
  1037. static inline void count_errors(unsigned short status, struct gfar_private *priv)
  1038. {
  1039. struct net_device_stats *stats = &priv->stats;
  1040. struct gfar_extra_stats *estats = &priv->extra_stats;
  1041. /* If the packet was truncated, none of the other errors
  1042. * matter */
  1043. if (status & RXBD_TRUNCATED) {
  1044. stats->rx_length_errors++;
  1045. estats->rx_trunc++;
  1046. return;
  1047. }
  1048. /* Count the errors, if there were any */
  1049. if (status & (RXBD_LARGE | RXBD_SHORT)) {
  1050. stats->rx_length_errors++;
  1051. if (status & RXBD_LARGE)
  1052. estats->rx_large++;
  1053. else
  1054. estats->rx_short++;
  1055. }
  1056. if (status & RXBD_NONOCTET) {
  1057. stats->rx_frame_errors++;
  1058. estats->rx_nonoctet++;
  1059. }
  1060. if (status & RXBD_CRCERR) {
  1061. estats->rx_crcerr++;
  1062. stats->rx_crc_errors++;
  1063. }
  1064. if (status & RXBD_OVERRUN) {
  1065. estats->rx_overrun++;
  1066. stats->rx_crc_errors++;
  1067. }
  1068. }
  1069. irqreturn_t gfar_receive(int irq, void *dev_id)
  1070. {
  1071. struct net_device *dev = (struct net_device *) dev_id;
  1072. struct gfar_private *priv = netdev_priv(dev);
  1073. #ifdef CONFIG_GFAR_NAPI
  1074. u32 tempval;
  1075. #else
  1076. unsigned long flags;
  1077. #endif
  1078. /* Clear IEVENT, so rx interrupt isn't called again
  1079. * because of this interrupt */
  1080. gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
  1081. /* support NAPI */
  1082. #ifdef CONFIG_GFAR_NAPI
  1083. if (netif_rx_schedule_prep(dev)) {
  1084. tempval = gfar_read(&priv->regs->imask);
  1085. tempval &= IMASK_RX_DISABLED;
  1086. gfar_write(&priv->regs->imask, tempval);
  1087. __netif_rx_schedule(dev);
  1088. } else {
  1089. if (netif_msg_rx_err(priv))
  1090. printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
  1091. dev->name, gfar_read(&priv->regs->ievent),
  1092. gfar_read(&priv->regs->imask));
  1093. }
  1094. #else
  1095. spin_lock_irqsave(&priv->rxlock, flags);
  1096. gfar_clean_rx_ring(dev, priv->rx_ring_size);
  1097. /* If we are coalescing interrupts, update the timer */
  1098. /* Otherwise, clear it */
  1099. if (priv->rxcoalescing)
  1100. gfar_write(&priv->regs->rxic,
  1101. mk_ic_value(priv->rxcount, priv->rxtime));
  1102. else
  1103. gfar_write(&priv->regs->rxic, 0);
  1104. spin_unlock_irqrestore(&priv->rxlock, flags);
  1105. #endif
  1106. return IRQ_HANDLED;
  1107. }
  1108. static inline int gfar_rx_vlan(struct sk_buff *skb,
  1109. struct vlan_group *vlgrp, unsigned short vlctl)
  1110. {
  1111. #ifdef CONFIG_GFAR_NAPI
  1112. return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
  1113. #else
  1114. return vlan_hwaccel_rx(skb, vlgrp, vlctl);
  1115. #endif
  1116. }
  1117. static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
  1118. {
  1119. /* If valid headers were found, and valid sums
  1120. * were verified, then we tell the kernel that no
  1121. * checksumming is necessary. Otherwise, it is */
  1122. if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
  1123. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1124. else
  1125. skb->ip_summed = CHECKSUM_NONE;
  1126. }
  1127. static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
  1128. {
  1129. struct rxfcb *fcb = (struct rxfcb *)skb->data;
  1130. /* Remove the FCB from the skb */
  1131. skb_pull(skb, GMAC_FCB_LEN);
  1132. return fcb;
  1133. }
  1134. /* gfar_process_frame() -- handle one incoming packet if skb
  1135. * isn't NULL. */
  1136. static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
  1137. int length)
  1138. {
  1139. struct gfar_private *priv = netdev_priv(dev);
  1140. struct rxfcb *fcb = NULL;
  1141. if (NULL == skb) {
  1142. if (netif_msg_rx_err(priv))
  1143. printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
  1144. priv->stats.rx_dropped++;
  1145. priv->extra_stats.rx_skbmissing++;
  1146. } else {
  1147. int ret;
  1148. /* Prep the skb for the packet */
  1149. skb_put(skb, length);
  1150. /* Grab the FCB if there is one */
  1151. if (gfar_uses_fcb(priv))
  1152. fcb = gfar_get_fcb(skb);
  1153. /* Remove the padded bytes, if there are any */
  1154. if (priv->padding)
  1155. skb_pull(skb, priv->padding);
  1156. if (priv->rx_csum_enable)
  1157. gfar_rx_checksum(skb, fcb);
  1158. /* Tell the skb what kind of packet this is */
  1159. skb->protocol = eth_type_trans(skb, dev);
  1160. /* Send the packet up the stack */
  1161. if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
  1162. ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
  1163. else
  1164. ret = RECEIVE(skb);
  1165. if (NET_RX_DROP == ret)
  1166. priv->extra_stats.kernel_dropped++;
  1167. }
  1168. return 0;
  1169. }
  1170. /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
  1171. * until the budget/quota has been reached. Returns the number
  1172. * of frames handled
  1173. */
  1174. int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
  1175. {
  1176. struct rxbd8 *bdp;
  1177. struct sk_buff *skb;
  1178. u16 pkt_len;
  1179. int howmany = 0;
  1180. struct gfar_private *priv = netdev_priv(dev);
  1181. /* Get the first full descriptor */
  1182. bdp = priv->cur_rx;
  1183. while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
  1184. skb = priv->rx_skbuff[priv->skb_currx];
  1185. if (!(bdp->status &
  1186. (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
  1187. | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
  1188. /* Increment the number of packets */
  1189. priv->stats.rx_packets++;
  1190. howmany++;
  1191. /* Remove the FCS from the packet length */
  1192. pkt_len = bdp->length - 4;
  1193. gfar_process_frame(dev, skb, pkt_len);
  1194. priv->stats.rx_bytes += pkt_len;
  1195. } else {
  1196. count_errors(bdp->status, priv);
  1197. if (skb)
  1198. dev_kfree_skb_any(skb);
  1199. priv->rx_skbuff[priv->skb_currx] = NULL;
  1200. }
  1201. dev->last_rx = jiffies;
  1202. /* Clear the status flags for this buffer */
  1203. bdp->status &= ~RXBD_STATS;
  1204. /* Add another skb for the future */
  1205. skb = gfar_new_skb(dev, bdp);
  1206. priv->rx_skbuff[priv->skb_currx] = skb;
  1207. /* Update to the next pointer */
  1208. if (bdp->status & RXBD_WRAP)
  1209. bdp = priv->rx_bd_base;
  1210. else
  1211. bdp++;
  1212. /* update to point at the next skb */
  1213. priv->skb_currx =
  1214. (priv->skb_currx +
  1215. 1) & RX_RING_MOD_MASK(priv->rx_ring_size);
  1216. }
  1217. /* Update the current rxbd pointer to be the next one */
  1218. priv->cur_rx = bdp;
  1219. return howmany;
  1220. }
  1221. #ifdef CONFIG_GFAR_NAPI
  1222. static int gfar_poll(struct net_device *dev, int *budget)
  1223. {
  1224. int howmany;
  1225. struct gfar_private *priv = netdev_priv(dev);
  1226. int rx_work_limit = *budget;
  1227. if (rx_work_limit > dev->quota)
  1228. rx_work_limit = dev->quota;
  1229. howmany = gfar_clean_rx_ring(dev, rx_work_limit);
  1230. dev->quota -= howmany;
  1231. rx_work_limit -= howmany;
  1232. *budget -= howmany;
  1233. if (rx_work_limit > 0) {
  1234. netif_rx_complete(dev);
  1235. /* Clear the halt bit in RSTAT */
  1236. gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
  1237. gfar_write(&priv->regs->imask, IMASK_DEFAULT);
  1238. /* If we are coalescing interrupts, update the timer */
  1239. /* Otherwise, clear it */
  1240. if (priv->rxcoalescing)
  1241. gfar_write(&priv->regs->rxic,
  1242. mk_ic_value(priv->rxcount, priv->rxtime));
  1243. else
  1244. gfar_write(&priv->regs->rxic, 0);
  1245. }
  1246. /* Return 1 if there's more work to do */
  1247. return (rx_work_limit > 0) ? 0 : 1;
  1248. }
  1249. #endif
  1250. #ifdef CONFIG_NET_POLL_CONTROLLER
  1251. /*
  1252. * Polling 'interrupt' - used by things like netconsole to send skbs
  1253. * without having to re-enable interrupts. It's not called while
  1254. * the interrupt routine is executing.
  1255. */
  1256. static void gfar_netpoll(struct net_device *dev)
  1257. {
  1258. struct gfar_private *priv = netdev_priv(dev);
  1259. /* If the device has multiple interrupts, run tx/rx */
  1260. if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
  1261. disable_irq(priv->interruptTransmit);
  1262. disable_irq(priv->interruptReceive);
  1263. disable_irq(priv->interruptError);
  1264. gfar_interrupt(priv->interruptTransmit, dev);
  1265. enable_irq(priv->interruptError);
  1266. enable_irq(priv->interruptReceive);
  1267. enable_irq(priv->interruptTransmit);
  1268. } else {
  1269. disable_irq(priv->interruptTransmit);
  1270. gfar_interrupt(priv->interruptTransmit, dev);
  1271. enable_irq(priv->interruptTransmit);
  1272. }
  1273. }
  1274. #endif
  1275. /* The interrupt handler for devices with one interrupt */
  1276. static irqreturn_t gfar_interrupt(int irq, void *dev_id)
  1277. {
  1278. struct net_device *dev = dev_id;
  1279. struct gfar_private *priv = netdev_priv(dev);
  1280. /* Save ievent for future reference */
  1281. u32 events = gfar_read(&priv->regs->ievent);
  1282. /* Check for reception */
  1283. if (events & IEVENT_RX_MASK)
  1284. gfar_receive(irq, dev_id);
  1285. /* Check for transmit completion */
  1286. if (events & IEVENT_TX_MASK)
  1287. gfar_transmit(irq, dev_id);
  1288. /* Check for errors */
  1289. if (events & IEVENT_ERR_MASK)
  1290. gfar_error(irq, dev_id);
  1291. return IRQ_HANDLED;
  1292. }
  1293. /* Called every time the controller might need to be made
  1294. * aware of new link state. The PHY code conveys this
  1295. * information through variables in the phydev structure, and this
  1296. * function converts those variables into the appropriate
  1297. * register values, and can bring down the device if needed.
  1298. */
  1299. static void adjust_link(struct net_device *dev)
  1300. {
  1301. struct gfar_private *priv = netdev_priv(dev);
  1302. struct gfar __iomem *regs = priv->regs;
  1303. unsigned long flags;
  1304. struct phy_device *phydev = priv->phydev;
  1305. int new_state = 0;
  1306. spin_lock_irqsave(&priv->txlock, flags);
  1307. if (phydev->link) {
  1308. u32 tempval = gfar_read(&regs->maccfg2);
  1309. u32 ecntrl = gfar_read(&regs->ecntrl);
  1310. /* Now we make sure that we can be in full duplex mode.
  1311. * If not, we operate in half-duplex mode. */
  1312. if (phydev->duplex != priv->oldduplex) {
  1313. new_state = 1;
  1314. if (!(phydev->duplex))
  1315. tempval &= ~(MACCFG2_FULL_DUPLEX);
  1316. else
  1317. tempval |= MACCFG2_FULL_DUPLEX;
  1318. priv->oldduplex = phydev->duplex;
  1319. }
  1320. if (phydev->speed != priv->oldspeed) {
  1321. new_state = 1;
  1322. switch (phydev->speed) {
  1323. case 1000:
  1324. tempval =
  1325. ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
  1326. break;
  1327. case 100:
  1328. case 10:
  1329. tempval =
  1330. ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
  1331. /* Reduced mode distinguishes
  1332. * between 10 and 100 */
  1333. if (phydev->speed == SPEED_100)
  1334. ecntrl |= ECNTRL_R100;
  1335. else
  1336. ecntrl &= ~(ECNTRL_R100);
  1337. break;
  1338. default:
  1339. if (netif_msg_link(priv))
  1340. printk(KERN_WARNING
  1341. "%s: Ack! Speed (%d) is not 10/100/1000!\n",
  1342. dev->name, phydev->speed);
  1343. break;
  1344. }
  1345. priv->oldspeed = phydev->speed;
  1346. }
  1347. gfar_write(&regs->maccfg2, tempval);
  1348. gfar_write(&regs->ecntrl, ecntrl);
  1349. if (!priv->oldlink) {
  1350. new_state = 1;
  1351. priv->oldlink = 1;
  1352. netif_schedule(dev);
  1353. }
  1354. } else if (priv->oldlink) {
  1355. new_state = 1;
  1356. priv->oldlink = 0;
  1357. priv->oldspeed = 0;
  1358. priv->oldduplex = -1;
  1359. }
  1360. if (new_state && netif_msg_link(priv))
  1361. phy_print_status(phydev);
  1362. spin_unlock_irqrestore(&priv->txlock, flags);
  1363. }
  1364. /* Update the hash table based on the current list of multicast
  1365. * addresses we subscribe to. Also, change the promiscuity of
  1366. * the device based on the flags (this function is called
  1367. * whenever dev->flags is changed */
  1368. static void gfar_set_multi(struct net_device *dev)
  1369. {
  1370. struct dev_mc_list *mc_ptr;
  1371. struct gfar_private *priv = netdev_priv(dev);
  1372. struct gfar __iomem *regs = priv->regs;
  1373. u32 tempval;
  1374. if(dev->flags & IFF_PROMISC) {
  1375. /* Set RCTRL to PROM */
  1376. tempval = gfar_read(&regs->rctrl);
  1377. tempval |= RCTRL_PROM;
  1378. gfar_write(&regs->rctrl, tempval);
  1379. } else {
  1380. /* Set RCTRL to not PROM */
  1381. tempval = gfar_read(&regs->rctrl);
  1382. tempval &= ~(RCTRL_PROM);
  1383. gfar_write(&regs->rctrl, tempval);
  1384. }
  1385. if(dev->flags & IFF_ALLMULTI) {
  1386. /* Set the hash to rx all multicast frames */
  1387. gfar_write(&regs->igaddr0, 0xffffffff);
  1388. gfar_write(&regs->igaddr1, 0xffffffff);
  1389. gfar_write(&regs->igaddr2, 0xffffffff);
  1390. gfar_write(&regs->igaddr3, 0xffffffff);
  1391. gfar_write(&regs->igaddr4, 0xffffffff);
  1392. gfar_write(&regs->igaddr5, 0xffffffff);
  1393. gfar_write(&regs->igaddr6, 0xffffffff);
  1394. gfar_write(&regs->igaddr7, 0xffffffff);
  1395. gfar_write(&regs->gaddr0, 0xffffffff);
  1396. gfar_write(&regs->gaddr1, 0xffffffff);
  1397. gfar_write(&regs->gaddr2, 0xffffffff);
  1398. gfar_write(&regs->gaddr3, 0xffffffff);
  1399. gfar_write(&regs->gaddr4, 0xffffffff);
  1400. gfar_write(&regs->gaddr5, 0xffffffff);
  1401. gfar_write(&regs->gaddr6, 0xffffffff);
  1402. gfar_write(&regs->gaddr7, 0xffffffff);
  1403. } else {
  1404. int em_num;
  1405. int idx;
  1406. /* zero out the hash */
  1407. gfar_write(&regs->igaddr0, 0x0);
  1408. gfar_write(&regs->igaddr1, 0x0);
  1409. gfar_write(&regs->igaddr2, 0x0);
  1410. gfar_write(&regs->igaddr3, 0x0);
  1411. gfar_write(&regs->igaddr4, 0x0);
  1412. gfar_write(&regs->igaddr5, 0x0);
  1413. gfar_write(&regs->igaddr6, 0x0);
  1414. gfar_write(&regs->igaddr7, 0x0);
  1415. gfar_write(&regs->gaddr0, 0x0);
  1416. gfar_write(&regs->gaddr1, 0x0);
  1417. gfar_write(&regs->gaddr2, 0x0);
  1418. gfar_write(&regs->gaddr3, 0x0);
  1419. gfar_write(&regs->gaddr4, 0x0);
  1420. gfar_write(&regs->gaddr5, 0x0);
  1421. gfar_write(&regs->gaddr6, 0x0);
  1422. gfar_write(&regs->gaddr7, 0x0);
  1423. /* If we have extended hash tables, we need to
  1424. * clear the exact match registers to prepare for
  1425. * setting them */
  1426. if (priv->extended_hash) {
  1427. em_num = GFAR_EM_NUM + 1;
  1428. gfar_clear_exact_match(dev);
  1429. idx = 1;
  1430. } else {
  1431. idx = 0;
  1432. em_num = 0;
  1433. }
  1434. if(dev->mc_count == 0)
  1435. return;
  1436. /* Parse the list, and set the appropriate bits */
  1437. for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
  1438. if (idx < em_num) {
  1439. gfar_set_mac_for_addr(dev, idx,
  1440. mc_ptr->dmi_addr);
  1441. idx++;
  1442. } else
  1443. gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
  1444. }
  1445. }
  1446. return;
  1447. }
  1448. /* Clears each of the exact match registers to zero, so they
  1449. * don't interfere with normal reception */
  1450. static void gfar_clear_exact_match(struct net_device *dev)
  1451. {
  1452. int idx;
  1453. u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
  1454. for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
  1455. gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
  1456. }
  1457. /* Set the appropriate hash bit for the given addr */
  1458. /* The algorithm works like so:
  1459. * 1) Take the Destination Address (ie the multicast address), and
  1460. * do a CRC on it (little endian), and reverse the bits of the
  1461. * result.
  1462. * 2) Use the 8 most significant bits as a hash into a 256-entry
  1463. * table. The table is controlled through 8 32-bit registers:
  1464. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
  1465. * gaddr7. This means that the 3 most significant bits in the
  1466. * hash index which gaddr register to use, and the 5 other bits
  1467. * indicate which bit (assuming an IBM numbering scheme, which
  1468. * for PowerPC (tm) is usually the case) in the register holds
  1469. * the entry. */
  1470. static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
  1471. {
  1472. u32 tempval;
  1473. struct gfar_private *priv = netdev_priv(dev);
  1474. u32 result = ether_crc(MAC_ADDR_LEN, addr);
  1475. int width = priv->hash_width;
  1476. u8 whichbit = (result >> (32 - width)) & 0x1f;
  1477. u8 whichreg = result >> (32 - width + 5);
  1478. u32 value = (1 << (31-whichbit));
  1479. tempval = gfar_read(priv->hash_regs[whichreg]);
  1480. tempval |= value;
  1481. gfar_write(priv->hash_regs[whichreg], tempval);
  1482. return;
  1483. }
  1484. /* There are multiple MAC Address register pairs on some controllers
  1485. * This function sets the numth pair to a given address
  1486. */
  1487. static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
  1488. {
  1489. struct gfar_private *priv = netdev_priv(dev);
  1490. int idx;
  1491. char tmpbuf[MAC_ADDR_LEN];
  1492. u32 tempval;
  1493. u32 __iomem *macptr = &priv->regs->macstnaddr1;
  1494. macptr += num*2;
  1495. /* Now copy it into the mac registers backwards, cuz */
  1496. /* little endian is silly */
  1497. for (idx = 0; idx < MAC_ADDR_LEN; idx++)
  1498. tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
  1499. gfar_write(macptr, *((u32 *) (tmpbuf)));
  1500. tempval = *((u32 *) (tmpbuf + 4));
  1501. gfar_write(macptr+1, tempval);
  1502. }
  1503. /* GFAR error interrupt handler */
  1504. static irqreturn_t gfar_error(int irq, void *dev_id)
  1505. {
  1506. struct net_device *dev = dev_id;
  1507. struct gfar_private *priv = netdev_priv(dev);
  1508. /* Save ievent for future reference */
  1509. u32 events = gfar_read(&priv->regs->ievent);
  1510. /* Clear IEVENT */
  1511. gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
  1512. /* Hmm... */
  1513. if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
  1514. printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
  1515. dev->name, events, gfar_read(&priv->regs->imask));
  1516. /* Update the error counters */
  1517. if (events & IEVENT_TXE) {
  1518. priv->stats.tx_errors++;
  1519. if (events & IEVENT_LC)
  1520. priv->stats.tx_window_errors++;
  1521. if (events & IEVENT_CRL)
  1522. priv->stats.tx_aborted_errors++;
  1523. if (events & IEVENT_XFUN) {
  1524. if (netif_msg_tx_err(priv))
  1525. printk(KERN_DEBUG "%s: TX FIFO underrun, "
  1526. "packet dropped.\n", dev->name);
  1527. priv->stats.tx_dropped++;
  1528. priv->extra_stats.tx_underrun++;
  1529. /* Reactivate the Tx Queues */
  1530. gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
  1531. }
  1532. if (netif_msg_tx_err(priv))
  1533. printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
  1534. }
  1535. if (events & IEVENT_BSY) {
  1536. priv->stats.rx_errors++;
  1537. priv->extra_stats.rx_bsy++;
  1538. gfar_receive(irq, dev_id);
  1539. #ifndef CONFIG_GFAR_NAPI
  1540. /* Clear the halt bit in RSTAT */
  1541. gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
  1542. #endif
  1543. if (netif_msg_rx_err(priv))
  1544. printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
  1545. dev->name, gfar_read(&priv->regs->rstat));
  1546. }
  1547. if (events & IEVENT_BABR) {
  1548. priv->stats.rx_errors++;
  1549. priv->extra_stats.rx_babr++;
  1550. if (netif_msg_rx_err(priv))
  1551. printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
  1552. }
  1553. if (events & IEVENT_EBERR) {
  1554. priv->extra_stats.eberr++;
  1555. if (netif_msg_rx_err(priv))
  1556. printk(KERN_DEBUG "%s: bus error\n", dev->name);
  1557. }
  1558. if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
  1559. printk(KERN_DEBUG "%s: control frame\n", dev->name);
  1560. if (events & IEVENT_BABT) {
  1561. priv->extra_stats.tx_babt++;
  1562. if (netif_msg_tx_err(priv))
  1563. printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
  1564. }
  1565. return IRQ_HANDLED;
  1566. }
  1567. /* Structure for a device driver */
  1568. static struct platform_driver gfar_driver = {
  1569. .probe = gfar_probe,
  1570. .remove = gfar_remove,
  1571. .driver = {
  1572. .name = "fsl-gianfar",
  1573. },
  1574. };
  1575. static int __init gfar_init(void)
  1576. {
  1577. int err = gfar_mdio_init();
  1578. if (err)
  1579. return err;
  1580. err = platform_driver_register(&gfar_driver);
  1581. if (err)
  1582. gfar_mdio_exit();
  1583. return err;
  1584. }
  1585. static void __exit gfar_exit(void)
  1586. {
  1587. platform_driver_unregister(&gfar_driver);
  1588. gfar_mdio_exit();
  1589. }
  1590. module_init(gfar_init);
  1591. module_exit(gfar_exit);