forcedeth.c 161 KB

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  1. /*
  2. * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
  3. *
  4. * Note: This driver is a cleanroom reimplementation based on reverse
  5. * engineered documentation written by Carl-Daniel Hailfinger
  6. * and Andrew de Quincey.
  7. *
  8. * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  9. * trademarks of NVIDIA Corporation in the United States and other
  10. * countries.
  11. *
  12. * Copyright (C) 2003,4,5 Manfred Spraul
  13. * Copyright (C) 2004 Andrew de Quincey (wol support)
  14. * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15. * IRQ rate fixes, bigendian fixes, cleanups, verification)
  16. * Copyright (c) 2004,5,6 NVIDIA Corporation
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License as published by
  20. * the Free Software Foundation; either version 2 of the License, or
  21. * (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  31. *
  32. * Changelog:
  33. * 0.01: 05 Oct 2003: First release that compiles without warnings.
  34. * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  35. * Check all PCI BARs for the register window.
  36. * udelay added to mii_rw.
  37. * 0.03: 06 Oct 2003: Initialize dev->irq.
  38. * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  39. * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  40. * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  41. * irq mask updated
  42. * 0.07: 14 Oct 2003: Further irq mask updates.
  43. * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  44. * added into irq handler, NULL check for drain_ring.
  45. * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  46. * requested interrupt sources.
  47. * 0.10: 20 Oct 2003: First cleanup for release.
  48. * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  49. * MAC Address init fix, set_multicast cleanup.
  50. * 0.12: 23 Oct 2003: Cleanups for release.
  51. * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  52. * Set link speed correctly. start rx before starting
  53. * tx (nv_start_rx sets the link speed).
  54. * 0.14: 25 Oct 2003: Nic dependant irq mask.
  55. * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  56. * open.
  57. * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  58. * increased to 1628 bytes.
  59. * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  60. * the tx length.
  61. * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  62. * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  63. * addresses, really stop rx if already running
  64. * in nv_start_rx, clean up a bit.
  65. * 0.20: 07 Dec 2003: alloc fixes
  66. * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  67. * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  68. * on close.
  69. * 0.23: 26 Jan 2004: various small cleanups
  70. * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  71. * 0.25: 09 Mar 2004: wol support
  72. * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  73. * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  74. * added CK804/MCP04 device IDs, code fixes
  75. * for registers, link status and other minor fixes.
  76. * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  77. * 0.29: 31 Aug 2004: Add backup timer for link change notification.
  78. * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  79. * into nv_close, otherwise reenabling for wol can
  80. * cause DMA to kfree'd memory.
  81. * 0.31: 14 Nov 2004: ethtool support for getting/setting link
  82. * capabilities.
  83. * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
  84. * 0.33: 16 May 2005: Support for MCP51 added.
  85. * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  86. * 0.35: 26 Jun 2005: Support for MCP55 added.
  87. * 0.36: 28 Jun 2005: Add jumbo frame support.
  88. * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  89. * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  90. * per-packet flags.
  91. * 0.39: 18 Jul 2005: Add 64bit descriptor support.
  92. * 0.40: 19 Jul 2005: Add support for mac address change.
  93. * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  94. * of nv_remove
  95. * 0.42: 06 Aug 2005: Fix lack of link speed initialization
  96. * in the second (and later) nv_open call
  97. * 0.43: 10 Aug 2005: Add support for tx checksum.
  98. * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
  99. * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
  100. * 0.46: 20 Oct 2005: Add irq optimization modes.
  101. * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
  102. * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
  103. * 0.49: 10 Dec 2005: Fix tso for large buffers.
  104. * 0.50: 20 Jan 2006: Add 8021pq tagging support.
  105. * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
  106. * 0.52: 20 Jan 2006: Add MSI/MSIX support.
  107. * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
  108. * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
  109. * 0.55: 22 Mar 2006: Add flow control (pause frame).
  110. * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
  111. * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
  112. * 0.58: 30 Oct 2006: Added support for sideband management unit.
  113. * 0.59: 30 Oct 2006: Added support for recoverable error.
  114. * 0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
  115. *
  116. * Known bugs:
  117. * We suspect that on some hardware no TX done interrupts are generated.
  118. * This means recovery from netif_stop_queue only happens if the hw timer
  119. * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  120. * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  121. * If your hardware reliably generates tx done interrupts, then you can remove
  122. * DEV_NEED_TIMERIRQ from the driver_data flags.
  123. * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  124. * superfluous timer interrupts from the nic.
  125. */
  126. #ifdef CONFIG_FORCEDETH_NAPI
  127. #define DRIVERNAPI "-NAPI"
  128. #else
  129. #define DRIVERNAPI
  130. #endif
  131. #define FORCEDETH_VERSION "0.60"
  132. #define DRV_NAME "forcedeth"
  133. #include <linux/module.h>
  134. #include <linux/types.h>
  135. #include <linux/pci.h>
  136. #include <linux/interrupt.h>
  137. #include <linux/netdevice.h>
  138. #include <linux/etherdevice.h>
  139. #include <linux/delay.h>
  140. #include <linux/spinlock.h>
  141. #include <linux/ethtool.h>
  142. #include <linux/timer.h>
  143. #include <linux/skbuff.h>
  144. #include <linux/mii.h>
  145. #include <linux/random.h>
  146. #include <linux/init.h>
  147. #include <linux/if_vlan.h>
  148. #include <linux/dma-mapping.h>
  149. #include <asm/irq.h>
  150. #include <asm/io.h>
  151. #include <asm/uaccess.h>
  152. #include <asm/system.h>
  153. #if 0
  154. #define dprintk printk
  155. #else
  156. #define dprintk(x...) do { } while (0)
  157. #endif
  158. /*
  159. * Hardware access:
  160. */
  161. #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
  162. #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
  163. #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
  164. #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
  165. #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
  166. #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
  167. #define DEV_HAS_MSI 0x0040 /* device supports MSI */
  168. #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
  169. #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
  170. #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
  171. #define DEV_HAS_STATISTICS_V1 0x0400 /* device supports hw statistics version 1 */
  172. #define DEV_HAS_STATISTICS_V2 0x0800 /* device supports hw statistics version 2 */
  173. #define DEV_HAS_TEST_EXTENDED 0x1000 /* device supports extended diagnostic test */
  174. #define DEV_HAS_MGMT_UNIT 0x2000 /* device supports management unit */
  175. enum {
  176. NvRegIrqStatus = 0x000,
  177. #define NVREG_IRQSTAT_MIIEVENT 0x040
  178. #define NVREG_IRQSTAT_MASK 0x81ff
  179. NvRegIrqMask = 0x004,
  180. #define NVREG_IRQ_RX_ERROR 0x0001
  181. #define NVREG_IRQ_RX 0x0002
  182. #define NVREG_IRQ_RX_NOBUF 0x0004
  183. #define NVREG_IRQ_TX_ERR 0x0008
  184. #define NVREG_IRQ_TX_OK 0x0010
  185. #define NVREG_IRQ_TIMER 0x0020
  186. #define NVREG_IRQ_LINK 0x0040
  187. #define NVREG_IRQ_RX_FORCED 0x0080
  188. #define NVREG_IRQ_TX_FORCED 0x0100
  189. #define NVREG_IRQ_RECOVER_ERROR 0x8000
  190. #define NVREG_IRQMASK_THROUGHPUT 0x00df
  191. #define NVREG_IRQMASK_CPU 0x0040
  192. #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
  193. #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
  194. #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
  195. #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
  196. NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
  197. NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
  198. NvRegUnknownSetupReg6 = 0x008,
  199. #define NVREG_UNKSETUP6_VAL 3
  200. /*
  201. * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
  202. * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
  203. */
  204. NvRegPollingInterval = 0x00c,
  205. #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
  206. #define NVREG_POLL_DEFAULT_CPU 13
  207. NvRegMSIMap0 = 0x020,
  208. NvRegMSIMap1 = 0x024,
  209. NvRegMSIIrqMask = 0x030,
  210. #define NVREG_MSI_VECTOR_0_ENABLED 0x01
  211. NvRegMisc1 = 0x080,
  212. #define NVREG_MISC1_PAUSE_TX 0x01
  213. #define NVREG_MISC1_HD 0x02
  214. #define NVREG_MISC1_FORCE 0x3b0f3c
  215. NvRegMacReset = 0x3c,
  216. #define NVREG_MAC_RESET_ASSERT 0x0F3
  217. NvRegTransmitterControl = 0x084,
  218. #define NVREG_XMITCTL_START 0x01
  219. #define NVREG_XMITCTL_MGMT_ST 0x40000000
  220. #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
  221. #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
  222. #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
  223. #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
  224. #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
  225. #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
  226. #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
  227. #define NVREG_XMITCTL_HOST_LOADED 0x00004000
  228. #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
  229. NvRegTransmitterStatus = 0x088,
  230. #define NVREG_XMITSTAT_BUSY 0x01
  231. NvRegPacketFilterFlags = 0x8c,
  232. #define NVREG_PFF_PAUSE_RX 0x08
  233. #define NVREG_PFF_ALWAYS 0x7F0000
  234. #define NVREG_PFF_PROMISC 0x80
  235. #define NVREG_PFF_MYADDR 0x20
  236. #define NVREG_PFF_LOOPBACK 0x10
  237. NvRegOffloadConfig = 0x90,
  238. #define NVREG_OFFLOAD_HOMEPHY 0x601
  239. #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
  240. NvRegReceiverControl = 0x094,
  241. #define NVREG_RCVCTL_START 0x01
  242. #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
  243. NvRegReceiverStatus = 0x98,
  244. #define NVREG_RCVSTAT_BUSY 0x01
  245. NvRegRandomSeed = 0x9c,
  246. #define NVREG_RNDSEED_MASK 0x00ff
  247. #define NVREG_RNDSEED_FORCE 0x7f00
  248. #define NVREG_RNDSEED_FORCE2 0x2d00
  249. #define NVREG_RNDSEED_FORCE3 0x7400
  250. NvRegTxDeferral = 0xA0,
  251. #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
  252. #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
  253. #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
  254. NvRegRxDeferral = 0xA4,
  255. #define NVREG_RX_DEFERRAL_DEFAULT 0x16
  256. NvRegMacAddrA = 0xA8,
  257. NvRegMacAddrB = 0xAC,
  258. NvRegMulticastAddrA = 0xB0,
  259. #define NVREG_MCASTADDRA_FORCE 0x01
  260. NvRegMulticastAddrB = 0xB4,
  261. NvRegMulticastMaskA = 0xB8,
  262. NvRegMulticastMaskB = 0xBC,
  263. NvRegPhyInterface = 0xC0,
  264. #define PHY_RGMII 0x10000000
  265. NvRegTxRingPhysAddr = 0x100,
  266. NvRegRxRingPhysAddr = 0x104,
  267. NvRegRingSizes = 0x108,
  268. #define NVREG_RINGSZ_TXSHIFT 0
  269. #define NVREG_RINGSZ_RXSHIFT 16
  270. NvRegTransmitPoll = 0x10c,
  271. #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
  272. NvRegLinkSpeed = 0x110,
  273. #define NVREG_LINKSPEED_FORCE 0x10000
  274. #define NVREG_LINKSPEED_10 1000
  275. #define NVREG_LINKSPEED_100 100
  276. #define NVREG_LINKSPEED_1000 50
  277. #define NVREG_LINKSPEED_MASK (0xFFF)
  278. NvRegUnknownSetupReg5 = 0x130,
  279. #define NVREG_UNKSETUP5_BIT31 (1<<31)
  280. NvRegTxWatermark = 0x13c,
  281. #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
  282. #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
  283. #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
  284. NvRegTxRxControl = 0x144,
  285. #define NVREG_TXRXCTL_KICK 0x0001
  286. #define NVREG_TXRXCTL_BIT1 0x0002
  287. #define NVREG_TXRXCTL_BIT2 0x0004
  288. #define NVREG_TXRXCTL_IDLE 0x0008
  289. #define NVREG_TXRXCTL_RESET 0x0010
  290. #define NVREG_TXRXCTL_RXCHECK 0x0400
  291. #define NVREG_TXRXCTL_DESC_1 0
  292. #define NVREG_TXRXCTL_DESC_2 0x002100
  293. #define NVREG_TXRXCTL_DESC_3 0xc02200
  294. #define NVREG_TXRXCTL_VLANSTRIP 0x00040
  295. #define NVREG_TXRXCTL_VLANINS 0x00080
  296. NvRegTxRingPhysAddrHigh = 0x148,
  297. NvRegRxRingPhysAddrHigh = 0x14C,
  298. NvRegTxPauseFrame = 0x170,
  299. #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
  300. #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
  301. NvRegMIIStatus = 0x180,
  302. #define NVREG_MIISTAT_ERROR 0x0001
  303. #define NVREG_MIISTAT_LINKCHANGE 0x0008
  304. #define NVREG_MIISTAT_MASK 0x000f
  305. #define NVREG_MIISTAT_MASK2 0x000f
  306. NvRegMIIMask = 0x184,
  307. #define NVREG_MII_LINKCHANGE 0x0008
  308. NvRegAdapterControl = 0x188,
  309. #define NVREG_ADAPTCTL_START 0x02
  310. #define NVREG_ADAPTCTL_LINKUP 0x04
  311. #define NVREG_ADAPTCTL_PHYVALID 0x40000
  312. #define NVREG_ADAPTCTL_RUNNING 0x100000
  313. #define NVREG_ADAPTCTL_PHYSHIFT 24
  314. NvRegMIISpeed = 0x18c,
  315. #define NVREG_MIISPEED_BIT8 (1<<8)
  316. #define NVREG_MIIDELAY 5
  317. NvRegMIIControl = 0x190,
  318. #define NVREG_MIICTL_INUSE 0x08000
  319. #define NVREG_MIICTL_WRITE 0x00400
  320. #define NVREG_MIICTL_ADDRSHIFT 5
  321. NvRegMIIData = 0x194,
  322. NvRegWakeUpFlags = 0x200,
  323. #define NVREG_WAKEUPFLAGS_VAL 0x7770
  324. #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
  325. #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
  326. #define NVREG_WAKEUPFLAGS_D3SHIFT 12
  327. #define NVREG_WAKEUPFLAGS_D2SHIFT 8
  328. #define NVREG_WAKEUPFLAGS_D1SHIFT 4
  329. #define NVREG_WAKEUPFLAGS_D0SHIFT 0
  330. #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
  331. #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
  332. #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
  333. #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
  334. NvRegPatternCRC = 0x204,
  335. NvRegPatternMask = 0x208,
  336. NvRegPowerCap = 0x268,
  337. #define NVREG_POWERCAP_D3SUPP (1<<30)
  338. #define NVREG_POWERCAP_D2SUPP (1<<26)
  339. #define NVREG_POWERCAP_D1SUPP (1<<25)
  340. NvRegPowerState = 0x26c,
  341. #define NVREG_POWERSTATE_POWEREDUP 0x8000
  342. #define NVREG_POWERSTATE_VALID 0x0100
  343. #define NVREG_POWERSTATE_MASK 0x0003
  344. #define NVREG_POWERSTATE_D0 0x0000
  345. #define NVREG_POWERSTATE_D1 0x0001
  346. #define NVREG_POWERSTATE_D2 0x0002
  347. #define NVREG_POWERSTATE_D3 0x0003
  348. NvRegTxCnt = 0x280,
  349. NvRegTxZeroReXmt = 0x284,
  350. NvRegTxOneReXmt = 0x288,
  351. NvRegTxManyReXmt = 0x28c,
  352. NvRegTxLateCol = 0x290,
  353. NvRegTxUnderflow = 0x294,
  354. NvRegTxLossCarrier = 0x298,
  355. NvRegTxExcessDef = 0x29c,
  356. NvRegTxRetryErr = 0x2a0,
  357. NvRegRxFrameErr = 0x2a4,
  358. NvRegRxExtraByte = 0x2a8,
  359. NvRegRxLateCol = 0x2ac,
  360. NvRegRxRunt = 0x2b0,
  361. NvRegRxFrameTooLong = 0x2b4,
  362. NvRegRxOverflow = 0x2b8,
  363. NvRegRxFCSErr = 0x2bc,
  364. NvRegRxFrameAlignErr = 0x2c0,
  365. NvRegRxLenErr = 0x2c4,
  366. NvRegRxUnicast = 0x2c8,
  367. NvRegRxMulticast = 0x2cc,
  368. NvRegRxBroadcast = 0x2d0,
  369. NvRegTxDef = 0x2d4,
  370. NvRegTxFrame = 0x2d8,
  371. NvRegRxCnt = 0x2dc,
  372. NvRegTxPause = 0x2e0,
  373. NvRegRxPause = 0x2e4,
  374. NvRegRxDropFrame = 0x2e8,
  375. NvRegVlanControl = 0x300,
  376. #define NVREG_VLANCONTROL_ENABLE 0x2000
  377. NvRegMSIXMap0 = 0x3e0,
  378. NvRegMSIXMap1 = 0x3e4,
  379. NvRegMSIXIrqStatus = 0x3f0,
  380. NvRegPowerState2 = 0x600,
  381. #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
  382. #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
  383. };
  384. /* Big endian: should work, but is untested */
  385. struct ring_desc {
  386. __le32 buf;
  387. __le32 flaglen;
  388. };
  389. struct ring_desc_ex {
  390. __le32 bufhigh;
  391. __le32 buflow;
  392. __le32 txvlan;
  393. __le32 flaglen;
  394. };
  395. union ring_type {
  396. struct ring_desc* orig;
  397. struct ring_desc_ex* ex;
  398. };
  399. #define FLAG_MASK_V1 0xffff0000
  400. #define FLAG_MASK_V2 0xffffc000
  401. #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
  402. #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
  403. #define NV_TX_LASTPACKET (1<<16)
  404. #define NV_TX_RETRYERROR (1<<19)
  405. #define NV_TX_FORCED_INTERRUPT (1<<24)
  406. #define NV_TX_DEFERRED (1<<26)
  407. #define NV_TX_CARRIERLOST (1<<27)
  408. #define NV_TX_LATECOLLISION (1<<28)
  409. #define NV_TX_UNDERFLOW (1<<29)
  410. #define NV_TX_ERROR (1<<30)
  411. #define NV_TX_VALID (1<<31)
  412. #define NV_TX2_LASTPACKET (1<<29)
  413. #define NV_TX2_RETRYERROR (1<<18)
  414. #define NV_TX2_FORCED_INTERRUPT (1<<30)
  415. #define NV_TX2_DEFERRED (1<<25)
  416. #define NV_TX2_CARRIERLOST (1<<26)
  417. #define NV_TX2_LATECOLLISION (1<<27)
  418. #define NV_TX2_UNDERFLOW (1<<28)
  419. /* error and valid are the same for both */
  420. #define NV_TX2_ERROR (1<<30)
  421. #define NV_TX2_VALID (1<<31)
  422. #define NV_TX2_TSO (1<<28)
  423. #define NV_TX2_TSO_SHIFT 14
  424. #define NV_TX2_TSO_MAX_SHIFT 14
  425. #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
  426. #define NV_TX2_CHECKSUM_L3 (1<<27)
  427. #define NV_TX2_CHECKSUM_L4 (1<<26)
  428. #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
  429. #define NV_RX_DESCRIPTORVALID (1<<16)
  430. #define NV_RX_MISSEDFRAME (1<<17)
  431. #define NV_RX_SUBSTRACT1 (1<<18)
  432. #define NV_RX_ERROR1 (1<<23)
  433. #define NV_RX_ERROR2 (1<<24)
  434. #define NV_RX_ERROR3 (1<<25)
  435. #define NV_RX_ERROR4 (1<<26)
  436. #define NV_RX_CRCERR (1<<27)
  437. #define NV_RX_OVERFLOW (1<<28)
  438. #define NV_RX_FRAMINGERR (1<<29)
  439. #define NV_RX_ERROR (1<<30)
  440. #define NV_RX_AVAIL (1<<31)
  441. #define NV_RX2_CHECKSUMMASK (0x1C000000)
  442. #define NV_RX2_CHECKSUMOK1 (0x10000000)
  443. #define NV_RX2_CHECKSUMOK2 (0x14000000)
  444. #define NV_RX2_CHECKSUMOK3 (0x18000000)
  445. #define NV_RX2_DESCRIPTORVALID (1<<29)
  446. #define NV_RX2_SUBSTRACT1 (1<<25)
  447. #define NV_RX2_ERROR1 (1<<18)
  448. #define NV_RX2_ERROR2 (1<<19)
  449. #define NV_RX2_ERROR3 (1<<20)
  450. #define NV_RX2_ERROR4 (1<<21)
  451. #define NV_RX2_CRCERR (1<<22)
  452. #define NV_RX2_OVERFLOW (1<<23)
  453. #define NV_RX2_FRAMINGERR (1<<24)
  454. /* error and avail are the same for both */
  455. #define NV_RX2_ERROR (1<<30)
  456. #define NV_RX2_AVAIL (1<<31)
  457. #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
  458. #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
  459. /* Miscelaneous hardware related defines: */
  460. #define NV_PCI_REGSZ_VER1 0x270
  461. #define NV_PCI_REGSZ_VER2 0x2d4
  462. #define NV_PCI_REGSZ_VER3 0x604
  463. /* various timeout delays: all in usec */
  464. #define NV_TXRX_RESET_DELAY 4
  465. #define NV_TXSTOP_DELAY1 10
  466. #define NV_TXSTOP_DELAY1MAX 500000
  467. #define NV_TXSTOP_DELAY2 100
  468. #define NV_RXSTOP_DELAY1 10
  469. #define NV_RXSTOP_DELAY1MAX 500000
  470. #define NV_RXSTOP_DELAY2 100
  471. #define NV_SETUP5_DELAY 5
  472. #define NV_SETUP5_DELAYMAX 50000
  473. #define NV_POWERUP_DELAY 5
  474. #define NV_POWERUP_DELAYMAX 5000
  475. #define NV_MIIBUSY_DELAY 50
  476. #define NV_MIIPHY_DELAY 10
  477. #define NV_MIIPHY_DELAYMAX 10000
  478. #define NV_MAC_RESET_DELAY 64
  479. #define NV_WAKEUPPATTERNS 5
  480. #define NV_WAKEUPMASKENTRIES 4
  481. /* General driver defaults */
  482. #define NV_WATCHDOG_TIMEO (5*HZ)
  483. #define RX_RING_DEFAULT 128
  484. #define TX_RING_DEFAULT 256
  485. #define RX_RING_MIN 128
  486. #define TX_RING_MIN 64
  487. #define RING_MAX_DESC_VER_1 1024
  488. #define RING_MAX_DESC_VER_2_3 16384
  489. /* rx/tx mac addr + type + vlan + align + slack*/
  490. #define NV_RX_HEADERS (64)
  491. /* even more slack. */
  492. #define NV_RX_ALLOC_PAD (64)
  493. /* maximum mtu size */
  494. #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
  495. #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
  496. #define OOM_REFILL (1+HZ/20)
  497. #define POLL_WAIT (1+HZ/100)
  498. #define LINK_TIMEOUT (3*HZ)
  499. #define STATS_INTERVAL (10*HZ)
  500. /*
  501. * desc_ver values:
  502. * The nic supports three different descriptor types:
  503. * - DESC_VER_1: Original
  504. * - DESC_VER_2: support for jumbo frames.
  505. * - DESC_VER_3: 64-bit format.
  506. */
  507. #define DESC_VER_1 1
  508. #define DESC_VER_2 2
  509. #define DESC_VER_3 3
  510. /* PHY defines */
  511. #define PHY_OUI_MARVELL 0x5043
  512. #define PHY_OUI_CICADA 0x03f1
  513. #define PHYID1_OUI_MASK 0x03ff
  514. #define PHYID1_OUI_SHFT 6
  515. #define PHYID2_OUI_MASK 0xfc00
  516. #define PHYID2_OUI_SHFT 10
  517. #define PHYID2_MODEL_MASK 0x03f0
  518. #define PHY_MODEL_MARVELL_E3016 0x220
  519. #define PHY_MARVELL_E3016_INITMASK 0x0300
  520. #define PHY_INIT1 0x0f000
  521. #define PHY_INIT2 0x0e00
  522. #define PHY_INIT3 0x01000
  523. #define PHY_INIT4 0x0200
  524. #define PHY_INIT5 0x0004
  525. #define PHY_INIT6 0x02000
  526. #define PHY_GIGABIT 0x0100
  527. #define PHY_TIMEOUT 0x1
  528. #define PHY_ERROR 0x2
  529. #define PHY_100 0x1
  530. #define PHY_1000 0x2
  531. #define PHY_HALF 0x100
  532. #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
  533. #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
  534. #define NV_PAUSEFRAME_RX_ENABLE 0x0004
  535. #define NV_PAUSEFRAME_TX_ENABLE 0x0008
  536. #define NV_PAUSEFRAME_RX_REQ 0x0010
  537. #define NV_PAUSEFRAME_TX_REQ 0x0020
  538. #define NV_PAUSEFRAME_AUTONEG 0x0040
  539. /* MSI/MSI-X defines */
  540. #define NV_MSI_X_MAX_VECTORS 8
  541. #define NV_MSI_X_VECTORS_MASK 0x000f
  542. #define NV_MSI_CAPABLE 0x0010
  543. #define NV_MSI_X_CAPABLE 0x0020
  544. #define NV_MSI_ENABLED 0x0040
  545. #define NV_MSI_X_ENABLED 0x0080
  546. #define NV_MSI_X_VECTOR_ALL 0x0
  547. #define NV_MSI_X_VECTOR_RX 0x0
  548. #define NV_MSI_X_VECTOR_TX 0x1
  549. #define NV_MSI_X_VECTOR_OTHER 0x2
  550. /* statistics */
  551. struct nv_ethtool_str {
  552. char name[ETH_GSTRING_LEN];
  553. };
  554. static const struct nv_ethtool_str nv_estats_str[] = {
  555. { "tx_bytes" },
  556. { "tx_zero_rexmt" },
  557. { "tx_one_rexmt" },
  558. { "tx_many_rexmt" },
  559. { "tx_late_collision" },
  560. { "tx_fifo_errors" },
  561. { "tx_carrier_errors" },
  562. { "tx_excess_deferral" },
  563. { "tx_retry_error" },
  564. { "rx_frame_error" },
  565. { "rx_extra_byte" },
  566. { "rx_late_collision" },
  567. { "rx_runt" },
  568. { "rx_frame_too_long" },
  569. { "rx_over_errors" },
  570. { "rx_crc_errors" },
  571. { "rx_frame_align_error" },
  572. { "rx_length_error" },
  573. { "rx_unicast" },
  574. { "rx_multicast" },
  575. { "rx_broadcast" },
  576. { "rx_packets" },
  577. { "rx_errors_total" },
  578. { "tx_errors_total" },
  579. /* version 2 stats */
  580. { "tx_deferral" },
  581. { "tx_packets" },
  582. { "rx_bytes" },
  583. { "tx_pause" },
  584. { "rx_pause" },
  585. { "rx_drop_frame" }
  586. };
  587. struct nv_ethtool_stats {
  588. u64 tx_bytes;
  589. u64 tx_zero_rexmt;
  590. u64 tx_one_rexmt;
  591. u64 tx_many_rexmt;
  592. u64 tx_late_collision;
  593. u64 tx_fifo_errors;
  594. u64 tx_carrier_errors;
  595. u64 tx_excess_deferral;
  596. u64 tx_retry_error;
  597. u64 rx_frame_error;
  598. u64 rx_extra_byte;
  599. u64 rx_late_collision;
  600. u64 rx_runt;
  601. u64 rx_frame_too_long;
  602. u64 rx_over_errors;
  603. u64 rx_crc_errors;
  604. u64 rx_frame_align_error;
  605. u64 rx_length_error;
  606. u64 rx_unicast;
  607. u64 rx_multicast;
  608. u64 rx_broadcast;
  609. u64 rx_packets;
  610. u64 rx_errors_total;
  611. u64 tx_errors_total;
  612. /* version 2 stats */
  613. u64 tx_deferral;
  614. u64 tx_packets;
  615. u64 rx_bytes;
  616. u64 tx_pause;
  617. u64 rx_pause;
  618. u64 rx_drop_frame;
  619. };
  620. #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
  621. #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
  622. /* diagnostics */
  623. #define NV_TEST_COUNT_BASE 3
  624. #define NV_TEST_COUNT_EXTENDED 4
  625. static const struct nv_ethtool_str nv_etests_str[] = {
  626. { "link (online/offline)" },
  627. { "register (offline) " },
  628. { "interrupt (offline) " },
  629. { "loopback (offline) " }
  630. };
  631. struct register_test {
  632. __le32 reg;
  633. __le32 mask;
  634. };
  635. static const struct register_test nv_registers_test[] = {
  636. { NvRegUnknownSetupReg6, 0x01 },
  637. { NvRegMisc1, 0x03c },
  638. { NvRegOffloadConfig, 0x03ff },
  639. { NvRegMulticastAddrA, 0xffffffff },
  640. { NvRegTxWatermark, 0x0ff },
  641. { NvRegWakeUpFlags, 0x07777 },
  642. { 0,0 }
  643. };
  644. struct nv_skb_map {
  645. struct sk_buff *skb;
  646. dma_addr_t dma;
  647. unsigned int dma_len;
  648. };
  649. /*
  650. * SMP locking:
  651. * All hardware access under dev->priv->lock, except the performance
  652. * critical parts:
  653. * - rx is (pseudo-) lockless: it relies on the single-threading provided
  654. * by the arch code for interrupts.
  655. * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
  656. * needs dev->priv->lock :-(
  657. * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
  658. */
  659. /* in dev: base, irq */
  660. struct fe_priv {
  661. spinlock_t lock;
  662. /* General data:
  663. * Locking: spin_lock(&np->lock); */
  664. struct net_device_stats stats;
  665. struct nv_ethtool_stats estats;
  666. int in_shutdown;
  667. u32 linkspeed;
  668. int duplex;
  669. int autoneg;
  670. int fixed_mode;
  671. int phyaddr;
  672. int wolenabled;
  673. unsigned int phy_oui;
  674. unsigned int phy_model;
  675. u16 gigabit;
  676. int intr_test;
  677. int recover_error;
  678. /* General data: RO fields */
  679. dma_addr_t ring_addr;
  680. struct pci_dev *pci_dev;
  681. u32 orig_mac[2];
  682. u32 irqmask;
  683. u32 desc_ver;
  684. u32 txrxctl_bits;
  685. u32 vlanctl_bits;
  686. u32 driver_data;
  687. u32 register_size;
  688. int rx_csum;
  689. u32 mac_in_use;
  690. void __iomem *base;
  691. /* rx specific fields.
  692. * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
  693. */
  694. union ring_type get_rx, put_rx, first_rx, last_rx;
  695. struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
  696. struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
  697. struct nv_skb_map *rx_skb;
  698. union ring_type rx_ring;
  699. unsigned int rx_buf_sz;
  700. unsigned int pkt_limit;
  701. struct timer_list oom_kick;
  702. struct timer_list nic_poll;
  703. struct timer_list stats_poll;
  704. u32 nic_poll_irq;
  705. int rx_ring_size;
  706. /* media detection workaround.
  707. * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
  708. */
  709. int need_linktimer;
  710. unsigned long link_timeout;
  711. /*
  712. * tx specific fields.
  713. */
  714. union ring_type get_tx, put_tx, first_tx, last_tx;
  715. struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
  716. struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
  717. struct nv_skb_map *tx_skb;
  718. union ring_type tx_ring;
  719. u32 tx_flags;
  720. int tx_ring_size;
  721. int tx_stop;
  722. /* vlan fields */
  723. struct vlan_group *vlangrp;
  724. /* msi/msi-x fields */
  725. u32 msi_flags;
  726. struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
  727. /* flow control */
  728. u32 pause_flags;
  729. };
  730. /*
  731. * Maximum number of loops until we assume that a bit in the irq mask
  732. * is stuck. Overridable with module param.
  733. */
  734. static int max_interrupt_work = 5;
  735. /*
  736. * Optimization can be either throuput mode or cpu mode
  737. *
  738. * Throughput Mode: Every tx and rx packet will generate an interrupt.
  739. * CPU Mode: Interrupts are controlled by a timer.
  740. */
  741. enum {
  742. NV_OPTIMIZATION_MODE_THROUGHPUT,
  743. NV_OPTIMIZATION_MODE_CPU
  744. };
  745. static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
  746. /*
  747. * Poll interval for timer irq
  748. *
  749. * This interval determines how frequent an interrupt is generated.
  750. * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
  751. * Min = 0, and Max = 65535
  752. */
  753. static int poll_interval = -1;
  754. /*
  755. * MSI interrupts
  756. */
  757. enum {
  758. NV_MSI_INT_DISABLED,
  759. NV_MSI_INT_ENABLED
  760. };
  761. static int msi = NV_MSI_INT_ENABLED;
  762. /*
  763. * MSIX interrupts
  764. */
  765. enum {
  766. NV_MSIX_INT_DISABLED,
  767. NV_MSIX_INT_ENABLED
  768. };
  769. static int msix = NV_MSIX_INT_DISABLED;
  770. /*
  771. * DMA 64bit
  772. */
  773. enum {
  774. NV_DMA_64BIT_DISABLED,
  775. NV_DMA_64BIT_ENABLED
  776. };
  777. static int dma_64bit = NV_DMA_64BIT_ENABLED;
  778. static inline struct fe_priv *get_nvpriv(struct net_device *dev)
  779. {
  780. return netdev_priv(dev);
  781. }
  782. static inline u8 __iomem *get_hwbase(struct net_device *dev)
  783. {
  784. return ((struct fe_priv *)netdev_priv(dev))->base;
  785. }
  786. static inline void pci_push(u8 __iomem *base)
  787. {
  788. /* force out pending posted writes */
  789. readl(base);
  790. }
  791. static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
  792. {
  793. return le32_to_cpu(prd->flaglen)
  794. & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
  795. }
  796. static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
  797. {
  798. return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
  799. }
  800. static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
  801. int delay, int delaymax, const char *msg)
  802. {
  803. u8 __iomem *base = get_hwbase(dev);
  804. pci_push(base);
  805. do {
  806. udelay(delay);
  807. delaymax -= delay;
  808. if (delaymax < 0) {
  809. if (msg)
  810. printk(msg);
  811. return 1;
  812. }
  813. } while ((readl(base + offset) & mask) != target);
  814. return 0;
  815. }
  816. #define NV_SETUP_RX_RING 0x01
  817. #define NV_SETUP_TX_RING 0x02
  818. static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
  819. {
  820. struct fe_priv *np = get_nvpriv(dev);
  821. u8 __iomem *base = get_hwbase(dev);
  822. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  823. if (rxtx_flags & NV_SETUP_RX_RING) {
  824. writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
  825. }
  826. if (rxtx_flags & NV_SETUP_TX_RING) {
  827. writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
  828. }
  829. } else {
  830. if (rxtx_flags & NV_SETUP_RX_RING) {
  831. writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
  832. writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
  833. }
  834. if (rxtx_flags & NV_SETUP_TX_RING) {
  835. writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
  836. writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
  837. }
  838. }
  839. }
  840. static void free_rings(struct net_device *dev)
  841. {
  842. struct fe_priv *np = get_nvpriv(dev);
  843. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  844. if (np->rx_ring.orig)
  845. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
  846. np->rx_ring.orig, np->ring_addr);
  847. } else {
  848. if (np->rx_ring.ex)
  849. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
  850. np->rx_ring.ex, np->ring_addr);
  851. }
  852. if (np->rx_skb)
  853. kfree(np->rx_skb);
  854. if (np->tx_skb)
  855. kfree(np->tx_skb);
  856. }
  857. static int using_multi_irqs(struct net_device *dev)
  858. {
  859. struct fe_priv *np = get_nvpriv(dev);
  860. if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
  861. ((np->msi_flags & NV_MSI_X_ENABLED) &&
  862. ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
  863. return 0;
  864. else
  865. return 1;
  866. }
  867. static void nv_enable_irq(struct net_device *dev)
  868. {
  869. struct fe_priv *np = get_nvpriv(dev);
  870. if (!using_multi_irqs(dev)) {
  871. if (np->msi_flags & NV_MSI_X_ENABLED)
  872. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  873. else
  874. enable_irq(dev->irq);
  875. } else {
  876. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  877. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  878. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  879. }
  880. }
  881. static void nv_disable_irq(struct net_device *dev)
  882. {
  883. struct fe_priv *np = get_nvpriv(dev);
  884. if (!using_multi_irqs(dev)) {
  885. if (np->msi_flags & NV_MSI_X_ENABLED)
  886. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  887. else
  888. disable_irq(dev->irq);
  889. } else {
  890. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  891. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  892. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  893. }
  894. }
  895. /* In MSIX mode, a write to irqmask behaves as XOR */
  896. static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
  897. {
  898. u8 __iomem *base = get_hwbase(dev);
  899. writel(mask, base + NvRegIrqMask);
  900. }
  901. static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
  902. {
  903. struct fe_priv *np = get_nvpriv(dev);
  904. u8 __iomem *base = get_hwbase(dev);
  905. if (np->msi_flags & NV_MSI_X_ENABLED) {
  906. writel(mask, base + NvRegIrqMask);
  907. } else {
  908. if (np->msi_flags & NV_MSI_ENABLED)
  909. writel(0, base + NvRegMSIIrqMask);
  910. writel(0, base + NvRegIrqMask);
  911. }
  912. }
  913. #define MII_READ (-1)
  914. /* mii_rw: read/write a register on the PHY.
  915. *
  916. * Caller must guarantee serialization
  917. */
  918. static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
  919. {
  920. u8 __iomem *base = get_hwbase(dev);
  921. u32 reg;
  922. int retval;
  923. writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
  924. reg = readl(base + NvRegMIIControl);
  925. if (reg & NVREG_MIICTL_INUSE) {
  926. writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
  927. udelay(NV_MIIBUSY_DELAY);
  928. }
  929. reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
  930. if (value != MII_READ) {
  931. writel(value, base + NvRegMIIData);
  932. reg |= NVREG_MIICTL_WRITE;
  933. }
  934. writel(reg, base + NvRegMIIControl);
  935. if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
  936. NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
  937. dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
  938. dev->name, miireg, addr);
  939. retval = -1;
  940. } else if (value != MII_READ) {
  941. /* it was a write operation - fewer failures are detectable */
  942. dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
  943. dev->name, value, miireg, addr);
  944. retval = 0;
  945. } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
  946. dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
  947. dev->name, miireg, addr);
  948. retval = -1;
  949. } else {
  950. retval = readl(base + NvRegMIIData);
  951. dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
  952. dev->name, miireg, addr, retval);
  953. }
  954. return retval;
  955. }
  956. static int phy_reset(struct net_device *dev, u32 bmcr_setup)
  957. {
  958. struct fe_priv *np = netdev_priv(dev);
  959. u32 miicontrol;
  960. unsigned int tries = 0;
  961. miicontrol = BMCR_RESET | bmcr_setup;
  962. if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
  963. return -1;
  964. }
  965. /* wait for 500ms */
  966. msleep(500);
  967. /* must wait till reset is deasserted */
  968. while (miicontrol & BMCR_RESET) {
  969. msleep(10);
  970. miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  971. /* FIXME: 100 tries seem excessive */
  972. if (tries++ > 100)
  973. return -1;
  974. }
  975. return 0;
  976. }
  977. static int phy_init(struct net_device *dev)
  978. {
  979. struct fe_priv *np = get_nvpriv(dev);
  980. u8 __iomem *base = get_hwbase(dev);
  981. u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
  982. /* phy errata for E3016 phy */
  983. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  984. reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
  985. reg &= ~PHY_MARVELL_E3016_INITMASK;
  986. if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
  987. printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
  988. return PHY_ERROR;
  989. }
  990. }
  991. /* set advertise register */
  992. reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  993. reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
  994. if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
  995. printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
  996. return PHY_ERROR;
  997. }
  998. /* get phy interface type */
  999. phyinterface = readl(base + NvRegPhyInterface);
  1000. /* see if gigabit phy */
  1001. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  1002. if (mii_status & PHY_GIGABIT) {
  1003. np->gigabit = PHY_GIGABIT;
  1004. mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  1005. mii_control_1000 &= ~ADVERTISE_1000HALF;
  1006. if (phyinterface & PHY_RGMII)
  1007. mii_control_1000 |= ADVERTISE_1000FULL;
  1008. else
  1009. mii_control_1000 &= ~ADVERTISE_1000FULL;
  1010. if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
  1011. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1012. return PHY_ERROR;
  1013. }
  1014. }
  1015. else
  1016. np->gigabit = 0;
  1017. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1018. mii_control |= BMCR_ANENABLE;
  1019. /* reset the phy
  1020. * (certain phys need bmcr to be setup with reset)
  1021. */
  1022. if (phy_reset(dev, mii_control)) {
  1023. printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
  1024. return PHY_ERROR;
  1025. }
  1026. /* phy vendor specific configuration */
  1027. if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
  1028. phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
  1029. phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
  1030. phy_reserved |= (PHY_INIT3 | PHY_INIT4);
  1031. if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
  1032. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1033. return PHY_ERROR;
  1034. }
  1035. phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
  1036. phy_reserved |= PHY_INIT5;
  1037. if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
  1038. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1039. return PHY_ERROR;
  1040. }
  1041. }
  1042. if (np->phy_oui == PHY_OUI_CICADA) {
  1043. phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
  1044. phy_reserved |= PHY_INIT6;
  1045. if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
  1046. printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
  1047. return PHY_ERROR;
  1048. }
  1049. }
  1050. /* some phys clear out pause advertisment on reset, set it back */
  1051. mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
  1052. /* restart auto negotiation */
  1053. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1054. mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
  1055. if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
  1056. return PHY_ERROR;
  1057. }
  1058. return 0;
  1059. }
  1060. static void nv_start_rx(struct net_device *dev)
  1061. {
  1062. struct fe_priv *np = netdev_priv(dev);
  1063. u8 __iomem *base = get_hwbase(dev);
  1064. u32 rx_ctrl = readl(base + NvRegReceiverControl);
  1065. dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
  1066. /* Already running? Stop it. */
  1067. if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
  1068. rx_ctrl &= ~NVREG_RCVCTL_START;
  1069. writel(rx_ctrl, base + NvRegReceiverControl);
  1070. pci_push(base);
  1071. }
  1072. writel(np->linkspeed, base + NvRegLinkSpeed);
  1073. pci_push(base);
  1074. rx_ctrl |= NVREG_RCVCTL_START;
  1075. if (np->mac_in_use)
  1076. rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
  1077. writel(rx_ctrl, base + NvRegReceiverControl);
  1078. dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
  1079. dev->name, np->duplex, np->linkspeed);
  1080. pci_push(base);
  1081. }
  1082. static void nv_stop_rx(struct net_device *dev)
  1083. {
  1084. struct fe_priv *np = netdev_priv(dev);
  1085. u8 __iomem *base = get_hwbase(dev);
  1086. u32 rx_ctrl = readl(base + NvRegReceiverControl);
  1087. dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
  1088. if (!np->mac_in_use)
  1089. rx_ctrl &= ~NVREG_RCVCTL_START;
  1090. else
  1091. rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
  1092. writel(rx_ctrl, base + NvRegReceiverControl);
  1093. reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
  1094. NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
  1095. KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
  1096. udelay(NV_RXSTOP_DELAY2);
  1097. if (!np->mac_in_use)
  1098. writel(0, base + NvRegLinkSpeed);
  1099. }
  1100. static void nv_start_tx(struct net_device *dev)
  1101. {
  1102. struct fe_priv *np = netdev_priv(dev);
  1103. u8 __iomem *base = get_hwbase(dev);
  1104. u32 tx_ctrl = readl(base + NvRegTransmitterControl);
  1105. dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
  1106. tx_ctrl |= NVREG_XMITCTL_START;
  1107. if (np->mac_in_use)
  1108. tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
  1109. writel(tx_ctrl, base + NvRegTransmitterControl);
  1110. pci_push(base);
  1111. }
  1112. static void nv_stop_tx(struct net_device *dev)
  1113. {
  1114. struct fe_priv *np = netdev_priv(dev);
  1115. u8 __iomem *base = get_hwbase(dev);
  1116. u32 tx_ctrl = readl(base + NvRegTransmitterControl);
  1117. dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
  1118. if (!np->mac_in_use)
  1119. tx_ctrl &= ~NVREG_XMITCTL_START;
  1120. else
  1121. tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
  1122. writel(tx_ctrl, base + NvRegTransmitterControl);
  1123. reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
  1124. NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
  1125. KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
  1126. udelay(NV_TXSTOP_DELAY2);
  1127. if (!np->mac_in_use)
  1128. writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
  1129. base + NvRegTransmitPoll);
  1130. }
  1131. static void nv_txrx_reset(struct net_device *dev)
  1132. {
  1133. struct fe_priv *np = netdev_priv(dev);
  1134. u8 __iomem *base = get_hwbase(dev);
  1135. dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
  1136. writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
  1137. pci_push(base);
  1138. udelay(NV_TXRX_RESET_DELAY);
  1139. writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
  1140. pci_push(base);
  1141. }
  1142. static void nv_mac_reset(struct net_device *dev)
  1143. {
  1144. struct fe_priv *np = netdev_priv(dev);
  1145. u8 __iomem *base = get_hwbase(dev);
  1146. dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
  1147. writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
  1148. pci_push(base);
  1149. writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
  1150. pci_push(base);
  1151. udelay(NV_MAC_RESET_DELAY);
  1152. writel(0, base + NvRegMacReset);
  1153. pci_push(base);
  1154. udelay(NV_MAC_RESET_DELAY);
  1155. writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
  1156. pci_push(base);
  1157. }
  1158. static void nv_get_hw_stats(struct net_device *dev)
  1159. {
  1160. struct fe_priv *np = netdev_priv(dev);
  1161. u8 __iomem *base = get_hwbase(dev);
  1162. np->estats.tx_bytes += readl(base + NvRegTxCnt);
  1163. np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
  1164. np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
  1165. np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
  1166. np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
  1167. np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
  1168. np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
  1169. np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
  1170. np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
  1171. np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
  1172. np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
  1173. np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
  1174. np->estats.rx_runt += readl(base + NvRegRxRunt);
  1175. np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
  1176. np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
  1177. np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
  1178. np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
  1179. np->estats.rx_length_error += readl(base + NvRegRxLenErr);
  1180. np->estats.rx_unicast += readl(base + NvRegRxUnicast);
  1181. np->estats.rx_multicast += readl(base + NvRegRxMulticast);
  1182. np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
  1183. np->estats.rx_packets =
  1184. np->estats.rx_unicast +
  1185. np->estats.rx_multicast +
  1186. np->estats.rx_broadcast;
  1187. np->estats.rx_errors_total =
  1188. np->estats.rx_crc_errors +
  1189. np->estats.rx_over_errors +
  1190. np->estats.rx_frame_error +
  1191. (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
  1192. np->estats.rx_late_collision +
  1193. np->estats.rx_runt +
  1194. np->estats.rx_frame_too_long;
  1195. np->estats.tx_errors_total =
  1196. np->estats.tx_late_collision +
  1197. np->estats.tx_fifo_errors +
  1198. np->estats.tx_carrier_errors +
  1199. np->estats.tx_excess_deferral +
  1200. np->estats.tx_retry_error;
  1201. if (np->driver_data & DEV_HAS_STATISTICS_V2) {
  1202. np->estats.tx_deferral += readl(base + NvRegTxDef);
  1203. np->estats.tx_packets += readl(base + NvRegTxFrame);
  1204. np->estats.rx_bytes += readl(base + NvRegRxCnt);
  1205. np->estats.tx_pause += readl(base + NvRegTxPause);
  1206. np->estats.rx_pause += readl(base + NvRegRxPause);
  1207. np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
  1208. }
  1209. }
  1210. /*
  1211. * nv_get_stats: dev->get_stats function
  1212. * Get latest stats value from the nic.
  1213. * Called with read_lock(&dev_base_lock) held for read -
  1214. * only synchronized against unregister_netdevice.
  1215. */
  1216. static struct net_device_stats *nv_get_stats(struct net_device *dev)
  1217. {
  1218. struct fe_priv *np = netdev_priv(dev);
  1219. /* If the nic supports hw counters then retrieve latest values */
  1220. if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
  1221. nv_get_hw_stats(dev);
  1222. /* copy to net_device stats */
  1223. np->stats.tx_bytes = np->estats.tx_bytes;
  1224. np->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
  1225. np->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
  1226. np->stats.rx_crc_errors = np->estats.rx_crc_errors;
  1227. np->stats.rx_over_errors = np->estats.rx_over_errors;
  1228. np->stats.rx_errors = np->estats.rx_errors_total;
  1229. np->stats.tx_errors = np->estats.tx_errors_total;
  1230. }
  1231. return &np->stats;
  1232. }
  1233. /*
  1234. * nv_alloc_rx: fill rx ring entries.
  1235. * Return 1 if the allocations for the skbs failed and the
  1236. * rx engine is without Available descriptors
  1237. */
  1238. static int nv_alloc_rx(struct net_device *dev)
  1239. {
  1240. struct fe_priv *np = netdev_priv(dev);
  1241. struct ring_desc* less_rx;
  1242. less_rx = np->get_rx.orig;
  1243. if (less_rx-- == np->first_rx.orig)
  1244. less_rx = np->last_rx.orig;
  1245. while (np->put_rx.orig != less_rx) {
  1246. struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
  1247. if (skb) {
  1248. skb->dev = dev;
  1249. np->put_rx_ctx->skb = skb;
  1250. np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
  1251. skb->end-skb->data, PCI_DMA_FROMDEVICE);
  1252. np->put_rx_ctx->dma_len = skb->end-skb->data;
  1253. np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
  1254. wmb();
  1255. np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
  1256. if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
  1257. np->put_rx.orig = np->first_rx.orig;
  1258. if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
  1259. np->put_rx_ctx = np->first_rx_ctx;
  1260. } else {
  1261. return 1;
  1262. }
  1263. }
  1264. return 0;
  1265. }
  1266. static int nv_alloc_rx_optimized(struct net_device *dev)
  1267. {
  1268. struct fe_priv *np = netdev_priv(dev);
  1269. struct ring_desc_ex* less_rx;
  1270. less_rx = np->get_rx.ex;
  1271. if (less_rx-- == np->first_rx.ex)
  1272. less_rx = np->last_rx.ex;
  1273. while (np->put_rx.ex != less_rx) {
  1274. struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
  1275. if (skb) {
  1276. skb->dev = dev;
  1277. np->put_rx_ctx->skb = skb;
  1278. np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
  1279. skb->end-skb->data, PCI_DMA_FROMDEVICE);
  1280. np->put_rx_ctx->dma_len = skb->end-skb->data;
  1281. np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
  1282. np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
  1283. wmb();
  1284. np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
  1285. if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
  1286. np->put_rx.ex = np->first_rx.ex;
  1287. if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
  1288. np->put_rx_ctx = np->first_rx_ctx;
  1289. } else {
  1290. return 1;
  1291. }
  1292. }
  1293. return 0;
  1294. }
  1295. /* If rx bufs are exhausted called after 50ms to attempt to refresh */
  1296. #ifdef CONFIG_FORCEDETH_NAPI
  1297. static void nv_do_rx_refill(unsigned long data)
  1298. {
  1299. struct net_device *dev = (struct net_device *) data;
  1300. /* Just reschedule NAPI rx processing */
  1301. netif_rx_schedule(dev);
  1302. }
  1303. #else
  1304. static void nv_do_rx_refill(unsigned long data)
  1305. {
  1306. struct net_device *dev = (struct net_device *) data;
  1307. struct fe_priv *np = netdev_priv(dev);
  1308. int retcode;
  1309. if (!using_multi_irqs(dev)) {
  1310. if (np->msi_flags & NV_MSI_X_ENABLED)
  1311. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  1312. else
  1313. disable_irq(dev->irq);
  1314. } else {
  1315. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  1316. }
  1317. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
  1318. retcode = nv_alloc_rx(dev);
  1319. else
  1320. retcode = nv_alloc_rx_optimized(dev);
  1321. if (retcode) {
  1322. spin_lock_irq(&np->lock);
  1323. if (!np->in_shutdown)
  1324. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  1325. spin_unlock_irq(&np->lock);
  1326. }
  1327. if (!using_multi_irqs(dev)) {
  1328. if (np->msi_flags & NV_MSI_X_ENABLED)
  1329. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  1330. else
  1331. enable_irq(dev->irq);
  1332. } else {
  1333. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  1334. }
  1335. }
  1336. #endif
  1337. static void nv_init_rx(struct net_device *dev)
  1338. {
  1339. struct fe_priv *np = netdev_priv(dev);
  1340. int i;
  1341. np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
  1342. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
  1343. np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
  1344. else
  1345. np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
  1346. np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
  1347. np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
  1348. for (i = 0; i < np->rx_ring_size; i++) {
  1349. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  1350. np->rx_ring.orig[i].flaglen = 0;
  1351. np->rx_ring.orig[i].buf = 0;
  1352. } else {
  1353. np->rx_ring.ex[i].flaglen = 0;
  1354. np->rx_ring.ex[i].txvlan = 0;
  1355. np->rx_ring.ex[i].bufhigh = 0;
  1356. np->rx_ring.ex[i].buflow = 0;
  1357. }
  1358. np->rx_skb[i].skb = NULL;
  1359. np->rx_skb[i].dma = 0;
  1360. }
  1361. }
  1362. static void nv_init_tx(struct net_device *dev)
  1363. {
  1364. struct fe_priv *np = netdev_priv(dev);
  1365. int i;
  1366. np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
  1367. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
  1368. np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
  1369. else
  1370. np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
  1371. np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
  1372. np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
  1373. for (i = 0; i < np->tx_ring_size; i++) {
  1374. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  1375. np->tx_ring.orig[i].flaglen = 0;
  1376. np->tx_ring.orig[i].buf = 0;
  1377. } else {
  1378. np->tx_ring.ex[i].flaglen = 0;
  1379. np->tx_ring.ex[i].txvlan = 0;
  1380. np->tx_ring.ex[i].bufhigh = 0;
  1381. np->tx_ring.ex[i].buflow = 0;
  1382. }
  1383. np->tx_skb[i].skb = NULL;
  1384. np->tx_skb[i].dma = 0;
  1385. }
  1386. }
  1387. static int nv_init_ring(struct net_device *dev)
  1388. {
  1389. struct fe_priv *np = netdev_priv(dev);
  1390. nv_init_tx(dev);
  1391. nv_init_rx(dev);
  1392. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
  1393. return nv_alloc_rx(dev);
  1394. else
  1395. return nv_alloc_rx_optimized(dev);
  1396. }
  1397. static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
  1398. {
  1399. struct fe_priv *np = netdev_priv(dev);
  1400. if (tx_skb->dma) {
  1401. pci_unmap_page(np->pci_dev, tx_skb->dma,
  1402. tx_skb->dma_len,
  1403. PCI_DMA_TODEVICE);
  1404. tx_skb->dma = 0;
  1405. }
  1406. if (tx_skb->skb) {
  1407. dev_kfree_skb_any(tx_skb->skb);
  1408. tx_skb->skb = NULL;
  1409. return 1;
  1410. } else {
  1411. return 0;
  1412. }
  1413. }
  1414. static void nv_drain_tx(struct net_device *dev)
  1415. {
  1416. struct fe_priv *np = netdev_priv(dev);
  1417. unsigned int i;
  1418. for (i = 0; i < np->tx_ring_size; i++) {
  1419. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  1420. np->tx_ring.orig[i].flaglen = 0;
  1421. np->tx_ring.orig[i].buf = 0;
  1422. } else {
  1423. np->tx_ring.ex[i].flaglen = 0;
  1424. np->tx_ring.ex[i].txvlan = 0;
  1425. np->tx_ring.ex[i].bufhigh = 0;
  1426. np->tx_ring.ex[i].buflow = 0;
  1427. }
  1428. if (nv_release_txskb(dev, &np->tx_skb[i]))
  1429. np->stats.tx_dropped++;
  1430. }
  1431. }
  1432. static void nv_drain_rx(struct net_device *dev)
  1433. {
  1434. struct fe_priv *np = netdev_priv(dev);
  1435. int i;
  1436. for (i = 0; i < np->rx_ring_size; i++) {
  1437. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  1438. np->rx_ring.orig[i].flaglen = 0;
  1439. np->rx_ring.orig[i].buf = 0;
  1440. } else {
  1441. np->rx_ring.ex[i].flaglen = 0;
  1442. np->rx_ring.ex[i].txvlan = 0;
  1443. np->rx_ring.ex[i].bufhigh = 0;
  1444. np->rx_ring.ex[i].buflow = 0;
  1445. }
  1446. wmb();
  1447. if (np->rx_skb[i].skb) {
  1448. pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
  1449. np->rx_skb[i].skb->end-np->rx_skb[i].skb->data,
  1450. PCI_DMA_FROMDEVICE);
  1451. dev_kfree_skb(np->rx_skb[i].skb);
  1452. np->rx_skb[i].skb = NULL;
  1453. }
  1454. }
  1455. }
  1456. static void drain_ring(struct net_device *dev)
  1457. {
  1458. nv_drain_tx(dev);
  1459. nv_drain_rx(dev);
  1460. }
  1461. static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
  1462. {
  1463. return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
  1464. }
  1465. /*
  1466. * nv_start_xmit: dev->hard_start_xmit function
  1467. * Called with netif_tx_lock held.
  1468. */
  1469. static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1470. {
  1471. struct fe_priv *np = netdev_priv(dev);
  1472. u32 tx_flags = 0;
  1473. u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
  1474. unsigned int fragments = skb_shinfo(skb)->nr_frags;
  1475. unsigned int i;
  1476. u32 offset = 0;
  1477. u32 bcnt;
  1478. u32 size = skb->len-skb->data_len;
  1479. u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1480. u32 empty_slots;
  1481. struct ring_desc* put_tx;
  1482. struct ring_desc* start_tx;
  1483. struct ring_desc* prev_tx;
  1484. struct nv_skb_map* prev_tx_ctx;
  1485. /* add fragments to entries count */
  1486. for (i = 0; i < fragments; i++) {
  1487. entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
  1488. ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1489. }
  1490. empty_slots = nv_get_empty_tx_slots(np);
  1491. if (unlikely(empty_slots <= entries)) {
  1492. spin_lock_irq(&np->lock);
  1493. netif_stop_queue(dev);
  1494. np->tx_stop = 1;
  1495. spin_unlock_irq(&np->lock);
  1496. return NETDEV_TX_BUSY;
  1497. }
  1498. start_tx = put_tx = np->put_tx.orig;
  1499. /* setup the header buffer */
  1500. do {
  1501. prev_tx = put_tx;
  1502. prev_tx_ctx = np->put_tx_ctx;
  1503. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1504. np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
  1505. PCI_DMA_TODEVICE);
  1506. np->put_tx_ctx->dma_len = bcnt;
  1507. put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
  1508. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1509. tx_flags = np->tx_flags;
  1510. offset += bcnt;
  1511. size -= bcnt;
  1512. if (unlikely(put_tx++ == np->last_tx.orig))
  1513. put_tx = np->first_tx.orig;
  1514. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  1515. np->put_tx_ctx = np->first_tx_ctx;
  1516. } while (size);
  1517. /* setup the fragments */
  1518. for (i = 0; i < fragments; i++) {
  1519. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1520. u32 size = frag->size;
  1521. offset = 0;
  1522. do {
  1523. prev_tx = put_tx;
  1524. prev_tx_ctx = np->put_tx_ctx;
  1525. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1526. np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
  1527. PCI_DMA_TODEVICE);
  1528. np->put_tx_ctx->dma_len = bcnt;
  1529. put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
  1530. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1531. offset += bcnt;
  1532. size -= bcnt;
  1533. if (unlikely(put_tx++ == np->last_tx.orig))
  1534. put_tx = np->first_tx.orig;
  1535. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  1536. np->put_tx_ctx = np->first_tx_ctx;
  1537. } while (size);
  1538. }
  1539. /* set last fragment flag */
  1540. prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
  1541. /* save skb in this slot's context area */
  1542. prev_tx_ctx->skb = skb;
  1543. if (skb_is_gso(skb))
  1544. tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
  1545. else
  1546. tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
  1547. NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
  1548. spin_lock_irq(&np->lock);
  1549. /* set tx flags */
  1550. start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
  1551. np->put_tx.orig = put_tx;
  1552. spin_unlock_irq(&np->lock);
  1553. dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
  1554. dev->name, entries, tx_flags_extra);
  1555. {
  1556. int j;
  1557. for (j=0; j<64; j++) {
  1558. if ((j%16) == 0)
  1559. dprintk("\n%03x:", j);
  1560. dprintk(" %02x", ((unsigned char*)skb->data)[j]);
  1561. }
  1562. dprintk("\n");
  1563. }
  1564. dev->trans_start = jiffies;
  1565. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  1566. return NETDEV_TX_OK;
  1567. }
  1568. static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
  1569. {
  1570. struct fe_priv *np = netdev_priv(dev);
  1571. u32 tx_flags = 0;
  1572. u32 tx_flags_extra;
  1573. unsigned int fragments = skb_shinfo(skb)->nr_frags;
  1574. unsigned int i;
  1575. u32 offset = 0;
  1576. u32 bcnt;
  1577. u32 size = skb->len-skb->data_len;
  1578. u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1579. u32 empty_slots;
  1580. struct ring_desc_ex* put_tx;
  1581. struct ring_desc_ex* start_tx;
  1582. struct ring_desc_ex* prev_tx;
  1583. struct nv_skb_map* prev_tx_ctx;
  1584. /* add fragments to entries count */
  1585. for (i = 0; i < fragments; i++) {
  1586. entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
  1587. ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1588. }
  1589. empty_slots = nv_get_empty_tx_slots(np);
  1590. if (unlikely(empty_slots <= entries)) {
  1591. spin_lock_irq(&np->lock);
  1592. netif_stop_queue(dev);
  1593. np->tx_stop = 1;
  1594. spin_unlock_irq(&np->lock);
  1595. return NETDEV_TX_BUSY;
  1596. }
  1597. start_tx = put_tx = np->put_tx.ex;
  1598. /* setup the header buffer */
  1599. do {
  1600. prev_tx = put_tx;
  1601. prev_tx_ctx = np->put_tx_ctx;
  1602. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1603. np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
  1604. PCI_DMA_TODEVICE);
  1605. np->put_tx_ctx->dma_len = bcnt;
  1606. put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
  1607. put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
  1608. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1609. tx_flags = NV_TX2_VALID;
  1610. offset += bcnt;
  1611. size -= bcnt;
  1612. if (unlikely(put_tx++ == np->last_tx.ex))
  1613. put_tx = np->first_tx.ex;
  1614. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  1615. np->put_tx_ctx = np->first_tx_ctx;
  1616. } while (size);
  1617. /* setup the fragments */
  1618. for (i = 0; i < fragments; i++) {
  1619. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1620. u32 size = frag->size;
  1621. offset = 0;
  1622. do {
  1623. prev_tx = put_tx;
  1624. prev_tx_ctx = np->put_tx_ctx;
  1625. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1626. np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
  1627. PCI_DMA_TODEVICE);
  1628. np->put_tx_ctx->dma_len = bcnt;
  1629. put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
  1630. put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
  1631. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1632. offset += bcnt;
  1633. size -= bcnt;
  1634. if (unlikely(put_tx++ == np->last_tx.ex))
  1635. put_tx = np->first_tx.ex;
  1636. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  1637. np->put_tx_ctx = np->first_tx_ctx;
  1638. } while (size);
  1639. }
  1640. /* set last fragment flag */
  1641. prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
  1642. /* save skb in this slot's context area */
  1643. prev_tx_ctx->skb = skb;
  1644. if (skb_is_gso(skb))
  1645. tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
  1646. else
  1647. tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
  1648. NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
  1649. /* vlan tag */
  1650. if (likely(!np->vlangrp)) {
  1651. start_tx->txvlan = 0;
  1652. } else {
  1653. if (vlan_tx_tag_present(skb))
  1654. start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
  1655. else
  1656. start_tx->txvlan = 0;
  1657. }
  1658. spin_lock_irq(&np->lock);
  1659. /* set tx flags */
  1660. start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
  1661. np->put_tx.ex = put_tx;
  1662. spin_unlock_irq(&np->lock);
  1663. dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
  1664. dev->name, entries, tx_flags_extra);
  1665. {
  1666. int j;
  1667. for (j=0; j<64; j++) {
  1668. if ((j%16) == 0)
  1669. dprintk("\n%03x:", j);
  1670. dprintk(" %02x", ((unsigned char*)skb->data)[j]);
  1671. }
  1672. dprintk("\n");
  1673. }
  1674. dev->trans_start = jiffies;
  1675. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  1676. return NETDEV_TX_OK;
  1677. }
  1678. /*
  1679. * nv_tx_done: check for completed packets, release the skbs.
  1680. *
  1681. * Caller must own np->lock.
  1682. */
  1683. static void nv_tx_done(struct net_device *dev)
  1684. {
  1685. struct fe_priv *np = netdev_priv(dev);
  1686. u32 flags;
  1687. struct ring_desc* orig_get_tx = np->get_tx.orig;
  1688. while ((np->get_tx.orig != np->put_tx.orig) &&
  1689. !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
  1690. dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
  1691. dev->name, flags);
  1692. pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
  1693. np->get_tx_ctx->dma_len,
  1694. PCI_DMA_TODEVICE);
  1695. np->get_tx_ctx->dma = 0;
  1696. if (np->desc_ver == DESC_VER_1) {
  1697. if (flags & NV_TX_LASTPACKET) {
  1698. if (flags & NV_TX_ERROR) {
  1699. if (flags & NV_TX_UNDERFLOW)
  1700. np->stats.tx_fifo_errors++;
  1701. if (flags & NV_TX_CARRIERLOST)
  1702. np->stats.tx_carrier_errors++;
  1703. np->stats.tx_errors++;
  1704. } else {
  1705. np->stats.tx_packets++;
  1706. np->stats.tx_bytes += np->get_tx_ctx->skb->len;
  1707. }
  1708. dev_kfree_skb_any(np->get_tx_ctx->skb);
  1709. np->get_tx_ctx->skb = NULL;
  1710. }
  1711. } else {
  1712. if (flags & NV_TX2_LASTPACKET) {
  1713. if (flags & NV_TX2_ERROR) {
  1714. if (flags & NV_TX2_UNDERFLOW)
  1715. np->stats.tx_fifo_errors++;
  1716. if (flags & NV_TX2_CARRIERLOST)
  1717. np->stats.tx_carrier_errors++;
  1718. np->stats.tx_errors++;
  1719. } else {
  1720. np->stats.tx_packets++;
  1721. np->stats.tx_bytes += np->get_tx_ctx->skb->len;
  1722. }
  1723. dev_kfree_skb_any(np->get_tx_ctx->skb);
  1724. np->get_tx_ctx->skb = NULL;
  1725. }
  1726. }
  1727. if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
  1728. np->get_tx.orig = np->first_tx.orig;
  1729. if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
  1730. np->get_tx_ctx = np->first_tx_ctx;
  1731. }
  1732. if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
  1733. np->tx_stop = 0;
  1734. netif_wake_queue(dev);
  1735. }
  1736. }
  1737. static void nv_tx_done_optimized(struct net_device *dev, int limit)
  1738. {
  1739. struct fe_priv *np = netdev_priv(dev);
  1740. u32 flags;
  1741. struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
  1742. while ((np->get_tx.ex != np->put_tx.ex) &&
  1743. !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
  1744. (limit-- > 0)) {
  1745. dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
  1746. dev->name, flags);
  1747. pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
  1748. np->get_tx_ctx->dma_len,
  1749. PCI_DMA_TODEVICE);
  1750. np->get_tx_ctx->dma = 0;
  1751. if (flags & NV_TX2_LASTPACKET) {
  1752. if (!(flags & NV_TX2_ERROR))
  1753. np->stats.tx_packets++;
  1754. dev_kfree_skb_any(np->get_tx_ctx->skb);
  1755. np->get_tx_ctx->skb = NULL;
  1756. }
  1757. if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
  1758. np->get_tx.ex = np->first_tx.ex;
  1759. if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
  1760. np->get_tx_ctx = np->first_tx_ctx;
  1761. }
  1762. if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
  1763. np->tx_stop = 0;
  1764. netif_wake_queue(dev);
  1765. }
  1766. }
  1767. /*
  1768. * nv_tx_timeout: dev->tx_timeout function
  1769. * Called with netif_tx_lock held.
  1770. */
  1771. static void nv_tx_timeout(struct net_device *dev)
  1772. {
  1773. struct fe_priv *np = netdev_priv(dev);
  1774. u8 __iomem *base = get_hwbase(dev);
  1775. u32 status;
  1776. if (np->msi_flags & NV_MSI_X_ENABLED)
  1777. status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
  1778. else
  1779. status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  1780. printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
  1781. {
  1782. int i;
  1783. printk(KERN_INFO "%s: Ring at %lx\n",
  1784. dev->name, (unsigned long)np->ring_addr);
  1785. printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
  1786. for (i=0;i<=np->register_size;i+= 32) {
  1787. printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
  1788. i,
  1789. readl(base + i + 0), readl(base + i + 4),
  1790. readl(base + i + 8), readl(base + i + 12),
  1791. readl(base + i + 16), readl(base + i + 20),
  1792. readl(base + i + 24), readl(base + i + 28));
  1793. }
  1794. printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
  1795. for (i=0;i<np->tx_ring_size;i+= 4) {
  1796. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  1797. printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
  1798. i,
  1799. le32_to_cpu(np->tx_ring.orig[i].buf),
  1800. le32_to_cpu(np->tx_ring.orig[i].flaglen),
  1801. le32_to_cpu(np->tx_ring.orig[i+1].buf),
  1802. le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
  1803. le32_to_cpu(np->tx_ring.orig[i+2].buf),
  1804. le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
  1805. le32_to_cpu(np->tx_ring.orig[i+3].buf),
  1806. le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
  1807. } else {
  1808. printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
  1809. i,
  1810. le32_to_cpu(np->tx_ring.ex[i].bufhigh),
  1811. le32_to_cpu(np->tx_ring.ex[i].buflow),
  1812. le32_to_cpu(np->tx_ring.ex[i].flaglen),
  1813. le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
  1814. le32_to_cpu(np->tx_ring.ex[i+1].buflow),
  1815. le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
  1816. le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
  1817. le32_to_cpu(np->tx_ring.ex[i+2].buflow),
  1818. le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
  1819. le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
  1820. le32_to_cpu(np->tx_ring.ex[i+3].buflow),
  1821. le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
  1822. }
  1823. }
  1824. }
  1825. spin_lock_irq(&np->lock);
  1826. /* 1) stop tx engine */
  1827. nv_stop_tx(dev);
  1828. /* 2) check that the packets were not sent already: */
  1829. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
  1830. nv_tx_done(dev);
  1831. else
  1832. nv_tx_done_optimized(dev, np->tx_ring_size);
  1833. /* 3) if there are dead entries: clear everything */
  1834. if (np->get_tx_ctx != np->put_tx_ctx) {
  1835. printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
  1836. nv_drain_tx(dev);
  1837. nv_init_tx(dev);
  1838. setup_hw_rings(dev, NV_SETUP_TX_RING);
  1839. }
  1840. netif_wake_queue(dev);
  1841. /* 4) restart tx engine */
  1842. nv_start_tx(dev);
  1843. spin_unlock_irq(&np->lock);
  1844. }
  1845. /*
  1846. * Called when the nic notices a mismatch between the actual data len on the
  1847. * wire and the len indicated in the 802 header
  1848. */
  1849. static int nv_getlen(struct net_device *dev, void *packet, int datalen)
  1850. {
  1851. int hdrlen; /* length of the 802 header */
  1852. int protolen; /* length as stored in the proto field */
  1853. /* 1) calculate len according to header */
  1854. if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
  1855. protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
  1856. hdrlen = VLAN_HLEN;
  1857. } else {
  1858. protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
  1859. hdrlen = ETH_HLEN;
  1860. }
  1861. dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
  1862. dev->name, datalen, protolen, hdrlen);
  1863. if (protolen > ETH_DATA_LEN)
  1864. return datalen; /* Value in proto field not a len, no checks possible */
  1865. protolen += hdrlen;
  1866. /* consistency checks: */
  1867. if (datalen > ETH_ZLEN) {
  1868. if (datalen >= protolen) {
  1869. /* more data on wire than in 802 header, trim of
  1870. * additional data.
  1871. */
  1872. dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
  1873. dev->name, protolen);
  1874. return protolen;
  1875. } else {
  1876. /* less data on wire than mentioned in header.
  1877. * Discard the packet.
  1878. */
  1879. dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
  1880. dev->name);
  1881. return -1;
  1882. }
  1883. } else {
  1884. /* short packet. Accept only if 802 values are also short */
  1885. if (protolen > ETH_ZLEN) {
  1886. dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
  1887. dev->name);
  1888. return -1;
  1889. }
  1890. dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
  1891. dev->name, datalen);
  1892. return datalen;
  1893. }
  1894. }
  1895. static int nv_rx_process(struct net_device *dev, int limit)
  1896. {
  1897. struct fe_priv *np = netdev_priv(dev);
  1898. u32 flags;
  1899. u32 rx_processed_cnt = 0;
  1900. struct sk_buff *skb;
  1901. int len;
  1902. while((np->get_rx.orig != np->put_rx.orig) &&
  1903. !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
  1904. (rx_processed_cnt++ < limit)) {
  1905. dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
  1906. dev->name, flags);
  1907. /*
  1908. * the packet is for us - immediately tear down the pci mapping.
  1909. * TODO: check if a prefetch of the first cacheline improves
  1910. * the performance.
  1911. */
  1912. pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
  1913. np->get_rx_ctx->dma_len,
  1914. PCI_DMA_FROMDEVICE);
  1915. skb = np->get_rx_ctx->skb;
  1916. np->get_rx_ctx->skb = NULL;
  1917. {
  1918. int j;
  1919. dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
  1920. for (j=0; j<64; j++) {
  1921. if ((j%16) == 0)
  1922. dprintk("\n%03x:", j);
  1923. dprintk(" %02x", ((unsigned char*)skb->data)[j]);
  1924. }
  1925. dprintk("\n");
  1926. }
  1927. /* look at what we actually got: */
  1928. if (np->desc_ver == DESC_VER_1) {
  1929. if (likely(flags & NV_RX_DESCRIPTORVALID)) {
  1930. len = flags & LEN_MASK_V1;
  1931. if (unlikely(flags & NV_RX_ERROR)) {
  1932. if (flags & NV_RX_ERROR4) {
  1933. len = nv_getlen(dev, skb->data, len);
  1934. if (len < 0) {
  1935. np->stats.rx_errors++;
  1936. dev_kfree_skb(skb);
  1937. goto next_pkt;
  1938. }
  1939. }
  1940. /* framing errors are soft errors */
  1941. else if (flags & NV_RX_FRAMINGERR) {
  1942. if (flags & NV_RX_SUBSTRACT1) {
  1943. len--;
  1944. }
  1945. }
  1946. /* the rest are hard errors */
  1947. else {
  1948. if (flags & NV_RX_MISSEDFRAME)
  1949. np->stats.rx_missed_errors++;
  1950. if (flags & NV_RX_CRCERR)
  1951. np->stats.rx_crc_errors++;
  1952. if (flags & NV_RX_OVERFLOW)
  1953. np->stats.rx_over_errors++;
  1954. np->stats.rx_errors++;
  1955. dev_kfree_skb(skb);
  1956. goto next_pkt;
  1957. }
  1958. }
  1959. } else {
  1960. dev_kfree_skb(skb);
  1961. goto next_pkt;
  1962. }
  1963. } else {
  1964. if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
  1965. len = flags & LEN_MASK_V2;
  1966. if (unlikely(flags & NV_RX2_ERROR)) {
  1967. if (flags & NV_RX2_ERROR4) {
  1968. len = nv_getlen(dev, skb->data, len);
  1969. if (len < 0) {
  1970. np->stats.rx_errors++;
  1971. dev_kfree_skb(skb);
  1972. goto next_pkt;
  1973. }
  1974. }
  1975. /* framing errors are soft errors */
  1976. else if (flags & NV_RX2_FRAMINGERR) {
  1977. if (flags & NV_RX2_SUBSTRACT1) {
  1978. len--;
  1979. }
  1980. }
  1981. /* the rest are hard errors */
  1982. else {
  1983. if (flags & NV_RX2_CRCERR)
  1984. np->stats.rx_crc_errors++;
  1985. if (flags & NV_RX2_OVERFLOW)
  1986. np->stats.rx_over_errors++;
  1987. np->stats.rx_errors++;
  1988. dev_kfree_skb(skb);
  1989. goto next_pkt;
  1990. }
  1991. }
  1992. if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
  1993. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1994. } else {
  1995. if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
  1996. (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
  1997. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1998. }
  1999. }
  2000. } else {
  2001. dev_kfree_skb(skb);
  2002. goto next_pkt;
  2003. }
  2004. }
  2005. /* got a valid packet - forward it to the network core */
  2006. skb_put(skb, len);
  2007. skb->protocol = eth_type_trans(skb, dev);
  2008. dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
  2009. dev->name, len, skb->protocol);
  2010. #ifdef CONFIG_FORCEDETH_NAPI
  2011. netif_receive_skb(skb);
  2012. #else
  2013. netif_rx(skb);
  2014. #endif
  2015. dev->last_rx = jiffies;
  2016. np->stats.rx_packets++;
  2017. np->stats.rx_bytes += len;
  2018. next_pkt:
  2019. if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
  2020. np->get_rx.orig = np->first_rx.orig;
  2021. if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
  2022. np->get_rx_ctx = np->first_rx_ctx;
  2023. }
  2024. return rx_processed_cnt;
  2025. }
  2026. static int nv_rx_process_optimized(struct net_device *dev, int limit)
  2027. {
  2028. struct fe_priv *np = netdev_priv(dev);
  2029. u32 flags;
  2030. u32 vlanflags = 0;
  2031. u32 rx_processed_cnt = 0;
  2032. struct sk_buff *skb;
  2033. int len;
  2034. while((np->get_rx.ex != np->put_rx.ex) &&
  2035. !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
  2036. (rx_processed_cnt++ < limit)) {
  2037. dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
  2038. dev->name, flags);
  2039. /*
  2040. * the packet is for us - immediately tear down the pci mapping.
  2041. * TODO: check if a prefetch of the first cacheline improves
  2042. * the performance.
  2043. */
  2044. pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
  2045. np->get_rx_ctx->dma_len,
  2046. PCI_DMA_FROMDEVICE);
  2047. skb = np->get_rx_ctx->skb;
  2048. np->get_rx_ctx->skb = NULL;
  2049. {
  2050. int j;
  2051. dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
  2052. for (j=0; j<64; j++) {
  2053. if ((j%16) == 0)
  2054. dprintk("\n%03x:", j);
  2055. dprintk(" %02x", ((unsigned char*)skb->data)[j]);
  2056. }
  2057. dprintk("\n");
  2058. }
  2059. /* look at what we actually got: */
  2060. if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
  2061. len = flags & LEN_MASK_V2;
  2062. if (unlikely(flags & NV_RX2_ERROR)) {
  2063. if (flags & NV_RX2_ERROR4) {
  2064. len = nv_getlen(dev, skb->data, len);
  2065. if (len < 0) {
  2066. dev_kfree_skb(skb);
  2067. goto next_pkt;
  2068. }
  2069. }
  2070. /* framing errors are soft errors */
  2071. else if (flags & NV_RX2_FRAMINGERR) {
  2072. if (flags & NV_RX2_SUBSTRACT1) {
  2073. len--;
  2074. }
  2075. }
  2076. /* the rest are hard errors */
  2077. else {
  2078. dev_kfree_skb(skb);
  2079. goto next_pkt;
  2080. }
  2081. }
  2082. if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
  2083. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2084. } else {
  2085. if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
  2086. (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
  2087. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2088. }
  2089. }
  2090. /* got a valid packet - forward it to the network core */
  2091. skb_put(skb, len);
  2092. skb->protocol = eth_type_trans(skb, dev);
  2093. prefetch(skb->data);
  2094. dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
  2095. dev->name, len, skb->protocol);
  2096. if (likely(!np->vlangrp)) {
  2097. #ifdef CONFIG_FORCEDETH_NAPI
  2098. netif_receive_skb(skb);
  2099. #else
  2100. netif_rx(skb);
  2101. #endif
  2102. } else {
  2103. vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
  2104. if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
  2105. #ifdef CONFIG_FORCEDETH_NAPI
  2106. vlan_hwaccel_receive_skb(skb, np->vlangrp,
  2107. vlanflags & NV_RX3_VLAN_TAG_MASK);
  2108. #else
  2109. vlan_hwaccel_rx(skb, np->vlangrp,
  2110. vlanflags & NV_RX3_VLAN_TAG_MASK);
  2111. #endif
  2112. } else {
  2113. #ifdef CONFIG_FORCEDETH_NAPI
  2114. netif_receive_skb(skb);
  2115. #else
  2116. netif_rx(skb);
  2117. #endif
  2118. }
  2119. }
  2120. dev->last_rx = jiffies;
  2121. np->stats.rx_packets++;
  2122. np->stats.rx_bytes += len;
  2123. } else {
  2124. dev_kfree_skb(skb);
  2125. }
  2126. next_pkt:
  2127. if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
  2128. np->get_rx.ex = np->first_rx.ex;
  2129. if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
  2130. np->get_rx_ctx = np->first_rx_ctx;
  2131. }
  2132. return rx_processed_cnt;
  2133. }
  2134. static void set_bufsize(struct net_device *dev)
  2135. {
  2136. struct fe_priv *np = netdev_priv(dev);
  2137. if (dev->mtu <= ETH_DATA_LEN)
  2138. np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
  2139. else
  2140. np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
  2141. }
  2142. /*
  2143. * nv_change_mtu: dev->change_mtu function
  2144. * Called with dev_base_lock held for read.
  2145. */
  2146. static int nv_change_mtu(struct net_device *dev, int new_mtu)
  2147. {
  2148. struct fe_priv *np = netdev_priv(dev);
  2149. int old_mtu;
  2150. if (new_mtu < 64 || new_mtu > np->pkt_limit)
  2151. return -EINVAL;
  2152. old_mtu = dev->mtu;
  2153. dev->mtu = new_mtu;
  2154. /* return early if the buffer sizes will not change */
  2155. if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
  2156. return 0;
  2157. if (old_mtu == new_mtu)
  2158. return 0;
  2159. /* synchronized against open : rtnl_lock() held by caller */
  2160. if (netif_running(dev)) {
  2161. u8 __iomem *base = get_hwbase(dev);
  2162. /*
  2163. * It seems that the nic preloads valid ring entries into an
  2164. * internal buffer. The procedure for flushing everything is
  2165. * guessed, there is probably a simpler approach.
  2166. * Changing the MTU is a rare event, it shouldn't matter.
  2167. */
  2168. nv_disable_irq(dev);
  2169. netif_tx_lock_bh(dev);
  2170. spin_lock(&np->lock);
  2171. /* stop engines */
  2172. nv_stop_rx(dev);
  2173. nv_stop_tx(dev);
  2174. nv_txrx_reset(dev);
  2175. /* drain rx queue */
  2176. nv_drain_rx(dev);
  2177. nv_drain_tx(dev);
  2178. /* reinit driver view of the rx queue */
  2179. set_bufsize(dev);
  2180. if (nv_init_ring(dev)) {
  2181. if (!np->in_shutdown)
  2182. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  2183. }
  2184. /* reinit nic view of the rx queue */
  2185. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  2186. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  2187. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  2188. base + NvRegRingSizes);
  2189. pci_push(base);
  2190. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  2191. pci_push(base);
  2192. /* restart rx engine */
  2193. nv_start_rx(dev);
  2194. nv_start_tx(dev);
  2195. spin_unlock(&np->lock);
  2196. netif_tx_unlock_bh(dev);
  2197. nv_enable_irq(dev);
  2198. }
  2199. return 0;
  2200. }
  2201. static void nv_copy_mac_to_hw(struct net_device *dev)
  2202. {
  2203. u8 __iomem *base = get_hwbase(dev);
  2204. u32 mac[2];
  2205. mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
  2206. (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
  2207. mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
  2208. writel(mac[0], base + NvRegMacAddrA);
  2209. writel(mac[1], base + NvRegMacAddrB);
  2210. }
  2211. /*
  2212. * nv_set_mac_address: dev->set_mac_address function
  2213. * Called with rtnl_lock() held.
  2214. */
  2215. static int nv_set_mac_address(struct net_device *dev, void *addr)
  2216. {
  2217. struct fe_priv *np = netdev_priv(dev);
  2218. struct sockaddr *macaddr = (struct sockaddr*)addr;
  2219. if (!is_valid_ether_addr(macaddr->sa_data))
  2220. return -EADDRNOTAVAIL;
  2221. /* synchronized against open : rtnl_lock() held by caller */
  2222. memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
  2223. if (netif_running(dev)) {
  2224. netif_tx_lock_bh(dev);
  2225. spin_lock_irq(&np->lock);
  2226. /* stop rx engine */
  2227. nv_stop_rx(dev);
  2228. /* set mac address */
  2229. nv_copy_mac_to_hw(dev);
  2230. /* restart rx engine */
  2231. nv_start_rx(dev);
  2232. spin_unlock_irq(&np->lock);
  2233. netif_tx_unlock_bh(dev);
  2234. } else {
  2235. nv_copy_mac_to_hw(dev);
  2236. }
  2237. return 0;
  2238. }
  2239. /*
  2240. * nv_set_multicast: dev->set_multicast function
  2241. * Called with netif_tx_lock held.
  2242. */
  2243. static void nv_set_multicast(struct net_device *dev)
  2244. {
  2245. struct fe_priv *np = netdev_priv(dev);
  2246. u8 __iomem *base = get_hwbase(dev);
  2247. u32 addr[2];
  2248. u32 mask[2];
  2249. u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
  2250. memset(addr, 0, sizeof(addr));
  2251. memset(mask, 0, sizeof(mask));
  2252. if (dev->flags & IFF_PROMISC) {
  2253. pff |= NVREG_PFF_PROMISC;
  2254. } else {
  2255. pff |= NVREG_PFF_MYADDR;
  2256. if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
  2257. u32 alwaysOff[2];
  2258. u32 alwaysOn[2];
  2259. alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
  2260. if (dev->flags & IFF_ALLMULTI) {
  2261. alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
  2262. } else {
  2263. struct dev_mc_list *walk;
  2264. walk = dev->mc_list;
  2265. while (walk != NULL) {
  2266. u32 a, b;
  2267. a = le32_to_cpu(*(u32 *) walk->dmi_addr);
  2268. b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
  2269. alwaysOn[0] &= a;
  2270. alwaysOff[0] &= ~a;
  2271. alwaysOn[1] &= b;
  2272. alwaysOff[1] &= ~b;
  2273. walk = walk->next;
  2274. }
  2275. }
  2276. addr[0] = alwaysOn[0];
  2277. addr[1] = alwaysOn[1];
  2278. mask[0] = alwaysOn[0] | alwaysOff[0];
  2279. mask[1] = alwaysOn[1] | alwaysOff[1];
  2280. }
  2281. }
  2282. addr[0] |= NVREG_MCASTADDRA_FORCE;
  2283. pff |= NVREG_PFF_ALWAYS;
  2284. spin_lock_irq(&np->lock);
  2285. nv_stop_rx(dev);
  2286. writel(addr[0], base + NvRegMulticastAddrA);
  2287. writel(addr[1], base + NvRegMulticastAddrB);
  2288. writel(mask[0], base + NvRegMulticastMaskA);
  2289. writel(mask[1], base + NvRegMulticastMaskB);
  2290. writel(pff, base + NvRegPacketFilterFlags);
  2291. dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
  2292. dev->name);
  2293. nv_start_rx(dev);
  2294. spin_unlock_irq(&np->lock);
  2295. }
  2296. static void nv_update_pause(struct net_device *dev, u32 pause_flags)
  2297. {
  2298. struct fe_priv *np = netdev_priv(dev);
  2299. u8 __iomem *base = get_hwbase(dev);
  2300. np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
  2301. if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
  2302. u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
  2303. if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
  2304. writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
  2305. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2306. } else {
  2307. writel(pff, base + NvRegPacketFilterFlags);
  2308. }
  2309. }
  2310. if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
  2311. u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
  2312. if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
  2313. writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
  2314. writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
  2315. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2316. } else {
  2317. writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
  2318. writel(regmisc, base + NvRegMisc1);
  2319. }
  2320. }
  2321. }
  2322. /**
  2323. * nv_update_linkspeed: Setup the MAC according to the link partner
  2324. * @dev: Network device to be configured
  2325. *
  2326. * The function queries the PHY and checks if there is a link partner.
  2327. * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
  2328. * set to 10 MBit HD.
  2329. *
  2330. * The function returns 0 if there is no link partner and 1 if there is
  2331. * a good link partner.
  2332. */
  2333. static int nv_update_linkspeed(struct net_device *dev)
  2334. {
  2335. struct fe_priv *np = netdev_priv(dev);
  2336. u8 __iomem *base = get_hwbase(dev);
  2337. int adv = 0;
  2338. int lpa = 0;
  2339. int adv_lpa, adv_pause, lpa_pause;
  2340. int newls = np->linkspeed;
  2341. int newdup = np->duplex;
  2342. int mii_status;
  2343. int retval = 0;
  2344. u32 control_1000, status_1000, phyreg, pause_flags, txreg;
  2345. /* BMSR_LSTATUS is latched, read it twice:
  2346. * we want the current value.
  2347. */
  2348. mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  2349. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  2350. if (!(mii_status & BMSR_LSTATUS)) {
  2351. dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
  2352. dev->name);
  2353. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2354. newdup = 0;
  2355. retval = 0;
  2356. goto set_speed;
  2357. }
  2358. if (np->autoneg == 0) {
  2359. dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
  2360. dev->name, np->fixed_mode);
  2361. if (np->fixed_mode & LPA_100FULL) {
  2362. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2363. newdup = 1;
  2364. } else if (np->fixed_mode & LPA_100HALF) {
  2365. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2366. newdup = 0;
  2367. } else if (np->fixed_mode & LPA_10FULL) {
  2368. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2369. newdup = 1;
  2370. } else {
  2371. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2372. newdup = 0;
  2373. }
  2374. retval = 1;
  2375. goto set_speed;
  2376. }
  2377. /* check auto negotiation is complete */
  2378. if (!(mii_status & BMSR_ANEGCOMPLETE)) {
  2379. /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
  2380. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2381. newdup = 0;
  2382. retval = 0;
  2383. dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
  2384. goto set_speed;
  2385. }
  2386. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  2387. lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
  2388. dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
  2389. dev->name, adv, lpa);
  2390. retval = 1;
  2391. if (np->gigabit == PHY_GIGABIT) {
  2392. control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  2393. status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
  2394. if ((control_1000 & ADVERTISE_1000FULL) &&
  2395. (status_1000 & LPA_1000FULL)) {
  2396. dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
  2397. dev->name);
  2398. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
  2399. newdup = 1;
  2400. goto set_speed;
  2401. }
  2402. }
  2403. /* FIXME: handle parallel detection properly */
  2404. adv_lpa = lpa & adv;
  2405. if (adv_lpa & LPA_100FULL) {
  2406. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2407. newdup = 1;
  2408. } else if (adv_lpa & LPA_100HALF) {
  2409. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2410. newdup = 0;
  2411. } else if (adv_lpa & LPA_10FULL) {
  2412. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2413. newdup = 1;
  2414. } else if (adv_lpa & LPA_10HALF) {
  2415. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2416. newdup = 0;
  2417. } else {
  2418. dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
  2419. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2420. newdup = 0;
  2421. }
  2422. set_speed:
  2423. if (np->duplex == newdup && np->linkspeed == newls)
  2424. return retval;
  2425. dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
  2426. dev->name, np->linkspeed, np->duplex, newls, newdup);
  2427. np->duplex = newdup;
  2428. np->linkspeed = newls;
  2429. if (np->gigabit == PHY_GIGABIT) {
  2430. phyreg = readl(base + NvRegRandomSeed);
  2431. phyreg &= ~(0x3FF00);
  2432. if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
  2433. phyreg |= NVREG_RNDSEED_FORCE3;
  2434. else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
  2435. phyreg |= NVREG_RNDSEED_FORCE2;
  2436. else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
  2437. phyreg |= NVREG_RNDSEED_FORCE;
  2438. writel(phyreg, base + NvRegRandomSeed);
  2439. }
  2440. phyreg = readl(base + NvRegPhyInterface);
  2441. phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
  2442. if (np->duplex == 0)
  2443. phyreg |= PHY_HALF;
  2444. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
  2445. phyreg |= PHY_100;
  2446. else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
  2447. phyreg |= PHY_1000;
  2448. writel(phyreg, base + NvRegPhyInterface);
  2449. if (phyreg & PHY_RGMII) {
  2450. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
  2451. txreg = NVREG_TX_DEFERRAL_RGMII_1000;
  2452. else
  2453. txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
  2454. } else {
  2455. txreg = NVREG_TX_DEFERRAL_DEFAULT;
  2456. }
  2457. writel(txreg, base + NvRegTxDeferral);
  2458. if (np->desc_ver == DESC_VER_1) {
  2459. txreg = NVREG_TX_WM_DESC1_DEFAULT;
  2460. } else {
  2461. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
  2462. txreg = NVREG_TX_WM_DESC2_3_1000;
  2463. else
  2464. txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
  2465. }
  2466. writel(txreg, base + NvRegTxWatermark);
  2467. writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
  2468. base + NvRegMisc1);
  2469. pci_push(base);
  2470. writel(np->linkspeed, base + NvRegLinkSpeed);
  2471. pci_push(base);
  2472. pause_flags = 0;
  2473. /* setup pause frame */
  2474. if (np->duplex != 0) {
  2475. if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
  2476. adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
  2477. lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
  2478. switch (adv_pause) {
  2479. case ADVERTISE_PAUSE_CAP:
  2480. if (lpa_pause & LPA_PAUSE_CAP) {
  2481. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2482. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  2483. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2484. }
  2485. break;
  2486. case ADVERTISE_PAUSE_ASYM:
  2487. if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
  2488. {
  2489. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2490. }
  2491. break;
  2492. case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
  2493. if (lpa_pause & LPA_PAUSE_CAP)
  2494. {
  2495. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2496. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  2497. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2498. }
  2499. if (lpa_pause == LPA_PAUSE_ASYM)
  2500. {
  2501. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2502. }
  2503. break;
  2504. }
  2505. } else {
  2506. pause_flags = np->pause_flags;
  2507. }
  2508. }
  2509. nv_update_pause(dev, pause_flags);
  2510. return retval;
  2511. }
  2512. static void nv_linkchange(struct net_device *dev)
  2513. {
  2514. if (nv_update_linkspeed(dev)) {
  2515. if (!netif_carrier_ok(dev)) {
  2516. netif_carrier_on(dev);
  2517. printk(KERN_INFO "%s: link up.\n", dev->name);
  2518. nv_start_rx(dev);
  2519. }
  2520. } else {
  2521. if (netif_carrier_ok(dev)) {
  2522. netif_carrier_off(dev);
  2523. printk(KERN_INFO "%s: link down.\n", dev->name);
  2524. nv_stop_rx(dev);
  2525. }
  2526. }
  2527. }
  2528. static void nv_link_irq(struct net_device *dev)
  2529. {
  2530. u8 __iomem *base = get_hwbase(dev);
  2531. u32 miistat;
  2532. miistat = readl(base + NvRegMIIStatus);
  2533. writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
  2534. dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
  2535. if (miistat & (NVREG_MIISTAT_LINKCHANGE))
  2536. nv_linkchange(dev);
  2537. dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
  2538. }
  2539. static irqreturn_t nv_nic_irq(int foo, void *data)
  2540. {
  2541. struct net_device *dev = (struct net_device *) data;
  2542. struct fe_priv *np = netdev_priv(dev);
  2543. u8 __iomem *base = get_hwbase(dev);
  2544. u32 events;
  2545. int i;
  2546. dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
  2547. for (i=0; ; i++) {
  2548. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  2549. events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  2550. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  2551. } else {
  2552. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
  2553. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  2554. }
  2555. dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
  2556. if (!(events & np->irqmask))
  2557. break;
  2558. spin_lock(&np->lock);
  2559. nv_tx_done(dev);
  2560. spin_unlock(&np->lock);
  2561. #ifdef CONFIG_FORCEDETH_NAPI
  2562. if (events & NVREG_IRQ_RX_ALL) {
  2563. netif_rx_schedule(dev);
  2564. /* Disable furthur receive irq's */
  2565. spin_lock(&np->lock);
  2566. np->irqmask &= ~NVREG_IRQ_RX_ALL;
  2567. if (np->msi_flags & NV_MSI_X_ENABLED)
  2568. writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
  2569. else
  2570. writel(np->irqmask, base + NvRegIrqMask);
  2571. spin_unlock(&np->lock);
  2572. }
  2573. #else
  2574. if (nv_rx_process(dev, dev->weight)) {
  2575. if (unlikely(nv_alloc_rx(dev))) {
  2576. spin_lock(&np->lock);
  2577. if (!np->in_shutdown)
  2578. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  2579. spin_unlock(&np->lock);
  2580. }
  2581. }
  2582. #endif
  2583. if (unlikely(events & NVREG_IRQ_LINK)) {
  2584. spin_lock(&np->lock);
  2585. nv_link_irq(dev);
  2586. spin_unlock(&np->lock);
  2587. }
  2588. if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
  2589. spin_lock(&np->lock);
  2590. nv_linkchange(dev);
  2591. spin_unlock(&np->lock);
  2592. np->link_timeout = jiffies + LINK_TIMEOUT;
  2593. }
  2594. if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
  2595. dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
  2596. dev->name, events);
  2597. }
  2598. if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
  2599. printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
  2600. dev->name, events);
  2601. }
  2602. if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
  2603. spin_lock(&np->lock);
  2604. /* disable interrupts on the nic */
  2605. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  2606. writel(0, base + NvRegIrqMask);
  2607. else
  2608. writel(np->irqmask, base + NvRegIrqMask);
  2609. pci_push(base);
  2610. if (!np->in_shutdown) {
  2611. np->nic_poll_irq = np->irqmask;
  2612. np->recover_error = 1;
  2613. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  2614. }
  2615. spin_unlock(&np->lock);
  2616. break;
  2617. }
  2618. if (unlikely(i > max_interrupt_work)) {
  2619. spin_lock(&np->lock);
  2620. /* disable interrupts on the nic */
  2621. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  2622. writel(0, base + NvRegIrqMask);
  2623. else
  2624. writel(np->irqmask, base + NvRegIrqMask);
  2625. pci_push(base);
  2626. if (!np->in_shutdown) {
  2627. np->nic_poll_irq = np->irqmask;
  2628. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  2629. }
  2630. printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
  2631. spin_unlock(&np->lock);
  2632. break;
  2633. }
  2634. }
  2635. dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
  2636. return IRQ_RETVAL(i);
  2637. }
  2638. #define TX_WORK_PER_LOOP 64
  2639. #define RX_WORK_PER_LOOP 64
  2640. /**
  2641. * All _optimized functions are used to help increase performance
  2642. * (reduce CPU and increase throughput). They use descripter version 3,
  2643. * compiler directives, and reduce memory accesses.
  2644. */
  2645. static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
  2646. {
  2647. struct net_device *dev = (struct net_device *) data;
  2648. struct fe_priv *np = netdev_priv(dev);
  2649. u8 __iomem *base = get_hwbase(dev);
  2650. u32 events;
  2651. int i;
  2652. dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
  2653. for (i=0; ; i++) {
  2654. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  2655. events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  2656. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  2657. } else {
  2658. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
  2659. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  2660. }
  2661. dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
  2662. if (!(events & np->irqmask))
  2663. break;
  2664. spin_lock(&np->lock);
  2665. nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
  2666. spin_unlock(&np->lock);
  2667. #ifdef CONFIG_FORCEDETH_NAPI
  2668. if (events & NVREG_IRQ_RX_ALL) {
  2669. netif_rx_schedule(dev);
  2670. /* Disable furthur receive irq's */
  2671. spin_lock(&np->lock);
  2672. np->irqmask &= ~NVREG_IRQ_RX_ALL;
  2673. if (np->msi_flags & NV_MSI_X_ENABLED)
  2674. writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
  2675. else
  2676. writel(np->irqmask, base + NvRegIrqMask);
  2677. spin_unlock(&np->lock);
  2678. }
  2679. #else
  2680. if (nv_rx_process_optimized(dev, dev->weight)) {
  2681. if (unlikely(nv_alloc_rx_optimized(dev))) {
  2682. spin_lock(&np->lock);
  2683. if (!np->in_shutdown)
  2684. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  2685. spin_unlock(&np->lock);
  2686. }
  2687. }
  2688. #endif
  2689. if (unlikely(events & NVREG_IRQ_LINK)) {
  2690. spin_lock(&np->lock);
  2691. nv_link_irq(dev);
  2692. spin_unlock(&np->lock);
  2693. }
  2694. if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
  2695. spin_lock(&np->lock);
  2696. nv_linkchange(dev);
  2697. spin_unlock(&np->lock);
  2698. np->link_timeout = jiffies + LINK_TIMEOUT;
  2699. }
  2700. if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
  2701. dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
  2702. dev->name, events);
  2703. }
  2704. if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
  2705. printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
  2706. dev->name, events);
  2707. }
  2708. if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
  2709. spin_lock(&np->lock);
  2710. /* disable interrupts on the nic */
  2711. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  2712. writel(0, base + NvRegIrqMask);
  2713. else
  2714. writel(np->irqmask, base + NvRegIrqMask);
  2715. pci_push(base);
  2716. if (!np->in_shutdown) {
  2717. np->nic_poll_irq = np->irqmask;
  2718. np->recover_error = 1;
  2719. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  2720. }
  2721. spin_unlock(&np->lock);
  2722. break;
  2723. }
  2724. if (unlikely(i > max_interrupt_work)) {
  2725. spin_lock(&np->lock);
  2726. /* disable interrupts on the nic */
  2727. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  2728. writel(0, base + NvRegIrqMask);
  2729. else
  2730. writel(np->irqmask, base + NvRegIrqMask);
  2731. pci_push(base);
  2732. if (!np->in_shutdown) {
  2733. np->nic_poll_irq = np->irqmask;
  2734. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  2735. }
  2736. printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
  2737. spin_unlock(&np->lock);
  2738. break;
  2739. }
  2740. }
  2741. dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
  2742. return IRQ_RETVAL(i);
  2743. }
  2744. static irqreturn_t nv_nic_irq_tx(int foo, void *data)
  2745. {
  2746. struct net_device *dev = (struct net_device *) data;
  2747. struct fe_priv *np = netdev_priv(dev);
  2748. u8 __iomem *base = get_hwbase(dev);
  2749. u32 events;
  2750. int i;
  2751. unsigned long flags;
  2752. dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
  2753. for (i=0; ; i++) {
  2754. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
  2755. writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
  2756. dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
  2757. if (!(events & np->irqmask))
  2758. break;
  2759. spin_lock_irqsave(&np->lock, flags);
  2760. nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
  2761. spin_unlock_irqrestore(&np->lock, flags);
  2762. if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
  2763. dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
  2764. dev->name, events);
  2765. }
  2766. if (unlikely(i > max_interrupt_work)) {
  2767. spin_lock_irqsave(&np->lock, flags);
  2768. /* disable interrupts on the nic */
  2769. writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
  2770. pci_push(base);
  2771. if (!np->in_shutdown) {
  2772. np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
  2773. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  2774. }
  2775. printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
  2776. spin_unlock_irqrestore(&np->lock, flags);
  2777. break;
  2778. }
  2779. }
  2780. dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
  2781. return IRQ_RETVAL(i);
  2782. }
  2783. #ifdef CONFIG_FORCEDETH_NAPI
  2784. static int nv_napi_poll(struct net_device *dev, int *budget)
  2785. {
  2786. int pkts, limit = min(*budget, dev->quota);
  2787. struct fe_priv *np = netdev_priv(dev);
  2788. u8 __iomem *base = get_hwbase(dev);
  2789. unsigned long flags;
  2790. int retcode;
  2791. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  2792. pkts = nv_rx_process(dev, limit);
  2793. retcode = nv_alloc_rx(dev);
  2794. } else {
  2795. pkts = nv_rx_process_optimized(dev, limit);
  2796. retcode = nv_alloc_rx_optimized(dev);
  2797. }
  2798. if (retcode) {
  2799. spin_lock_irqsave(&np->lock, flags);
  2800. if (!np->in_shutdown)
  2801. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  2802. spin_unlock_irqrestore(&np->lock, flags);
  2803. }
  2804. if (pkts < limit) {
  2805. /* all done, no more packets present */
  2806. netif_rx_complete(dev);
  2807. /* re-enable receive interrupts */
  2808. spin_lock_irqsave(&np->lock, flags);
  2809. np->irqmask |= NVREG_IRQ_RX_ALL;
  2810. if (np->msi_flags & NV_MSI_X_ENABLED)
  2811. writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
  2812. else
  2813. writel(np->irqmask, base + NvRegIrqMask);
  2814. spin_unlock_irqrestore(&np->lock, flags);
  2815. return 0;
  2816. } else {
  2817. /* used up our quantum, so reschedule */
  2818. dev->quota -= pkts;
  2819. *budget -= pkts;
  2820. return 1;
  2821. }
  2822. }
  2823. #endif
  2824. #ifdef CONFIG_FORCEDETH_NAPI
  2825. static irqreturn_t nv_nic_irq_rx(int foo, void *data)
  2826. {
  2827. struct net_device *dev = (struct net_device *) data;
  2828. u8 __iomem *base = get_hwbase(dev);
  2829. u32 events;
  2830. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
  2831. writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
  2832. if (events) {
  2833. netif_rx_schedule(dev);
  2834. /* disable receive interrupts on the nic */
  2835. writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
  2836. pci_push(base);
  2837. }
  2838. return IRQ_HANDLED;
  2839. }
  2840. #else
  2841. static irqreturn_t nv_nic_irq_rx(int foo, void *data)
  2842. {
  2843. struct net_device *dev = (struct net_device *) data;
  2844. struct fe_priv *np = netdev_priv(dev);
  2845. u8 __iomem *base = get_hwbase(dev);
  2846. u32 events;
  2847. int i;
  2848. unsigned long flags;
  2849. dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
  2850. for (i=0; ; i++) {
  2851. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
  2852. writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
  2853. dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
  2854. if (!(events & np->irqmask))
  2855. break;
  2856. if (nv_rx_process_optimized(dev, dev->weight)) {
  2857. if (unlikely(nv_alloc_rx_optimized(dev))) {
  2858. spin_lock_irqsave(&np->lock, flags);
  2859. if (!np->in_shutdown)
  2860. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  2861. spin_unlock_irqrestore(&np->lock, flags);
  2862. }
  2863. }
  2864. if (unlikely(i > max_interrupt_work)) {
  2865. spin_lock_irqsave(&np->lock, flags);
  2866. /* disable interrupts on the nic */
  2867. writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
  2868. pci_push(base);
  2869. if (!np->in_shutdown) {
  2870. np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
  2871. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  2872. }
  2873. printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
  2874. spin_unlock_irqrestore(&np->lock, flags);
  2875. break;
  2876. }
  2877. }
  2878. dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
  2879. return IRQ_RETVAL(i);
  2880. }
  2881. #endif
  2882. static irqreturn_t nv_nic_irq_other(int foo, void *data)
  2883. {
  2884. struct net_device *dev = (struct net_device *) data;
  2885. struct fe_priv *np = netdev_priv(dev);
  2886. u8 __iomem *base = get_hwbase(dev);
  2887. u32 events;
  2888. int i;
  2889. unsigned long flags;
  2890. dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
  2891. for (i=0; ; i++) {
  2892. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
  2893. writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
  2894. dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
  2895. if (!(events & np->irqmask))
  2896. break;
  2897. /* check tx in case we reached max loop limit in tx isr */
  2898. spin_lock_irqsave(&np->lock, flags);
  2899. nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
  2900. spin_unlock_irqrestore(&np->lock, flags);
  2901. if (events & NVREG_IRQ_LINK) {
  2902. spin_lock_irqsave(&np->lock, flags);
  2903. nv_link_irq(dev);
  2904. spin_unlock_irqrestore(&np->lock, flags);
  2905. }
  2906. if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
  2907. spin_lock_irqsave(&np->lock, flags);
  2908. nv_linkchange(dev);
  2909. spin_unlock_irqrestore(&np->lock, flags);
  2910. np->link_timeout = jiffies + LINK_TIMEOUT;
  2911. }
  2912. if (events & NVREG_IRQ_RECOVER_ERROR) {
  2913. spin_lock_irq(&np->lock);
  2914. /* disable interrupts on the nic */
  2915. writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
  2916. pci_push(base);
  2917. if (!np->in_shutdown) {
  2918. np->nic_poll_irq |= NVREG_IRQ_OTHER;
  2919. np->recover_error = 1;
  2920. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  2921. }
  2922. spin_unlock_irq(&np->lock);
  2923. break;
  2924. }
  2925. if (events & (NVREG_IRQ_UNKNOWN)) {
  2926. printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
  2927. dev->name, events);
  2928. }
  2929. if (unlikely(i > max_interrupt_work)) {
  2930. spin_lock_irqsave(&np->lock, flags);
  2931. /* disable interrupts on the nic */
  2932. writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
  2933. pci_push(base);
  2934. if (!np->in_shutdown) {
  2935. np->nic_poll_irq |= NVREG_IRQ_OTHER;
  2936. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  2937. }
  2938. printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
  2939. spin_unlock_irqrestore(&np->lock, flags);
  2940. break;
  2941. }
  2942. }
  2943. dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
  2944. return IRQ_RETVAL(i);
  2945. }
  2946. static irqreturn_t nv_nic_irq_test(int foo, void *data)
  2947. {
  2948. struct net_device *dev = (struct net_device *) data;
  2949. struct fe_priv *np = netdev_priv(dev);
  2950. u8 __iomem *base = get_hwbase(dev);
  2951. u32 events;
  2952. dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
  2953. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  2954. events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  2955. writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
  2956. } else {
  2957. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
  2958. writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
  2959. }
  2960. pci_push(base);
  2961. dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
  2962. if (!(events & NVREG_IRQ_TIMER))
  2963. return IRQ_RETVAL(0);
  2964. spin_lock(&np->lock);
  2965. np->intr_test = 1;
  2966. spin_unlock(&np->lock);
  2967. dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
  2968. return IRQ_RETVAL(1);
  2969. }
  2970. static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
  2971. {
  2972. u8 __iomem *base = get_hwbase(dev);
  2973. int i;
  2974. u32 msixmap = 0;
  2975. /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
  2976. * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
  2977. * the remaining 8 interrupts.
  2978. */
  2979. for (i = 0; i < 8; i++) {
  2980. if ((irqmask >> i) & 0x1) {
  2981. msixmap |= vector << (i << 2);
  2982. }
  2983. }
  2984. writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
  2985. msixmap = 0;
  2986. for (i = 0; i < 8; i++) {
  2987. if ((irqmask >> (i + 8)) & 0x1) {
  2988. msixmap |= vector << (i << 2);
  2989. }
  2990. }
  2991. writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
  2992. }
  2993. static int nv_request_irq(struct net_device *dev, int intr_test)
  2994. {
  2995. struct fe_priv *np = get_nvpriv(dev);
  2996. u8 __iomem *base = get_hwbase(dev);
  2997. int ret = 1;
  2998. int i;
  2999. irqreturn_t (*handler)(int foo, void *data);
  3000. if (intr_test) {
  3001. handler = nv_nic_irq_test;
  3002. } else {
  3003. if (np->desc_ver == DESC_VER_3)
  3004. handler = nv_nic_irq_optimized;
  3005. else
  3006. handler = nv_nic_irq;
  3007. }
  3008. if (np->msi_flags & NV_MSI_X_CAPABLE) {
  3009. for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
  3010. np->msi_x_entry[i].entry = i;
  3011. }
  3012. if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
  3013. np->msi_flags |= NV_MSI_X_ENABLED;
  3014. if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
  3015. /* Request irq for rx handling */
  3016. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
  3017. printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
  3018. pci_disable_msix(np->pci_dev);
  3019. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3020. goto out_err;
  3021. }
  3022. /* Request irq for tx handling */
  3023. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
  3024. printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
  3025. pci_disable_msix(np->pci_dev);
  3026. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3027. goto out_free_rx;
  3028. }
  3029. /* Request irq for link and timer handling */
  3030. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
  3031. printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
  3032. pci_disable_msix(np->pci_dev);
  3033. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3034. goto out_free_tx;
  3035. }
  3036. /* map interrupts to their respective vector */
  3037. writel(0, base + NvRegMSIXMap0);
  3038. writel(0, base + NvRegMSIXMap1);
  3039. set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
  3040. set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
  3041. set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
  3042. } else {
  3043. /* Request irq for all interrupts */
  3044. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
  3045. printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
  3046. pci_disable_msix(np->pci_dev);
  3047. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3048. goto out_err;
  3049. }
  3050. /* map interrupts to vector 0 */
  3051. writel(0, base + NvRegMSIXMap0);
  3052. writel(0, base + NvRegMSIXMap1);
  3053. }
  3054. }
  3055. }
  3056. if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
  3057. if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
  3058. np->msi_flags |= NV_MSI_ENABLED;
  3059. if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
  3060. printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
  3061. pci_disable_msi(np->pci_dev);
  3062. np->msi_flags &= ~NV_MSI_ENABLED;
  3063. goto out_err;
  3064. }
  3065. /* map interrupts to vector 0 */
  3066. writel(0, base + NvRegMSIMap0);
  3067. writel(0, base + NvRegMSIMap1);
  3068. /* enable msi vector 0 */
  3069. writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
  3070. }
  3071. }
  3072. if (ret != 0) {
  3073. if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
  3074. goto out_err;
  3075. }
  3076. return 0;
  3077. out_free_tx:
  3078. free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
  3079. out_free_rx:
  3080. free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
  3081. out_err:
  3082. return 1;
  3083. }
  3084. static void nv_free_irq(struct net_device *dev)
  3085. {
  3086. struct fe_priv *np = get_nvpriv(dev);
  3087. int i;
  3088. if (np->msi_flags & NV_MSI_X_ENABLED) {
  3089. for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
  3090. free_irq(np->msi_x_entry[i].vector, dev);
  3091. }
  3092. pci_disable_msix(np->pci_dev);
  3093. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3094. } else {
  3095. free_irq(np->pci_dev->irq, dev);
  3096. if (np->msi_flags & NV_MSI_ENABLED) {
  3097. pci_disable_msi(np->pci_dev);
  3098. np->msi_flags &= ~NV_MSI_ENABLED;
  3099. }
  3100. }
  3101. }
  3102. static void nv_do_nic_poll(unsigned long data)
  3103. {
  3104. struct net_device *dev = (struct net_device *) data;
  3105. struct fe_priv *np = netdev_priv(dev);
  3106. u8 __iomem *base = get_hwbase(dev);
  3107. u32 mask = 0;
  3108. /*
  3109. * First disable irq(s) and then
  3110. * reenable interrupts on the nic, we have to do this before calling
  3111. * nv_nic_irq because that may decide to do otherwise
  3112. */
  3113. if (!using_multi_irqs(dev)) {
  3114. if (np->msi_flags & NV_MSI_X_ENABLED)
  3115. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  3116. else
  3117. disable_irq_lockdep(dev->irq);
  3118. mask = np->irqmask;
  3119. } else {
  3120. if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
  3121. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  3122. mask |= NVREG_IRQ_RX_ALL;
  3123. }
  3124. if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
  3125. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  3126. mask |= NVREG_IRQ_TX_ALL;
  3127. }
  3128. if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
  3129. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  3130. mask |= NVREG_IRQ_OTHER;
  3131. }
  3132. }
  3133. np->nic_poll_irq = 0;
  3134. if (np->recover_error) {
  3135. np->recover_error = 0;
  3136. printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
  3137. if (netif_running(dev)) {
  3138. netif_tx_lock_bh(dev);
  3139. spin_lock(&np->lock);
  3140. /* stop engines */
  3141. nv_stop_rx(dev);
  3142. nv_stop_tx(dev);
  3143. nv_txrx_reset(dev);
  3144. /* drain rx queue */
  3145. nv_drain_rx(dev);
  3146. nv_drain_tx(dev);
  3147. /* reinit driver view of the rx queue */
  3148. set_bufsize(dev);
  3149. if (nv_init_ring(dev)) {
  3150. if (!np->in_shutdown)
  3151. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3152. }
  3153. /* reinit nic view of the rx queue */
  3154. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  3155. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  3156. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  3157. base + NvRegRingSizes);
  3158. pci_push(base);
  3159. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  3160. pci_push(base);
  3161. /* restart rx engine */
  3162. nv_start_rx(dev);
  3163. nv_start_tx(dev);
  3164. spin_unlock(&np->lock);
  3165. netif_tx_unlock_bh(dev);
  3166. }
  3167. }
  3168. /* FIXME: Do we need synchronize_irq(dev->irq) here? */
  3169. writel(mask, base + NvRegIrqMask);
  3170. pci_push(base);
  3171. if (!using_multi_irqs(dev)) {
  3172. if (np->desc_ver == DESC_VER_3)
  3173. nv_nic_irq_optimized(0, dev);
  3174. else
  3175. nv_nic_irq(0, dev);
  3176. if (np->msi_flags & NV_MSI_X_ENABLED)
  3177. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  3178. else
  3179. enable_irq_lockdep(dev->irq);
  3180. } else {
  3181. if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
  3182. nv_nic_irq_rx(0, dev);
  3183. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  3184. }
  3185. if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
  3186. nv_nic_irq_tx(0, dev);
  3187. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  3188. }
  3189. if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
  3190. nv_nic_irq_other(0, dev);
  3191. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  3192. }
  3193. }
  3194. }
  3195. #ifdef CONFIG_NET_POLL_CONTROLLER
  3196. static void nv_poll_controller(struct net_device *dev)
  3197. {
  3198. nv_do_nic_poll((unsigned long) dev);
  3199. }
  3200. #endif
  3201. static void nv_do_stats_poll(unsigned long data)
  3202. {
  3203. struct net_device *dev = (struct net_device *) data;
  3204. struct fe_priv *np = netdev_priv(dev);
  3205. nv_get_hw_stats(dev);
  3206. if (!np->in_shutdown)
  3207. mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
  3208. }
  3209. static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  3210. {
  3211. struct fe_priv *np = netdev_priv(dev);
  3212. strcpy(info->driver, "forcedeth");
  3213. strcpy(info->version, FORCEDETH_VERSION);
  3214. strcpy(info->bus_info, pci_name(np->pci_dev));
  3215. }
  3216. static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
  3217. {
  3218. struct fe_priv *np = netdev_priv(dev);
  3219. wolinfo->supported = WAKE_MAGIC;
  3220. spin_lock_irq(&np->lock);
  3221. if (np->wolenabled)
  3222. wolinfo->wolopts = WAKE_MAGIC;
  3223. spin_unlock_irq(&np->lock);
  3224. }
  3225. static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
  3226. {
  3227. struct fe_priv *np = netdev_priv(dev);
  3228. u8 __iomem *base = get_hwbase(dev);
  3229. u32 flags = 0;
  3230. if (wolinfo->wolopts == 0) {
  3231. np->wolenabled = 0;
  3232. } else if (wolinfo->wolopts & WAKE_MAGIC) {
  3233. np->wolenabled = 1;
  3234. flags = NVREG_WAKEUPFLAGS_ENABLE;
  3235. }
  3236. if (netif_running(dev)) {
  3237. spin_lock_irq(&np->lock);
  3238. writel(flags, base + NvRegWakeUpFlags);
  3239. spin_unlock_irq(&np->lock);
  3240. }
  3241. return 0;
  3242. }
  3243. static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  3244. {
  3245. struct fe_priv *np = netdev_priv(dev);
  3246. int adv;
  3247. spin_lock_irq(&np->lock);
  3248. ecmd->port = PORT_MII;
  3249. if (!netif_running(dev)) {
  3250. /* We do not track link speed / duplex setting if the
  3251. * interface is disabled. Force a link check */
  3252. if (nv_update_linkspeed(dev)) {
  3253. if (!netif_carrier_ok(dev))
  3254. netif_carrier_on(dev);
  3255. } else {
  3256. if (netif_carrier_ok(dev))
  3257. netif_carrier_off(dev);
  3258. }
  3259. }
  3260. if (netif_carrier_ok(dev)) {
  3261. switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
  3262. case NVREG_LINKSPEED_10:
  3263. ecmd->speed = SPEED_10;
  3264. break;
  3265. case NVREG_LINKSPEED_100:
  3266. ecmd->speed = SPEED_100;
  3267. break;
  3268. case NVREG_LINKSPEED_1000:
  3269. ecmd->speed = SPEED_1000;
  3270. break;
  3271. }
  3272. ecmd->duplex = DUPLEX_HALF;
  3273. if (np->duplex)
  3274. ecmd->duplex = DUPLEX_FULL;
  3275. } else {
  3276. ecmd->speed = -1;
  3277. ecmd->duplex = -1;
  3278. }
  3279. ecmd->autoneg = np->autoneg;
  3280. ecmd->advertising = ADVERTISED_MII;
  3281. if (np->autoneg) {
  3282. ecmd->advertising |= ADVERTISED_Autoneg;
  3283. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3284. if (adv & ADVERTISE_10HALF)
  3285. ecmd->advertising |= ADVERTISED_10baseT_Half;
  3286. if (adv & ADVERTISE_10FULL)
  3287. ecmd->advertising |= ADVERTISED_10baseT_Full;
  3288. if (adv & ADVERTISE_100HALF)
  3289. ecmd->advertising |= ADVERTISED_100baseT_Half;
  3290. if (adv & ADVERTISE_100FULL)
  3291. ecmd->advertising |= ADVERTISED_100baseT_Full;
  3292. if (np->gigabit == PHY_GIGABIT) {
  3293. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3294. if (adv & ADVERTISE_1000FULL)
  3295. ecmd->advertising |= ADVERTISED_1000baseT_Full;
  3296. }
  3297. }
  3298. ecmd->supported = (SUPPORTED_Autoneg |
  3299. SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
  3300. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  3301. SUPPORTED_MII);
  3302. if (np->gigabit == PHY_GIGABIT)
  3303. ecmd->supported |= SUPPORTED_1000baseT_Full;
  3304. ecmd->phy_address = np->phyaddr;
  3305. ecmd->transceiver = XCVR_EXTERNAL;
  3306. /* ignore maxtxpkt, maxrxpkt for now */
  3307. spin_unlock_irq(&np->lock);
  3308. return 0;
  3309. }
  3310. static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  3311. {
  3312. struct fe_priv *np = netdev_priv(dev);
  3313. if (ecmd->port != PORT_MII)
  3314. return -EINVAL;
  3315. if (ecmd->transceiver != XCVR_EXTERNAL)
  3316. return -EINVAL;
  3317. if (ecmd->phy_address != np->phyaddr) {
  3318. /* TODO: support switching between multiple phys. Should be
  3319. * trivial, but not enabled due to lack of test hardware. */
  3320. return -EINVAL;
  3321. }
  3322. if (ecmd->autoneg == AUTONEG_ENABLE) {
  3323. u32 mask;
  3324. mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3325. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
  3326. if (np->gigabit == PHY_GIGABIT)
  3327. mask |= ADVERTISED_1000baseT_Full;
  3328. if ((ecmd->advertising & mask) == 0)
  3329. return -EINVAL;
  3330. } else if (ecmd->autoneg == AUTONEG_DISABLE) {
  3331. /* Note: autonegotiation disable, speed 1000 intentionally
  3332. * forbidden - noone should need that. */
  3333. if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
  3334. return -EINVAL;
  3335. if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
  3336. return -EINVAL;
  3337. } else {
  3338. return -EINVAL;
  3339. }
  3340. netif_carrier_off(dev);
  3341. if (netif_running(dev)) {
  3342. nv_disable_irq(dev);
  3343. netif_tx_lock_bh(dev);
  3344. spin_lock(&np->lock);
  3345. /* stop engines */
  3346. nv_stop_rx(dev);
  3347. nv_stop_tx(dev);
  3348. spin_unlock(&np->lock);
  3349. netif_tx_unlock_bh(dev);
  3350. }
  3351. if (ecmd->autoneg == AUTONEG_ENABLE) {
  3352. int adv, bmcr;
  3353. np->autoneg = 1;
  3354. /* advertise only what has been requested */
  3355. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3356. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3357. if (ecmd->advertising & ADVERTISED_10baseT_Half)
  3358. adv |= ADVERTISE_10HALF;
  3359. if (ecmd->advertising & ADVERTISED_10baseT_Full)
  3360. adv |= ADVERTISE_10FULL;
  3361. if (ecmd->advertising & ADVERTISED_100baseT_Half)
  3362. adv |= ADVERTISE_100HALF;
  3363. if (ecmd->advertising & ADVERTISED_100baseT_Full)
  3364. adv |= ADVERTISE_100FULL;
  3365. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
  3366. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3367. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  3368. adv |= ADVERTISE_PAUSE_ASYM;
  3369. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3370. if (np->gigabit == PHY_GIGABIT) {
  3371. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3372. adv &= ~ADVERTISE_1000FULL;
  3373. if (ecmd->advertising & ADVERTISED_1000baseT_Full)
  3374. adv |= ADVERTISE_1000FULL;
  3375. mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
  3376. }
  3377. if (netif_running(dev))
  3378. printk(KERN_INFO "%s: link down.\n", dev->name);
  3379. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3380. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  3381. bmcr |= BMCR_ANENABLE;
  3382. /* reset the phy in order for settings to stick,
  3383. * and cause autoneg to start */
  3384. if (phy_reset(dev, bmcr)) {
  3385. printk(KERN_INFO "%s: phy reset failed\n", dev->name);
  3386. return -EINVAL;
  3387. }
  3388. } else {
  3389. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3390. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3391. }
  3392. } else {
  3393. int adv, bmcr;
  3394. np->autoneg = 0;
  3395. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3396. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3397. if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
  3398. adv |= ADVERTISE_10HALF;
  3399. if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
  3400. adv |= ADVERTISE_10FULL;
  3401. if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
  3402. adv |= ADVERTISE_100HALF;
  3403. if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
  3404. adv |= ADVERTISE_100FULL;
  3405. np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
  3406. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
  3407. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3408. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  3409. }
  3410. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
  3411. adv |= ADVERTISE_PAUSE_ASYM;
  3412. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  3413. }
  3414. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3415. np->fixed_mode = adv;
  3416. if (np->gigabit == PHY_GIGABIT) {
  3417. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3418. adv &= ~ADVERTISE_1000FULL;
  3419. mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
  3420. }
  3421. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3422. bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
  3423. if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
  3424. bmcr |= BMCR_FULLDPLX;
  3425. if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
  3426. bmcr |= BMCR_SPEED100;
  3427. if (np->phy_oui == PHY_OUI_MARVELL) {
  3428. /* reset the phy in order for forced mode settings to stick */
  3429. if (phy_reset(dev, bmcr)) {
  3430. printk(KERN_INFO "%s: phy reset failed\n", dev->name);
  3431. return -EINVAL;
  3432. }
  3433. } else {
  3434. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3435. if (netif_running(dev)) {
  3436. /* Wait a bit and then reconfigure the nic. */
  3437. udelay(10);
  3438. nv_linkchange(dev);
  3439. }
  3440. }
  3441. }
  3442. if (netif_running(dev)) {
  3443. nv_start_rx(dev);
  3444. nv_start_tx(dev);
  3445. nv_enable_irq(dev);
  3446. }
  3447. return 0;
  3448. }
  3449. #define FORCEDETH_REGS_VER 1
  3450. static int nv_get_regs_len(struct net_device *dev)
  3451. {
  3452. struct fe_priv *np = netdev_priv(dev);
  3453. return np->register_size;
  3454. }
  3455. static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
  3456. {
  3457. struct fe_priv *np = netdev_priv(dev);
  3458. u8 __iomem *base = get_hwbase(dev);
  3459. u32 *rbuf = buf;
  3460. int i;
  3461. regs->version = FORCEDETH_REGS_VER;
  3462. spin_lock_irq(&np->lock);
  3463. for (i = 0;i <= np->register_size/sizeof(u32); i++)
  3464. rbuf[i] = readl(base + i*sizeof(u32));
  3465. spin_unlock_irq(&np->lock);
  3466. }
  3467. static int nv_nway_reset(struct net_device *dev)
  3468. {
  3469. struct fe_priv *np = netdev_priv(dev);
  3470. int ret;
  3471. if (np->autoneg) {
  3472. int bmcr;
  3473. netif_carrier_off(dev);
  3474. if (netif_running(dev)) {
  3475. nv_disable_irq(dev);
  3476. netif_tx_lock_bh(dev);
  3477. spin_lock(&np->lock);
  3478. /* stop engines */
  3479. nv_stop_rx(dev);
  3480. nv_stop_tx(dev);
  3481. spin_unlock(&np->lock);
  3482. netif_tx_unlock_bh(dev);
  3483. printk(KERN_INFO "%s: link down.\n", dev->name);
  3484. }
  3485. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3486. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  3487. bmcr |= BMCR_ANENABLE;
  3488. /* reset the phy in order for settings to stick*/
  3489. if (phy_reset(dev, bmcr)) {
  3490. printk(KERN_INFO "%s: phy reset failed\n", dev->name);
  3491. return -EINVAL;
  3492. }
  3493. } else {
  3494. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3495. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3496. }
  3497. if (netif_running(dev)) {
  3498. nv_start_rx(dev);
  3499. nv_start_tx(dev);
  3500. nv_enable_irq(dev);
  3501. }
  3502. ret = 0;
  3503. } else {
  3504. ret = -EINVAL;
  3505. }
  3506. return ret;
  3507. }
  3508. static int nv_set_tso(struct net_device *dev, u32 value)
  3509. {
  3510. struct fe_priv *np = netdev_priv(dev);
  3511. if ((np->driver_data & DEV_HAS_CHECKSUM))
  3512. return ethtool_op_set_tso(dev, value);
  3513. else
  3514. return -EOPNOTSUPP;
  3515. }
  3516. static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  3517. {
  3518. struct fe_priv *np = netdev_priv(dev);
  3519. ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
  3520. ring->rx_mini_max_pending = 0;
  3521. ring->rx_jumbo_max_pending = 0;
  3522. ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
  3523. ring->rx_pending = np->rx_ring_size;
  3524. ring->rx_mini_pending = 0;
  3525. ring->rx_jumbo_pending = 0;
  3526. ring->tx_pending = np->tx_ring_size;
  3527. }
  3528. static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  3529. {
  3530. struct fe_priv *np = netdev_priv(dev);
  3531. u8 __iomem *base = get_hwbase(dev);
  3532. u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
  3533. dma_addr_t ring_addr;
  3534. if (ring->rx_pending < RX_RING_MIN ||
  3535. ring->tx_pending < TX_RING_MIN ||
  3536. ring->rx_mini_pending != 0 ||
  3537. ring->rx_jumbo_pending != 0 ||
  3538. (np->desc_ver == DESC_VER_1 &&
  3539. (ring->rx_pending > RING_MAX_DESC_VER_1 ||
  3540. ring->tx_pending > RING_MAX_DESC_VER_1)) ||
  3541. (np->desc_ver != DESC_VER_1 &&
  3542. (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
  3543. ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
  3544. return -EINVAL;
  3545. }
  3546. /* allocate new rings */
  3547. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  3548. rxtx_ring = pci_alloc_consistent(np->pci_dev,
  3549. sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
  3550. &ring_addr);
  3551. } else {
  3552. rxtx_ring = pci_alloc_consistent(np->pci_dev,
  3553. sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
  3554. &ring_addr);
  3555. }
  3556. rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
  3557. tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
  3558. if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
  3559. /* fall back to old rings */
  3560. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  3561. if (rxtx_ring)
  3562. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
  3563. rxtx_ring, ring_addr);
  3564. } else {
  3565. if (rxtx_ring)
  3566. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
  3567. rxtx_ring, ring_addr);
  3568. }
  3569. if (rx_skbuff)
  3570. kfree(rx_skbuff);
  3571. if (tx_skbuff)
  3572. kfree(tx_skbuff);
  3573. goto exit;
  3574. }
  3575. if (netif_running(dev)) {
  3576. nv_disable_irq(dev);
  3577. netif_tx_lock_bh(dev);
  3578. spin_lock(&np->lock);
  3579. /* stop engines */
  3580. nv_stop_rx(dev);
  3581. nv_stop_tx(dev);
  3582. nv_txrx_reset(dev);
  3583. /* drain queues */
  3584. nv_drain_rx(dev);
  3585. nv_drain_tx(dev);
  3586. /* delete queues */
  3587. free_rings(dev);
  3588. }
  3589. /* set new values */
  3590. np->rx_ring_size = ring->rx_pending;
  3591. np->tx_ring_size = ring->tx_pending;
  3592. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  3593. np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
  3594. np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
  3595. } else {
  3596. np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
  3597. np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
  3598. }
  3599. np->rx_skb = (struct nv_skb_map*)rx_skbuff;
  3600. np->tx_skb = (struct nv_skb_map*)tx_skbuff;
  3601. np->ring_addr = ring_addr;
  3602. memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
  3603. memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
  3604. if (netif_running(dev)) {
  3605. /* reinit driver view of the queues */
  3606. set_bufsize(dev);
  3607. if (nv_init_ring(dev)) {
  3608. if (!np->in_shutdown)
  3609. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3610. }
  3611. /* reinit nic view of the queues */
  3612. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  3613. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  3614. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  3615. base + NvRegRingSizes);
  3616. pci_push(base);
  3617. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  3618. pci_push(base);
  3619. /* restart engines */
  3620. nv_start_rx(dev);
  3621. nv_start_tx(dev);
  3622. spin_unlock(&np->lock);
  3623. netif_tx_unlock_bh(dev);
  3624. nv_enable_irq(dev);
  3625. }
  3626. return 0;
  3627. exit:
  3628. return -ENOMEM;
  3629. }
  3630. static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
  3631. {
  3632. struct fe_priv *np = netdev_priv(dev);
  3633. pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
  3634. pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
  3635. pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
  3636. }
  3637. static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
  3638. {
  3639. struct fe_priv *np = netdev_priv(dev);
  3640. int adv, bmcr;
  3641. if ((!np->autoneg && np->duplex == 0) ||
  3642. (np->autoneg && !pause->autoneg && np->duplex == 0)) {
  3643. printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
  3644. dev->name);
  3645. return -EINVAL;
  3646. }
  3647. if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
  3648. printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
  3649. return -EINVAL;
  3650. }
  3651. netif_carrier_off(dev);
  3652. if (netif_running(dev)) {
  3653. nv_disable_irq(dev);
  3654. netif_tx_lock_bh(dev);
  3655. spin_lock(&np->lock);
  3656. /* stop engines */
  3657. nv_stop_rx(dev);
  3658. nv_stop_tx(dev);
  3659. spin_unlock(&np->lock);
  3660. netif_tx_unlock_bh(dev);
  3661. }
  3662. np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
  3663. if (pause->rx_pause)
  3664. np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
  3665. if (pause->tx_pause)
  3666. np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
  3667. if (np->autoneg && pause->autoneg) {
  3668. np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
  3669. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3670. adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3671. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
  3672. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3673. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  3674. adv |= ADVERTISE_PAUSE_ASYM;
  3675. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3676. if (netif_running(dev))
  3677. printk(KERN_INFO "%s: link down.\n", dev->name);
  3678. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3679. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3680. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3681. } else {
  3682. np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
  3683. if (pause->rx_pause)
  3684. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  3685. if (pause->tx_pause)
  3686. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  3687. if (!netif_running(dev))
  3688. nv_update_linkspeed(dev);
  3689. else
  3690. nv_update_pause(dev, np->pause_flags);
  3691. }
  3692. if (netif_running(dev)) {
  3693. nv_start_rx(dev);
  3694. nv_start_tx(dev);
  3695. nv_enable_irq(dev);
  3696. }
  3697. return 0;
  3698. }
  3699. static u32 nv_get_rx_csum(struct net_device *dev)
  3700. {
  3701. struct fe_priv *np = netdev_priv(dev);
  3702. return (np->rx_csum) != 0;
  3703. }
  3704. static int nv_set_rx_csum(struct net_device *dev, u32 data)
  3705. {
  3706. struct fe_priv *np = netdev_priv(dev);
  3707. u8 __iomem *base = get_hwbase(dev);
  3708. int retcode = 0;
  3709. if (np->driver_data & DEV_HAS_CHECKSUM) {
  3710. if (data) {
  3711. np->rx_csum = 1;
  3712. np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
  3713. } else {
  3714. np->rx_csum = 0;
  3715. /* vlan is dependent on rx checksum offload */
  3716. if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
  3717. np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
  3718. }
  3719. if (netif_running(dev)) {
  3720. spin_lock_irq(&np->lock);
  3721. writel(np->txrxctl_bits, base + NvRegTxRxControl);
  3722. spin_unlock_irq(&np->lock);
  3723. }
  3724. } else {
  3725. return -EINVAL;
  3726. }
  3727. return retcode;
  3728. }
  3729. static int nv_set_tx_csum(struct net_device *dev, u32 data)
  3730. {
  3731. struct fe_priv *np = netdev_priv(dev);
  3732. if (np->driver_data & DEV_HAS_CHECKSUM)
  3733. return ethtool_op_set_tx_hw_csum(dev, data);
  3734. else
  3735. return -EOPNOTSUPP;
  3736. }
  3737. static int nv_set_sg(struct net_device *dev, u32 data)
  3738. {
  3739. struct fe_priv *np = netdev_priv(dev);
  3740. if (np->driver_data & DEV_HAS_CHECKSUM)
  3741. return ethtool_op_set_sg(dev, data);
  3742. else
  3743. return -EOPNOTSUPP;
  3744. }
  3745. static int nv_get_stats_count(struct net_device *dev)
  3746. {
  3747. struct fe_priv *np = netdev_priv(dev);
  3748. if (np->driver_data & DEV_HAS_STATISTICS_V1)
  3749. return NV_DEV_STATISTICS_V1_COUNT;
  3750. else if (np->driver_data & DEV_HAS_STATISTICS_V2)
  3751. return NV_DEV_STATISTICS_V2_COUNT;
  3752. else
  3753. return 0;
  3754. }
  3755. static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
  3756. {
  3757. struct fe_priv *np = netdev_priv(dev);
  3758. /* update stats */
  3759. nv_do_stats_poll((unsigned long)dev);
  3760. memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
  3761. }
  3762. static int nv_self_test_count(struct net_device *dev)
  3763. {
  3764. struct fe_priv *np = netdev_priv(dev);
  3765. if (np->driver_data & DEV_HAS_TEST_EXTENDED)
  3766. return NV_TEST_COUNT_EXTENDED;
  3767. else
  3768. return NV_TEST_COUNT_BASE;
  3769. }
  3770. static int nv_link_test(struct net_device *dev)
  3771. {
  3772. struct fe_priv *np = netdev_priv(dev);
  3773. int mii_status;
  3774. mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  3775. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  3776. /* check phy link status */
  3777. if (!(mii_status & BMSR_LSTATUS))
  3778. return 0;
  3779. else
  3780. return 1;
  3781. }
  3782. static int nv_register_test(struct net_device *dev)
  3783. {
  3784. u8 __iomem *base = get_hwbase(dev);
  3785. int i = 0;
  3786. u32 orig_read, new_read;
  3787. do {
  3788. orig_read = readl(base + nv_registers_test[i].reg);
  3789. /* xor with mask to toggle bits */
  3790. orig_read ^= nv_registers_test[i].mask;
  3791. writel(orig_read, base + nv_registers_test[i].reg);
  3792. new_read = readl(base + nv_registers_test[i].reg);
  3793. if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
  3794. return 0;
  3795. /* restore original value */
  3796. orig_read ^= nv_registers_test[i].mask;
  3797. writel(orig_read, base + nv_registers_test[i].reg);
  3798. } while (nv_registers_test[++i].reg != 0);
  3799. return 1;
  3800. }
  3801. static int nv_interrupt_test(struct net_device *dev)
  3802. {
  3803. struct fe_priv *np = netdev_priv(dev);
  3804. u8 __iomem *base = get_hwbase(dev);
  3805. int ret = 1;
  3806. int testcnt;
  3807. u32 save_msi_flags, save_poll_interval = 0;
  3808. if (netif_running(dev)) {
  3809. /* free current irq */
  3810. nv_free_irq(dev);
  3811. save_poll_interval = readl(base+NvRegPollingInterval);
  3812. }
  3813. /* flag to test interrupt handler */
  3814. np->intr_test = 0;
  3815. /* setup test irq */
  3816. save_msi_flags = np->msi_flags;
  3817. np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
  3818. np->msi_flags |= 0x001; /* setup 1 vector */
  3819. if (nv_request_irq(dev, 1))
  3820. return 0;
  3821. /* setup timer interrupt */
  3822. writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
  3823. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  3824. nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
  3825. /* wait for at least one interrupt */
  3826. msleep(100);
  3827. spin_lock_irq(&np->lock);
  3828. /* flag should be set within ISR */
  3829. testcnt = np->intr_test;
  3830. if (!testcnt)
  3831. ret = 2;
  3832. nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
  3833. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  3834. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  3835. else
  3836. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  3837. spin_unlock_irq(&np->lock);
  3838. nv_free_irq(dev);
  3839. np->msi_flags = save_msi_flags;
  3840. if (netif_running(dev)) {
  3841. writel(save_poll_interval, base + NvRegPollingInterval);
  3842. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  3843. /* restore original irq */
  3844. if (nv_request_irq(dev, 0))
  3845. return 0;
  3846. }
  3847. return ret;
  3848. }
  3849. static int nv_loopback_test(struct net_device *dev)
  3850. {
  3851. struct fe_priv *np = netdev_priv(dev);
  3852. u8 __iomem *base = get_hwbase(dev);
  3853. struct sk_buff *tx_skb, *rx_skb;
  3854. dma_addr_t test_dma_addr;
  3855. u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
  3856. u32 flags;
  3857. int len, i, pkt_len;
  3858. u8 *pkt_data;
  3859. u32 filter_flags = 0;
  3860. u32 misc1_flags = 0;
  3861. int ret = 1;
  3862. if (netif_running(dev)) {
  3863. nv_disable_irq(dev);
  3864. filter_flags = readl(base + NvRegPacketFilterFlags);
  3865. misc1_flags = readl(base + NvRegMisc1);
  3866. } else {
  3867. nv_txrx_reset(dev);
  3868. }
  3869. /* reinit driver view of the rx queue */
  3870. set_bufsize(dev);
  3871. nv_init_ring(dev);
  3872. /* setup hardware for loopback */
  3873. writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
  3874. writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
  3875. /* reinit nic view of the rx queue */
  3876. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  3877. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  3878. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  3879. base + NvRegRingSizes);
  3880. pci_push(base);
  3881. /* restart rx engine */
  3882. nv_start_rx(dev);
  3883. nv_start_tx(dev);
  3884. /* setup packet for tx */
  3885. pkt_len = ETH_DATA_LEN;
  3886. tx_skb = dev_alloc_skb(pkt_len);
  3887. if (!tx_skb) {
  3888. printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
  3889. " of %s\n", dev->name);
  3890. ret = 0;
  3891. goto out;
  3892. }
  3893. pkt_data = skb_put(tx_skb, pkt_len);
  3894. for (i = 0; i < pkt_len; i++)
  3895. pkt_data[i] = (u8)(i & 0xff);
  3896. test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
  3897. tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
  3898. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  3899. np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
  3900. np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
  3901. } else {
  3902. np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
  3903. np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
  3904. np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
  3905. }
  3906. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  3907. pci_push(get_hwbase(dev));
  3908. msleep(500);
  3909. /* check for rx of the packet */
  3910. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  3911. flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
  3912. len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
  3913. } else {
  3914. flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
  3915. len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
  3916. }
  3917. if (flags & NV_RX_AVAIL) {
  3918. ret = 0;
  3919. } else if (np->desc_ver == DESC_VER_1) {
  3920. if (flags & NV_RX_ERROR)
  3921. ret = 0;
  3922. } else {
  3923. if (flags & NV_RX2_ERROR) {
  3924. ret = 0;
  3925. }
  3926. }
  3927. if (ret) {
  3928. if (len != pkt_len) {
  3929. ret = 0;
  3930. dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
  3931. dev->name, len, pkt_len);
  3932. } else {
  3933. rx_skb = np->rx_skb[0].skb;
  3934. for (i = 0; i < pkt_len; i++) {
  3935. if (rx_skb->data[i] != (u8)(i & 0xff)) {
  3936. ret = 0;
  3937. dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
  3938. dev->name, i);
  3939. break;
  3940. }
  3941. }
  3942. }
  3943. } else {
  3944. dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
  3945. }
  3946. pci_unmap_page(np->pci_dev, test_dma_addr,
  3947. tx_skb->end-tx_skb->data,
  3948. PCI_DMA_TODEVICE);
  3949. dev_kfree_skb_any(tx_skb);
  3950. out:
  3951. /* stop engines */
  3952. nv_stop_rx(dev);
  3953. nv_stop_tx(dev);
  3954. nv_txrx_reset(dev);
  3955. /* drain rx queue */
  3956. nv_drain_rx(dev);
  3957. nv_drain_tx(dev);
  3958. if (netif_running(dev)) {
  3959. writel(misc1_flags, base + NvRegMisc1);
  3960. writel(filter_flags, base + NvRegPacketFilterFlags);
  3961. nv_enable_irq(dev);
  3962. }
  3963. return ret;
  3964. }
  3965. static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
  3966. {
  3967. struct fe_priv *np = netdev_priv(dev);
  3968. u8 __iomem *base = get_hwbase(dev);
  3969. int result;
  3970. memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
  3971. if (!nv_link_test(dev)) {
  3972. test->flags |= ETH_TEST_FL_FAILED;
  3973. buffer[0] = 1;
  3974. }
  3975. if (test->flags & ETH_TEST_FL_OFFLINE) {
  3976. if (netif_running(dev)) {
  3977. netif_stop_queue(dev);
  3978. netif_poll_disable(dev);
  3979. netif_tx_lock_bh(dev);
  3980. spin_lock_irq(&np->lock);
  3981. nv_disable_hw_interrupts(dev, np->irqmask);
  3982. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  3983. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  3984. } else {
  3985. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  3986. }
  3987. /* stop engines */
  3988. nv_stop_rx(dev);
  3989. nv_stop_tx(dev);
  3990. nv_txrx_reset(dev);
  3991. /* drain rx queue */
  3992. nv_drain_rx(dev);
  3993. nv_drain_tx(dev);
  3994. spin_unlock_irq(&np->lock);
  3995. netif_tx_unlock_bh(dev);
  3996. }
  3997. if (!nv_register_test(dev)) {
  3998. test->flags |= ETH_TEST_FL_FAILED;
  3999. buffer[1] = 1;
  4000. }
  4001. result = nv_interrupt_test(dev);
  4002. if (result != 1) {
  4003. test->flags |= ETH_TEST_FL_FAILED;
  4004. buffer[2] = 1;
  4005. }
  4006. if (result == 0) {
  4007. /* bail out */
  4008. return;
  4009. }
  4010. if (!nv_loopback_test(dev)) {
  4011. test->flags |= ETH_TEST_FL_FAILED;
  4012. buffer[3] = 1;
  4013. }
  4014. if (netif_running(dev)) {
  4015. /* reinit driver view of the rx queue */
  4016. set_bufsize(dev);
  4017. if (nv_init_ring(dev)) {
  4018. if (!np->in_shutdown)
  4019. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  4020. }
  4021. /* reinit nic view of the rx queue */
  4022. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4023. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4024. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4025. base + NvRegRingSizes);
  4026. pci_push(base);
  4027. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4028. pci_push(base);
  4029. /* restart rx engine */
  4030. nv_start_rx(dev);
  4031. nv_start_tx(dev);
  4032. netif_start_queue(dev);
  4033. netif_poll_enable(dev);
  4034. nv_enable_hw_interrupts(dev, np->irqmask);
  4035. }
  4036. }
  4037. }
  4038. static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
  4039. {
  4040. switch (stringset) {
  4041. case ETH_SS_STATS:
  4042. memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
  4043. break;
  4044. case ETH_SS_TEST:
  4045. memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
  4046. break;
  4047. }
  4048. }
  4049. static const struct ethtool_ops ops = {
  4050. .get_drvinfo = nv_get_drvinfo,
  4051. .get_link = ethtool_op_get_link,
  4052. .get_wol = nv_get_wol,
  4053. .set_wol = nv_set_wol,
  4054. .get_settings = nv_get_settings,
  4055. .set_settings = nv_set_settings,
  4056. .get_regs_len = nv_get_regs_len,
  4057. .get_regs = nv_get_regs,
  4058. .nway_reset = nv_nway_reset,
  4059. .get_perm_addr = ethtool_op_get_perm_addr,
  4060. .get_tso = ethtool_op_get_tso,
  4061. .set_tso = nv_set_tso,
  4062. .get_ringparam = nv_get_ringparam,
  4063. .set_ringparam = nv_set_ringparam,
  4064. .get_pauseparam = nv_get_pauseparam,
  4065. .set_pauseparam = nv_set_pauseparam,
  4066. .get_rx_csum = nv_get_rx_csum,
  4067. .set_rx_csum = nv_set_rx_csum,
  4068. .get_tx_csum = ethtool_op_get_tx_csum,
  4069. .set_tx_csum = nv_set_tx_csum,
  4070. .get_sg = ethtool_op_get_sg,
  4071. .set_sg = nv_set_sg,
  4072. .get_strings = nv_get_strings,
  4073. .get_stats_count = nv_get_stats_count,
  4074. .get_ethtool_stats = nv_get_ethtool_stats,
  4075. .self_test_count = nv_self_test_count,
  4076. .self_test = nv_self_test,
  4077. };
  4078. static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  4079. {
  4080. struct fe_priv *np = get_nvpriv(dev);
  4081. spin_lock_irq(&np->lock);
  4082. /* save vlan group */
  4083. np->vlangrp = grp;
  4084. if (grp) {
  4085. /* enable vlan on MAC */
  4086. np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
  4087. } else {
  4088. /* disable vlan on MAC */
  4089. np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
  4090. np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
  4091. }
  4092. writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4093. spin_unlock_irq(&np->lock);
  4094. };
  4095. static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
  4096. {
  4097. /* nothing to do */
  4098. };
  4099. /* The mgmt unit and driver use a semaphore to access the phy during init */
  4100. static int nv_mgmt_acquire_sema(struct net_device *dev)
  4101. {
  4102. u8 __iomem *base = get_hwbase(dev);
  4103. int i;
  4104. u32 tx_ctrl, mgmt_sema;
  4105. for (i = 0; i < 10; i++) {
  4106. mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
  4107. if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
  4108. break;
  4109. msleep(500);
  4110. }
  4111. if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
  4112. return 0;
  4113. for (i = 0; i < 2; i++) {
  4114. tx_ctrl = readl(base + NvRegTransmitterControl);
  4115. tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
  4116. writel(tx_ctrl, base + NvRegTransmitterControl);
  4117. /* verify that semaphore was acquired */
  4118. tx_ctrl = readl(base + NvRegTransmitterControl);
  4119. if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
  4120. ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
  4121. return 1;
  4122. else
  4123. udelay(50);
  4124. }
  4125. return 0;
  4126. }
  4127. static int nv_open(struct net_device *dev)
  4128. {
  4129. struct fe_priv *np = netdev_priv(dev);
  4130. u8 __iomem *base = get_hwbase(dev);
  4131. int ret = 1;
  4132. int oom, i;
  4133. dprintk(KERN_DEBUG "nv_open: begin\n");
  4134. /* erase previous misconfiguration */
  4135. if (np->driver_data & DEV_HAS_POWER_CNTRL)
  4136. nv_mac_reset(dev);
  4137. writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
  4138. writel(0, base + NvRegMulticastAddrB);
  4139. writel(0, base + NvRegMulticastMaskA);
  4140. writel(0, base + NvRegMulticastMaskB);
  4141. writel(0, base + NvRegPacketFilterFlags);
  4142. writel(0, base + NvRegTransmitterControl);
  4143. writel(0, base + NvRegReceiverControl);
  4144. writel(0, base + NvRegAdapterControl);
  4145. if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
  4146. writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
  4147. /* initialize descriptor rings */
  4148. set_bufsize(dev);
  4149. oom = nv_init_ring(dev);
  4150. writel(0, base + NvRegLinkSpeed);
  4151. writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
  4152. nv_txrx_reset(dev);
  4153. writel(0, base + NvRegUnknownSetupReg6);
  4154. np->in_shutdown = 0;
  4155. /* give hw rings */
  4156. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4157. writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4158. base + NvRegRingSizes);
  4159. writel(np->linkspeed, base + NvRegLinkSpeed);
  4160. if (np->desc_ver == DESC_VER_1)
  4161. writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
  4162. else
  4163. writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
  4164. writel(np->txrxctl_bits, base + NvRegTxRxControl);
  4165. writel(np->vlanctl_bits, base + NvRegVlanControl);
  4166. pci_push(base);
  4167. writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
  4168. reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
  4169. NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
  4170. KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
  4171. writel(0, base + NvRegMIIMask);
  4172. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4173. writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
  4174. writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
  4175. writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
  4176. writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
  4177. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4178. writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
  4179. get_random_bytes(&i, sizeof(i));
  4180. writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
  4181. writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
  4182. writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
  4183. if (poll_interval == -1) {
  4184. if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
  4185. writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
  4186. else
  4187. writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
  4188. }
  4189. else
  4190. writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
  4191. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  4192. writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
  4193. base + NvRegAdapterControl);
  4194. writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
  4195. writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
  4196. if (np->wolenabled)
  4197. writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
  4198. i = readl(base + NvRegPowerState);
  4199. if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
  4200. writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
  4201. pci_push(base);
  4202. udelay(10);
  4203. writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
  4204. nv_disable_hw_interrupts(dev, np->irqmask);
  4205. pci_push(base);
  4206. writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
  4207. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4208. pci_push(base);
  4209. if (nv_request_irq(dev, 0)) {
  4210. goto out_drain;
  4211. }
  4212. /* ask for interrupts */
  4213. nv_enable_hw_interrupts(dev, np->irqmask);
  4214. spin_lock_irq(&np->lock);
  4215. writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
  4216. writel(0, base + NvRegMulticastAddrB);
  4217. writel(0, base + NvRegMulticastMaskA);
  4218. writel(0, base + NvRegMulticastMaskB);
  4219. writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
  4220. /* One manual link speed update: Interrupts are enabled, future link
  4221. * speed changes cause interrupts and are handled by nv_link_irq().
  4222. */
  4223. {
  4224. u32 miistat;
  4225. miistat = readl(base + NvRegMIIStatus);
  4226. writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
  4227. dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
  4228. }
  4229. /* set linkspeed to invalid value, thus force nv_update_linkspeed
  4230. * to init hw */
  4231. np->linkspeed = 0;
  4232. ret = nv_update_linkspeed(dev);
  4233. nv_start_rx(dev);
  4234. nv_start_tx(dev);
  4235. netif_start_queue(dev);
  4236. netif_poll_enable(dev);
  4237. if (ret) {
  4238. netif_carrier_on(dev);
  4239. } else {
  4240. printk("%s: no link during initialization.\n", dev->name);
  4241. netif_carrier_off(dev);
  4242. }
  4243. if (oom)
  4244. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  4245. /* start statistics timer */
  4246. if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
  4247. mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
  4248. spin_unlock_irq(&np->lock);
  4249. return 0;
  4250. out_drain:
  4251. drain_ring(dev);
  4252. return ret;
  4253. }
  4254. static int nv_close(struct net_device *dev)
  4255. {
  4256. struct fe_priv *np = netdev_priv(dev);
  4257. u8 __iomem *base;
  4258. spin_lock_irq(&np->lock);
  4259. np->in_shutdown = 1;
  4260. spin_unlock_irq(&np->lock);
  4261. netif_poll_disable(dev);
  4262. synchronize_irq(dev->irq);
  4263. del_timer_sync(&np->oom_kick);
  4264. del_timer_sync(&np->nic_poll);
  4265. del_timer_sync(&np->stats_poll);
  4266. netif_stop_queue(dev);
  4267. spin_lock_irq(&np->lock);
  4268. nv_stop_tx(dev);
  4269. nv_stop_rx(dev);
  4270. nv_txrx_reset(dev);
  4271. /* disable interrupts on the nic or we will lock up */
  4272. base = get_hwbase(dev);
  4273. nv_disable_hw_interrupts(dev, np->irqmask);
  4274. pci_push(base);
  4275. dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
  4276. spin_unlock_irq(&np->lock);
  4277. nv_free_irq(dev);
  4278. drain_ring(dev);
  4279. if (np->wolenabled)
  4280. nv_start_rx(dev);
  4281. /* FIXME: power down nic */
  4282. return 0;
  4283. }
  4284. static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  4285. {
  4286. struct net_device *dev;
  4287. struct fe_priv *np;
  4288. unsigned long addr;
  4289. u8 __iomem *base;
  4290. int err, i;
  4291. u32 powerstate, txreg;
  4292. u32 phystate_orig = 0, phystate;
  4293. int phyinitialized = 0;
  4294. dev = alloc_etherdev(sizeof(struct fe_priv));
  4295. err = -ENOMEM;
  4296. if (!dev)
  4297. goto out;
  4298. np = netdev_priv(dev);
  4299. np->pci_dev = pci_dev;
  4300. spin_lock_init(&np->lock);
  4301. SET_MODULE_OWNER(dev);
  4302. SET_NETDEV_DEV(dev, &pci_dev->dev);
  4303. init_timer(&np->oom_kick);
  4304. np->oom_kick.data = (unsigned long) dev;
  4305. np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
  4306. init_timer(&np->nic_poll);
  4307. np->nic_poll.data = (unsigned long) dev;
  4308. np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
  4309. init_timer(&np->stats_poll);
  4310. np->stats_poll.data = (unsigned long) dev;
  4311. np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
  4312. err = pci_enable_device(pci_dev);
  4313. if (err) {
  4314. printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
  4315. err, pci_name(pci_dev));
  4316. goto out_free;
  4317. }
  4318. pci_set_master(pci_dev);
  4319. err = pci_request_regions(pci_dev, DRV_NAME);
  4320. if (err < 0)
  4321. goto out_disable;
  4322. if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
  4323. np->register_size = NV_PCI_REGSZ_VER3;
  4324. else if (id->driver_data & DEV_HAS_STATISTICS_V1)
  4325. np->register_size = NV_PCI_REGSZ_VER2;
  4326. else
  4327. np->register_size = NV_PCI_REGSZ_VER1;
  4328. err = -EINVAL;
  4329. addr = 0;
  4330. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  4331. dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
  4332. pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
  4333. pci_resource_len(pci_dev, i),
  4334. pci_resource_flags(pci_dev, i));
  4335. if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
  4336. pci_resource_len(pci_dev, i) >= np->register_size) {
  4337. addr = pci_resource_start(pci_dev, i);
  4338. break;
  4339. }
  4340. }
  4341. if (i == DEVICE_COUNT_RESOURCE) {
  4342. printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
  4343. pci_name(pci_dev));
  4344. goto out_relreg;
  4345. }
  4346. /* copy of driver data */
  4347. np->driver_data = id->driver_data;
  4348. /* handle different descriptor versions */
  4349. if (id->driver_data & DEV_HAS_HIGH_DMA) {
  4350. /* packet format 3: supports 40-bit addressing */
  4351. np->desc_ver = DESC_VER_3;
  4352. np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
  4353. if (dma_64bit) {
  4354. if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
  4355. printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
  4356. pci_name(pci_dev));
  4357. } else {
  4358. dev->features |= NETIF_F_HIGHDMA;
  4359. printk(KERN_INFO "forcedeth: using HIGHDMA\n");
  4360. }
  4361. if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
  4362. printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
  4363. pci_name(pci_dev));
  4364. }
  4365. }
  4366. } else if (id->driver_data & DEV_HAS_LARGEDESC) {
  4367. /* packet format 2: supports jumbo frames */
  4368. np->desc_ver = DESC_VER_2;
  4369. np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
  4370. } else {
  4371. /* original packet format */
  4372. np->desc_ver = DESC_VER_1;
  4373. np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
  4374. }
  4375. np->pkt_limit = NV_PKTLIMIT_1;
  4376. if (id->driver_data & DEV_HAS_LARGEDESC)
  4377. np->pkt_limit = NV_PKTLIMIT_2;
  4378. if (id->driver_data & DEV_HAS_CHECKSUM) {
  4379. np->rx_csum = 1;
  4380. np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
  4381. dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
  4382. dev->features |= NETIF_F_TSO;
  4383. }
  4384. np->vlanctl_bits = 0;
  4385. if (id->driver_data & DEV_HAS_VLAN) {
  4386. np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
  4387. dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
  4388. dev->vlan_rx_register = nv_vlan_rx_register;
  4389. dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
  4390. }
  4391. np->msi_flags = 0;
  4392. if ((id->driver_data & DEV_HAS_MSI) && msi) {
  4393. np->msi_flags |= NV_MSI_CAPABLE;
  4394. }
  4395. if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
  4396. np->msi_flags |= NV_MSI_X_CAPABLE;
  4397. }
  4398. np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
  4399. if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
  4400. np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
  4401. }
  4402. err = -ENOMEM;
  4403. np->base = ioremap(addr, np->register_size);
  4404. if (!np->base)
  4405. goto out_relreg;
  4406. dev->base_addr = (unsigned long)np->base;
  4407. dev->irq = pci_dev->irq;
  4408. np->rx_ring_size = RX_RING_DEFAULT;
  4409. np->tx_ring_size = TX_RING_DEFAULT;
  4410. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
  4411. np->rx_ring.orig = pci_alloc_consistent(pci_dev,
  4412. sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
  4413. &np->ring_addr);
  4414. if (!np->rx_ring.orig)
  4415. goto out_unmap;
  4416. np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
  4417. } else {
  4418. np->rx_ring.ex = pci_alloc_consistent(pci_dev,
  4419. sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
  4420. &np->ring_addr);
  4421. if (!np->rx_ring.ex)
  4422. goto out_unmap;
  4423. np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
  4424. }
  4425. np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL);
  4426. np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL);
  4427. if (!np->rx_skb || !np->tx_skb)
  4428. goto out_freering;
  4429. memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
  4430. memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
  4431. dev->open = nv_open;
  4432. dev->stop = nv_close;
  4433. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
  4434. dev->hard_start_xmit = nv_start_xmit;
  4435. else
  4436. dev->hard_start_xmit = nv_start_xmit_optimized;
  4437. dev->get_stats = nv_get_stats;
  4438. dev->change_mtu = nv_change_mtu;
  4439. dev->set_mac_address = nv_set_mac_address;
  4440. dev->set_multicast_list = nv_set_multicast;
  4441. #ifdef CONFIG_NET_POLL_CONTROLLER
  4442. dev->poll_controller = nv_poll_controller;
  4443. #endif
  4444. dev->weight = RX_WORK_PER_LOOP;
  4445. #ifdef CONFIG_FORCEDETH_NAPI
  4446. dev->poll = nv_napi_poll;
  4447. #endif
  4448. SET_ETHTOOL_OPS(dev, &ops);
  4449. dev->tx_timeout = nv_tx_timeout;
  4450. dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
  4451. pci_set_drvdata(pci_dev, dev);
  4452. /* read the mac address */
  4453. base = get_hwbase(dev);
  4454. np->orig_mac[0] = readl(base + NvRegMacAddrA);
  4455. np->orig_mac[1] = readl(base + NvRegMacAddrB);
  4456. /* check the workaround bit for correct mac address order */
  4457. txreg = readl(base + NvRegTransmitPoll);
  4458. if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
  4459. /* mac address is already in correct order */
  4460. dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
  4461. dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
  4462. dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
  4463. dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
  4464. dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
  4465. dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
  4466. } else {
  4467. /* need to reverse mac address to correct order */
  4468. dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
  4469. dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
  4470. dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
  4471. dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
  4472. dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
  4473. dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
  4474. /* set permanent address to be correct aswell */
  4475. np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
  4476. (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
  4477. np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
  4478. writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
  4479. }
  4480. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  4481. if (!is_valid_ether_addr(dev->perm_addr)) {
  4482. /*
  4483. * Bad mac address. At least one bios sets the mac address
  4484. * to 01:23:45:67:89:ab
  4485. */
  4486. printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
  4487. pci_name(pci_dev),
  4488. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  4489. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  4490. printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
  4491. dev->dev_addr[0] = 0x00;
  4492. dev->dev_addr[1] = 0x00;
  4493. dev->dev_addr[2] = 0x6c;
  4494. get_random_bytes(&dev->dev_addr[3], 3);
  4495. }
  4496. dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
  4497. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  4498. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  4499. /* set mac address */
  4500. nv_copy_mac_to_hw(dev);
  4501. /* disable WOL */
  4502. writel(0, base + NvRegWakeUpFlags);
  4503. np->wolenabled = 0;
  4504. if (id->driver_data & DEV_HAS_POWER_CNTRL) {
  4505. u8 revision_id;
  4506. pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
  4507. /* take phy and nic out of low power mode */
  4508. powerstate = readl(base + NvRegPowerState2);
  4509. powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
  4510. if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
  4511. id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
  4512. revision_id >= 0xA3)
  4513. powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
  4514. writel(powerstate, base + NvRegPowerState2);
  4515. }
  4516. if (np->desc_ver == DESC_VER_1) {
  4517. np->tx_flags = NV_TX_VALID;
  4518. } else {
  4519. np->tx_flags = NV_TX2_VALID;
  4520. }
  4521. if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
  4522. np->irqmask = NVREG_IRQMASK_THROUGHPUT;
  4523. if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
  4524. np->msi_flags |= 0x0003;
  4525. } else {
  4526. np->irqmask = NVREG_IRQMASK_CPU;
  4527. if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
  4528. np->msi_flags |= 0x0001;
  4529. }
  4530. if (id->driver_data & DEV_NEED_TIMERIRQ)
  4531. np->irqmask |= NVREG_IRQ_TIMER;
  4532. if (id->driver_data & DEV_NEED_LINKTIMER) {
  4533. dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
  4534. np->need_linktimer = 1;
  4535. np->link_timeout = jiffies + LINK_TIMEOUT;
  4536. } else {
  4537. dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
  4538. np->need_linktimer = 0;
  4539. }
  4540. /* clear phy state and temporarily halt phy interrupts */
  4541. writel(0, base + NvRegMIIMask);
  4542. phystate = readl(base + NvRegAdapterControl);
  4543. if (phystate & NVREG_ADAPTCTL_RUNNING) {
  4544. phystate_orig = 1;
  4545. phystate &= ~NVREG_ADAPTCTL_RUNNING;
  4546. writel(phystate, base + NvRegAdapterControl);
  4547. }
  4548. writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
  4549. if (id->driver_data & DEV_HAS_MGMT_UNIT) {
  4550. /* management unit running on the mac? */
  4551. if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
  4552. np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
  4553. dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
  4554. for (i = 0; i < 5000; i++) {
  4555. msleep(1);
  4556. if (nv_mgmt_acquire_sema(dev)) {
  4557. /* management unit setup the phy already? */
  4558. if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
  4559. NVREG_XMITCTL_SYNC_PHY_INIT) {
  4560. /* phy is inited by mgmt unit */
  4561. phyinitialized = 1;
  4562. dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
  4563. } else {
  4564. /* we need to init the phy */
  4565. }
  4566. break;
  4567. }
  4568. }
  4569. }
  4570. }
  4571. /* find a suitable phy */
  4572. for (i = 1; i <= 32; i++) {
  4573. int id1, id2;
  4574. int phyaddr = i & 0x1F;
  4575. spin_lock_irq(&np->lock);
  4576. id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
  4577. spin_unlock_irq(&np->lock);
  4578. if (id1 < 0 || id1 == 0xffff)
  4579. continue;
  4580. spin_lock_irq(&np->lock);
  4581. id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
  4582. spin_unlock_irq(&np->lock);
  4583. if (id2 < 0 || id2 == 0xffff)
  4584. continue;
  4585. np->phy_model = id2 & PHYID2_MODEL_MASK;
  4586. id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
  4587. id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
  4588. dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
  4589. pci_name(pci_dev), id1, id2, phyaddr);
  4590. np->phyaddr = phyaddr;
  4591. np->phy_oui = id1 | id2;
  4592. break;
  4593. }
  4594. if (i == 33) {
  4595. printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
  4596. pci_name(pci_dev));
  4597. goto out_error;
  4598. }
  4599. if (!phyinitialized) {
  4600. /* reset it */
  4601. phy_init(dev);
  4602. } else {
  4603. /* see if it is a gigabit phy */
  4604. u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  4605. if (mii_status & PHY_GIGABIT) {
  4606. np->gigabit = PHY_GIGABIT;
  4607. }
  4608. }
  4609. /* set default link speed settings */
  4610. np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  4611. np->duplex = 0;
  4612. np->autoneg = 1;
  4613. err = register_netdev(dev);
  4614. if (err) {
  4615. printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
  4616. goto out_error;
  4617. }
  4618. printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
  4619. dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
  4620. pci_name(pci_dev));
  4621. return 0;
  4622. out_error:
  4623. if (phystate_orig)
  4624. writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
  4625. pci_set_drvdata(pci_dev, NULL);
  4626. out_freering:
  4627. free_rings(dev);
  4628. out_unmap:
  4629. iounmap(get_hwbase(dev));
  4630. out_relreg:
  4631. pci_release_regions(pci_dev);
  4632. out_disable:
  4633. pci_disable_device(pci_dev);
  4634. out_free:
  4635. free_netdev(dev);
  4636. out:
  4637. return err;
  4638. }
  4639. static void __devexit nv_remove(struct pci_dev *pci_dev)
  4640. {
  4641. struct net_device *dev = pci_get_drvdata(pci_dev);
  4642. struct fe_priv *np = netdev_priv(dev);
  4643. u8 __iomem *base = get_hwbase(dev);
  4644. unregister_netdev(dev);
  4645. /* special op: write back the misordered MAC address - otherwise
  4646. * the next nv_probe would see a wrong address.
  4647. */
  4648. writel(np->orig_mac[0], base + NvRegMacAddrA);
  4649. writel(np->orig_mac[1], base + NvRegMacAddrB);
  4650. /* free all structures */
  4651. free_rings(dev);
  4652. iounmap(get_hwbase(dev));
  4653. pci_release_regions(pci_dev);
  4654. pci_disable_device(pci_dev);
  4655. free_netdev(dev);
  4656. pci_set_drvdata(pci_dev, NULL);
  4657. }
  4658. #ifdef CONFIG_PM
  4659. static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
  4660. {
  4661. struct net_device *dev = pci_get_drvdata(pdev);
  4662. struct fe_priv *np = netdev_priv(dev);
  4663. if (!netif_running(dev))
  4664. goto out;
  4665. netif_device_detach(dev);
  4666. // Gross.
  4667. nv_close(dev);
  4668. pci_save_state(pdev);
  4669. pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
  4670. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  4671. out:
  4672. return 0;
  4673. }
  4674. static int nv_resume(struct pci_dev *pdev)
  4675. {
  4676. struct net_device *dev = pci_get_drvdata(pdev);
  4677. int rc = 0;
  4678. if (!netif_running(dev))
  4679. goto out;
  4680. netif_device_attach(dev);
  4681. pci_set_power_state(pdev, PCI_D0);
  4682. pci_restore_state(pdev);
  4683. pci_enable_wake(pdev, PCI_D0, 0);
  4684. rc = nv_open(dev);
  4685. out:
  4686. return rc;
  4687. }
  4688. #else
  4689. #define nv_suspend NULL
  4690. #define nv_resume NULL
  4691. #endif /* CONFIG_PM */
  4692. static struct pci_device_id pci_tbl[] = {
  4693. { /* nForce Ethernet Controller */
  4694. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
  4695. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  4696. },
  4697. { /* nForce2 Ethernet Controller */
  4698. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
  4699. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  4700. },
  4701. { /* nForce3 Ethernet Controller */
  4702. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
  4703. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  4704. },
  4705. { /* nForce3 Ethernet Controller */
  4706. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
  4707. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  4708. },
  4709. { /* nForce3 Ethernet Controller */
  4710. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
  4711. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  4712. },
  4713. { /* nForce3 Ethernet Controller */
  4714. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
  4715. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  4716. },
  4717. { /* nForce3 Ethernet Controller */
  4718. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
  4719. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  4720. },
  4721. { /* CK804 Ethernet Controller */
  4722. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
  4723. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
  4724. },
  4725. { /* CK804 Ethernet Controller */
  4726. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
  4727. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
  4728. },
  4729. { /* MCP04 Ethernet Controller */
  4730. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
  4731. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
  4732. },
  4733. { /* MCP04 Ethernet Controller */
  4734. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
  4735. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
  4736. },
  4737. { /* MCP51 Ethernet Controller */
  4738. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
  4739. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
  4740. },
  4741. { /* MCP51 Ethernet Controller */
  4742. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
  4743. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
  4744. },
  4745. { /* MCP55 Ethernet Controller */
  4746. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
  4747. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4748. },
  4749. { /* MCP55 Ethernet Controller */
  4750. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
  4751. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4752. },
  4753. { /* MCP61 Ethernet Controller */
  4754. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
  4755. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4756. },
  4757. { /* MCP61 Ethernet Controller */
  4758. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
  4759. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4760. },
  4761. { /* MCP61 Ethernet Controller */
  4762. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
  4763. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4764. },
  4765. { /* MCP61 Ethernet Controller */
  4766. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
  4767. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4768. },
  4769. { /* MCP65 Ethernet Controller */
  4770. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
  4771. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4772. },
  4773. { /* MCP65 Ethernet Controller */
  4774. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
  4775. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4776. },
  4777. { /* MCP65 Ethernet Controller */
  4778. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
  4779. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4780. },
  4781. { /* MCP65 Ethernet Controller */
  4782. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
  4783. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4784. },
  4785. { /* MCP67 Ethernet Controller */
  4786. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
  4787. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4788. },
  4789. { /* MCP67 Ethernet Controller */
  4790. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
  4791. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4792. },
  4793. { /* MCP67 Ethernet Controller */
  4794. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
  4795. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4796. },
  4797. { /* MCP67 Ethernet Controller */
  4798. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
  4799. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
  4800. },
  4801. {0,},
  4802. };
  4803. static struct pci_driver driver = {
  4804. .name = "forcedeth",
  4805. .id_table = pci_tbl,
  4806. .probe = nv_probe,
  4807. .remove = __devexit_p(nv_remove),
  4808. .suspend = nv_suspend,
  4809. .resume = nv_resume,
  4810. };
  4811. static int __init init_nic(void)
  4812. {
  4813. printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
  4814. return pci_register_driver(&driver);
  4815. }
  4816. static void __exit exit_nic(void)
  4817. {
  4818. pci_unregister_driver(&driver);
  4819. }
  4820. module_param(max_interrupt_work, int, 0);
  4821. MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
  4822. module_param(optimization_mode, int, 0);
  4823. MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
  4824. module_param(poll_interval, int, 0);
  4825. MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
  4826. module_param(msi, int, 0);
  4827. MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
  4828. module_param(msix, int, 0);
  4829. MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
  4830. module_param(dma_64bit, int, 0);
  4831. MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
  4832. MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
  4833. MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
  4834. MODULE_LICENSE("GPL");
  4835. MODULE_DEVICE_TABLE(pci, pci_tbl);
  4836. module_init(init_nic);
  4837. module_exit(exit_nic);