fec.h 6.9 KB

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  1. /****************************************************************************/
  2. /*
  3. * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
  4. * processors.
  5. *
  6. * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
  7. * (C) Copyright 2000-2001, Lineo (www.lineo.com)
  8. */
  9. /****************************************************************************/
  10. #ifndef FEC_H
  11. #define FEC_H
  12. /****************************************************************************/
  13. #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
  14. defined(CONFIG_M520x) || defined(CONFIG_M532x)
  15. /*
  16. * Just figures, Motorola would have to change the offsets for
  17. * registers in the same peripheral device on different models
  18. * of the ColdFire!
  19. */
  20. typedef struct fec {
  21. unsigned long fec_reserved0;
  22. unsigned long fec_ievent; /* Interrupt event reg */
  23. unsigned long fec_imask; /* Interrupt mask reg */
  24. unsigned long fec_reserved1;
  25. unsigned long fec_r_des_active; /* Receive descriptor reg */
  26. unsigned long fec_x_des_active; /* Transmit descriptor reg */
  27. unsigned long fec_reserved2[3];
  28. unsigned long fec_ecntrl; /* Ethernet control reg */
  29. unsigned long fec_reserved3[6];
  30. unsigned long fec_mii_data; /* MII manage frame reg */
  31. unsigned long fec_mii_speed; /* MII speed control reg */
  32. unsigned long fec_reserved4[7];
  33. unsigned long fec_mib_ctrlstat; /* MIB control/status reg */
  34. unsigned long fec_reserved5[7];
  35. unsigned long fec_r_cntrl; /* Receive control reg */
  36. unsigned long fec_reserved6[15];
  37. unsigned long fec_x_cntrl; /* Transmit Control reg */
  38. unsigned long fec_reserved7[7];
  39. unsigned long fec_addr_low; /* Low 32bits MAC address */
  40. unsigned long fec_addr_high; /* High 16bits MAC address */
  41. unsigned long fec_opd; /* Opcode + Pause duration */
  42. unsigned long fec_reserved8[10];
  43. unsigned long fec_hash_table_high; /* High 32bits hash table */
  44. unsigned long fec_hash_table_low; /* Low 32bits hash table */
  45. unsigned long fec_grp_hash_table_high;/* High 32bits hash table */
  46. unsigned long fec_grp_hash_table_low; /* Low 32bits hash table */
  47. unsigned long fec_reserved9[7];
  48. unsigned long fec_x_wmrk; /* FIFO transmit water mark */
  49. unsigned long fec_reserved10;
  50. unsigned long fec_r_bound; /* FIFO receive bound reg */
  51. unsigned long fec_r_fstart; /* FIFO receive start reg */
  52. unsigned long fec_reserved11[11];
  53. unsigned long fec_r_des_start; /* Receive descriptor ring */
  54. unsigned long fec_x_des_start; /* Transmit descriptor ring */
  55. unsigned long fec_r_buff_size; /* Maximum receive buff size */
  56. } fec_t;
  57. #else
  58. /*
  59. * Define device register set address map.
  60. */
  61. typedef struct fec {
  62. unsigned long fec_ecntrl; /* Ethernet control reg */
  63. unsigned long fec_ievent; /* Interrupt even reg */
  64. unsigned long fec_imask; /* Interrupt mask reg */
  65. unsigned long fec_ivec; /* Interrupt vec status reg */
  66. unsigned long fec_r_des_active; /* Receive descriptor reg */
  67. unsigned long fec_x_des_active; /* Transmit descriptor reg */
  68. unsigned long fec_reserved1[10];
  69. unsigned long fec_mii_data; /* MII manage frame reg */
  70. unsigned long fec_mii_speed; /* MII speed control reg */
  71. unsigned long fec_reserved2[17];
  72. unsigned long fec_r_bound; /* FIFO receive bound reg */
  73. unsigned long fec_r_fstart; /* FIFO receive start reg */
  74. unsigned long fec_reserved3[4];
  75. unsigned long fec_x_wmrk; /* FIFO transmit water mark */
  76. unsigned long fec_reserved4;
  77. unsigned long fec_x_fstart; /* FIFO transmit start reg */
  78. unsigned long fec_reserved5[21];
  79. unsigned long fec_r_cntrl; /* Receive control reg */
  80. unsigned long fec_max_frm_len; /* Maximum frame length reg */
  81. unsigned long fec_reserved6[14];
  82. unsigned long fec_x_cntrl; /* Transmit Control reg */
  83. unsigned long fec_reserved7[158];
  84. unsigned long fec_addr_low; /* Low 32bits MAC address */
  85. unsigned long fec_addr_high; /* High 16bits MAC address */
  86. unsigned long fec_hash_table_high; /* High 32bits hash table */
  87. unsigned long fec_hash_table_low; /* Low 32bits hash table */
  88. unsigned long fec_r_des_start; /* Receive descriptor ring */
  89. unsigned long fec_x_des_start; /* Transmit descriptor ring */
  90. unsigned long fec_r_buff_size; /* Maximum receive buff size */
  91. unsigned long reserved8[9];
  92. unsigned long fec_fifo_ram[112]; /* FIFO RAM buffer */
  93. } fec_t;
  94. #endif /* CONFIG_M5272 */
  95. /*
  96. * Define the buffer descriptor structure.
  97. */
  98. typedef struct bufdesc {
  99. unsigned short cbd_sc; /* Control and status info */
  100. unsigned short cbd_datlen; /* Data length */
  101. unsigned long cbd_bufaddr; /* Buffer address */
  102. } cbd_t;
  103. /*
  104. * The following definitions courtesy of commproc.h, which where
  105. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
  106. */
  107. #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
  108. #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
  109. #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
  110. #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
  111. #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
  112. #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
  113. #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
  114. #define BD_SC_BR ((ushort)0x0020) /* Break received */
  115. #define BD_SC_FR ((ushort)0x0010) /* Framing error */
  116. #define BD_SC_PR ((ushort)0x0008) /* Parity error */
  117. #define BD_SC_OV ((ushort)0x0002) /* Overrun */
  118. #define BD_SC_CD ((ushort)0x0001) /* ?? */
  119. /* Buffer descriptor control/status used by Ethernet receive.
  120. */
  121. #define BD_ENET_RX_EMPTY ((ushort)0x8000)
  122. #define BD_ENET_RX_WRAP ((ushort)0x2000)
  123. #define BD_ENET_RX_INTR ((ushort)0x1000)
  124. #define BD_ENET_RX_LAST ((ushort)0x0800)
  125. #define BD_ENET_RX_FIRST ((ushort)0x0400)
  126. #define BD_ENET_RX_MISS ((ushort)0x0100)
  127. #define BD_ENET_RX_LG ((ushort)0x0020)
  128. #define BD_ENET_RX_NO ((ushort)0x0010)
  129. #define BD_ENET_RX_SH ((ushort)0x0008)
  130. #define BD_ENET_RX_CR ((ushort)0x0004)
  131. #define BD_ENET_RX_OV ((ushort)0x0002)
  132. #define BD_ENET_RX_CL ((ushort)0x0001)
  133. #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
  134. /* Buffer descriptor control/status used by Ethernet transmit.
  135. */
  136. #define BD_ENET_TX_READY ((ushort)0x8000)
  137. #define BD_ENET_TX_PAD ((ushort)0x4000)
  138. #define BD_ENET_TX_WRAP ((ushort)0x2000)
  139. #define BD_ENET_TX_INTR ((ushort)0x1000)
  140. #define BD_ENET_TX_LAST ((ushort)0x0800)
  141. #define BD_ENET_TX_TC ((ushort)0x0400)
  142. #define BD_ENET_TX_DEF ((ushort)0x0200)
  143. #define BD_ENET_TX_HB ((ushort)0x0100)
  144. #define BD_ENET_TX_LC ((ushort)0x0080)
  145. #define BD_ENET_TX_RL ((ushort)0x0040)
  146. #define BD_ENET_TX_RCMASK ((ushort)0x003c)
  147. #define BD_ENET_TX_UN ((ushort)0x0002)
  148. #define BD_ENET_TX_CSL ((ushort)0x0001)
  149. #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
  150. /****************************************************************************/
  151. #endif /* FEC_H */