fec.c 67 KB

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  1. /*
  2. * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
  3. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  4. *
  5. * This version of the driver is specific to the FADS implementation,
  6. * since the board contains control registers external to the processor
  7. * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
  8. * describes connections using the internal parallel port I/O, which
  9. * is basically all of Port D.
  10. *
  11. * Right now, I am very wasteful with the buffers. I allocate memory
  12. * pages and then divide them into 2K frame buffers. This way I know I
  13. * have buffers large enough to hold one frame within one buffer descriptor.
  14. * Once I get this working, I will use 64 or 128 byte CPM buffers, which
  15. * will be much more memory efficient and will easily handle lots of
  16. * small packets.
  17. *
  18. * Much better multiple PHY support by Magnus Damm.
  19. * Copyright (c) 2000 Ericsson Radio Systems AB.
  20. *
  21. * Support for FEC controller of ColdFire processors.
  22. * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
  23. *
  24. * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
  25. * Copyright (c) 2004-2006 Macq Electronique SA.
  26. */
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/string.h>
  30. #include <linux/ptrace.h>
  31. #include <linux/errno.h>
  32. #include <linux/ioport.h>
  33. #include <linux/slab.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/pci.h>
  36. #include <linux/init.h>
  37. #include <linux/delay.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/skbuff.h>
  41. #include <linux/spinlock.h>
  42. #include <linux/workqueue.h>
  43. #include <linux/bitops.h>
  44. #include <asm/irq.h>
  45. #include <asm/uaccess.h>
  46. #include <asm/io.h>
  47. #include <asm/pgtable.h>
  48. #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
  49. defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
  50. defined(CONFIG_M520x) || defined(CONFIG_M532x)
  51. #include <asm/coldfire.h>
  52. #include <asm/mcfsim.h>
  53. #include "fec.h"
  54. #else
  55. #include <asm/8xx_immap.h>
  56. #include <asm/mpc8xx.h>
  57. #include "commproc.h"
  58. #endif
  59. #if defined(CONFIG_FEC2)
  60. #define FEC_MAX_PORTS 2
  61. #else
  62. #define FEC_MAX_PORTS 1
  63. #endif
  64. /*
  65. * Define the fixed address of the FEC hardware.
  66. */
  67. static unsigned int fec_hw[] = {
  68. #if defined(CONFIG_M5272)
  69. (MCF_MBAR + 0x840),
  70. #elif defined(CONFIG_M527x)
  71. (MCF_MBAR + 0x1000),
  72. (MCF_MBAR + 0x1800),
  73. #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
  74. (MCF_MBAR + 0x1000),
  75. #elif defined(CONFIG_M520x)
  76. (MCF_MBAR+0x30000),
  77. #elif defined(CONFIG_M532x)
  78. (MCF_MBAR+0xfc030000),
  79. #else
  80. &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
  81. #endif
  82. };
  83. static unsigned char fec_mac_default[] = {
  84. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  85. };
  86. /*
  87. * Some hardware gets it MAC address out of local flash memory.
  88. * if this is non-zero then assume it is the address to get MAC from.
  89. */
  90. #if defined(CONFIG_NETtel)
  91. #define FEC_FLASHMAC 0xf0006006
  92. #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
  93. #define FEC_FLASHMAC 0xf0006000
  94. #elif defined (CONFIG_MTD_KeyTechnology)
  95. #define FEC_FLASHMAC 0xffe04000
  96. #elif defined(CONFIG_CANCam)
  97. #define FEC_FLASHMAC 0xf0020000
  98. #elif defined (CONFIG_M5272C3)
  99. #define FEC_FLASHMAC (0xffe04000 + 4)
  100. #elif defined(CONFIG_MOD5272)
  101. #define FEC_FLASHMAC 0xffc0406b
  102. #else
  103. #define FEC_FLASHMAC 0
  104. #endif
  105. /* Forward declarations of some structures to support different PHYs
  106. */
  107. typedef struct {
  108. uint mii_data;
  109. void (*funct)(uint mii_reg, struct net_device *dev);
  110. } phy_cmd_t;
  111. typedef struct {
  112. uint id;
  113. char *name;
  114. const phy_cmd_t *config;
  115. const phy_cmd_t *startup;
  116. const phy_cmd_t *ack_int;
  117. const phy_cmd_t *shutdown;
  118. } phy_info_t;
  119. /* The number of Tx and Rx buffers. These are allocated from the page
  120. * pool. The code may assume these are power of two, so it it best
  121. * to keep them that size.
  122. * We don't need to allocate pages for the transmitter. We just use
  123. * the skbuffer directly.
  124. */
  125. #define FEC_ENET_RX_PAGES 8
  126. #define FEC_ENET_RX_FRSIZE 2048
  127. #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
  128. #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
  129. #define FEC_ENET_TX_FRSIZE 2048
  130. #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
  131. #define TX_RING_SIZE 16 /* Must be power of two */
  132. #define TX_RING_MOD_MASK 15 /* for this to work */
  133. #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
  134. #error "FEC: descriptor ring size constants too large"
  135. #endif
  136. /* Interrupt events/masks.
  137. */
  138. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  139. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  140. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  141. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  142. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  143. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  144. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  145. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  146. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  147. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  148. /* The FEC stores dest/src/type, data, and checksum for receive packets.
  149. */
  150. #define PKT_MAXBUF_SIZE 1518
  151. #define PKT_MINBUF_SIZE 64
  152. #define PKT_MAXBLR_SIZE 1520
  153. /*
  154. * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
  155. * size bits. Other FEC hardware does not, so we need to take that into
  156. * account when setting it.
  157. */
  158. #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
  159. defined(CONFIG_M520x) || defined(CONFIG_M532x)
  160. #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
  161. #else
  162. #define OPT_FRAME_SIZE 0
  163. #endif
  164. /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
  165. * tx_bd_base always point to the base of the buffer descriptors. The
  166. * cur_rx and cur_tx point to the currently available buffer.
  167. * The dirty_tx tracks the current buffer that is being sent by the
  168. * controller. The cur_tx and dirty_tx are equal under both completely
  169. * empty and completely full conditions. The empty/ready indicator in
  170. * the buffer descriptor determines the actual condition.
  171. */
  172. struct fec_enet_private {
  173. /* Hardware registers of the FEC device */
  174. volatile fec_t *hwp;
  175. /* The saved address of a sent-in-place packet/buffer, for skfree(). */
  176. unsigned char *tx_bounce[TX_RING_SIZE];
  177. struct sk_buff* tx_skbuff[TX_RING_SIZE];
  178. ushort skb_cur;
  179. ushort skb_dirty;
  180. /* CPM dual port RAM relative addresses.
  181. */
  182. cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
  183. cbd_t *tx_bd_base;
  184. cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
  185. cbd_t *dirty_tx; /* The ring entries to be free()ed. */
  186. struct net_device_stats stats;
  187. uint tx_full;
  188. spinlock_t lock;
  189. uint phy_id;
  190. uint phy_id_done;
  191. uint phy_status;
  192. uint phy_speed;
  193. phy_info_t const *phy;
  194. struct work_struct phy_task;
  195. uint sequence_done;
  196. uint mii_phy_task_queued;
  197. uint phy_addr;
  198. int index;
  199. int opened;
  200. int link;
  201. int old_link;
  202. int full_duplex;
  203. };
  204. static int fec_enet_open(struct net_device *dev);
  205. static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
  206. static void fec_enet_mii(struct net_device *dev);
  207. static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
  208. static void fec_enet_tx(struct net_device *dev);
  209. static void fec_enet_rx(struct net_device *dev);
  210. static int fec_enet_close(struct net_device *dev);
  211. static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
  212. static void set_multicast_list(struct net_device *dev);
  213. static void fec_restart(struct net_device *dev, int duplex);
  214. static void fec_stop(struct net_device *dev);
  215. static void fec_set_mac_address(struct net_device *dev);
  216. /* MII processing. We keep this as simple as possible. Requests are
  217. * placed on the list (if there is room). When the request is finished
  218. * by the MII, an optional function may be called.
  219. */
  220. typedef struct mii_list {
  221. uint mii_regval;
  222. void (*mii_func)(uint val, struct net_device *dev);
  223. struct mii_list *mii_next;
  224. } mii_list_t;
  225. #define NMII 20
  226. static mii_list_t mii_cmds[NMII];
  227. static mii_list_t *mii_free;
  228. static mii_list_t *mii_head;
  229. static mii_list_t *mii_tail;
  230. static int mii_queue(struct net_device *dev, int request,
  231. void (*func)(uint, struct net_device *));
  232. /* Make MII read/write commands for the FEC.
  233. */
  234. #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
  235. #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
  236. (VAL & 0xffff))
  237. #define mk_mii_end 0
  238. /* Transmitter timeout.
  239. */
  240. #define TX_TIMEOUT (2*HZ)
  241. /* Register definitions for the PHY.
  242. */
  243. #define MII_REG_CR 0 /* Control Register */
  244. #define MII_REG_SR 1 /* Status Register */
  245. #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
  246. #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
  247. #define MII_REG_ANAR 4 /* A-N Advertisement Register */
  248. #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
  249. #define MII_REG_ANER 6 /* A-N Expansion Register */
  250. #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
  251. #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
  252. /* values for phy_status */
  253. #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
  254. #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
  255. #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
  256. #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
  257. #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
  258. #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
  259. #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
  260. #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
  261. #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
  262. #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
  263. #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
  264. #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
  265. #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
  266. #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
  267. #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
  268. static int
  269. fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
  270. {
  271. struct fec_enet_private *fep;
  272. volatile fec_t *fecp;
  273. volatile cbd_t *bdp;
  274. unsigned short status;
  275. fep = netdev_priv(dev);
  276. fecp = (volatile fec_t*)dev->base_addr;
  277. if (!fep->link) {
  278. /* Link is down or autonegotiation is in progress. */
  279. return 1;
  280. }
  281. /* Fill in a Tx ring entry */
  282. bdp = fep->cur_tx;
  283. status = bdp->cbd_sc;
  284. #ifndef final_version
  285. if (status & BD_ENET_TX_READY) {
  286. /* Ooops. All transmit buffers are full. Bail out.
  287. * This should not happen, since dev->tbusy should be set.
  288. */
  289. printk("%s: tx queue full!.\n", dev->name);
  290. return 1;
  291. }
  292. #endif
  293. /* Clear all of the status flags.
  294. */
  295. status &= ~BD_ENET_TX_STATS;
  296. /* Set buffer length and buffer pointer.
  297. */
  298. bdp->cbd_bufaddr = __pa(skb->data);
  299. bdp->cbd_datlen = skb->len;
  300. /*
  301. * On some FEC implementations data must be aligned on
  302. * 4-byte boundaries. Use bounce buffers to copy data
  303. * and get it aligned. Ugh.
  304. */
  305. if (bdp->cbd_bufaddr & 0x3) {
  306. unsigned int index;
  307. index = bdp - fep->tx_bd_base;
  308. memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
  309. bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
  310. }
  311. /* Save skb pointer.
  312. */
  313. fep->tx_skbuff[fep->skb_cur] = skb;
  314. fep->stats.tx_bytes += skb->len;
  315. fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
  316. /* Push the data cache so the CPM does not get stale memory
  317. * data.
  318. */
  319. flush_dcache_range((unsigned long)skb->data,
  320. (unsigned long)skb->data + skb->len);
  321. spin_lock_irq(&fep->lock);
  322. /* Send it on its way. Tell FEC it's ready, interrupt when done,
  323. * it's the last BD of the frame, and to put the CRC on the end.
  324. */
  325. status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
  326. | BD_ENET_TX_LAST | BD_ENET_TX_TC);
  327. bdp->cbd_sc = status;
  328. dev->trans_start = jiffies;
  329. /* Trigger transmission start */
  330. fecp->fec_x_des_active = 0;
  331. /* If this was the last BD in the ring, start at the beginning again.
  332. */
  333. if (status & BD_ENET_TX_WRAP) {
  334. bdp = fep->tx_bd_base;
  335. } else {
  336. bdp++;
  337. }
  338. if (bdp == fep->dirty_tx) {
  339. fep->tx_full = 1;
  340. netif_stop_queue(dev);
  341. }
  342. fep->cur_tx = (cbd_t *)bdp;
  343. spin_unlock_irq(&fep->lock);
  344. return 0;
  345. }
  346. static void
  347. fec_timeout(struct net_device *dev)
  348. {
  349. struct fec_enet_private *fep = netdev_priv(dev);
  350. printk("%s: transmit timed out.\n", dev->name);
  351. fep->stats.tx_errors++;
  352. #ifndef final_version
  353. {
  354. int i;
  355. cbd_t *bdp;
  356. printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
  357. (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
  358. (unsigned long)fep->dirty_tx,
  359. (unsigned long)fep->cur_rx);
  360. bdp = fep->tx_bd_base;
  361. printk(" tx: %u buffers\n", TX_RING_SIZE);
  362. for (i = 0 ; i < TX_RING_SIZE; i++) {
  363. printk(" %08x: %04x %04x %08x\n",
  364. (uint) bdp,
  365. bdp->cbd_sc,
  366. bdp->cbd_datlen,
  367. (int) bdp->cbd_bufaddr);
  368. bdp++;
  369. }
  370. bdp = fep->rx_bd_base;
  371. printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
  372. for (i = 0 ; i < RX_RING_SIZE; i++) {
  373. printk(" %08x: %04x %04x %08x\n",
  374. (uint) bdp,
  375. bdp->cbd_sc,
  376. bdp->cbd_datlen,
  377. (int) bdp->cbd_bufaddr);
  378. bdp++;
  379. }
  380. }
  381. #endif
  382. fec_restart(dev, fep->full_duplex);
  383. netif_wake_queue(dev);
  384. }
  385. /* The interrupt handler.
  386. * This is called from the MPC core interrupt.
  387. */
  388. static irqreturn_t
  389. fec_enet_interrupt(int irq, void * dev_id)
  390. {
  391. struct net_device *dev = dev_id;
  392. volatile fec_t *fecp;
  393. uint int_events;
  394. int handled = 0;
  395. fecp = (volatile fec_t*)dev->base_addr;
  396. /* Get the interrupt events that caused us to be here.
  397. */
  398. while ((int_events = fecp->fec_ievent) != 0) {
  399. fecp->fec_ievent = int_events;
  400. /* Handle receive event in its own function.
  401. */
  402. if (int_events & FEC_ENET_RXF) {
  403. handled = 1;
  404. fec_enet_rx(dev);
  405. }
  406. /* Transmit OK, or non-fatal error. Update the buffer
  407. descriptors. FEC handles all errors, we just discover
  408. them as part of the transmit process.
  409. */
  410. if (int_events & FEC_ENET_TXF) {
  411. handled = 1;
  412. fec_enet_tx(dev);
  413. }
  414. if (int_events & FEC_ENET_MII) {
  415. handled = 1;
  416. fec_enet_mii(dev);
  417. }
  418. }
  419. return IRQ_RETVAL(handled);
  420. }
  421. static void
  422. fec_enet_tx(struct net_device *dev)
  423. {
  424. struct fec_enet_private *fep;
  425. volatile cbd_t *bdp;
  426. unsigned short status;
  427. struct sk_buff *skb;
  428. fep = netdev_priv(dev);
  429. spin_lock(&fep->lock);
  430. bdp = fep->dirty_tx;
  431. while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
  432. if (bdp == fep->cur_tx && fep->tx_full == 0) break;
  433. skb = fep->tx_skbuff[fep->skb_dirty];
  434. /* Check for errors. */
  435. if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
  436. BD_ENET_TX_RL | BD_ENET_TX_UN |
  437. BD_ENET_TX_CSL)) {
  438. fep->stats.tx_errors++;
  439. if (status & BD_ENET_TX_HB) /* No heartbeat */
  440. fep->stats.tx_heartbeat_errors++;
  441. if (status & BD_ENET_TX_LC) /* Late collision */
  442. fep->stats.tx_window_errors++;
  443. if (status & BD_ENET_TX_RL) /* Retrans limit */
  444. fep->stats.tx_aborted_errors++;
  445. if (status & BD_ENET_TX_UN) /* Underrun */
  446. fep->stats.tx_fifo_errors++;
  447. if (status & BD_ENET_TX_CSL) /* Carrier lost */
  448. fep->stats.tx_carrier_errors++;
  449. } else {
  450. fep->stats.tx_packets++;
  451. }
  452. #ifndef final_version
  453. if (status & BD_ENET_TX_READY)
  454. printk("HEY! Enet xmit interrupt and TX_READY.\n");
  455. #endif
  456. /* Deferred means some collisions occurred during transmit,
  457. * but we eventually sent the packet OK.
  458. */
  459. if (status & BD_ENET_TX_DEF)
  460. fep->stats.collisions++;
  461. /* Free the sk buffer associated with this last transmit.
  462. */
  463. dev_kfree_skb_any(skb);
  464. fep->tx_skbuff[fep->skb_dirty] = NULL;
  465. fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
  466. /* Update pointer to next buffer descriptor to be transmitted.
  467. */
  468. if (status & BD_ENET_TX_WRAP)
  469. bdp = fep->tx_bd_base;
  470. else
  471. bdp++;
  472. /* Since we have freed up a buffer, the ring is no longer
  473. * full.
  474. */
  475. if (fep->tx_full) {
  476. fep->tx_full = 0;
  477. if (netif_queue_stopped(dev))
  478. netif_wake_queue(dev);
  479. }
  480. }
  481. fep->dirty_tx = (cbd_t *)bdp;
  482. spin_unlock(&fep->lock);
  483. }
  484. /* During a receive, the cur_rx points to the current incoming buffer.
  485. * When we update through the ring, if the next incoming buffer has
  486. * not been given to the system, we just set the empty indicator,
  487. * effectively tossing the packet.
  488. */
  489. static void
  490. fec_enet_rx(struct net_device *dev)
  491. {
  492. struct fec_enet_private *fep;
  493. volatile fec_t *fecp;
  494. volatile cbd_t *bdp;
  495. unsigned short status;
  496. struct sk_buff *skb;
  497. ushort pkt_len;
  498. __u8 *data;
  499. #ifdef CONFIG_M532x
  500. flush_cache_all();
  501. #endif
  502. fep = netdev_priv(dev);
  503. fecp = (volatile fec_t*)dev->base_addr;
  504. /* First, grab all of the stats for the incoming packet.
  505. * These get messed up if we get called due to a busy condition.
  506. */
  507. bdp = fep->cur_rx;
  508. while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
  509. #ifndef final_version
  510. /* Since we have allocated space to hold a complete frame,
  511. * the last indicator should be set.
  512. */
  513. if ((status & BD_ENET_RX_LAST) == 0)
  514. printk("FEC ENET: rcv is not +last\n");
  515. #endif
  516. if (!fep->opened)
  517. goto rx_processing_done;
  518. /* Check for errors. */
  519. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
  520. BD_ENET_RX_CR | BD_ENET_RX_OV)) {
  521. fep->stats.rx_errors++;
  522. if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
  523. /* Frame too long or too short. */
  524. fep->stats.rx_length_errors++;
  525. }
  526. if (status & BD_ENET_RX_NO) /* Frame alignment */
  527. fep->stats.rx_frame_errors++;
  528. if (status & BD_ENET_RX_CR) /* CRC Error */
  529. fep->stats.rx_crc_errors++;
  530. if (status & BD_ENET_RX_OV) /* FIFO overrun */
  531. fep->stats.rx_fifo_errors++;
  532. }
  533. /* Report late collisions as a frame error.
  534. * On this error, the BD is closed, but we don't know what we
  535. * have in the buffer. So, just drop this frame on the floor.
  536. */
  537. if (status & BD_ENET_RX_CL) {
  538. fep->stats.rx_errors++;
  539. fep->stats.rx_frame_errors++;
  540. goto rx_processing_done;
  541. }
  542. /* Process the incoming frame.
  543. */
  544. fep->stats.rx_packets++;
  545. pkt_len = bdp->cbd_datlen;
  546. fep->stats.rx_bytes += pkt_len;
  547. data = (__u8*)__va(bdp->cbd_bufaddr);
  548. /* This does 16 byte alignment, exactly what we need.
  549. * The packet length includes FCS, but we don't want to
  550. * include that when passing upstream as it messes up
  551. * bridging applications.
  552. */
  553. skb = dev_alloc_skb(pkt_len-4);
  554. if (skb == NULL) {
  555. printk("%s: Memory squeeze, dropping packet.\n", dev->name);
  556. fep->stats.rx_dropped++;
  557. } else {
  558. skb->dev = dev;
  559. skb_put(skb,pkt_len-4); /* Make room */
  560. eth_copy_and_sum(skb, data, pkt_len-4, 0);
  561. skb->protocol=eth_type_trans(skb,dev);
  562. netif_rx(skb);
  563. }
  564. rx_processing_done:
  565. /* Clear the status flags for this buffer.
  566. */
  567. status &= ~BD_ENET_RX_STATS;
  568. /* Mark the buffer empty.
  569. */
  570. status |= BD_ENET_RX_EMPTY;
  571. bdp->cbd_sc = status;
  572. /* Update BD pointer to next entry.
  573. */
  574. if (status & BD_ENET_RX_WRAP)
  575. bdp = fep->rx_bd_base;
  576. else
  577. bdp++;
  578. #if 1
  579. /* Doing this here will keep the FEC running while we process
  580. * incoming frames. On a heavily loaded network, we should be
  581. * able to keep up at the expense of system resources.
  582. */
  583. fecp->fec_r_des_active = 0;
  584. #endif
  585. } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
  586. fep->cur_rx = (cbd_t *)bdp;
  587. #if 0
  588. /* Doing this here will allow us to process all frames in the
  589. * ring before the FEC is allowed to put more there. On a heavily
  590. * loaded network, some frames may be lost. Unfortunately, this
  591. * increases the interrupt overhead since we can potentially work
  592. * our way back to the interrupt return only to come right back
  593. * here.
  594. */
  595. fecp->fec_r_des_active = 0;
  596. #endif
  597. }
  598. /* called from interrupt context */
  599. static void
  600. fec_enet_mii(struct net_device *dev)
  601. {
  602. struct fec_enet_private *fep;
  603. volatile fec_t *ep;
  604. mii_list_t *mip;
  605. uint mii_reg;
  606. fep = netdev_priv(dev);
  607. ep = fep->hwp;
  608. mii_reg = ep->fec_mii_data;
  609. spin_lock(&fep->lock);
  610. if ((mip = mii_head) == NULL) {
  611. printk("MII and no head!\n");
  612. goto unlock;
  613. }
  614. if (mip->mii_func != NULL)
  615. (*(mip->mii_func))(mii_reg, dev);
  616. mii_head = mip->mii_next;
  617. mip->mii_next = mii_free;
  618. mii_free = mip;
  619. if ((mip = mii_head) != NULL)
  620. ep->fec_mii_data = mip->mii_regval;
  621. unlock:
  622. spin_unlock(&fep->lock);
  623. }
  624. static int
  625. mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
  626. {
  627. struct fec_enet_private *fep;
  628. unsigned long flags;
  629. mii_list_t *mip;
  630. int retval;
  631. /* Add PHY address to register command.
  632. */
  633. fep = netdev_priv(dev);
  634. regval |= fep->phy_addr << 23;
  635. retval = 0;
  636. spin_lock_irqsave(&fep->lock,flags);
  637. if ((mip = mii_free) != NULL) {
  638. mii_free = mip->mii_next;
  639. mip->mii_regval = regval;
  640. mip->mii_func = func;
  641. mip->mii_next = NULL;
  642. if (mii_head) {
  643. mii_tail->mii_next = mip;
  644. mii_tail = mip;
  645. }
  646. else {
  647. mii_head = mii_tail = mip;
  648. fep->hwp->fec_mii_data = regval;
  649. }
  650. }
  651. else {
  652. retval = 1;
  653. }
  654. spin_unlock_irqrestore(&fep->lock,flags);
  655. return(retval);
  656. }
  657. static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
  658. {
  659. int k;
  660. if(!c)
  661. return;
  662. for(k = 0; (c+k)->mii_data != mk_mii_end; k++) {
  663. mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
  664. }
  665. }
  666. static void mii_parse_sr(uint mii_reg, struct net_device *dev)
  667. {
  668. struct fec_enet_private *fep = netdev_priv(dev);
  669. volatile uint *s = &(fep->phy_status);
  670. uint status;
  671. status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
  672. if (mii_reg & 0x0004)
  673. status |= PHY_STAT_LINK;
  674. if (mii_reg & 0x0010)
  675. status |= PHY_STAT_FAULT;
  676. if (mii_reg & 0x0020)
  677. status |= PHY_STAT_ANC;
  678. *s = status;
  679. }
  680. static void mii_parse_cr(uint mii_reg, struct net_device *dev)
  681. {
  682. struct fec_enet_private *fep = netdev_priv(dev);
  683. volatile uint *s = &(fep->phy_status);
  684. uint status;
  685. status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
  686. if (mii_reg & 0x1000)
  687. status |= PHY_CONF_ANE;
  688. if (mii_reg & 0x4000)
  689. status |= PHY_CONF_LOOP;
  690. *s = status;
  691. }
  692. static void mii_parse_anar(uint mii_reg, struct net_device *dev)
  693. {
  694. struct fec_enet_private *fep = netdev_priv(dev);
  695. volatile uint *s = &(fep->phy_status);
  696. uint status;
  697. status = *s & ~(PHY_CONF_SPMASK);
  698. if (mii_reg & 0x0020)
  699. status |= PHY_CONF_10HDX;
  700. if (mii_reg & 0x0040)
  701. status |= PHY_CONF_10FDX;
  702. if (mii_reg & 0x0080)
  703. status |= PHY_CONF_100HDX;
  704. if (mii_reg & 0x00100)
  705. status |= PHY_CONF_100FDX;
  706. *s = status;
  707. }
  708. /* ------------------------------------------------------------------------- */
  709. /* The Level one LXT970 is used by many boards */
  710. #define MII_LXT970_MIRROR 16 /* Mirror register */
  711. #define MII_LXT970_IER 17 /* Interrupt Enable Register */
  712. #define MII_LXT970_ISR 18 /* Interrupt Status Register */
  713. #define MII_LXT970_CONFIG 19 /* Configuration Register */
  714. #define MII_LXT970_CSR 20 /* Chip Status Register */
  715. static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
  716. {
  717. struct fec_enet_private *fep = netdev_priv(dev);
  718. volatile uint *s = &(fep->phy_status);
  719. uint status;
  720. status = *s & ~(PHY_STAT_SPMASK);
  721. if (mii_reg & 0x0800) {
  722. if (mii_reg & 0x1000)
  723. status |= PHY_STAT_100FDX;
  724. else
  725. status |= PHY_STAT_100HDX;
  726. } else {
  727. if (mii_reg & 0x1000)
  728. status |= PHY_STAT_10FDX;
  729. else
  730. status |= PHY_STAT_10HDX;
  731. }
  732. *s = status;
  733. }
  734. static phy_cmd_t const phy_cmd_lxt970_config[] = {
  735. { mk_mii_read(MII_REG_CR), mii_parse_cr },
  736. { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
  737. { mk_mii_end, }
  738. };
  739. static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
  740. { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
  741. { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
  742. { mk_mii_end, }
  743. };
  744. static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
  745. /* read SR and ISR to acknowledge */
  746. { mk_mii_read(MII_REG_SR), mii_parse_sr },
  747. { mk_mii_read(MII_LXT970_ISR), NULL },
  748. /* find out the current status */
  749. { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
  750. { mk_mii_end, }
  751. };
  752. static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
  753. { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
  754. { mk_mii_end, }
  755. };
  756. static phy_info_t const phy_info_lxt970 = {
  757. .id = 0x07810000,
  758. .name = "LXT970",
  759. .config = phy_cmd_lxt970_config,
  760. .startup = phy_cmd_lxt970_startup,
  761. .ack_int = phy_cmd_lxt970_ack_int,
  762. .shutdown = phy_cmd_lxt970_shutdown
  763. };
  764. /* ------------------------------------------------------------------------- */
  765. /* The Level one LXT971 is used on some of my custom boards */
  766. /* register definitions for the 971 */
  767. #define MII_LXT971_PCR 16 /* Port Control Register */
  768. #define MII_LXT971_SR2 17 /* Status Register 2 */
  769. #define MII_LXT971_IER 18 /* Interrupt Enable Register */
  770. #define MII_LXT971_ISR 19 /* Interrupt Status Register */
  771. #define MII_LXT971_LCR 20 /* LED Control Register */
  772. #define MII_LXT971_TCR 30 /* Transmit Control Register */
  773. /*
  774. * I had some nice ideas of running the MDIO faster...
  775. * The 971 should support 8MHz and I tried it, but things acted really
  776. * weird, so 2.5 MHz ought to be enough for anyone...
  777. */
  778. static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
  779. {
  780. struct fec_enet_private *fep = netdev_priv(dev);
  781. volatile uint *s = &(fep->phy_status);
  782. uint status;
  783. status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
  784. if (mii_reg & 0x0400) {
  785. fep->link = 1;
  786. status |= PHY_STAT_LINK;
  787. } else {
  788. fep->link = 0;
  789. }
  790. if (mii_reg & 0x0080)
  791. status |= PHY_STAT_ANC;
  792. if (mii_reg & 0x4000) {
  793. if (mii_reg & 0x0200)
  794. status |= PHY_STAT_100FDX;
  795. else
  796. status |= PHY_STAT_100HDX;
  797. } else {
  798. if (mii_reg & 0x0200)
  799. status |= PHY_STAT_10FDX;
  800. else
  801. status |= PHY_STAT_10HDX;
  802. }
  803. if (mii_reg & 0x0008)
  804. status |= PHY_STAT_FAULT;
  805. *s = status;
  806. }
  807. static phy_cmd_t const phy_cmd_lxt971_config[] = {
  808. /* limit to 10MBit because my prototype board
  809. * doesn't work with 100. */
  810. { mk_mii_read(MII_REG_CR), mii_parse_cr },
  811. { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
  812. { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
  813. { mk_mii_end, }
  814. };
  815. static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
  816. { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
  817. { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
  818. { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
  819. /* Somehow does the 971 tell me that the link is down
  820. * the first read after power-up.
  821. * read here to get a valid value in ack_int */
  822. { mk_mii_read(MII_REG_SR), mii_parse_sr },
  823. { mk_mii_end, }
  824. };
  825. static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
  826. /* acknowledge the int before reading status ! */
  827. { mk_mii_read(MII_LXT971_ISR), NULL },
  828. /* find out the current status */
  829. { mk_mii_read(MII_REG_SR), mii_parse_sr },
  830. { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
  831. { mk_mii_end, }
  832. };
  833. static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
  834. { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
  835. { mk_mii_end, }
  836. };
  837. static phy_info_t const phy_info_lxt971 = {
  838. .id = 0x0001378e,
  839. .name = "LXT971",
  840. .config = phy_cmd_lxt971_config,
  841. .startup = phy_cmd_lxt971_startup,
  842. .ack_int = phy_cmd_lxt971_ack_int,
  843. .shutdown = phy_cmd_lxt971_shutdown
  844. };
  845. /* ------------------------------------------------------------------------- */
  846. /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
  847. /* register definitions */
  848. #define MII_QS6612_MCR 17 /* Mode Control Register */
  849. #define MII_QS6612_FTR 27 /* Factory Test Register */
  850. #define MII_QS6612_MCO 28 /* Misc. Control Register */
  851. #define MII_QS6612_ISR 29 /* Interrupt Source Register */
  852. #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
  853. #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
  854. static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
  855. {
  856. struct fec_enet_private *fep = netdev_priv(dev);
  857. volatile uint *s = &(fep->phy_status);
  858. uint status;
  859. status = *s & ~(PHY_STAT_SPMASK);
  860. switch((mii_reg >> 2) & 7) {
  861. case 1: status |= PHY_STAT_10HDX; break;
  862. case 2: status |= PHY_STAT_100HDX; break;
  863. case 5: status |= PHY_STAT_10FDX; break;
  864. case 6: status |= PHY_STAT_100FDX; break;
  865. }
  866. *s = status;
  867. }
  868. static phy_cmd_t const phy_cmd_qs6612_config[] = {
  869. /* The PHY powers up isolated on the RPX,
  870. * so send a command to allow operation.
  871. */
  872. { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
  873. /* parse cr and anar to get some info */
  874. { mk_mii_read(MII_REG_CR), mii_parse_cr },
  875. { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
  876. { mk_mii_end, }
  877. };
  878. static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
  879. { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
  880. { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
  881. { mk_mii_end, }
  882. };
  883. static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
  884. /* we need to read ISR, SR and ANER to acknowledge */
  885. { mk_mii_read(MII_QS6612_ISR), NULL },
  886. { mk_mii_read(MII_REG_SR), mii_parse_sr },
  887. { mk_mii_read(MII_REG_ANER), NULL },
  888. /* read pcr to get info */
  889. { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
  890. { mk_mii_end, }
  891. };
  892. static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
  893. { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
  894. { mk_mii_end, }
  895. };
  896. static phy_info_t const phy_info_qs6612 = {
  897. .id = 0x00181440,
  898. .name = "QS6612",
  899. .config = phy_cmd_qs6612_config,
  900. .startup = phy_cmd_qs6612_startup,
  901. .ack_int = phy_cmd_qs6612_ack_int,
  902. .shutdown = phy_cmd_qs6612_shutdown
  903. };
  904. /* ------------------------------------------------------------------------- */
  905. /* AMD AM79C874 phy */
  906. /* register definitions for the 874 */
  907. #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
  908. #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
  909. #define MII_AM79C874_DR 18 /* Diagnostic Register */
  910. #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
  911. #define MII_AM79C874_MCR 21 /* ModeControl Register */
  912. #define MII_AM79C874_DC 23 /* Disconnect Counter */
  913. #define MII_AM79C874_REC 24 /* Recieve Error Counter */
  914. static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
  915. {
  916. struct fec_enet_private *fep = netdev_priv(dev);
  917. volatile uint *s = &(fep->phy_status);
  918. uint status;
  919. status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
  920. if (mii_reg & 0x0080)
  921. status |= PHY_STAT_ANC;
  922. if (mii_reg & 0x0400)
  923. status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
  924. else
  925. status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
  926. *s = status;
  927. }
  928. static phy_cmd_t const phy_cmd_am79c874_config[] = {
  929. { mk_mii_read(MII_REG_CR), mii_parse_cr },
  930. { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
  931. { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
  932. { mk_mii_end, }
  933. };
  934. static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
  935. { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
  936. { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
  937. { mk_mii_read(MII_REG_SR), mii_parse_sr },
  938. { mk_mii_end, }
  939. };
  940. static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
  941. /* find out the current status */
  942. { mk_mii_read(MII_REG_SR), mii_parse_sr },
  943. { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
  944. /* we only need to read ISR to acknowledge */
  945. { mk_mii_read(MII_AM79C874_ICSR), NULL },
  946. { mk_mii_end, }
  947. };
  948. static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
  949. { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
  950. { mk_mii_end, }
  951. };
  952. static phy_info_t const phy_info_am79c874 = {
  953. .id = 0x00022561,
  954. .name = "AM79C874",
  955. .config = phy_cmd_am79c874_config,
  956. .startup = phy_cmd_am79c874_startup,
  957. .ack_int = phy_cmd_am79c874_ack_int,
  958. .shutdown = phy_cmd_am79c874_shutdown
  959. };
  960. /* ------------------------------------------------------------------------- */
  961. /* Kendin KS8721BL phy */
  962. /* register definitions for the 8721 */
  963. #define MII_KS8721BL_RXERCR 21
  964. #define MII_KS8721BL_ICSR 22
  965. #define MII_KS8721BL_PHYCR 31
  966. static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
  967. { mk_mii_read(MII_REG_CR), mii_parse_cr },
  968. { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
  969. { mk_mii_end, }
  970. };
  971. static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
  972. { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
  973. { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
  974. { mk_mii_read(MII_REG_SR), mii_parse_sr },
  975. { mk_mii_end, }
  976. };
  977. static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
  978. /* find out the current status */
  979. { mk_mii_read(MII_REG_SR), mii_parse_sr },
  980. /* we only need to read ISR to acknowledge */
  981. { mk_mii_read(MII_KS8721BL_ICSR), NULL },
  982. { mk_mii_end, }
  983. };
  984. static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
  985. { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
  986. { mk_mii_end, }
  987. };
  988. static phy_info_t const phy_info_ks8721bl = {
  989. .id = 0x00022161,
  990. .name = "KS8721BL",
  991. .config = phy_cmd_ks8721bl_config,
  992. .startup = phy_cmd_ks8721bl_startup,
  993. .ack_int = phy_cmd_ks8721bl_ack_int,
  994. .shutdown = phy_cmd_ks8721bl_shutdown
  995. };
  996. /* ------------------------------------------------------------------------- */
  997. /* register definitions for the DP83848 */
  998. #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
  999. static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
  1000. {
  1001. struct fec_enet_private *fep = dev->priv;
  1002. volatile uint *s = &(fep->phy_status);
  1003. *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
  1004. /* Link up */
  1005. if (mii_reg & 0x0001) {
  1006. fep->link = 1;
  1007. *s |= PHY_STAT_LINK;
  1008. } else
  1009. fep->link = 0;
  1010. /* Status of link */
  1011. if (mii_reg & 0x0010) /* Autonegotioation complete */
  1012. *s |= PHY_STAT_ANC;
  1013. if (mii_reg & 0x0002) { /* 10MBps? */
  1014. if (mii_reg & 0x0004) /* Full Duplex? */
  1015. *s |= PHY_STAT_10FDX;
  1016. else
  1017. *s |= PHY_STAT_10HDX;
  1018. } else { /* 100 Mbps? */
  1019. if (mii_reg & 0x0004) /* Full Duplex? */
  1020. *s |= PHY_STAT_100FDX;
  1021. else
  1022. *s |= PHY_STAT_100HDX;
  1023. }
  1024. if (mii_reg & 0x0008)
  1025. *s |= PHY_STAT_FAULT;
  1026. }
  1027. static phy_info_t phy_info_dp83848= {
  1028. 0x020005c9,
  1029. "DP83848",
  1030. (const phy_cmd_t []) { /* config */
  1031. { mk_mii_read(MII_REG_CR), mii_parse_cr },
  1032. { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
  1033. { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
  1034. { mk_mii_end, }
  1035. },
  1036. (const phy_cmd_t []) { /* startup - enable interrupts */
  1037. { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
  1038. { mk_mii_read(MII_REG_SR), mii_parse_sr },
  1039. { mk_mii_end, }
  1040. },
  1041. (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
  1042. { mk_mii_end, }
  1043. },
  1044. (const phy_cmd_t []) { /* shutdown */
  1045. { mk_mii_end, }
  1046. },
  1047. };
  1048. /* ------------------------------------------------------------------------- */
  1049. static phy_info_t const * const phy_info[] = {
  1050. &phy_info_lxt970,
  1051. &phy_info_lxt971,
  1052. &phy_info_qs6612,
  1053. &phy_info_am79c874,
  1054. &phy_info_ks8721bl,
  1055. &phy_info_dp83848,
  1056. NULL
  1057. };
  1058. /* ------------------------------------------------------------------------- */
  1059. #if !defined(CONFIG_M532x)
  1060. #ifdef CONFIG_RPXCLASSIC
  1061. static void
  1062. mii_link_interrupt(void *dev_id);
  1063. #else
  1064. static irqreturn_t
  1065. mii_link_interrupt(int irq, void * dev_id);
  1066. #endif
  1067. #endif
  1068. #if defined(CONFIG_M5272)
  1069. /*
  1070. * Code specific to Coldfire 5272 setup.
  1071. */
  1072. static void __inline__ fec_request_intrs(struct net_device *dev)
  1073. {
  1074. volatile unsigned long *icrp;
  1075. static const struct idesc {
  1076. char *name;
  1077. unsigned short irq;
  1078. irq_handler_t handler;
  1079. } *idp, id[] = {
  1080. { "fec(RX)", 86, fec_enet_interrupt },
  1081. { "fec(TX)", 87, fec_enet_interrupt },
  1082. { "fec(OTHER)", 88, fec_enet_interrupt },
  1083. { "fec(MII)", 66, mii_link_interrupt },
  1084. { NULL },
  1085. };
  1086. /* Setup interrupt handlers. */
  1087. for (idp = id; idp->name; idp++) {
  1088. if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0)
  1089. printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
  1090. }
  1091. /* Unmask interrupt at ColdFire 5272 SIM */
  1092. icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
  1093. *icrp = 0x00000ddd;
  1094. icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
  1095. *icrp = (*icrp & 0x70777777) | 0x0d000000;
  1096. }
  1097. static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
  1098. {
  1099. volatile fec_t *fecp;
  1100. fecp = fep->hwp;
  1101. fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
  1102. fecp->fec_x_cntrl = 0x00;
  1103. /*
  1104. * Set MII speed to 2.5 MHz
  1105. * See 5272 manual section 11.5.8: MSCR
  1106. */
  1107. fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
  1108. fecp->fec_mii_speed = fep->phy_speed;
  1109. fec_restart(dev, 0);
  1110. }
  1111. static void __inline__ fec_get_mac(struct net_device *dev)
  1112. {
  1113. struct fec_enet_private *fep = netdev_priv(dev);
  1114. volatile fec_t *fecp;
  1115. unsigned char *iap, tmpaddr[ETH_ALEN];
  1116. fecp = fep->hwp;
  1117. if (FEC_FLASHMAC) {
  1118. /*
  1119. * Get MAC address from FLASH.
  1120. * If it is all 1's or 0's, use the default.
  1121. */
  1122. iap = (unsigned char *)FEC_FLASHMAC;
  1123. if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
  1124. (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
  1125. iap = fec_mac_default;
  1126. if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
  1127. (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
  1128. iap = fec_mac_default;
  1129. } else {
  1130. *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
  1131. *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
  1132. iap = &tmpaddr[0];
  1133. }
  1134. memcpy(dev->dev_addr, iap, ETH_ALEN);
  1135. /* Adjust MAC if using default MAC address */
  1136. if (iap == fec_mac_default)
  1137. dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
  1138. }
  1139. static void __inline__ fec_enable_phy_intr(void)
  1140. {
  1141. }
  1142. static void __inline__ fec_disable_phy_intr(void)
  1143. {
  1144. volatile unsigned long *icrp;
  1145. icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
  1146. *icrp = (*icrp & 0x70777777) | 0x08000000;
  1147. }
  1148. static void __inline__ fec_phy_ack_intr(void)
  1149. {
  1150. volatile unsigned long *icrp;
  1151. /* Acknowledge the interrupt */
  1152. icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
  1153. *icrp = (*icrp & 0x77777777) | 0x08000000;
  1154. }
  1155. static void __inline__ fec_localhw_setup(void)
  1156. {
  1157. }
  1158. /*
  1159. * Do not need to make region uncached on 5272.
  1160. */
  1161. static void __inline__ fec_uncache(unsigned long addr)
  1162. {
  1163. }
  1164. /* ------------------------------------------------------------------------- */
  1165. #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
  1166. /*
  1167. * Code specific to Coldfire 5230/5231/5232/5234/5235,
  1168. * the 5270/5271/5274/5275 and 5280/5282 setups.
  1169. */
  1170. static void __inline__ fec_request_intrs(struct net_device *dev)
  1171. {
  1172. struct fec_enet_private *fep;
  1173. int b;
  1174. static const struct idesc {
  1175. char *name;
  1176. unsigned short irq;
  1177. } *idp, id[] = {
  1178. { "fec(TXF)", 23 },
  1179. { "fec(TXB)", 24 },
  1180. { "fec(TXFIFO)", 25 },
  1181. { "fec(TXCR)", 26 },
  1182. { "fec(RXF)", 27 },
  1183. { "fec(RXB)", 28 },
  1184. { "fec(MII)", 29 },
  1185. { "fec(LC)", 30 },
  1186. { "fec(HBERR)", 31 },
  1187. { "fec(GRA)", 32 },
  1188. { "fec(EBERR)", 33 },
  1189. { "fec(BABT)", 34 },
  1190. { "fec(BABR)", 35 },
  1191. { NULL },
  1192. };
  1193. fep = netdev_priv(dev);
  1194. b = (fep->index) ? 128 : 64;
  1195. /* Setup interrupt handlers. */
  1196. for (idp = id; idp->name; idp++) {
  1197. if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0)
  1198. printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
  1199. }
  1200. /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
  1201. {
  1202. volatile unsigned char *icrp;
  1203. volatile unsigned long *imrp;
  1204. int i, ilip;
  1205. b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
  1206. icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
  1207. MCFINTC_ICR0);
  1208. for (i = 23, ilip = 0x28; (i < 36); i++)
  1209. icrp[i] = ilip--;
  1210. imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
  1211. MCFINTC_IMRH);
  1212. *imrp &= ~0x0000000f;
  1213. imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
  1214. MCFINTC_IMRL);
  1215. *imrp &= ~0xff800001;
  1216. }
  1217. #if defined(CONFIG_M528x)
  1218. /* Set up gpio outputs for MII lines */
  1219. {
  1220. volatile u16 *gpio_paspar;
  1221. volatile u8 *gpio_pehlpar;
  1222. gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
  1223. gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
  1224. *gpio_paspar |= 0x0f00;
  1225. *gpio_pehlpar = 0xc0;
  1226. }
  1227. #endif
  1228. }
  1229. static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
  1230. {
  1231. volatile fec_t *fecp;
  1232. fecp = fep->hwp;
  1233. fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
  1234. fecp->fec_x_cntrl = 0x00;
  1235. /*
  1236. * Set MII speed to 2.5 MHz
  1237. * See 5282 manual section 17.5.4.7: MSCR
  1238. */
  1239. fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
  1240. fecp->fec_mii_speed = fep->phy_speed;
  1241. fec_restart(dev, 0);
  1242. }
  1243. static void __inline__ fec_get_mac(struct net_device *dev)
  1244. {
  1245. struct fec_enet_private *fep = netdev_priv(dev);
  1246. volatile fec_t *fecp;
  1247. unsigned char *iap, tmpaddr[ETH_ALEN];
  1248. fecp = fep->hwp;
  1249. if (FEC_FLASHMAC) {
  1250. /*
  1251. * Get MAC address from FLASH.
  1252. * If it is all 1's or 0's, use the default.
  1253. */
  1254. iap = FEC_FLASHMAC;
  1255. if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
  1256. (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
  1257. iap = fec_mac_default;
  1258. if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
  1259. (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
  1260. iap = fec_mac_default;
  1261. } else {
  1262. *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
  1263. *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
  1264. iap = &tmpaddr[0];
  1265. }
  1266. memcpy(dev->dev_addr, iap, ETH_ALEN);
  1267. /* Adjust MAC if using default MAC address */
  1268. if (iap == fec_mac_default)
  1269. dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
  1270. }
  1271. static void __inline__ fec_enable_phy_intr(void)
  1272. {
  1273. }
  1274. static void __inline__ fec_disable_phy_intr(void)
  1275. {
  1276. }
  1277. static void __inline__ fec_phy_ack_intr(void)
  1278. {
  1279. }
  1280. static void __inline__ fec_localhw_setup(void)
  1281. {
  1282. }
  1283. /*
  1284. * Do not need to make region uncached on 5272.
  1285. */
  1286. static void __inline__ fec_uncache(unsigned long addr)
  1287. {
  1288. }
  1289. /* ------------------------------------------------------------------------- */
  1290. #elif defined(CONFIG_M520x)
  1291. /*
  1292. * Code specific to Coldfire 520x
  1293. */
  1294. static void __inline__ fec_request_intrs(struct net_device *dev)
  1295. {
  1296. struct fec_enet_private *fep;
  1297. int b;
  1298. static const struct idesc {
  1299. char *name;
  1300. unsigned short irq;
  1301. } *idp, id[] = {
  1302. { "fec(TXF)", 23 },
  1303. { "fec(TXB)", 24 },
  1304. { "fec(TXFIFO)", 25 },
  1305. { "fec(TXCR)", 26 },
  1306. { "fec(RXF)", 27 },
  1307. { "fec(RXB)", 28 },
  1308. { "fec(MII)", 29 },
  1309. { "fec(LC)", 30 },
  1310. { "fec(HBERR)", 31 },
  1311. { "fec(GRA)", 32 },
  1312. { "fec(EBERR)", 33 },
  1313. { "fec(BABT)", 34 },
  1314. { "fec(BABR)", 35 },
  1315. { NULL },
  1316. };
  1317. fep = netdev_priv(dev);
  1318. b = 64 + 13;
  1319. /* Setup interrupt handlers. */
  1320. for (idp = id; idp->name; idp++) {
  1321. if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
  1322. printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
  1323. }
  1324. /* Unmask interrupts at ColdFire interrupt controller */
  1325. {
  1326. volatile unsigned char *icrp;
  1327. volatile unsigned long *imrp;
  1328. icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
  1329. MCFINTC_ICR0);
  1330. for (b = 36; (b < 49); b++)
  1331. icrp[b] = 0x04;
  1332. imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
  1333. MCFINTC_IMRH);
  1334. *imrp &= ~0x0001FFF0;
  1335. }
  1336. *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
  1337. *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
  1338. }
  1339. static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
  1340. {
  1341. volatile fec_t *fecp;
  1342. fecp = fep->hwp;
  1343. fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
  1344. fecp->fec_x_cntrl = 0x00;
  1345. /*
  1346. * Set MII speed to 2.5 MHz
  1347. * See 5282 manual section 17.5.4.7: MSCR
  1348. */
  1349. fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
  1350. fecp->fec_mii_speed = fep->phy_speed;
  1351. fec_restart(dev, 0);
  1352. }
  1353. static void __inline__ fec_get_mac(struct net_device *dev)
  1354. {
  1355. struct fec_enet_private *fep = netdev_priv(dev);
  1356. volatile fec_t *fecp;
  1357. unsigned char *iap, tmpaddr[ETH_ALEN];
  1358. fecp = fep->hwp;
  1359. if (FEC_FLASHMAC) {
  1360. /*
  1361. * Get MAC address from FLASH.
  1362. * If it is all 1's or 0's, use the default.
  1363. */
  1364. iap = FEC_FLASHMAC;
  1365. if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
  1366. (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
  1367. iap = fec_mac_default;
  1368. if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
  1369. (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
  1370. iap = fec_mac_default;
  1371. } else {
  1372. *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
  1373. *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
  1374. iap = &tmpaddr[0];
  1375. }
  1376. memcpy(dev->dev_addr, iap, ETH_ALEN);
  1377. /* Adjust MAC if using default MAC address */
  1378. if (iap == fec_mac_default)
  1379. dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
  1380. }
  1381. static void __inline__ fec_enable_phy_intr(void)
  1382. {
  1383. }
  1384. static void __inline__ fec_disable_phy_intr(void)
  1385. {
  1386. }
  1387. static void __inline__ fec_phy_ack_intr(void)
  1388. {
  1389. }
  1390. static void __inline__ fec_localhw_setup(void)
  1391. {
  1392. }
  1393. static void __inline__ fec_uncache(unsigned long addr)
  1394. {
  1395. }
  1396. /* ------------------------------------------------------------------------- */
  1397. #elif defined(CONFIG_M532x)
  1398. /*
  1399. * Code specific for M532x
  1400. */
  1401. static void __inline__ fec_request_intrs(struct net_device *dev)
  1402. {
  1403. struct fec_enet_private *fep;
  1404. int b;
  1405. static const struct idesc {
  1406. char *name;
  1407. unsigned short irq;
  1408. } *idp, id[] = {
  1409. { "fec(TXF)", 36 },
  1410. { "fec(TXB)", 37 },
  1411. { "fec(TXFIFO)", 38 },
  1412. { "fec(TXCR)", 39 },
  1413. { "fec(RXF)", 40 },
  1414. { "fec(RXB)", 41 },
  1415. { "fec(MII)", 42 },
  1416. { "fec(LC)", 43 },
  1417. { "fec(HBERR)", 44 },
  1418. { "fec(GRA)", 45 },
  1419. { "fec(EBERR)", 46 },
  1420. { "fec(BABT)", 47 },
  1421. { "fec(BABR)", 48 },
  1422. { NULL },
  1423. };
  1424. fep = netdev_priv(dev);
  1425. b = (fep->index) ? 128 : 64;
  1426. /* Setup interrupt handlers. */
  1427. for (idp = id; idp->name; idp++) {
  1428. if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
  1429. printk("FEC: Could not allocate %s IRQ(%d)!\n",
  1430. idp->name, b+idp->irq);
  1431. }
  1432. /* Unmask interrupts */
  1433. MCF_INTC0_ICR36 = 0x2;
  1434. MCF_INTC0_ICR37 = 0x2;
  1435. MCF_INTC0_ICR38 = 0x2;
  1436. MCF_INTC0_ICR39 = 0x2;
  1437. MCF_INTC0_ICR40 = 0x2;
  1438. MCF_INTC0_ICR41 = 0x2;
  1439. MCF_INTC0_ICR42 = 0x2;
  1440. MCF_INTC0_ICR43 = 0x2;
  1441. MCF_INTC0_ICR44 = 0x2;
  1442. MCF_INTC0_ICR45 = 0x2;
  1443. MCF_INTC0_ICR46 = 0x2;
  1444. MCF_INTC0_ICR47 = 0x2;
  1445. MCF_INTC0_ICR48 = 0x2;
  1446. MCF_INTC0_IMRH &= ~(
  1447. MCF_INTC_IMRH_INT_MASK36 |
  1448. MCF_INTC_IMRH_INT_MASK37 |
  1449. MCF_INTC_IMRH_INT_MASK38 |
  1450. MCF_INTC_IMRH_INT_MASK39 |
  1451. MCF_INTC_IMRH_INT_MASK40 |
  1452. MCF_INTC_IMRH_INT_MASK41 |
  1453. MCF_INTC_IMRH_INT_MASK42 |
  1454. MCF_INTC_IMRH_INT_MASK43 |
  1455. MCF_INTC_IMRH_INT_MASK44 |
  1456. MCF_INTC_IMRH_INT_MASK45 |
  1457. MCF_INTC_IMRH_INT_MASK46 |
  1458. MCF_INTC_IMRH_INT_MASK47 |
  1459. MCF_INTC_IMRH_INT_MASK48 );
  1460. /* Set up gpio outputs for MII lines */
  1461. MCF_GPIO_PAR_FECI2C |= (0 |
  1462. MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
  1463. MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
  1464. MCF_GPIO_PAR_FEC = (0 |
  1465. MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
  1466. MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
  1467. }
  1468. static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
  1469. {
  1470. volatile fec_t *fecp;
  1471. fecp = fep->hwp;
  1472. fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
  1473. fecp->fec_x_cntrl = 0x00;
  1474. /*
  1475. * Set MII speed to 2.5 MHz
  1476. */
  1477. fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
  1478. fecp->fec_mii_speed = fep->phy_speed;
  1479. fec_restart(dev, 0);
  1480. }
  1481. static void __inline__ fec_get_mac(struct net_device *dev)
  1482. {
  1483. struct fec_enet_private *fep = netdev_priv(dev);
  1484. volatile fec_t *fecp;
  1485. unsigned char *iap, tmpaddr[ETH_ALEN];
  1486. fecp = fep->hwp;
  1487. if (FEC_FLASHMAC) {
  1488. /*
  1489. * Get MAC address from FLASH.
  1490. * If it is all 1's or 0's, use the default.
  1491. */
  1492. iap = FEC_FLASHMAC;
  1493. if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
  1494. (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
  1495. iap = fec_mac_default;
  1496. if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
  1497. (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
  1498. iap = fec_mac_default;
  1499. } else {
  1500. *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
  1501. *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
  1502. iap = &tmpaddr[0];
  1503. }
  1504. memcpy(dev->dev_addr, iap, ETH_ALEN);
  1505. /* Adjust MAC if using default MAC address */
  1506. if (iap == fec_mac_default)
  1507. dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
  1508. }
  1509. static void __inline__ fec_enable_phy_intr(void)
  1510. {
  1511. }
  1512. static void __inline__ fec_disable_phy_intr(void)
  1513. {
  1514. }
  1515. static void __inline__ fec_phy_ack_intr(void)
  1516. {
  1517. }
  1518. static void __inline__ fec_localhw_setup(void)
  1519. {
  1520. }
  1521. /*
  1522. * Do not need to make region uncached on 532x.
  1523. */
  1524. static void __inline__ fec_uncache(unsigned long addr)
  1525. {
  1526. }
  1527. /* ------------------------------------------------------------------------- */
  1528. #else
  1529. /*
  1530. * Code specific to the MPC860T setup.
  1531. */
  1532. static void __inline__ fec_request_intrs(struct net_device *dev)
  1533. {
  1534. volatile immap_t *immap;
  1535. immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
  1536. if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
  1537. panic("Could not allocate FEC IRQ!");
  1538. #ifdef CONFIG_RPXCLASSIC
  1539. /* Make Port C, bit 15 an input that causes interrupts.
  1540. */
  1541. immap->im_ioport.iop_pcpar &= ~0x0001;
  1542. immap->im_ioport.iop_pcdir &= ~0x0001;
  1543. immap->im_ioport.iop_pcso &= ~0x0001;
  1544. immap->im_ioport.iop_pcint |= 0x0001;
  1545. cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
  1546. /* Make LEDS reflect Link status.
  1547. */
  1548. *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
  1549. #endif
  1550. #ifdef CONFIG_FADS
  1551. if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
  1552. panic("Could not allocate MII IRQ!");
  1553. #endif
  1554. }
  1555. static void __inline__ fec_get_mac(struct net_device *dev)
  1556. {
  1557. bd_t *bd;
  1558. bd = (bd_t *)__res;
  1559. memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
  1560. #ifdef CONFIG_RPXCLASSIC
  1561. /* The Embedded Planet boards have only one MAC address in
  1562. * the EEPROM, but can have two Ethernet ports. For the
  1563. * FEC port, we create another address by setting one of
  1564. * the address bits above something that would have (up to
  1565. * now) been allocated.
  1566. */
  1567. dev->dev_adrd[3] |= 0x80;
  1568. #endif
  1569. }
  1570. static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
  1571. {
  1572. extern uint _get_IMMR(void);
  1573. volatile immap_t *immap;
  1574. volatile fec_t *fecp;
  1575. fecp = fep->hwp;
  1576. immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
  1577. /* Configure all of port D for MII.
  1578. */
  1579. immap->im_ioport.iop_pdpar = 0x1fff;
  1580. /* Bits moved from Rev. D onward.
  1581. */
  1582. if ((_get_IMMR() & 0xffff) < 0x0501)
  1583. immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
  1584. else
  1585. immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
  1586. /* Set MII speed to 2.5 MHz
  1587. */
  1588. fecp->fec_mii_speed = fep->phy_speed =
  1589. ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
  1590. }
  1591. static void __inline__ fec_enable_phy_intr(void)
  1592. {
  1593. volatile fec_t *fecp;
  1594. fecp = fep->hwp;
  1595. /* Enable MII command finished interrupt
  1596. */
  1597. fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
  1598. }
  1599. static void __inline__ fec_disable_phy_intr(void)
  1600. {
  1601. }
  1602. static void __inline__ fec_phy_ack_intr(void)
  1603. {
  1604. }
  1605. static void __inline__ fec_localhw_setup(void)
  1606. {
  1607. volatile fec_t *fecp;
  1608. fecp = fep->hwp;
  1609. fecp->fec_r_hash = PKT_MAXBUF_SIZE;
  1610. /* Enable big endian and don't care about SDMA FC.
  1611. */
  1612. fecp->fec_fun_code = 0x78000000;
  1613. }
  1614. static void __inline__ fec_uncache(unsigned long addr)
  1615. {
  1616. pte_t *pte;
  1617. pte = va_to_pte(mem_addr);
  1618. pte_val(*pte) |= _PAGE_NO_CACHE;
  1619. flush_tlb_page(init_mm.mmap, mem_addr);
  1620. }
  1621. #endif
  1622. /* ------------------------------------------------------------------------- */
  1623. static void mii_display_status(struct net_device *dev)
  1624. {
  1625. struct fec_enet_private *fep = netdev_priv(dev);
  1626. volatile uint *s = &(fep->phy_status);
  1627. if (!fep->link && !fep->old_link) {
  1628. /* Link is still down - don't print anything */
  1629. return;
  1630. }
  1631. printk("%s: status: ", dev->name);
  1632. if (!fep->link) {
  1633. printk("link down");
  1634. } else {
  1635. printk("link up");
  1636. switch(*s & PHY_STAT_SPMASK) {
  1637. case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
  1638. case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
  1639. case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
  1640. case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
  1641. default:
  1642. printk(", Unknown speed/duplex");
  1643. }
  1644. if (*s & PHY_STAT_ANC)
  1645. printk(", auto-negotiation complete");
  1646. }
  1647. if (*s & PHY_STAT_FAULT)
  1648. printk(", remote fault");
  1649. printk(".\n");
  1650. }
  1651. static void mii_display_config(struct net_device *dev)
  1652. {
  1653. struct fec_enet_private *fep = netdev_priv(dev);
  1654. uint status = fep->phy_status;
  1655. /*
  1656. ** When we get here, phy_task is already removed from
  1657. ** the workqueue. It is thus safe to allow to reuse it.
  1658. */
  1659. fep->mii_phy_task_queued = 0;
  1660. printk("%s: config: auto-negotiation ", dev->name);
  1661. if (status & PHY_CONF_ANE)
  1662. printk("on");
  1663. else
  1664. printk("off");
  1665. if (status & PHY_CONF_100FDX)
  1666. printk(", 100FDX");
  1667. if (status & PHY_CONF_100HDX)
  1668. printk(", 100HDX");
  1669. if (status & PHY_CONF_10FDX)
  1670. printk(", 10FDX");
  1671. if (status & PHY_CONF_10HDX)
  1672. printk(", 10HDX");
  1673. if (!(status & PHY_CONF_SPMASK))
  1674. printk(", No speed/duplex selected?");
  1675. if (status & PHY_CONF_LOOP)
  1676. printk(", loopback enabled");
  1677. printk(".\n");
  1678. fep->sequence_done = 1;
  1679. }
  1680. static void mii_relink(struct net_device *dev)
  1681. {
  1682. struct fec_enet_private *fep = netdev_priv(dev);
  1683. int duplex;
  1684. /*
  1685. ** When we get here, phy_task is already removed from
  1686. ** the workqueue. It is thus safe to allow to reuse it.
  1687. */
  1688. fep->mii_phy_task_queued = 0;
  1689. fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
  1690. mii_display_status(dev);
  1691. fep->old_link = fep->link;
  1692. if (fep->link) {
  1693. duplex = 0;
  1694. if (fep->phy_status
  1695. & (PHY_STAT_100FDX | PHY_STAT_10FDX))
  1696. duplex = 1;
  1697. fec_restart(dev, duplex);
  1698. }
  1699. else
  1700. fec_stop(dev);
  1701. #if 0
  1702. enable_irq(fep->mii_irq);
  1703. #endif
  1704. }
  1705. /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
  1706. static void mii_queue_relink(uint mii_reg, struct net_device *dev)
  1707. {
  1708. struct fec_enet_private *fep = netdev_priv(dev);
  1709. /*
  1710. ** We cannot queue phy_task twice in the workqueue. It
  1711. ** would cause an endless loop in the workqueue.
  1712. ** Fortunately, if the last mii_relink entry has not yet been
  1713. ** executed now, it will do the job for the current interrupt,
  1714. ** which is just what we want.
  1715. */
  1716. if (fep->mii_phy_task_queued)
  1717. return;
  1718. fep->mii_phy_task_queued = 1;
  1719. INIT_WORK(&fep->phy_task, (void*)mii_relink, dev);
  1720. schedule_work(&fep->phy_task);
  1721. }
  1722. /* mii_queue_config is called in interrupt context from fec_enet_mii */
  1723. static void mii_queue_config(uint mii_reg, struct net_device *dev)
  1724. {
  1725. struct fec_enet_private *fep = netdev_priv(dev);
  1726. if (fep->mii_phy_task_queued)
  1727. return;
  1728. fep->mii_phy_task_queued = 1;
  1729. INIT_WORK(&fep->phy_task, (void*)mii_display_config, dev);
  1730. schedule_work(&fep->phy_task);
  1731. }
  1732. phy_cmd_t const phy_cmd_relink[] = {
  1733. { mk_mii_read(MII_REG_CR), mii_queue_relink },
  1734. { mk_mii_end, }
  1735. };
  1736. phy_cmd_t const phy_cmd_config[] = {
  1737. { mk_mii_read(MII_REG_CR), mii_queue_config },
  1738. { mk_mii_end, }
  1739. };
  1740. /* Read remainder of PHY ID.
  1741. */
  1742. static void
  1743. mii_discover_phy3(uint mii_reg, struct net_device *dev)
  1744. {
  1745. struct fec_enet_private *fep;
  1746. int i;
  1747. fep = netdev_priv(dev);
  1748. fep->phy_id |= (mii_reg & 0xffff);
  1749. printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
  1750. for(i = 0; phy_info[i]; i++) {
  1751. if(phy_info[i]->id == (fep->phy_id >> 4))
  1752. break;
  1753. }
  1754. if (phy_info[i])
  1755. printk(" -- %s\n", phy_info[i]->name);
  1756. else
  1757. printk(" -- unknown PHY!\n");
  1758. fep->phy = phy_info[i];
  1759. fep->phy_id_done = 1;
  1760. }
  1761. /* Scan all of the MII PHY addresses looking for someone to respond
  1762. * with a valid ID. This usually happens quickly.
  1763. */
  1764. static void
  1765. mii_discover_phy(uint mii_reg, struct net_device *dev)
  1766. {
  1767. struct fec_enet_private *fep;
  1768. volatile fec_t *fecp;
  1769. uint phytype;
  1770. fep = netdev_priv(dev);
  1771. fecp = fep->hwp;
  1772. if (fep->phy_addr < 32) {
  1773. if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
  1774. /* Got first part of ID, now get remainder.
  1775. */
  1776. fep->phy_id = phytype << 16;
  1777. mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
  1778. mii_discover_phy3);
  1779. }
  1780. else {
  1781. fep->phy_addr++;
  1782. mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
  1783. mii_discover_phy);
  1784. }
  1785. } else {
  1786. printk("FEC: No PHY device found.\n");
  1787. /* Disable external MII interface */
  1788. fecp->fec_mii_speed = fep->phy_speed = 0;
  1789. fec_disable_phy_intr();
  1790. }
  1791. }
  1792. /* This interrupt occurs when the PHY detects a link change.
  1793. */
  1794. #ifdef CONFIG_RPXCLASSIC
  1795. static void
  1796. mii_link_interrupt(void *dev_id)
  1797. #else
  1798. static irqreturn_t
  1799. mii_link_interrupt(int irq, void * dev_id)
  1800. #endif
  1801. {
  1802. struct net_device *dev = dev_id;
  1803. struct fec_enet_private *fep = netdev_priv(dev);
  1804. fec_phy_ack_intr();
  1805. #if 0
  1806. disable_irq(fep->mii_irq); /* disable now, enable later */
  1807. #endif
  1808. mii_do_cmd(dev, fep->phy->ack_int);
  1809. mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
  1810. return IRQ_HANDLED;
  1811. }
  1812. static int
  1813. fec_enet_open(struct net_device *dev)
  1814. {
  1815. struct fec_enet_private *fep = netdev_priv(dev);
  1816. /* I should reset the ring buffers here, but I don't yet know
  1817. * a simple way to do that.
  1818. */
  1819. fec_set_mac_address(dev);
  1820. fep->sequence_done = 0;
  1821. fep->link = 0;
  1822. if (fep->phy) {
  1823. mii_do_cmd(dev, fep->phy->ack_int);
  1824. mii_do_cmd(dev, fep->phy->config);
  1825. mii_do_cmd(dev, phy_cmd_config); /* display configuration */
  1826. /* Poll until the PHY tells us its configuration
  1827. * (not link state).
  1828. * Request is initiated by mii_do_cmd above, but answer
  1829. * comes by interrupt.
  1830. * This should take about 25 usec per register at 2.5 MHz,
  1831. * and we read approximately 5 registers.
  1832. */
  1833. while(!fep->sequence_done)
  1834. schedule();
  1835. mii_do_cmd(dev, fep->phy->startup);
  1836. /* Set the initial link state to true. A lot of hardware
  1837. * based on this device does not implement a PHY interrupt,
  1838. * so we are never notified of link change.
  1839. */
  1840. fep->link = 1;
  1841. } else {
  1842. fep->link = 1; /* lets just try it and see */
  1843. /* no phy, go full duplex, it's most likely a hub chip */
  1844. fec_restart(dev, 1);
  1845. }
  1846. netif_start_queue(dev);
  1847. fep->opened = 1;
  1848. return 0; /* Success */
  1849. }
  1850. static int
  1851. fec_enet_close(struct net_device *dev)
  1852. {
  1853. struct fec_enet_private *fep = netdev_priv(dev);
  1854. /* Don't know what to do yet.
  1855. */
  1856. fep->opened = 0;
  1857. netif_stop_queue(dev);
  1858. fec_stop(dev);
  1859. return 0;
  1860. }
  1861. static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
  1862. {
  1863. struct fec_enet_private *fep = netdev_priv(dev);
  1864. return &fep->stats;
  1865. }
  1866. /* Set or clear the multicast filter for this adaptor.
  1867. * Skeleton taken from sunlance driver.
  1868. * The CPM Ethernet implementation allows Multicast as well as individual
  1869. * MAC address filtering. Some of the drivers check to make sure it is
  1870. * a group multicast address, and discard those that are not. I guess I
  1871. * will do the same for now, but just remove the test if you want
  1872. * individual filtering as well (do the upper net layers want or support
  1873. * this kind of feature?).
  1874. */
  1875. #define HASH_BITS 6 /* #bits in hash */
  1876. #define CRC32_POLY 0xEDB88320
  1877. static void set_multicast_list(struct net_device *dev)
  1878. {
  1879. struct fec_enet_private *fep;
  1880. volatile fec_t *ep;
  1881. struct dev_mc_list *dmi;
  1882. unsigned int i, j, bit, data, crc;
  1883. unsigned char hash;
  1884. fep = netdev_priv(dev);
  1885. ep = fep->hwp;
  1886. if (dev->flags&IFF_PROMISC) {
  1887. ep->fec_r_cntrl |= 0x0008;
  1888. } else {
  1889. ep->fec_r_cntrl &= ~0x0008;
  1890. if (dev->flags & IFF_ALLMULTI) {
  1891. /* Catch all multicast addresses, so set the
  1892. * filter to all 1's.
  1893. */
  1894. ep->fec_hash_table_high = 0xffffffff;
  1895. ep->fec_hash_table_low = 0xffffffff;
  1896. } else {
  1897. /* Clear filter and add the addresses in hash register.
  1898. */
  1899. ep->fec_hash_table_high = 0;
  1900. ep->fec_hash_table_low = 0;
  1901. dmi = dev->mc_list;
  1902. for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
  1903. {
  1904. /* Only support group multicast for now.
  1905. */
  1906. if (!(dmi->dmi_addr[0] & 1))
  1907. continue;
  1908. /* calculate crc32 value of mac address
  1909. */
  1910. crc = 0xffffffff;
  1911. for (i = 0; i < dmi->dmi_addrlen; i++)
  1912. {
  1913. data = dmi->dmi_addr[i];
  1914. for (bit = 0; bit < 8; bit++, data >>= 1)
  1915. {
  1916. crc = (crc >> 1) ^
  1917. (((crc ^ data) & 1) ? CRC32_POLY : 0);
  1918. }
  1919. }
  1920. /* only upper 6 bits (HASH_BITS) are used
  1921. which point to specific bit in he hash registers
  1922. */
  1923. hash = (crc >> (32 - HASH_BITS)) & 0x3f;
  1924. if (hash > 31)
  1925. ep->fec_hash_table_high |= 1 << (hash - 32);
  1926. else
  1927. ep->fec_hash_table_low |= 1 << hash;
  1928. }
  1929. }
  1930. }
  1931. }
  1932. /* Set a MAC change in hardware.
  1933. */
  1934. static void
  1935. fec_set_mac_address(struct net_device *dev)
  1936. {
  1937. volatile fec_t *fecp;
  1938. fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
  1939. /* Set station address. */
  1940. fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
  1941. (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
  1942. fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
  1943. (dev->dev_addr[4] << 24);
  1944. }
  1945. /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
  1946. */
  1947. /*
  1948. * XXX: We need to clean up on failure exits here.
  1949. */
  1950. int __init fec_enet_init(struct net_device *dev)
  1951. {
  1952. struct fec_enet_private *fep = netdev_priv(dev);
  1953. unsigned long mem_addr;
  1954. volatile cbd_t *bdp;
  1955. cbd_t *cbd_base;
  1956. volatile fec_t *fecp;
  1957. int i, j;
  1958. static int index = 0;
  1959. /* Only allow us to be probed once. */
  1960. if (index >= FEC_MAX_PORTS)
  1961. return -ENXIO;
  1962. /* Allocate memory for buffer descriptors.
  1963. */
  1964. mem_addr = __get_free_page(GFP_KERNEL);
  1965. if (mem_addr == 0) {
  1966. printk("FEC: allocate descriptor memory failed?\n");
  1967. return -ENOMEM;
  1968. }
  1969. /* Create an Ethernet device instance.
  1970. */
  1971. fecp = (volatile fec_t *) fec_hw[index];
  1972. fep->index = index;
  1973. fep->hwp = fecp;
  1974. /* Whack a reset. We should wait for this.
  1975. */
  1976. fecp->fec_ecntrl = 1;
  1977. udelay(10);
  1978. /* Set the Ethernet address. If using multiple Enets on the 8xx,
  1979. * this needs some work to get unique addresses.
  1980. *
  1981. * This is our default MAC address unless the user changes
  1982. * it via eth_mac_addr (our dev->set_mac_addr handler).
  1983. */
  1984. fec_get_mac(dev);
  1985. cbd_base = (cbd_t *)mem_addr;
  1986. /* XXX: missing check for allocation failure */
  1987. fec_uncache(mem_addr);
  1988. /* Set receive and transmit descriptor base.
  1989. */
  1990. fep->rx_bd_base = cbd_base;
  1991. fep->tx_bd_base = cbd_base + RX_RING_SIZE;
  1992. fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
  1993. fep->cur_rx = fep->rx_bd_base;
  1994. fep->skb_cur = fep->skb_dirty = 0;
  1995. /* Initialize the receive buffer descriptors.
  1996. */
  1997. bdp = fep->rx_bd_base;
  1998. for (i=0; i<FEC_ENET_RX_PAGES; i++) {
  1999. /* Allocate a page.
  2000. */
  2001. mem_addr = __get_free_page(GFP_KERNEL);
  2002. /* XXX: missing check for allocation failure */
  2003. fec_uncache(mem_addr);
  2004. /* Initialize the BD for every fragment in the page.
  2005. */
  2006. for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
  2007. bdp->cbd_sc = BD_ENET_RX_EMPTY;
  2008. bdp->cbd_bufaddr = __pa(mem_addr);
  2009. mem_addr += FEC_ENET_RX_FRSIZE;
  2010. bdp++;
  2011. }
  2012. }
  2013. /* Set the last buffer to wrap.
  2014. */
  2015. bdp--;
  2016. bdp->cbd_sc |= BD_SC_WRAP;
  2017. /* ...and the same for transmmit.
  2018. */
  2019. bdp = fep->tx_bd_base;
  2020. for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
  2021. if (j >= FEC_ENET_TX_FRPPG) {
  2022. mem_addr = __get_free_page(GFP_KERNEL);
  2023. j = 1;
  2024. } else {
  2025. mem_addr += FEC_ENET_TX_FRSIZE;
  2026. j++;
  2027. }
  2028. fep->tx_bounce[i] = (unsigned char *) mem_addr;
  2029. /* Initialize the BD for every fragment in the page.
  2030. */
  2031. bdp->cbd_sc = 0;
  2032. bdp->cbd_bufaddr = 0;
  2033. bdp++;
  2034. }
  2035. /* Set the last buffer to wrap.
  2036. */
  2037. bdp--;
  2038. bdp->cbd_sc |= BD_SC_WRAP;
  2039. /* Set receive and transmit descriptor base.
  2040. */
  2041. fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
  2042. fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
  2043. /* Install our interrupt handlers. This varies depending on
  2044. * the architecture.
  2045. */
  2046. fec_request_intrs(dev);
  2047. fecp->fec_hash_table_high = 0;
  2048. fecp->fec_hash_table_low = 0;
  2049. fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
  2050. fecp->fec_ecntrl = 2;
  2051. fecp->fec_r_des_active = 0;
  2052. dev->base_addr = (unsigned long)fecp;
  2053. /* The FEC Ethernet specific entries in the device structure. */
  2054. dev->open = fec_enet_open;
  2055. dev->hard_start_xmit = fec_enet_start_xmit;
  2056. dev->tx_timeout = fec_timeout;
  2057. dev->watchdog_timeo = TX_TIMEOUT;
  2058. dev->stop = fec_enet_close;
  2059. dev->get_stats = fec_enet_get_stats;
  2060. dev->set_multicast_list = set_multicast_list;
  2061. for (i=0; i<NMII-1; i++)
  2062. mii_cmds[i].mii_next = &mii_cmds[i+1];
  2063. mii_free = mii_cmds;
  2064. /* setup MII interface */
  2065. fec_set_mii(dev, fep);
  2066. /* Clear and enable interrupts */
  2067. fecp->fec_ievent = 0xffc00000;
  2068. fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
  2069. FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
  2070. /* Queue up command to detect the PHY and initialize the
  2071. * remainder of the interface.
  2072. */
  2073. fep->phy_id_done = 0;
  2074. fep->phy_addr = 0;
  2075. mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
  2076. index++;
  2077. return 0;
  2078. }
  2079. /* This function is called to start or restart the FEC during a link
  2080. * change. This only happens when switching between half and full
  2081. * duplex.
  2082. */
  2083. static void
  2084. fec_restart(struct net_device *dev, int duplex)
  2085. {
  2086. struct fec_enet_private *fep;
  2087. volatile cbd_t *bdp;
  2088. volatile fec_t *fecp;
  2089. int i;
  2090. fep = netdev_priv(dev);
  2091. fecp = fep->hwp;
  2092. /* Whack a reset. We should wait for this.
  2093. */
  2094. fecp->fec_ecntrl = 1;
  2095. udelay(10);
  2096. /* Clear any outstanding interrupt.
  2097. */
  2098. fecp->fec_ievent = 0xffc00000;
  2099. fec_enable_phy_intr();
  2100. /* Set station address.
  2101. */
  2102. fec_set_mac_address(dev);
  2103. /* Reset all multicast.
  2104. */
  2105. fecp->fec_hash_table_high = 0;
  2106. fecp->fec_hash_table_low = 0;
  2107. /* Set maximum receive buffer size.
  2108. */
  2109. fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
  2110. fec_localhw_setup();
  2111. /* Set receive and transmit descriptor base.
  2112. */
  2113. fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
  2114. fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
  2115. fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
  2116. fep->cur_rx = fep->rx_bd_base;
  2117. /* Reset SKB transmit buffers.
  2118. */
  2119. fep->skb_cur = fep->skb_dirty = 0;
  2120. for (i=0; i<=TX_RING_MOD_MASK; i++) {
  2121. if (fep->tx_skbuff[i] != NULL) {
  2122. dev_kfree_skb_any(fep->tx_skbuff[i]);
  2123. fep->tx_skbuff[i] = NULL;
  2124. }
  2125. }
  2126. /* Initialize the receive buffer descriptors.
  2127. */
  2128. bdp = fep->rx_bd_base;
  2129. for (i=0; i<RX_RING_SIZE; i++) {
  2130. /* Initialize the BD for every fragment in the page.
  2131. */
  2132. bdp->cbd_sc = BD_ENET_RX_EMPTY;
  2133. bdp++;
  2134. }
  2135. /* Set the last buffer to wrap.
  2136. */
  2137. bdp--;
  2138. bdp->cbd_sc |= BD_SC_WRAP;
  2139. /* ...and the same for transmmit.
  2140. */
  2141. bdp = fep->tx_bd_base;
  2142. for (i=0; i<TX_RING_SIZE; i++) {
  2143. /* Initialize the BD for every fragment in the page.
  2144. */
  2145. bdp->cbd_sc = 0;
  2146. bdp->cbd_bufaddr = 0;
  2147. bdp++;
  2148. }
  2149. /* Set the last buffer to wrap.
  2150. */
  2151. bdp--;
  2152. bdp->cbd_sc |= BD_SC_WRAP;
  2153. /* Enable MII mode.
  2154. */
  2155. if (duplex) {
  2156. fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
  2157. fecp->fec_x_cntrl = 0x04; /* FD enable */
  2158. }
  2159. else {
  2160. /* MII enable|No Rcv on Xmit */
  2161. fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
  2162. fecp->fec_x_cntrl = 0x00;
  2163. }
  2164. fep->full_duplex = duplex;
  2165. /* Set MII speed.
  2166. */
  2167. fecp->fec_mii_speed = fep->phy_speed;
  2168. /* And last, enable the transmit and receive processing.
  2169. */
  2170. fecp->fec_ecntrl = 2;
  2171. fecp->fec_r_des_active = 0;
  2172. /* Enable interrupts we wish to service.
  2173. */
  2174. fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
  2175. FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
  2176. }
  2177. static void
  2178. fec_stop(struct net_device *dev)
  2179. {
  2180. volatile fec_t *fecp;
  2181. struct fec_enet_private *fep;
  2182. fep = netdev_priv(dev);
  2183. fecp = fep->hwp;
  2184. /*
  2185. ** We cannot expect a graceful transmit stop without link !!!
  2186. */
  2187. if (fep->link)
  2188. {
  2189. fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
  2190. udelay(10);
  2191. if (!(fecp->fec_ievent & FEC_ENET_GRA))
  2192. printk("fec_stop : Graceful transmit stop did not complete !\n");
  2193. }
  2194. /* Whack a reset. We should wait for this.
  2195. */
  2196. fecp->fec_ecntrl = 1;
  2197. udelay(10);
  2198. /* Clear outstanding MII command interrupts.
  2199. */
  2200. fecp->fec_ievent = FEC_ENET_MII;
  2201. fec_enable_phy_intr();
  2202. fecp->fec_imask = FEC_ENET_MII;
  2203. fecp->fec_mii_speed = fep->phy_speed;
  2204. }
  2205. static int __init fec_enet_module_init(void)
  2206. {
  2207. struct net_device *dev;
  2208. int i, j, err;
  2209. printk("FEC ENET Version 0.2\n");
  2210. for (i = 0; (i < FEC_MAX_PORTS); i++) {
  2211. dev = alloc_etherdev(sizeof(struct fec_enet_private));
  2212. if (!dev)
  2213. return -ENOMEM;
  2214. err = fec_enet_init(dev);
  2215. if (err) {
  2216. free_netdev(dev);
  2217. continue;
  2218. }
  2219. if (register_netdev(dev) != 0) {
  2220. /* XXX: missing cleanup here */
  2221. free_netdev(dev);
  2222. return -EIO;
  2223. }
  2224. printk("%s: ethernet ", dev->name);
  2225. for (j = 0; (j < 5); j++)
  2226. printk("%02x:", dev->dev_addr[j]);
  2227. printk("%02x\n", dev->dev_addr[5]);
  2228. }
  2229. return 0;
  2230. }
  2231. module_init(fec_enet_module_init);
  2232. MODULE_LICENSE("GPL");