eexpress.h 4.7 KB

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  1. /*
  2. * eexpress.h: Intel EtherExpress16 defines
  3. */
  4. /*
  5. * EtherExpress card register addresses
  6. * as offsets from the base IO region (dev->base_addr)
  7. */
  8. #define DATAPORT 0x0000
  9. #define WRITE_PTR 0x0002
  10. #define READ_PTR 0x0004
  11. #define SIGNAL_CA 0x0006
  12. #define SET_IRQ 0x0007
  13. #define SM_PTR 0x0008
  14. #define MEM_Dec 0x000a
  15. #define MEM_Ctrl 0x000b
  16. #define MEM_Page_Ctrl 0x000c
  17. #define Config 0x000d
  18. #define EEPROM_Ctrl 0x000e
  19. #define ID_PORT 0x000f
  20. #define MEM_ECtrl 0x000f
  21. /*
  22. * card register defines
  23. */
  24. /* SET_IRQ */
  25. #define SIRQ_en 0x08
  26. #define SIRQ_dis 0x00
  27. /* EEPROM_Ctrl */
  28. #define EC_Clk 0x01
  29. #define EC_CS 0x02
  30. #define EC_Wr 0x04
  31. #define EC_Rd 0x08
  32. #define ASIC_RST 0x40
  33. #define i586_RST 0x80
  34. #define eeprom_delay() { udelay(40); }
  35. /*
  36. * i82586 Memory Configuration
  37. */
  38. /* (System Configuration Pointer) System start up block, read after 586_RST */
  39. #define SCP_START 0xfff6
  40. /* Intermediate System Configuration Pointer */
  41. #define ISCP_START 0x0000
  42. /* System Command Block */
  43. #define SCB_START 0x0008
  44. /* Start of buffer region. Everything before this is used for control
  45. * structures and the CU configuration program. The memory layout is
  46. * determined in eexp_hw_probe(), once we know how much memory is
  47. * available on the card.
  48. */
  49. #define TX_BUF_START 0x0100
  50. #define TX_BUF_SIZE ((24+ETH_FRAME_LEN+31)&~0x1f)
  51. #define RX_BUF_SIZE ((32+ETH_FRAME_LEN+31)&~0x1f)
  52. /*
  53. * SCB defines
  54. */
  55. /* these functions take the SCB status word and test the relevant status bit */
  56. #define SCB_complete(s) ((s&0x8000)!=0)
  57. #define SCB_rxdframe(s) ((s&0x4000)!=0)
  58. #define SCB_CUdead(s) ((s&0x2000)!=0)
  59. #define SCB_RUdead(s) ((s&0x1000)!=0)
  60. #define SCB_ack(s) (s & 0xf000)
  61. /* Command unit status: 0=idle, 1=suspended, 2=active */
  62. #define SCB_CUstat(s) ((s&0x0300)>>8)
  63. /* Receive unit status: 0=idle, 1=suspended, 2=out of resources, 4=ready */
  64. #define SCB_RUstat(s) ((s&0x0070)>>4)
  65. /* SCB commands */
  66. #define SCB_CUnop 0x0000
  67. #define SCB_CUstart 0x0100
  68. #define SCB_CUresume 0x0200
  69. #define SCB_CUsuspend 0x0300
  70. #define SCB_CUabort 0x0400
  71. #define SCB_resetchip 0x0080
  72. #define SCB_RUnop 0x0000
  73. #define SCB_RUstart 0x0010
  74. #define SCB_RUresume 0x0020
  75. #define SCB_RUsuspend 0x0030
  76. #define SCB_RUabort 0x0040
  77. /*
  78. * Command block defines
  79. */
  80. #define Stat_Done(s) ((s&0x8000)!=0)
  81. #define Stat_Busy(s) ((s&0x4000)!=0)
  82. #define Stat_OK(s) ((s&0x2000)!=0)
  83. #define Stat_Abort(s) ((s&0x1000)!=0)
  84. #define Stat_STFail ((s&0x0800)!=0)
  85. #define Stat_TNoCar(s) ((s&0x0400)!=0)
  86. #define Stat_TNoCTS(s) ((s&0x0200)!=0)
  87. #define Stat_TNoDMA(s) ((s&0x0100)!=0)
  88. #define Stat_TDefer(s) ((s&0x0080)!=0)
  89. #define Stat_TColl(s) ((s&0x0040)!=0)
  90. #define Stat_TXColl(s) ((s&0x0020)!=0)
  91. #define Stat_NoColl(s) (s&0x000f)
  92. /* Cmd_END will end AFTER the command if this is the first
  93. * command block after an SCB_CUstart, but BEFORE the command
  94. * for all subsequent commands. Best strategy is to place
  95. * Cmd_INT on the last command in the sequence, followed by a
  96. * dummy Cmd_Nop with Cmd_END after this.
  97. */
  98. #define Cmd_END 0x8000
  99. #define Cmd_SUS 0x4000
  100. #define Cmd_INT 0x2000
  101. #define Cmd_Nop 0x0000
  102. #define Cmd_SetAddr 0x0001
  103. #define Cmd_Config 0x0002
  104. #define Cmd_MCast 0x0003
  105. #define Cmd_Xmit 0x0004
  106. #define Cmd_TDR 0x0005
  107. #define Cmd_Dump 0x0006
  108. #define Cmd_Diag 0x0007
  109. /*
  110. * Frame Descriptor (Receive block) defines
  111. */
  112. #define FD_Done(s) ((s&0x8000)!=0)
  113. #define FD_Busy(s) ((s&0x4000)!=0)
  114. #define FD_OK(s) ((s&0x2000)!=0)
  115. #define FD_CRC(s) ((s&0x0800)!=0)
  116. #define FD_Align(s) ((s&0x0400)!=0)
  117. #define FD_Resrc(s) ((s&0x0200)!=0)
  118. #define FD_DMA(s) ((s&0x0100)!=0)
  119. #define FD_Short(s) ((s&0x0080)!=0)
  120. #define FD_NoEOF(s) ((s&0x0040)!=0)
  121. struct rfd_header {
  122. volatile unsigned long flags;
  123. volatile unsigned short link;
  124. volatile unsigned short rbd_offset;
  125. volatile unsigned short dstaddr1;
  126. volatile unsigned short dstaddr2;
  127. volatile unsigned short dstaddr3;
  128. volatile unsigned short srcaddr1;
  129. volatile unsigned short srcaddr2;
  130. volatile unsigned short srcaddr3;
  131. volatile unsigned short length;
  132. /* This is actually a Receive Buffer Descriptor. The way we
  133. * arrange memory means that an RBD always follows the RFD that
  134. * points to it, so they might as well be in the same structure.
  135. */
  136. volatile unsigned short actual_count;
  137. volatile unsigned short next_rbd;
  138. volatile unsigned short buf_addr1;
  139. volatile unsigned short buf_addr2;
  140. volatile unsigned short size;
  141. };
  142. /* Returned data from the Time Domain Reflectometer */
  143. #define TDR_LINKOK (1<<15)
  144. #define TDR_XCVRPROBLEM (1<<14)
  145. #define TDR_OPEN (1<<13)
  146. #define TDR_SHORT (1<<12)
  147. #define TDR_TIME 0x7ff