dm9000.h 3.9 KB

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  1. /*
  2. * dm9000 Ethernet
  3. */
  4. #ifndef _DM9000X_H_
  5. #define _DM9000X_H_
  6. #define DM9000_ID 0x90000A46
  7. /* although the registers are 16 bit, they are 32-bit aligned.
  8. */
  9. #define DM9000_NCR 0x00
  10. #define DM9000_NSR 0x01
  11. #define DM9000_TCR 0x02
  12. #define DM9000_TSR1 0x03
  13. #define DM9000_TSR2 0x04
  14. #define DM9000_RCR 0x05
  15. #define DM9000_RSR 0x06
  16. #define DM9000_ROCR 0x07
  17. #define DM9000_BPTR 0x08
  18. #define DM9000_FCTR 0x09
  19. #define DM9000_FCR 0x0A
  20. #define DM9000_EPCR 0x0B
  21. #define DM9000_EPAR 0x0C
  22. #define DM9000_EPDRL 0x0D
  23. #define DM9000_EPDRH 0x0E
  24. #define DM9000_WCR 0x0F
  25. #define DM9000_PAR 0x10
  26. #define DM9000_MAR 0x16
  27. #define DM9000_GPCR 0x1e
  28. #define DM9000_GPR 0x1f
  29. #define DM9000_TRPAL 0x22
  30. #define DM9000_TRPAH 0x23
  31. #define DM9000_RWPAL 0x24
  32. #define DM9000_RWPAH 0x25
  33. #define DM9000_VIDL 0x28
  34. #define DM9000_VIDH 0x29
  35. #define DM9000_PIDL 0x2A
  36. #define DM9000_PIDH 0x2B
  37. #define DM9000_CHIPR 0x2C
  38. #define DM9000_SMCR 0x2F
  39. #define DM9000_MRCMDX 0xF0
  40. #define DM9000_MRCMD 0xF2
  41. #define DM9000_MRRL 0xF4
  42. #define DM9000_MRRH 0xF5
  43. #define DM9000_MWCMDX 0xF6
  44. #define DM9000_MWCMD 0xF8
  45. #define DM9000_MWRL 0xFA
  46. #define DM9000_MWRH 0xFB
  47. #define DM9000_TXPLL 0xFC
  48. #define DM9000_TXPLH 0xFD
  49. #define DM9000_ISR 0xFE
  50. #define DM9000_IMR 0xFF
  51. #define NCR_EXT_PHY (1<<7)
  52. #define NCR_WAKEEN (1<<6)
  53. #define NCR_FCOL (1<<4)
  54. #define NCR_FDX (1<<3)
  55. #define NCR_LBK (3<<1)
  56. #define NCR_RST (1<<0)
  57. #define NSR_SPEED (1<<7)
  58. #define NSR_LINKST (1<<6)
  59. #define NSR_WAKEST (1<<5)
  60. #define NSR_TX2END (1<<3)
  61. #define NSR_TX1END (1<<2)
  62. #define NSR_RXOV (1<<1)
  63. #define TCR_TJDIS (1<<6)
  64. #define TCR_EXCECM (1<<5)
  65. #define TCR_PAD_DIS2 (1<<4)
  66. #define TCR_CRC_DIS2 (1<<3)
  67. #define TCR_PAD_DIS1 (1<<2)
  68. #define TCR_CRC_DIS1 (1<<1)
  69. #define TCR_TXREQ (1<<0)
  70. #define TSR_TJTO (1<<7)
  71. #define TSR_LC (1<<6)
  72. #define TSR_NC (1<<5)
  73. #define TSR_LCOL (1<<4)
  74. #define TSR_COL (1<<3)
  75. #define TSR_EC (1<<2)
  76. #define RCR_WTDIS (1<<6)
  77. #define RCR_DIS_LONG (1<<5)
  78. #define RCR_DIS_CRC (1<<4)
  79. #define RCR_ALL (1<<3)
  80. #define RCR_RUNT (1<<2)
  81. #define RCR_PRMSC (1<<1)
  82. #define RCR_RXEN (1<<0)
  83. #define RSR_RF (1<<7)
  84. #define RSR_MF (1<<6)
  85. #define RSR_LCS (1<<5)
  86. #define RSR_RWTO (1<<4)
  87. #define RSR_PLE (1<<3)
  88. #define RSR_AE (1<<2)
  89. #define RSR_CE (1<<1)
  90. #define RSR_FOE (1<<0)
  91. #define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
  92. #define FCTR_LWOT(ot) ( ot & 0xf )
  93. #define IMR_PAR (1<<7)
  94. #define IMR_ROOM (1<<3)
  95. #define IMR_ROM (1<<2)
  96. #define IMR_PTM (1<<1)
  97. #define IMR_PRM (1<<0)
  98. #define ISR_ROOS (1<<3)
  99. #define ISR_ROS (1<<2)
  100. #define ISR_PTS (1<<1)
  101. #define ISR_PRS (1<<0)
  102. #define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
  103. #define EPCR_REEP (1<<5)
  104. #define EPCR_WEP (1<<4)
  105. #define EPCR_EPOS (1<<3)
  106. #define EPCR_ERPRR (1<<2)
  107. #define EPCR_ERPRW (1<<1)
  108. #define EPCR_ERRE (1<<0)
  109. #define GPCR_GEP_CNTL (1<<0)
  110. #define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
  111. #define DM9000_PKT_MAX 1536 /* Received packet max size */
  112. #endif /* _DM9000X_H_ */