dgrs_plx9060.h 5.3 KB

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  1. /*
  2. * PLX 9060 PCI Interface chip
  3. */
  4. /*
  5. * PCI configuration registers, same offset on local and PCI sides,
  6. * but on PCI side, must use PCI BIOS calls to read/write.
  7. */
  8. #define PCI_PLXREGS_BASE_ADDR 0x10
  9. #define PCI_PLXREGS_IO_ADDR 0x14
  10. #define PCI_SPACE0_BASE_ADDR 0x18
  11. #define PCI_ROM_BASE_ADDR 0x30
  12. # define PCI_ROM_ENABLED 0x00000001
  13. #define PCI_INT_LINE 0x3C
  14. /*
  15. * Registers accessible directly from PCI and local side.
  16. * Offset is from PCI side. Add PLX_LCL_OFFSET for local address.
  17. */
  18. #define PLX_LCL_OFFSET 0x80 /* Offset of regs from local side */
  19. /*
  20. * Local Configuration Registers
  21. */
  22. #define PLX_SPACE0_RANGE 0x00 /* Range for PCI to Lcl Addr Space 0 */
  23. #define PLX_SPACE0_BASE_ADDR 0x04 /* Lcl Base address remap */
  24. #define PLX_ROM_RANGE 0x10 /* Range for expansion ROM (DMA) */
  25. #define PLX_ROM_BASE_ADDR 0x14 /* Lcl base address remap for ROM */
  26. #define PLX_BUS_REGION 0x18 /* Bus Region Descriptors */
  27. /*
  28. * Shared Run Time Registers
  29. */
  30. #define PLX_MBOX0 0x40
  31. #define PLX_MBOX1 0x44
  32. #define PLX_MBOX2 0x48
  33. #define PLX_MBOX3 0x4C
  34. #define PLX_MBOX4 0x50
  35. #define PLX_MBOX5 0x54
  36. #define PLX_MBOX6 0x58
  37. #define PLX_MBOX7 0x5C
  38. #define PLX_PCI2LCL_DOORBELL 0x60
  39. #define PLX_LCL2PCI_DOORBELL 0x64
  40. #define PLX_INT_CSR 0x68 /* Interrupt Control/Status */
  41. # define PLX_LSERR_ENABLE 0x00000001
  42. # define PLX_LSERR_PE 0x00000002
  43. # define PLX_SERR 0x00000004
  44. # undef PLX_UNUSED /* 0x00000008 */
  45. # undef PLX_UNUSED /* 0x00000010 */
  46. # undef PLX_UNUSED /* 0x00000020 */
  47. # undef PLX_UNUSED /* 0x00000040 */
  48. # undef PLX_UNUSED /* 0x00000080 */
  49. # define PLX_PCI_IE 0x00000100
  50. # define PLX_PCI_DOORBELL_IE 0x00000200
  51. # define PLX_PCI_ABORT_IE 0x00000400
  52. # define PLX_PCI_LOCAL_IE 0x00000800
  53. # define PLX_RETRY_ABORT_ENABLE 0x00001000
  54. # define PLX_PCI_DOORBELL_INT 0x00002000
  55. # define PLX_PCI_ABORT_INT 0x00004000
  56. # define PLX_PCI_LOCAL_INT 0x00008000
  57. # define PLX_LCL_IE 0x00010000
  58. # define PLX_LCL_DOORBELL_IE 0x00020000
  59. # define PLX_LCL_DMA0_IE 0x00040000
  60. # define PLX_LCL_DMA1_IE 0x00080000
  61. # define PLX_LCL_DOORBELL_INT 0x00100000
  62. # define PLX_LCL_DMA0_INT 0x00200000
  63. # define PLX_LCL_DMA1_INT 0x00400000
  64. # define PLX_LCL_BIST_INT 0x00800000
  65. # define PLX_BM_DIRECT_ 0x01000000
  66. # define PLX_BM_DMA0_ 0x02000000
  67. # define PLX_BM_DMA1_ 0x04000000
  68. # define PLX_BM_ABORT_ 0x08000000
  69. # undef PLX_UNUSED /* 0x10000000 */
  70. # undef PLX_UNUSED /* 0x20000000 */
  71. # undef PLX_UNUSED /* 0x40000000 */
  72. # undef PLX_UNUSED /* 0x80000000 */
  73. #define PLX_MISC_CSR 0x6c /* EEPROM,PCI,User,Init Control/Status*/
  74. # define PLX_USEROUT 0x00010000
  75. # define PLX_USERIN 0x00020000
  76. # define PLX_EECK 0x01000000
  77. # define PLX_EECS 0x02000000
  78. # define PLX_EEWD 0x04000000
  79. # define PLX_EERD 0x08000000
  80. /*
  81. * DMA registers. Offset is from local side
  82. */
  83. #define PLX_DMA0_MODE 0x100
  84. # define PLX_DMA_MODE_WIDTH32 0x00000003
  85. # define PLX_DMA_MODE_WAITSTATES(X) ((X)<<2)
  86. # define PLX_DMA_MODE_NOREADY 0x00000000
  87. # define PLX_DMA_MODE_READY 0x00000040
  88. # define PLX_DMA_MODE_NOBTERM 0x00000000
  89. # define PLX_DMA_MODE_BTERM 0x00000080
  90. # define PLX_DMA_MODE_NOBURST 0x00000000
  91. # define PLX_DMA_MODE_BURST 0x00000100
  92. # define PLX_DMA_MODE_NOCHAIN 0x00000000
  93. # define PLX_DMA_MODE_CHAIN 0x00000200
  94. # define PLX_DMA_MODE_DONE_IE 0x00000400
  95. # define PLX_DMA_MODE_ADDR_HOLD 0x00000800
  96. #define PLX_DMA0_PCI_ADDR 0x104
  97. /* non-chaining mode PCI address */
  98. #define PLX_DMA0_LCL_ADDR 0x108
  99. /* non-chaining mode local address */
  100. #define PLX_DMA0_SIZE 0x10C
  101. /* non-chaining mode length */
  102. #define PLX_DMA0_DESCRIPTOR 0x110
  103. # define PLX_DMA_DESC_EOC 0x00000002
  104. # define PLX_DMA_DESC_TC_IE 0x00000004
  105. # define PLX_DMA_DESC_TO_HOST 0x00000008
  106. # define PLX_DMA_DESC_TO_BOARD 0x00000000
  107. # define PLX_DMA_DESC_NEXTADDR 0xFFFFfff0
  108. #define PLX_DMA1_MODE 0x114
  109. #define PLX_DMA1_PCI_ADDR 0x118
  110. #define PLX_DMA1_LCL_ADDR 0x11C
  111. #define PLX_DMA1_SIZE 0x110
  112. #define PLX_DMA1_DESCRIPTOR 0x124
  113. #define PLX_DMA_CSR 0x128
  114. # define PLX_DMA_CSR_0_ENABLE 0x00000001
  115. # define PLX_DMA_CSR_0_START 0x00000002
  116. # define PLX_DMA_CSR_0_ABORT 0x00000004
  117. # define PLX_DMA_CSR_0_CLR_INTR 0x00000008
  118. # define PLX_DMA_CSR_0_DONE 0x00000010
  119. # define PLX_DMA_CSR_1_ENABLE 0x00000100
  120. # define PLX_DMA_CSR_1_START 0x00000200
  121. # define PLX_DMA_CSR_1_ABORT 0x00000400
  122. # define PLX_DMA_CSR_1_CLR_INTR 0x00000800
  123. # define PLX_DMA_CSR_1_DONE 0x00001000
  124. #define PLX_DMA_ARB0 0x12C
  125. # define PLX_DMA_ARB0_LATENCY_T 0x000000FF
  126. # define PLX_DMA_ARB0_PAUSE_T 0x0000FF00
  127. # define PLX_DMA_ARB0_LATENCY_EN 0x00010000
  128. # define PLX_DMA_ARB0_PAUSE_EN 0x00020000
  129. # define PLX_DMA_ARB0_BREQ_EN 0x00040000
  130. # define PLX_DMA_ARB0_PRI 0x00180000
  131. # define PLX_DMA_ARB0_PRI_ROUND 0x00000000
  132. # define PLX_DMA_ARB0_PRI_0 0x00080000
  133. # define PLX_DMA_ARB0_PRI_1 0x00100000
  134. #define PLX_DMA_ARB1 0x130
  135. /* Chan 0: FIFO DEPTH=16 */
  136. # define PLX_DMA_ARB1_0_P2L_LW_TRIG(X) ( ((X)&15) << 0 )
  137. # define PLX_DMA_ARB1_0_L2P_LR_TRIG(X) ( ((X)&15) << 4 )
  138. # define PLX_DMA_ARB1_0_L2P_PW_TRIG(X) ( ((X)&15) << 8 )
  139. # define PLX_DMA_ARB1_0_P2L_PR_TRIG(X) ( ((X)&15) << 12 )
  140. /* Chan 1: FIFO DEPTH=8 */
  141. # define PLX_DMA_ARB1_1_P2L_LW_TRIG(X) ( ((X)& 7) << 16 )
  142. # define PLX_DMA_ARB1_1_L2P_LR_TRIG(X) ( ((X)& 7) << 20 )
  143. # define PLX_DMA_ARB1_1_L2P_PW_TRIG(X) ( ((X)& 7) << 24 )
  144. # define PLX_DMA_ARB1_1_P2L_PR_TRIG(X) ( ((X)& 7) << 28 )
  145. typedef struct _dmachain
  146. {
  147. ulong pciaddr;
  148. ulong lcladdr;
  149. ulong len;
  150. ulong next;
  151. } DMACHAIN;