dgrs.c 38 KB

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  1. /*
  2. * Digi RightSwitch SE-X loadable device driver for Linux
  3. *
  4. * The RightSwitch is a 4 (EISA) or 6 (PCI) port etherswitch and
  5. * a NIC on an internal board.
  6. *
  7. * Author: Rick Richardson, rick@remotepoint.com
  8. * Derived from the SVR4.2 (UnixWare) driver for the same card.
  9. *
  10. * Copyright 1995-1996 Digi International Inc.
  11. *
  12. * This software may be used and distributed according to the terms
  13. * of the GNU General Public License, incorporated herein by reference.
  14. *
  15. * For information on purchasing a RightSwitch SE-4 or SE-6
  16. * board, please contact Digi's sales department at 1-612-912-3444
  17. * or 1-800-DIGIBRD. Outside the U.S., please check our Web page
  18. * at http://www.dgii.com for sales offices worldwide.
  19. *
  20. * OPERATION:
  21. * When compiled as a loadable module, this driver can operate
  22. * the board as either a 4/6 port switch with a 5th or 7th port
  23. * that is a conventional NIC interface as far as the host is
  24. * concerned, OR as 4/6 independent NICs. To select multi-NIC
  25. * mode, add "nicmode=1" on the insmod load line for the driver.
  26. *
  27. * This driver uses the "dev" common ethernet device structure
  28. * and a private "priv" (dev->priv) structure that contains
  29. * mostly DGRS-specific information and statistics. To keep
  30. * the code for both the switch mode and the multi-NIC mode
  31. * as similar as possible, I have introduced the concept of
  32. * "dev0"/"priv0" and "devN"/"privN" pointer pairs in subroutines
  33. * where needed. The first pair of pointers points to the
  34. * "dev" and "priv" structures of the zeroth (0th) device
  35. * interface associated with a board. The second pair of
  36. * pointers points to the current (Nth) device interface
  37. * for the board: the one for which we are processing data.
  38. *
  39. * In switch mode, the pairs of pointers are always the same,
  40. * that is, dev0 == devN and priv0 == privN. This is just
  41. * like previous releases of this driver which did not support
  42. * NIC mode.
  43. *
  44. * In multi-NIC mode, the pairs of pointers may be different.
  45. * We use the devN and privN pointers to reference just the
  46. * name, port number, and statistics for the current interface.
  47. * We use the dev0 and priv0 pointers to access the variables
  48. * that control access to the board, such as board address
  49. * and simulated 82596 variables. This is because there is
  50. * only one "fake" 82596 that serves as the interface to
  51. * the board. We do not want to try to keep the variables
  52. * associated with this 82596 in sync across all devices.
  53. *
  54. * This scheme works well. As you will see, except for
  55. * initialization, there is very little difference between
  56. * the two modes as far as this driver is concerned. On the
  57. * receive side in NIC mode, the interrupt *always* comes in on
  58. * the 0th interface (dev0/priv0). We then figure out which
  59. * real 82596 port it came in on from looking at the "chan"
  60. * member that the board firmware adds at the end of each
  61. * RBD (a.k.a. TBD). We get the channel number like this:
  62. * int chan = ((I596_RBD *) S2H(cbp->xmit.tbdp))->chan;
  63. *
  64. * On the transmit side in multi-NIC mode, we specify the
  65. * output 82596 port by setting the new "dstchan" structure
  66. * member that is at the end of the RFD, like this:
  67. * priv0->rfdp->dstchan = privN->chan;
  68. *
  69. * TODO:
  70. * - Multi-NIC mode is not yet supported when the driver is linked
  71. * into the kernel.
  72. * - Better handling of multicast addresses.
  73. *
  74. * Fixes:
  75. * Arnaldo Carvalho de Melo <acme@conectiva.com.br> - 11/01/2001
  76. * - fix dgrs_found_device wrt checking kmalloc return and
  77. * rollbacking the partial steps of the whole process when
  78. * one of the devices can't be allocated. Fix SET_MODULE_OWNER
  79. * on the loop to use devN instead of repeated calls to dev.
  80. *
  81. * davej <davej@suse.de> - 9/2/2001
  82. * - Enable PCI device before reading ioaddr/irq
  83. *
  84. */
  85. #include <linux/module.h>
  86. #include <linux/eisa.h>
  87. #include <linux/kernel.h>
  88. #include <linux/string.h>
  89. #include <linux/delay.h>
  90. #include <linux/errno.h>
  91. #include <linux/ioport.h>
  92. #include <linux/slab.h>
  93. #include <linux/interrupt.h>
  94. #include <linux/pci.h>
  95. #include <linux/init.h>
  96. #include <linux/netdevice.h>
  97. #include <linux/etherdevice.h>
  98. #include <linux/skbuff.h>
  99. #include <linux/bitops.h>
  100. #include <asm/io.h>
  101. #include <asm/byteorder.h>
  102. #include <asm/uaccess.h>
  103. static char version[] __initdata =
  104. "$Id: dgrs.c,v 1.1.1.1 2007/06/12 07:27:11 eyryu Exp $";
  105. /*
  106. * DGRS include files
  107. */
  108. typedef unsigned char uchar;
  109. #define vol volatile
  110. #include "dgrs.h"
  111. #include "dgrs_es4h.h"
  112. #include "dgrs_plx9060.h"
  113. #include "dgrs_i82596.h"
  114. #include "dgrs_ether.h"
  115. #include "dgrs_asstruct.h"
  116. #include "dgrs_bcomm.h"
  117. #ifdef CONFIG_PCI
  118. static struct pci_device_id dgrs_pci_tbl[] = {
  119. { SE6_PCI_VENDOR_ID, SE6_PCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID, },
  120. { } /* Terminating entry */
  121. };
  122. MODULE_DEVICE_TABLE(pci, dgrs_pci_tbl);
  123. #endif
  124. #ifdef CONFIG_EISA
  125. static struct eisa_device_id dgrs_eisa_tbl[] = {
  126. { "DBI0A01" },
  127. { }
  128. };
  129. MODULE_DEVICE_TABLE(eisa, dgrs_eisa_tbl);
  130. #endif
  131. MODULE_LICENSE("GPL");
  132. /*
  133. * Firmware. Compiled separately for local compilation,
  134. * but #included for Linux distribution.
  135. */
  136. #ifndef NOFW
  137. #include "dgrs_firmware.c"
  138. #else
  139. extern int dgrs_firmnum;
  140. extern char dgrs_firmver[];
  141. extern char dgrs_firmdate[];
  142. extern uchar dgrs_code[];
  143. extern int dgrs_ncode;
  144. #endif
  145. /*
  146. * Linux out*() is backwards from all other operating systems
  147. */
  148. #define OUTB(ADDR, VAL) outb(VAL, ADDR)
  149. #define OUTW(ADDR, VAL) outw(VAL, ADDR)
  150. #define OUTL(ADDR, VAL) outl(VAL, ADDR)
  151. /*
  152. * Macros to convert switch to host and host to switch addresses
  153. * (assumes a local variable priv points to board dependent struct)
  154. */
  155. #define S2H(A) ( ((unsigned long)(A)&0x00ffffff) + priv0->vmem )
  156. #define S2HN(A) ( ((unsigned long)(A)&0x00ffffff) + privN->vmem )
  157. #define H2S(A) ( ((char *) (A) - priv0->vmem) + 0xA3000000 )
  158. /*
  159. * Convert a switch address to a "safe" address for use with the
  160. * PLX 9060 DMA registers and the associated HW kludge that allows
  161. * for host access of the DMA registers.
  162. */
  163. #define S2DMA(A) ( (unsigned long)(A) & 0x00ffffff)
  164. /*
  165. * "Space.c" variables, now settable from module interface
  166. * Use the name below, minus the "dgrs_" prefix. See init_module().
  167. */
  168. static int dgrs_debug = 1;
  169. static int dgrs_dma = 1;
  170. static int dgrs_spantree = -1;
  171. static int dgrs_hashexpire = -1;
  172. static uchar dgrs_ipaddr[4] = { 0xff, 0xff, 0xff, 0xff};
  173. static uchar dgrs_iptrap[4] = { 0xff, 0xff, 0xff, 0xff};
  174. static __u32 dgrs_ipxnet = -1;
  175. static int dgrs_nicmode;
  176. /*
  177. * Private per-board data structure (dev->priv)
  178. */
  179. typedef struct
  180. {
  181. /*
  182. * Stuff for generic ethercard I/F
  183. */
  184. struct net_device_stats stats;
  185. /*
  186. * DGRS specific data
  187. */
  188. char *vmem;
  189. struct bios_comm *bcomm; /* Firmware BIOS comm structure */
  190. PORT *port; /* Ptr to PORT[0] struct in VM */
  191. I596_SCB *scbp; /* Ptr to SCB struct in VM */
  192. I596_RFD *rfdp; /* Current RFD list */
  193. I596_RBD *rbdp; /* Current RBD list */
  194. volatile int intrcnt; /* Count of interrupts */
  195. /*
  196. * SE-4 (EISA) board variables
  197. */
  198. uchar is_reg; /* EISA: Value for ES4H_IS reg */
  199. /*
  200. * SE-6 (PCI) board variables
  201. *
  202. * The PLX "expansion rom" space is used for DMA register
  203. * access from the host on the SE-6. These are the physical
  204. * and virtual addresses of that space.
  205. */
  206. ulong plxreg; /* Phys address of PLX chip */
  207. char *vplxreg; /* Virtual address of PLX chip */
  208. ulong plxdma; /* Phys addr of PLX "expansion rom" */
  209. ulong volatile *vplxdma; /* Virtual addr of "expansion rom" */
  210. int use_dma; /* Flag: use DMA */
  211. DMACHAIN *dmadesc_s; /* area for DMA chains (SW addr.) */
  212. DMACHAIN *dmadesc_h; /* area for DMA chains (Host Virtual) */
  213. /*
  214. * Multi-NIC mode variables
  215. *
  216. * All entries of the devtbl[] array are valid for the 0th
  217. * device (i.e. eth0, but not eth1...eth5). devtbl[0] is
  218. * valid for all devices (i.e. eth0, eth1, ..., eth5).
  219. */
  220. int nports; /* Number of physical ports (4 or 6) */
  221. int chan; /* Channel # (1-6) for this device */
  222. struct net_device *devtbl[6]; /* Ptrs to N device structs */
  223. } DGRS_PRIV;
  224. /*
  225. * reset or un-reset the IDT processor
  226. */
  227. static void
  228. proc_reset(struct net_device *dev0, int reset)
  229. {
  230. DGRS_PRIV *priv0 = (DGRS_PRIV *) dev0->priv;
  231. if (priv0->plxreg)
  232. {
  233. ulong val;
  234. val = inl(dev0->base_addr + PLX_MISC_CSR);
  235. if (reset)
  236. val |= SE6_RESET;
  237. else
  238. val &= ~SE6_RESET;
  239. OUTL(dev0->base_addr + PLX_MISC_CSR, val);
  240. }
  241. else
  242. {
  243. OUTB(dev0->base_addr + ES4H_PC, reset ? ES4H_PC_RESET : 0);
  244. }
  245. }
  246. /*
  247. * See if the board supports bus master DMA
  248. */
  249. static int
  250. check_board_dma(struct net_device *dev0)
  251. {
  252. DGRS_PRIV *priv0 = (DGRS_PRIV *) dev0->priv;
  253. ulong x;
  254. /*
  255. * If Space.c says not to use DMA, or if it's not a PLX based
  256. * PCI board, or if the expansion ROM space is not PCI
  257. * configured, then return false.
  258. */
  259. if (!dgrs_dma || !priv0->plxreg || !priv0->plxdma)
  260. return (0);
  261. /*
  262. * Set the local address remap register of the "expansion rom"
  263. * area to 0x80000000 so that we can use it to access the DMA
  264. * registers from the host side.
  265. */
  266. OUTL(dev0->base_addr + PLX_ROM_BASE_ADDR, 0x80000000);
  267. /*
  268. * Set the PCI region descriptor to:
  269. * Space 0:
  270. * disable read-prefetch
  271. * enable READY
  272. * enable BURST
  273. * 0 internal wait states
  274. * Expansion ROM: (used for host DMA register access)
  275. * disable read-prefetch
  276. * enable READY
  277. * disable BURST
  278. * 0 internal wait states
  279. */
  280. OUTL(dev0->base_addr + PLX_BUS_REGION, 0x49430343);
  281. /*
  282. * Now map the DMA registers into our virtual space
  283. */
  284. priv0->vplxdma = (ulong *) ioremap (priv0->plxdma, 256);
  285. if (!priv0->vplxdma)
  286. {
  287. printk("%s: can't *remap() the DMA regs\n", dev0->name);
  288. return (0);
  289. }
  290. /*
  291. * Now test to see if we can access the DMA registers
  292. * If we write -1 and get back 1FFF, then we accessed the
  293. * DMA register. Otherwise, we probably have an old board
  294. * and wrote into regular RAM.
  295. */
  296. priv0->vplxdma[PLX_DMA0_MODE/4] = 0xFFFFFFFF;
  297. x = priv0->vplxdma[PLX_DMA0_MODE/4];
  298. if (x != 0x00001FFF) {
  299. iounmap((void *)priv0->vplxdma);
  300. return (0);
  301. }
  302. return (1);
  303. }
  304. /*
  305. * Initiate DMA using PLX part on PCI board. Spin the
  306. * processor until completed. All addresses are physical!
  307. *
  308. * If pciaddr is NULL, then it's a chaining DMA, and lcladdr is
  309. * the address of the first DMA descriptor in the chain.
  310. *
  311. * If pciaddr is not NULL, then it's a single DMA.
  312. *
  313. * In either case, "lcladdr" must have been fixed up to make
  314. * sure the MSB isn't set using the S2DMA macro before passing
  315. * the address to this routine.
  316. */
  317. static int
  318. do_plx_dma(
  319. struct net_device *dev,
  320. ulong pciaddr,
  321. ulong lcladdr,
  322. int len,
  323. int to_host
  324. )
  325. {
  326. int i;
  327. ulong csr = 0;
  328. DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
  329. if (pciaddr)
  330. {
  331. /*
  332. * Do a single, non-chain DMA
  333. */
  334. priv->vplxdma[PLX_DMA0_PCI_ADDR/4] = pciaddr;
  335. priv->vplxdma[PLX_DMA0_LCL_ADDR/4] = lcladdr;
  336. priv->vplxdma[PLX_DMA0_SIZE/4] = len;
  337. priv->vplxdma[PLX_DMA0_DESCRIPTOR/4] = to_host
  338. ? PLX_DMA_DESC_TO_HOST
  339. : PLX_DMA_DESC_TO_BOARD;
  340. priv->vplxdma[PLX_DMA0_MODE/4] =
  341. PLX_DMA_MODE_WIDTH32
  342. | PLX_DMA_MODE_WAITSTATES(0)
  343. | PLX_DMA_MODE_READY
  344. | PLX_DMA_MODE_NOBTERM
  345. | PLX_DMA_MODE_BURST
  346. | PLX_DMA_MODE_NOCHAIN;
  347. }
  348. else
  349. {
  350. /*
  351. * Do a chaining DMA
  352. */
  353. priv->vplxdma[PLX_DMA0_MODE/4] =
  354. PLX_DMA_MODE_WIDTH32
  355. | PLX_DMA_MODE_WAITSTATES(0)
  356. | PLX_DMA_MODE_READY
  357. | PLX_DMA_MODE_NOBTERM
  358. | PLX_DMA_MODE_BURST
  359. | PLX_DMA_MODE_CHAIN;
  360. priv->vplxdma[PLX_DMA0_DESCRIPTOR/4] = lcladdr;
  361. }
  362. priv->vplxdma[PLX_DMA_CSR/4] =
  363. PLX_DMA_CSR_0_ENABLE | PLX_DMA_CSR_0_START;
  364. /*
  365. * Wait for DMA to complete
  366. */
  367. for (i = 0; i < 1000000; ++i)
  368. {
  369. /*
  370. * Spin the host CPU for 1 usec, so we don't thrash
  371. * the PCI bus while the PLX 9060 is doing DMA.
  372. */
  373. udelay(1);
  374. csr = (volatile unsigned long) priv->vplxdma[PLX_DMA_CSR/4];
  375. if (csr & PLX_DMA_CSR_0_DONE)
  376. break;
  377. }
  378. if ( ! (csr & PLX_DMA_CSR_0_DONE) )
  379. {
  380. printk("%s: DMA done never occurred. DMA disabled.\n",
  381. dev->name);
  382. priv->use_dma = 0;
  383. return 1;
  384. }
  385. return 0;
  386. }
  387. /*
  388. * dgrs_rcv_frame()
  389. *
  390. * Process a received frame. This is called from the interrupt
  391. * routine, and works for both switch mode and multi-NIC mode.
  392. *
  393. * Note that when in multi-NIC mode, we want to always access the
  394. * hardware using the dev and priv structures of the first port,
  395. * so that we are using only one set of variables to maintain
  396. * the board interface status, but we want to use the Nth port
  397. * dev and priv structures to maintain statistics and to pass
  398. * the packet up.
  399. *
  400. * Only the first device structure is attached to the interrupt.
  401. * We use the special "chan" variable at the end of the first RBD
  402. * to select the Nth device in multi-NIC mode.
  403. *
  404. * We currently do chained DMA on a per-packet basis when the
  405. * packet is "long", and we spin the CPU a short time polling
  406. * for DMA completion. This avoids a second interrupt overhead,
  407. * and gives the best performance for light traffic to the host.
  408. *
  409. * However, a better scheme that could be implemented would be
  410. * to see how many packets are outstanding for the host, and if
  411. * the number is "large", create a long chain to DMA several
  412. * packets into the host in one go. In this case, we would set
  413. * up some state variables to let the host CPU continue doing
  414. * other things until a DMA completion interrupt comes along.
  415. */
  416. static void
  417. dgrs_rcv_frame(
  418. struct net_device *dev0,
  419. DGRS_PRIV *priv0,
  420. I596_CB *cbp
  421. )
  422. {
  423. int len;
  424. I596_TBD *tbdp;
  425. struct sk_buff *skb;
  426. uchar *putp;
  427. uchar *p;
  428. struct net_device *devN;
  429. DGRS_PRIV *privN;
  430. /*
  431. * Determine Nth priv and dev structure pointers
  432. */
  433. if (dgrs_nicmode)
  434. { /* Multi-NIC mode */
  435. int chan = ((I596_RBD *) S2H(cbp->xmit.tbdp))->chan;
  436. devN = priv0->devtbl[chan-1];
  437. /*
  438. * If devN is null, we got an interrupt before the I/F
  439. * has been initialized. Pitch the packet.
  440. */
  441. if (devN == NULL)
  442. goto out;
  443. privN = (DGRS_PRIV *) devN->priv;
  444. }
  445. else
  446. { /* Switch mode */
  447. devN = dev0;
  448. privN = priv0;
  449. }
  450. if (0) printk("%s: rcv len=%ld\n", devN->name, cbp->xmit.count);
  451. /*
  452. * Allocate a message block big enough to hold the whole frame
  453. */
  454. len = cbp->xmit.count;
  455. if ((skb = dev_alloc_skb(len+5)) == NULL)
  456. {
  457. printk("%s: dev_alloc_skb failed for rcv buffer\n", devN->name);
  458. ++privN->stats.rx_dropped;
  459. /* discarding the frame */
  460. goto out;
  461. }
  462. skb->dev = devN;
  463. skb_reserve(skb, 2); /* Align IP header */
  464. again:
  465. putp = p = skb_put(skb, len);
  466. /*
  467. * There are three modes here for doing the packet copy.
  468. * If we have DMA, and the packet is "long", we use the
  469. * chaining mode of DMA. If it's shorter, we use single
  470. * DMA's. Otherwise, we use memcpy().
  471. */
  472. if (priv0->use_dma && priv0->dmadesc_h && len > 64)
  473. {
  474. /*
  475. * If we can use DMA and it's a long frame, copy it using
  476. * DMA chaining.
  477. */
  478. DMACHAIN *ddp_h; /* Host virtual DMA desc. pointer */
  479. DMACHAIN *ddp_s; /* Switch physical DMA desc. pointer */
  480. uchar *phys_p;
  481. /*
  482. * Get the physical address of the STREAMS buffer.
  483. * NOTE: allocb() guarantees that the whole buffer
  484. * is in a single page if the length < 4096.
  485. */
  486. phys_p = (uchar *) virt_to_phys(putp);
  487. ddp_h = priv0->dmadesc_h;
  488. ddp_s = priv0->dmadesc_s;
  489. tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
  490. for (;;)
  491. {
  492. int count;
  493. int amt;
  494. count = tbdp->count;
  495. amt = count & 0x3fff;
  496. if (amt == 0)
  497. break; /* For safety */
  498. if ( (p-putp) >= len)
  499. {
  500. printk("%s: cbp = %lx\n", devN->name, (long) H2S(cbp));
  501. proc_reset(dev0, 1); /* Freeze IDT */
  502. break; /* For Safety */
  503. }
  504. ddp_h->pciaddr = (ulong) phys_p;
  505. ddp_h->lcladdr = S2DMA(tbdp->buf);
  506. ddp_h->len = amt;
  507. phys_p += amt;
  508. p += amt;
  509. if (count & I596_TBD_EOF)
  510. {
  511. ddp_h->next = PLX_DMA_DESC_TO_HOST
  512. | PLX_DMA_DESC_EOC;
  513. ++ddp_h;
  514. break;
  515. }
  516. else
  517. {
  518. ++ddp_s;
  519. ddp_h->next = PLX_DMA_DESC_TO_HOST
  520. | (ulong) ddp_s;
  521. tbdp = (I596_TBD *) S2H(tbdp->next);
  522. ++ddp_h;
  523. }
  524. }
  525. if (ddp_h - priv0->dmadesc_h)
  526. {
  527. int rc;
  528. rc = do_plx_dma(dev0,
  529. 0, (ulong) priv0->dmadesc_s, len, 0);
  530. if (rc)
  531. {
  532. printk("%s: Chained DMA failure\n", devN->name);
  533. goto again;
  534. }
  535. }
  536. }
  537. else if (priv0->use_dma)
  538. {
  539. /*
  540. * If we can use DMA and it's a shorter frame, copy it
  541. * using single DMA transfers.
  542. */
  543. uchar *phys_p;
  544. /*
  545. * Get the physical address of the STREAMS buffer.
  546. * NOTE: allocb() guarantees that the whole buffer
  547. * is in a single page if the length < 4096.
  548. */
  549. phys_p = (uchar *) virt_to_phys(putp);
  550. tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
  551. for (;;)
  552. {
  553. int count;
  554. int amt;
  555. int rc;
  556. count = tbdp->count;
  557. amt = count & 0x3fff;
  558. if (amt == 0)
  559. break; /* For safety */
  560. if ( (p-putp) >= len)
  561. {
  562. printk("%s: cbp = %lx\n", devN->name, (long) H2S(cbp));
  563. proc_reset(dev0, 1); /* Freeze IDT */
  564. break; /* For Safety */
  565. }
  566. rc = do_plx_dma(dev0, (ulong) phys_p,
  567. S2DMA(tbdp->buf), amt, 1);
  568. if (rc)
  569. {
  570. memcpy(p, S2H(tbdp->buf), amt);
  571. printk("%s: Single DMA failed\n", devN->name);
  572. }
  573. phys_p += amt;
  574. p += amt;
  575. if (count & I596_TBD_EOF)
  576. break;
  577. tbdp = (I596_TBD *) S2H(tbdp->next);
  578. }
  579. }
  580. else
  581. {
  582. /*
  583. * Otherwise, copy it piece by piece using memcpy()
  584. */
  585. tbdp = (I596_TBD *) S2H(cbp->xmit.tbdp);
  586. for (;;)
  587. {
  588. int count;
  589. int amt;
  590. count = tbdp->count;
  591. amt = count & 0x3fff;
  592. if (amt == 0)
  593. break; /* For safety */
  594. if ( (p-putp) >= len)
  595. {
  596. printk("%s: cbp = %lx\n", devN->name, (long) H2S(cbp));
  597. proc_reset(dev0, 1); /* Freeze IDT */
  598. break; /* For Safety */
  599. }
  600. memcpy(p, S2H(tbdp->buf), amt);
  601. p += amt;
  602. if (count & I596_TBD_EOF)
  603. break;
  604. tbdp = (I596_TBD *) S2H(tbdp->next);
  605. }
  606. }
  607. /*
  608. * Pass the frame to upper half
  609. */
  610. skb->protocol = eth_type_trans(skb, devN);
  611. netif_rx(skb);
  612. devN->last_rx = jiffies;
  613. ++privN->stats.rx_packets;
  614. privN->stats.rx_bytes += len;
  615. out:
  616. cbp->xmit.status = I596_CB_STATUS_C | I596_CB_STATUS_OK;
  617. }
  618. /*
  619. * Start transmission of a frame
  620. *
  621. * The interface to the board is simple: we pretend that we are
  622. * a fifth 82596 ethernet controller 'receiving' data, and copy the
  623. * data into the same structures that a real 82596 would. This way,
  624. * the board firmware handles the host 'port' the same as any other.
  625. *
  626. * NOTE: we do not use Bus master DMA for this routine. Turns out
  627. * that it is not needed. Slave writes over the PCI bus are about
  628. * as fast as DMA, due to the fact that the PLX part can do burst
  629. * writes. The same is not true for data being read from the board.
  630. *
  631. * For multi-NIC mode, we tell the firmware the desired 82596
  632. * output port by setting the special "dstchan" member at the
  633. * end of the traditional 82596 RFD structure.
  634. */
  635. static int dgrs_start_xmit(struct sk_buff *skb, struct net_device *devN)
  636. {
  637. DGRS_PRIV *privN = (DGRS_PRIV *) devN->priv;
  638. struct net_device *dev0;
  639. DGRS_PRIV *priv0;
  640. I596_RBD *rbdp;
  641. int count;
  642. int i, len, amt;
  643. /*
  644. * Determine 0th priv and dev structure pointers
  645. */
  646. if (dgrs_nicmode)
  647. {
  648. dev0 = privN->devtbl[0];
  649. priv0 = (DGRS_PRIV *) dev0->priv;
  650. }
  651. else
  652. {
  653. dev0 = devN;
  654. priv0 = privN;
  655. }
  656. if (dgrs_debug > 1)
  657. printk("%s: xmit len=%d\n", devN->name, (int) skb->len);
  658. devN->trans_start = jiffies;
  659. netif_start_queue(devN);
  660. if (priv0->rfdp->cmd & I596_RFD_EL)
  661. { /* Out of RFD's */
  662. if (0) printk("%s: NO RFD's\n", devN->name);
  663. goto no_resources;
  664. }
  665. rbdp = priv0->rbdp;
  666. count = 0;
  667. priv0->rfdp->rbdp = (I596_RBD *) H2S(rbdp);
  668. i = 0; len = skb->len;
  669. for (;;)
  670. {
  671. if (rbdp->size & I596_RBD_EL)
  672. { /* Out of RBD's */
  673. if (0) printk("%s: NO RBD's\n", devN->name);
  674. goto no_resources;
  675. }
  676. amt = min_t(unsigned int, len, rbdp->size - count);
  677. memcpy( (char *) S2H(rbdp->buf) + count, skb->data + i, amt);
  678. i += amt;
  679. count += amt;
  680. len -= amt;
  681. if (len == 0)
  682. {
  683. if (skb->len < 60)
  684. rbdp->count = 60 | I596_RBD_EOF;
  685. else
  686. rbdp->count = count | I596_RBD_EOF;
  687. rbdp = (I596_RBD *) S2H(rbdp->next);
  688. goto frame_done;
  689. }
  690. else if (count < 32)
  691. {
  692. /* More data to come, but we used less than 32
  693. * bytes of this RBD. Keep filling this RBD.
  694. */
  695. {} /* Yes, we do nothing here */
  696. }
  697. else
  698. {
  699. rbdp->count = count;
  700. rbdp = (I596_RBD *) S2H(rbdp->next);
  701. count = 0;
  702. }
  703. }
  704. frame_done:
  705. priv0->rbdp = rbdp;
  706. if (dgrs_nicmode)
  707. priv0->rfdp->dstchan = privN->chan;
  708. priv0->rfdp->status = I596_RFD_C | I596_RFD_OK;
  709. priv0->rfdp = (I596_RFD *) S2H(priv0->rfdp->next);
  710. ++privN->stats.tx_packets;
  711. dev_kfree_skb (skb);
  712. return (0);
  713. no_resources:
  714. priv0->scbp->status |= I596_SCB_RNR; /* simulate I82596 */
  715. return (-EAGAIN);
  716. }
  717. /*
  718. * Open the interface
  719. */
  720. static int
  721. dgrs_open( struct net_device *dev )
  722. {
  723. netif_start_queue(dev);
  724. return (0);
  725. }
  726. /*
  727. * Close the interface
  728. */
  729. static int dgrs_close( struct net_device *dev )
  730. {
  731. netif_stop_queue(dev);
  732. return (0);
  733. }
  734. /*
  735. * Get statistics
  736. */
  737. static struct net_device_stats *dgrs_get_stats( struct net_device *dev )
  738. {
  739. DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
  740. return (&priv->stats);
  741. }
  742. /*
  743. * Set multicast list and/or promiscuous mode
  744. */
  745. static void dgrs_set_multicast_list( struct net_device *dev)
  746. {
  747. DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
  748. priv->port->is_promisc = (dev->flags & IFF_PROMISC) ? 1 : 0;
  749. }
  750. /*
  751. * Unique ioctl's
  752. */
  753. static int dgrs_ioctl(struct net_device *devN, struct ifreq *ifr, int cmd)
  754. {
  755. DGRS_PRIV *privN = (DGRS_PRIV *) devN->priv;
  756. DGRS_IOCTL ioc;
  757. int i;
  758. if (cmd != DGRSIOCTL)
  759. return -EINVAL;
  760. if(copy_from_user(&ioc, ifr->ifr_data, sizeof(DGRS_IOCTL)))
  761. return -EFAULT;
  762. switch (ioc.cmd)
  763. {
  764. case DGRS_GETMEM:
  765. if (ioc.len != sizeof(ulong))
  766. return -EINVAL;
  767. if(copy_to_user(ioc.data, &devN->mem_start, ioc.len))
  768. return -EFAULT;
  769. return (0);
  770. case DGRS_SETFILTER:
  771. if (!capable(CAP_NET_ADMIN))
  772. return -EPERM;
  773. if (ioc.port > privN->bcomm->bc_nports)
  774. return -EINVAL;
  775. if (ioc.filter >= NFILTERS)
  776. return -EINVAL;
  777. if (ioc.len > privN->bcomm->bc_filter_area_len)
  778. return -EINVAL;
  779. /* Wait for old command to finish */
  780. for (i = 0; i < 1000; ++i)
  781. {
  782. if ( (volatile long) privN->bcomm->bc_filter_cmd <= 0 )
  783. break;
  784. udelay(1);
  785. }
  786. if (i >= 1000)
  787. return -EIO;
  788. privN->bcomm->bc_filter_port = ioc.port;
  789. privN->bcomm->bc_filter_num = ioc.filter;
  790. privN->bcomm->bc_filter_len = ioc.len;
  791. if (ioc.len)
  792. {
  793. if(copy_from_user(S2HN(privN->bcomm->bc_filter_area),
  794. ioc.data, ioc.len))
  795. return -EFAULT;
  796. privN->bcomm->bc_filter_cmd = BC_FILTER_SET;
  797. }
  798. else
  799. privN->bcomm->bc_filter_cmd = BC_FILTER_CLR;
  800. return(0);
  801. default:
  802. return -EOPNOTSUPP;
  803. }
  804. }
  805. /*
  806. * Process interrupts
  807. *
  808. * dev, priv will always refer to the 0th device in Multi-NIC mode.
  809. */
  810. static irqreturn_t dgrs_intr(int irq, void *dev_id)
  811. {
  812. struct net_device *dev0 = dev_id;
  813. DGRS_PRIV *priv0 = dev0->priv;
  814. I596_CB *cbp;
  815. int cmd;
  816. int i;
  817. ++priv0->intrcnt;
  818. if (1) ++priv0->bcomm->bc_cnt[4];
  819. if (0)
  820. {
  821. static int cnt = 100;
  822. if (--cnt > 0)
  823. printk("%s: interrupt: irq %d\n", dev0->name, irq);
  824. }
  825. /*
  826. * Get 596 command
  827. */
  828. cmd = priv0->scbp->cmd;
  829. /*
  830. * See if RU has been restarted
  831. */
  832. if ( (cmd & I596_SCB_RUC) == I596_SCB_RUC_START)
  833. {
  834. if (0) printk("%s: RUC start\n", dev0->name);
  835. priv0->rfdp = (I596_RFD *) S2H(priv0->scbp->rfdp);
  836. priv0->rbdp = (I596_RBD *) S2H(priv0->rfdp->rbdp);
  837. priv0->scbp->status &= ~(I596_SCB_RNR|I596_SCB_RUS);
  838. /*
  839. * Tell upper half (halves)
  840. */
  841. if (dgrs_nicmode)
  842. {
  843. for (i = 0; i < priv0->nports; ++i)
  844. netif_wake_queue (priv0->devtbl[i]);
  845. }
  846. else
  847. netif_wake_queue (dev0);
  848. /* if (bd->flags & TX_QUEUED)
  849. DL_sched(bd, bdd); */
  850. }
  851. /*
  852. * See if any CU commands to process
  853. */
  854. if ( (cmd & I596_SCB_CUC) != I596_SCB_CUC_START)
  855. {
  856. priv0->scbp->cmd = 0; /* Ignore all other commands */
  857. goto ack_intr;
  858. }
  859. priv0->scbp->status &= ~(I596_SCB_CNA|I596_SCB_CUS);
  860. /*
  861. * Process a command
  862. */
  863. cbp = (I596_CB *) S2H(priv0->scbp->cbp);
  864. priv0->scbp->cmd = 0; /* Safe to clear the command */
  865. for (;;)
  866. {
  867. switch (cbp->nop.cmd & I596_CB_CMD)
  868. {
  869. case I596_CB_CMD_XMIT:
  870. dgrs_rcv_frame(dev0, priv0, cbp);
  871. break;
  872. default:
  873. cbp->nop.status = I596_CB_STATUS_C | I596_CB_STATUS_OK;
  874. break;
  875. }
  876. if (cbp->nop.cmd & I596_CB_CMD_EL)
  877. break;
  878. cbp = (I596_CB *) S2H(cbp->nop.next);
  879. }
  880. priv0->scbp->status |= I596_SCB_CNA;
  881. /*
  882. * Ack the interrupt
  883. */
  884. ack_intr:
  885. if (priv0->plxreg)
  886. OUTL(dev0->base_addr + PLX_LCL2PCI_DOORBELL, 1);
  887. return IRQ_HANDLED;
  888. }
  889. /*
  890. * Download the board firmware
  891. */
  892. static int __init
  893. dgrs_download(struct net_device *dev0)
  894. {
  895. DGRS_PRIV *priv0 = (DGRS_PRIV *) dev0->priv;
  896. int is;
  897. unsigned long i;
  898. static const int iv2is[16] = {
  899. 0, 0, 0, ES4H_IS_INT3,
  900. 0, ES4H_IS_INT5, 0, ES4H_IS_INT7,
  901. 0, 0, ES4H_IS_INT10, ES4H_IS_INT11,
  902. ES4H_IS_INT12, 0, 0, ES4H_IS_INT15 };
  903. /*
  904. * Map in the dual port memory
  905. */
  906. priv0->vmem = ioremap(dev0->mem_start, 2048*1024);
  907. if (!priv0->vmem)
  908. {
  909. printk("%s: cannot map in board memory\n", dev0->name);
  910. return -ENXIO;
  911. }
  912. /*
  913. * Hold the processor and configure the board addresses
  914. */
  915. if (priv0->plxreg)
  916. { /* PCI bus */
  917. proc_reset(dev0, 1);
  918. }
  919. else
  920. { /* EISA bus */
  921. is = iv2is[dev0->irq & 0x0f];
  922. if (!is)
  923. {
  924. printk("%s: Illegal IRQ %d\n", dev0->name, dev0->irq);
  925. iounmap(priv0->vmem);
  926. priv0->vmem = NULL;
  927. return -ENXIO;
  928. }
  929. OUTB(dev0->base_addr + ES4H_AS_31_24,
  930. (uchar) (dev0->mem_start >> 24) );
  931. OUTB(dev0->base_addr + ES4H_AS_23_16,
  932. (uchar) (dev0->mem_start >> 16) );
  933. priv0->is_reg = ES4H_IS_LINEAR | is |
  934. ((uchar) (dev0->mem_start >> 8) & ES4H_IS_AS15);
  935. OUTB(dev0->base_addr + ES4H_IS, priv0->is_reg);
  936. OUTB(dev0->base_addr + ES4H_EC, ES4H_EC_ENABLE);
  937. OUTB(dev0->base_addr + ES4H_PC, ES4H_PC_RESET);
  938. OUTB(dev0->base_addr + ES4H_MW, ES4H_MW_ENABLE | 0x00);
  939. }
  940. /*
  941. * See if we can do DMA on the SE-6
  942. */
  943. priv0->use_dma = check_board_dma(dev0);
  944. if (priv0->use_dma)
  945. printk("%s: Bus Master DMA is enabled.\n", dev0->name);
  946. /*
  947. * Load and verify the code at the desired address
  948. */
  949. memcpy(priv0->vmem, dgrs_code, dgrs_ncode); /* Load code */
  950. if (memcmp(priv0->vmem, dgrs_code, dgrs_ncode))
  951. {
  952. iounmap(priv0->vmem);
  953. priv0->vmem = NULL;
  954. printk("%s: download compare failed\n", dev0->name);
  955. return -ENXIO;
  956. }
  957. /*
  958. * Configurables
  959. */
  960. priv0->bcomm = (struct bios_comm *) (priv0->vmem + 0x0100);
  961. priv0->bcomm->bc_nowait = 1; /* Tell board to make printf not wait */
  962. priv0->bcomm->bc_squelch = 0; /* Flag from Space.c */
  963. priv0->bcomm->bc_150ohm = 0; /* Flag from Space.c */
  964. priv0->bcomm->bc_spew = 0; /* Debug flag from Space.c */
  965. priv0->bcomm->bc_maxrfd = 0; /* Debug flag from Space.c */
  966. priv0->bcomm->bc_maxrbd = 0; /* Debug flag from Space.c */
  967. /*
  968. * Tell board we are operating in switch mode (1) or in
  969. * multi-NIC mode (2).
  970. */
  971. priv0->bcomm->bc_host = dgrs_nicmode ? BC_MULTINIC : BC_SWITCH;
  972. /*
  973. * Request memory space on board for DMA chains
  974. */
  975. if (priv0->use_dma)
  976. priv0->bcomm->bc_hostarea_len = (2048/64) * 16;
  977. /*
  978. * NVRAM configurables from Space.c
  979. */
  980. priv0->bcomm->bc_spantree = dgrs_spantree;
  981. priv0->bcomm->bc_hashexpire = dgrs_hashexpire;
  982. memcpy(priv0->bcomm->bc_ipaddr, dgrs_ipaddr, 4);
  983. memcpy(priv0->bcomm->bc_iptrap, dgrs_iptrap, 4);
  984. memcpy(priv0->bcomm->bc_ipxnet, &dgrs_ipxnet, 4);
  985. /*
  986. * Release processor, wait 8 seconds for board to initialize
  987. */
  988. proc_reset(dev0, 0);
  989. for (i = jiffies + 8 * HZ; time_after(i, jiffies); )
  990. {
  991. barrier(); /* Gcc 2.95 needs this */
  992. if (priv0->bcomm->bc_status >= BC_RUN)
  993. break;
  994. }
  995. if (priv0->bcomm->bc_status < BC_RUN)
  996. {
  997. printk("%s: board not operating\n", dev0->name);
  998. iounmap(priv0->vmem);
  999. priv0->vmem = NULL;
  1000. return -ENXIO;
  1001. }
  1002. priv0->port = (PORT *) S2H(priv0->bcomm->bc_port);
  1003. priv0->scbp = (I596_SCB *) S2H(priv0->port->scbp);
  1004. priv0->rfdp = (I596_RFD *) S2H(priv0->scbp->rfdp);
  1005. priv0->rbdp = (I596_RBD *) S2H(priv0->rfdp->rbdp);
  1006. priv0->scbp->status = I596_SCB_CNA; /* CU is idle */
  1007. /*
  1008. * Get switch physical and host virtual pointers to DMA
  1009. * chaining area. NOTE: the MSB of the switch physical
  1010. * address *must* be turned off. Otherwise, the HW kludge
  1011. * that allows host access of the PLX DMA registers will
  1012. * erroneously select the PLX registers.
  1013. */
  1014. priv0->dmadesc_s = (DMACHAIN *) S2DMA(priv0->bcomm->bc_hostarea);
  1015. if (priv0->dmadesc_s)
  1016. priv0->dmadesc_h = (DMACHAIN *) S2H(priv0->dmadesc_s);
  1017. else
  1018. priv0->dmadesc_h = NULL;
  1019. /*
  1020. * Enable board interrupts
  1021. */
  1022. if (priv0->plxreg)
  1023. { /* PCI bus */
  1024. OUTL(dev0->base_addr + PLX_INT_CSR,
  1025. inl(dev0->base_addr + PLX_INT_CSR)
  1026. | PLX_PCI_DOORBELL_IE); /* Enable intr to host */
  1027. OUTL(dev0->base_addr + PLX_LCL2PCI_DOORBELL, 1);
  1028. }
  1029. else
  1030. { /* EISA bus */
  1031. }
  1032. return (0);
  1033. }
  1034. /*
  1035. * Probe (init) a board
  1036. */
  1037. static int __init
  1038. dgrs_probe1(struct net_device *dev)
  1039. {
  1040. DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
  1041. unsigned long i;
  1042. int rc;
  1043. printk("%s: Digi RightSwitch io=%lx mem=%lx irq=%d plx=%lx dma=%lx\n",
  1044. dev->name, dev->base_addr, dev->mem_start, dev->irq,
  1045. priv->plxreg, priv->plxdma);
  1046. /*
  1047. * Download the firmware and light the processor
  1048. */
  1049. rc = dgrs_download(dev);
  1050. if (rc)
  1051. goto err_out;
  1052. /*
  1053. * Get ether address of board
  1054. */
  1055. printk("%s: Ethernet address", dev->name);
  1056. memcpy(dev->dev_addr, priv->port->ethaddr, 6);
  1057. for (i = 0; i < 6; ++i)
  1058. printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
  1059. printk("\n");
  1060. if (dev->dev_addr[0] & 1)
  1061. {
  1062. printk("%s: Illegal Ethernet Address\n", dev->name);
  1063. rc = -ENXIO;
  1064. goto err_out;
  1065. }
  1066. /*
  1067. * ACK outstanding interrupts, hook the interrupt,
  1068. * and verify that we are getting interrupts from the board.
  1069. */
  1070. if (priv->plxreg)
  1071. OUTL(dev->base_addr + PLX_LCL2PCI_DOORBELL, 1);
  1072. rc = request_irq(dev->irq, &dgrs_intr, IRQF_SHARED, "RightSwitch", dev);
  1073. if (rc)
  1074. goto err_out;
  1075. priv->intrcnt = 0;
  1076. for (i = jiffies + 2*HZ + HZ/2; time_after(i, jiffies); )
  1077. {
  1078. cpu_relax();
  1079. if (priv->intrcnt >= 2)
  1080. break;
  1081. }
  1082. if (priv->intrcnt < 2)
  1083. {
  1084. printk(KERN_ERR "%s: Not interrupting on IRQ %d (%d)\n",
  1085. dev->name, dev->irq, priv->intrcnt);
  1086. rc = -ENXIO;
  1087. goto err_free_irq;
  1088. }
  1089. /*
  1090. * Entry points...
  1091. */
  1092. dev->open = &dgrs_open;
  1093. dev->stop = &dgrs_close;
  1094. dev->get_stats = &dgrs_get_stats;
  1095. dev->hard_start_xmit = &dgrs_start_xmit;
  1096. dev->set_multicast_list = &dgrs_set_multicast_list;
  1097. dev->do_ioctl = &dgrs_ioctl;
  1098. return rc;
  1099. err_free_irq:
  1100. free_irq(dev->irq, dev);
  1101. err_out:
  1102. return rc;
  1103. }
  1104. static int __init
  1105. dgrs_initclone(struct net_device *dev)
  1106. {
  1107. DGRS_PRIV *priv = (DGRS_PRIV *) dev->priv;
  1108. int i;
  1109. printk("%s: Digi RightSwitch port %d ",
  1110. dev->name, priv->chan);
  1111. for (i = 0; i < 6; ++i)
  1112. printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
  1113. printk("\n");
  1114. return (0);
  1115. }
  1116. static struct net_device * __init
  1117. dgrs_found_device(
  1118. int io,
  1119. ulong mem,
  1120. int irq,
  1121. ulong plxreg,
  1122. ulong plxdma,
  1123. struct device *pdev
  1124. )
  1125. {
  1126. DGRS_PRIV *priv;
  1127. struct net_device *dev;
  1128. int i, ret = -ENOMEM;
  1129. dev = alloc_etherdev(sizeof(DGRS_PRIV));
  1130. if (!dev)
  1131. goto err0;
  1132. priv = (DGRS_PRIV *)dev->priv;
  1133. dev->base_addr = io;
  1134. dev->mem_start = mem;
  1135. dev->mem_end = mem + 2048 * 1024 - 1;
  1136. dev->irq = irq;
  1137. priv->plxreg = plxreg;
  1138. priv->plxdma = plxdma;
  1139. priv->vplxdma = NULL;
  1140. priv->chan = 1;
  1141. priv->devtbl[0] = dev;
  1142. SET_MODULE_OWNER(dev);
  1143. SET_NETDEV_DEV(dev, pdev);
  1144. ret = dgrs_probe1(dev);
  1145. if (ret)
  1146. goto err1;
  1147. ret = register_netdev(dev);
  1148. if (ret)
  1149. goto err2;
  1150. if ( !dgrs_nicmode )
  1151. return dev; /* Switch mode, we are done */
  1152. /*
  1153. * Operating card as N separate NICs
  1154. */
  1155. priv->nports = priv->bcomm->bc_nports;
  1156. for (i = 1; i < priv->nports; ++i)
  1157. {
  1158. struct net_device *devN;
  1159. DGRS_PRIV *privN;
  1160. /* Allocate new dev and priv structures */
  1161. devN = alloc_etherdev(sizeof(DGRS_PRIV));
  1162. ret = -ENOMEM;
  1163. if (!devN)
  1164. goto fail;
  1165. /* Don't copy the network device structure! */
  1166. /* copy the priv structure of dev[0] */
  1167. privN = (DGRS_PRIV *)devN->priv;
  1168. *privN = *priv;
  1169. /* ... and zero out VM areas */
  1170. privN->vmem = NULL;
  1171. privN->vplxdma = NULL;
  1172. /* ... and zero out IRQ */
  1173. devN->irq = 0;
  1174. /* ... and base MAC address off address of 1st port */
  1175. devN->dev_addr[5] += i;
  1176. ret = dgrs_initclone(devN);
  1177. if (ret)
  1178. goto fail;
  1179. SET_MODULE_OWNER(devN);
  1180. SET_NETDEV_DEV(dev, pdev);
  1181. ret = register_netdev(devN);
  1182. if (ret) {
  1183. free_netdev(devN);
  1184. goto fail;
  1185. }
  1186. privN->chan = i+1;
  1187. priv->devtbl[i] = devN;
  1188. }
  1189. return dev;
  1190. fail:
  1191. while (i >= 0) {
  1192. struct net_device *d = priv->devtbl[i--];
  1193. unregister_netdev(d);
  1194. free_netdev(d);
  1195. }
  1196. err2:
  1197. free_irq(dev->irq, dev);
  1198. err1:
  1199. free_netdev(dev);
  1200. err0:
  1201. return ERR_PTR(ret);
  1202. }
  1203. static void __devexit dgrs_remove(struct net_device *dev)
  1204. {
  1205. DGRS_PRIV *priv = dev->priv;
  1206. int i;
  1207. unregister_netdev(dev);
  1208. for (i = 1; i < priv->nports; ++i) {
  1209. struct net_device *d = priv->devtbl[i];
  1210. if (d) {
  1211. unregister_netdev(d);
  1212. free_netdev(d);
  1213. }
  1214. }
  1215. proc_reset(priv->devtbl[0], 1);
  1216. if (priv->vmem)
  1217. iounmap(priv->vmem);
  1218. if (priv->vplxdma)
  1219. iounmap((uchar *) priv->vplxdma);
  1220. if (dev->irq)
  1221. free_irq(dev->irq, dev);
  1222. for (i = 1; i < priv->nports; ++i) {
  1223. if (priv->devtbl[i])
  1224. unregister_netdev(priv->devtbl[i]);
  1225. }
  1226. }
  1227. #ifdef CONFIG_PCI
  1228. static int __init dgrs_pci_probe(struct pci_dev *pdev,
  1229. const struct pci_device_id *ent)
  1230. {
  1231. struct net_device *dev;
  1232. int err;
  1233. uint io;
  1234. uint mem;
  1235. uint irq;
  1236. uint plxreg;
  1237. uint plxdma;
  1238. /*
  1239. * Get and check the bus-master and latency values.
  1240. * Some PCI BIOSes fail to set the master-enable bit,
  1241. * and the latency timer must be set to the maximum
  1242. * value to avoid data corruption that occurs when the
  1243. * timer expires during a transfer. Yes, it's a bug.
  1244. */
  1245. err = pci_enable_device(pdev);
  1246. if (err)
  1247. return err;
  1248. err = pci_request_regions(pdev, "RightSwitch");
  1249. if (err)
  1250. return err;
  1251. pci_set_master(pdev);
  1252. plxreg = pci_resource_start (pdev, 0);
  1253. io = pci_resource_start (pdev, 1);
  1254. mem = pci_resource_start (pdev, 2);
  1255. pci_read_config_dword(pdev, 0x30, &plxdma);
  1256. irq = pdev->irq;
  1257. plxdma &= ~15;
  1258. /*
  1259. * On some BIOSES, the PLX "expansion rom" (used for DMA)
  1260. * address comes up as "0". This is probably because
  1261. * the BIOS doesn't see a valid 55 AA ROM signature at
  1262. * the "ROM" start and zeroes the address. To get
  1263. * around this problem the SE-6 is configured to ask
  1264. * for 4 MB of space for the dual port memory. We then
  1265. * must set its range back to 2 MB, and use the upper
  1266. * half for DMA register access
  1267. */
  1268. OUTL(io + PLX_SPACE0_RANGE, 0xFFE00000L);
  1269. if (plxdma == 0)
  1270. plxdma = mem + (2048L * 1024L);
  1271. pci_write_config_dword(pdev, 0x30, plxdma + 1);
  1272. pci_read_config_dword(pdev, 0x30, &plxdma);
  1273. plxdma &= ~15;
  1274. dev = dgrs_found_device(io, mem, irq, plxreg, plxdma, &pdev->dev);
  1275. if (IS_ERR(dev)) {
  1276. pci_release_regions(pdev);
  1277. return PTR_ERR(dev);
  1278. }
  1279. pci_set_drvdata(pdev, dev);
  1280. return 0;
  1281. }
  1282. static void __devexit dgrs_pci_remove(struct pci_dev *pdev)
  1283. {
  1284. struct net_device *dev = pci_get_drvdata(pdev);
  1285. dgrs_remove(dev);
  1286. pci_release_regions(pdev);
  1287. free_netdev(dev);
  1288. }
  1289. static struct pci_driver dgrs_pci_driver = {
  1290. .name = "dgrs",
  1291. .id_table = dgrs_pci_tbl,
  1292. .probe = dgrs_pci_probe,
  1293. .remove = __devexit_p(dgrs_pci_remove),
  1294. };
  1295. #else
  1296. static struct pci_driver dgrs_pci_driver = {};
  1297. #endif
  1298. #ifdef CONFIG_EISA
  1299. static int is2iv[8] __initdata = { 0, 3, 5, 7, 10, 11, 12, 15 };
  1300. static int __init dgrs_eisa_probe (struct device *gendev)
  1301. {
  1302. struct net_device *dev;
  1303. struct eisa_device *edev = to_eisa_device(gendev);
  1304. uint io = edev->base_addr;
  1305. uint mem;
  1306. uint irq;
  1307. int rc = -ENODEV; /* Not EISA configured */
  1308. if (!request_region(io, 256, "RightSwitch")) {
  1309. printk(KERN_ERR "dgrs: eisa io 0x%x, which is busy.\n", io);
  1310. return -EBUSY;
  1311. }
  1312. if ( ! (inb(io+ES4H_EC) & ES4H_EC_ENABLE) )
  1313. goto err_out;
  1314. mem = (inb(io+ES4H_AS_31_24) << 24)
  1315. + (inb(io+ES4H_AS_23_16) << 16);
  1316. irq = is2iv[ inb(io+ES4H_IS) & ES4H_IS_INTMASK ];
  1317. dev = dgrs_found_device(io, mem, irq, 0L, 0L, gendev);
  1318. if (IS_ERR(dev)) {
  1319. rc = PTR_ERR(dev);
  1320. goto err_out;
  1321. }
  1322. gendev->driver_data = dev;
  1323. return 0;
  1324. err_out:
  1325. release_region(io, 256);
  1326. return rc;
  1327. }
  1328. static int __devexit dgrs_eisa_remove(struct device *gendev)
  1329. {
  1330. struct net_device *dev = gendev->driver_data;
  1331. dgrs_remove(dev);
  1332. release_region(dev->base_addr, 256);
  1333. free_netdev(dev);
  1334. return 0;
  1335. }
  1336. static struct eisa_driver dgrs_eisa_driver = {
  1337. .id_table = dgrs_eisa_tbl,
  1338. .driver = {
  1339. .name = "dgrs",
  1340. .probe = dgrs_eisa_probe,
  1341. .remove = __devexit_p(dgrs_eisa_remove),
  1342. }
  1343. };
  1344. #endif
  1345. /*
  1346. * Variables that can be overriden from module command line
  1347. */
  1348. static int debug = -1;
  1349. static int dma = -1;
  1350. static int hashexpire = -1;
  1351. static int spantree = -1;
  1352. static int ipaddr[4] = { -1 };
  1353. static int iptrap[4] = { -1 };
  1354. static __u32 ipxnet = -1;
  1355. static int nicmode = -1;
  1356. module_param(debug, int, 0);
  1357. module_param(dma, int, 0);
  1358. module_param(hashexpire, int, 0);
  1359. module_param(spantree, int, 0);
  1360. module_param_array(ipaddr, int, NULL, 0);
  1361. module_param_array(iptrap, int, NULL, 0);
  1362. module_param(ipxnet, int, 0);
  1363. module_param(nicmode, int, 0);
  1364. MODULE_PARM_DESC(debug, "Digi RightSwitch enable debugging (0-1)");
  1365. MODULE_PARM_DESC(dma, "Digi RightSwitch enable BM DMA (0-1)");
  1366. MODULE_PARM_DESC(nicmode, "Digi RightSwitch operating mode (1: switch, 2: multi-NIC)");
  1367. static int __init dgrs_init_module (void)
  1368. {
  1369. int i;
  1370. int err;
  1371. /*
  1372. * Command line variable overrides
  1373. * debug=NNN
  1374. * dma=0/1
  1375. * spantree=0/1
  1376. * hashexpire=NNN
  1377. * ipaddr=A,B,C,D
  1378. * iptrap=A,B,C,D
  1379. * ipxnet=NNN
  1380. * nicmode=NNN
  1381. */
  1382. if (debug >= 0)
  1383. dgrs_debug = debug;
  1384. if (dma >= 0)
  1385. dgrs_dma = dma;
  1386. if (nicmode >= 0)
  1387. dgrs_nicmode = nicmode;
  1388. if (hashexpire >= 0)
  1389. dgrs_hashexpire = hashexpire;
  1390. if (spantree >= 0)
  1391. dgrs_spantree = spantree;
  1392. if (ipaddr[0] != -1)
  1393. for (i = 0; i < 4; ++i)
  1394. dgrs_ipaddr[i] = ipaddr[i];
  1395. if (iptrap[0] != -1)
  1396. for (i = 0; i < 4; ++i)
  1397. dgrs_iptrap[i] = iptrap[i];
  1398. if (ipxnet != -1)
  1399. dgrs_ipxnet = htonl( ipxnet );
  1400. if (dgrs_debug)
  1401. {
  1402. printk(KERN_INFO "dgrs: SW=%s FW=Build %d %s\nFW Version=%s\n",
  1403. version, dgrs_firmnum, dgrs_firmdate, dgrs_firmver);
  1404. }
  1405. /*
  1406. * Find and configure all the cards
  1407. */
  1408. #ifdef CONFIG_EISA
  1409. err = eisa_driver_register(&dgrs_eisa_driver);
  1410. if (err)
  1411. return err;
  1412. #endif
  1413. err = pci_register_driver(&dgrs_pci_driver);
  1414. if (err)
  1415. return err;
  1416. return 0;
  1417. }
  1418. static void __exit dgrs_cleanup_module (void)
  1419. {
  1420. #ifdef CONFIG_EISA
  1421. eisa_driver_unregister (&dgrs_eisa_driver);
  1422. #endif
  1423. #ifdef CONFIG_PCI
  1424. pci_unregister_driver (&dgrs_pci_driver);
  1425. #endif
  1426. }
  1427. module_init(dgrs_init_module);
  1428. module_exit(dgrs_cleanup_module);