defxx.c 114 KB

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  1. /*
  2. * File Name:
  3. * defxx.c
  4. *
  5. * Copyright Information:
  6. * Copyright Digital Equipment Corporation 1996.
  7. *
  8. * This software may be used and distributed according to the terms of
  9. * the GNU General Public License, incorporated herein by reference.
  10. *
  11. * Abstract:
  12. * A Linux device driver supporting the Digital Equipment Corporation
  13. * FDDI TURBOchannel, EISA and PCI controller families. Supported
  14. * adapters include:
  15. *
  16. * DEC FDDIcontroller/TURBOchannel (DEFTA)
  17. * DEC FDDIcontroller/EISA (DEFEA)
  18. * DEC FDDIcontroller/PCI (DEFPA)
  19. *
  20. * The original author:
  21. * LVS Lawrence V. Stefani <lstefani@yahoo.com>
  22. *
  23. * Maintainers:
  24. * macro Maciej W. Rozycki <macro@linux-mips.org>
  25. *
  26. * Credits:
  27. * I'd like to thank Patricia Cross for helping me get started with
  28. * Linux, David Davies for a lot of help upgrading and configuring
  29. * my development system and for answering many OS and driver
  30. * development questions, and Alan Cox for recommendations and
  31. * integration help on getting FDDI support into Linux. LVS
  32. *
  33. * Driver Architecture:
  34. * The driver architecture is largely based on previous driver work
  35. * for other operating systems. The upper edge interface and
  36. * functions were largely taken from existing Linux device drivers
  37. * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
  38. * driver.
  39. *
  40. * Adapter Probe -
  41. * The driver scans for supported EISA adapters by reading the
  42. * SLOT ID register for each EISA slot and making a match
  43. * against the expected value.
  44. *
  45. * Bus-Specific Initialization -
  46. * This driver currently supports both EISA and PCI controller
  47. * families. While the custom DMA chip and FDDI logic is similar
  48. * or identical, the bus logic is very different. After
  49. * initialization, the only bus-specific differences is in how the
  50. * driver enables and disables interrupts. Other than that, the
  51. * run-time critical code behaves the same on both families.
  52. * It's important to note that both adapter families are configured
  53. * to I/O map, rather than memory map, the adapter registers.
  54. *
  55. * Driver Open/Close -
  56. * In the driver open routine, the driver ISR (interrupt service
  57. * routine) is registered and the adapter is brought to an
  58. * operational state. In the driver close routine, the opposite
  59. * occurs; the driver ISR is deregistered and the adapter is
  60. * brought to a safe, but closed state. Users may use consecutive
  61. * commands to bring the adapter up and down as in the following
  62. * example:
  63. * ifconfig fddi0 up
  64. * ifconfig fddi0 down
  65. * ifconfig fddi0 up
  66. *
  67. * Driver Shutdown -
  68. * Apparently, there is no shutdown or halt routine support under
  69. * Linux. This routine would be called during "reboot" or
  70. * "shutdown" to allow the driver to place the adapter in a safe
  71. * state before a warm reboot occurs. To be really safe, the user
  72. * should close the adapter before shutdown (eg. ifconfig fddi0 down)
  73. * to ensure that the adapter DMA engine is taken off-line. However,
  74. * the current driver code anticipates this problem and always issues
  75. * a soft reset of the adapter at the beginning of driver initialization.
  76. * A future driver enhancement in this area may occur in 2.1.X where
  77. * Alan indicated that a shutdown handler may be implemented.
  78. *
  79. * Interrupt Service Routine -
  80. * The driver supports shared interrupts, so the ISR is registered for
  81. * each board with the appropriate flag and the pointer to that board's
  82. * device structure. This provides the context during interrupt
  83. * processing to support shared interrupts and multiple boards.
  84. *
  85. * Interrupt enabling/disabling can occur at many levels. At the host
  86. * end, you can disable system interrupts, or disable interrupts at the
  87. * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
  88. * have a bus-logic chip interrupt enable/disable as well as a DMA
  89. * controller interrupt enable/disable.
  90. *
  91. * The driver currently enables and disables adapter interrupts at the
  92. * bus-logic chip and assumes that Linux will take care of clearing or
  93. * acknowledging any host-based interrupt chips.
  94. *
  95. * Control Functions -
  96. * Control functions are those used to support functions such as adding
  97. * or deleting multicast addresses, enabling or disabling packet
  98. * reception filters, or other custom/proprietary commands. Presently,
  99. * the driver supports the "get statistics", "set multicast list", and
  100. * "set mac address" functions defined by Linux. A list of possible
  101. * enhancements include:
  102. *
  103. * - Custom ioctl interface for executing port interface commands
  104. * - Custom ioctl interface for adding unicast addresses to
  105. * adapter CAM (to support bridge functions).
  106. * - Custom ioctl interface for supporting firmware upgrades.
  107. *
  108. * Hardware (port interface) Support Routines -
  109. * The driver function names that start with "dfx_hw_" represent
  110. * low-level port interface routines that are called frequently. They
  111. * include issuing a DMA or port control command to the adapter,
  112. * resetting the adapter, or reading the adapter state. Since the
  113. * driver initialization and run-time code must make calls into the
  114. * port interface, these routines were written to be as generic and
  115. * usable as possible.
  116. *
  117. * Receive Path -
  118. * The adapter DMA engine supports a 256 entry receive descriptor block
  119. * of which up to 255 entries can be used at any given time. The
  120. * architecture is a standard producer, consumer, completion model in
  121. * which the driver "produces" receive buffers to the adapter, the
  122. * adapter "consumes" the receive buffers by DMAing incoming packet data,
  123. * and the driver "completes" the receive buffers by servicing the
  124. * incoming packet, then "produces" a new buffer and starts the cycle
  125. * again. Receive buffers can be fragmented in up to 16 fragments
  126. * (descriptor entries). For simplicity, this driver posts
  127. * single-fragment receive buffers of 4608 bytes, then allocates a
  128. * sk_buff, copies the data, then reposts the buffer. To reduce CPU
  129. * utilization, a better approach would be to pass up the receive
  130. * buffer (no extra copy) then allocate and post a replacement buffer.
  131. * This is a performance enhancement that should be looked into at
  132. * some point.
  133. *
  134. * Transmit Path -
  135. * Like the receive path, the adapter DMA engine supports a 256 entry
  136. * transmit descriptor block of which up to 255 entries can be used at
  137. * any given time. Transmit buffers can be fragmented in up to 255
  138. * fragments (descriptor entries). This driver always posts one
  139. * fragment per transmit packet request.
  140. *
  141. * The fragment contains the entire packet from FC to end of data.
  142. * Before posting the buffer to the adapter, the driver sets a three-byte
  143. * packet request header (PRH) which is required by the Motorola MAC chip
  144. * used on the adapters. The PRH tells the MAC the type of token to
  145. * receive/send, whether or not to generate and append the CRC, whether
  146. * synchronous or asynchronous framing is used, etc. Since the PRH
  147. * definition is not necessarily consistent across all FDDI chipsets,
  148. * the driver, rather than the common FDDI packet handler routines,
  149. * sets these bytes.
  150. *
  151. * To reduce the amount of descriptor fetches needed per transmit request,
  152. * the driver takes advantage of the fact that there are at least three
  153. * bytes available before the skb->data field on the outgoing transmit
  154. * request. This is guaranteed by having fddi_setup() in net_init.c set
  155. * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
  156. * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
  157. * bytes which we'll use to store the PRH.
  158. *
  159. * There's a subtle advantage to adding these pad bytes to the
  160. * hard_header_len, it ensures that the data portion of the packet for
  161. * an 802.2 SNAP frame is longword aligned. Other FDDI driver
  162. * implementations may not need the extra padding and can start copying
  163. * or DMAing directly from the FC byte which starts at skb->data. Should
  164. * another driver implementation need ADDITIONAL padding, the net_init.c
  165. * module should be updated and dev->hard_header_len should be increased.
  166. * NOTE: To maintain the alignment on the data portion of the packet,
  167. * dev->hard_header_len should always be evenly divisible by 4 and at
  168. * least 24 bytes in size.
  169. *
  170. * Modification History:
  171. * Date Name Description
  172. * 16-Aug-96 LVS Created.
  173. * 20-Aug-96 LVS Updated dfx_probe so that version information
  174. * string is only displayed if 1 or more cards are
  175. * found. Changed dfx_rcv_queue_process to copy
  176. * 3 NULL bytes before FC to ensure that data is
  177. * longword aligned in receive buffer.
  178. * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
  179. * LLC group promiscuous mode if multicast list
  180. * is too large. LLC individual/group promiscuous
  181. * mode is now disabled if IFF_PROMISC flag not set.
  182. * dfx_xmt_queue_pkt no longer checks for NULL skb
  183. * on Alan Cox recommendation. Added node address
  184. * override support.
  185. * 12-Sep-96 LVS Reset current address to factory address during
  186. * device open. Updated transmit path to post a
  187. * single fragment which includes PRH->end of data.
  188. * Mar 2000 AC Did various cleanups for 2.3.x
  189. * Jun 2000 jgarzik PCI and resource alloc cleanups
  190. * Jul 2000 tjeerd Much cleanup and some bug fixes
  191. * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
  192. * Feb 2001 Skb allocation fixes
  193. * Feb 2001 davej PCI enable cleanups.
  194. * 04 Aug 2003 macro Converted to the DMA API.
  195. * 14 Aug 2004 macro Fix device names reported.
  196. * 14 Jun 2005 macro Use irqreturn_t.
  197. * 23 Oct 2006 macro Big-endian host support.
  198. * 14 Dec 2006 macro TURBOchannel support.
  199. */
  200. /* Include files */
  201. #include <linux/bitops.h>
  202. #include <linux/delay.h>
  203. #include <linux/dma-mapping.h>
  204. #include <linux/eisa.h>
  205. #include <linux/errno.h>
  206. #include <linux/fddidevice.h>
  207. #include <linux/init.h>
  208. #include <linux/interrupt.h>
  209. #include <linux/ioport.h>
  210. #include <linux/kernel.h>
  211. #include <linux/module.h>
  212. #include <linux/netdevice.h>
  213. #include <linux/pci.h>
  214. #include <linux/skbuff.h>
  215. #include <linux/slab.h>
  216. #include <linux/string.h>
  217. #include <linux/tc.h>
  218. #include <asm/byteorder.h>
  219. #include <asm/io.h>
  220. #include "defxx.h"
  221. /* Version information string should be updated prior to each new release! */
  222. #define DRV_NAME "defxx"
  223. #define DRV_VERSION "v1.10"
  224. #define DRV_RELDATE "2006/12/14"
  225. static char version[] __devinitdata =
  226. DRV_NAME ": " DRV_VERSION " " DRV_RELDATE
  227. " Lawrence V. Stefani and others\n";
  228. #define DYNAMIC_BUFFERS 1
  229. #define SKBUFF_RX_COPYBREAK 200
  230. /*
  231. * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
  232. * alignment for compatibility with old EISA boards.
  233. */
  234. #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
  235. #define __unused __attribute__ ((unused))
  236. #ifdef CONFIG_PCI
  237. #define DFX_BUS_PCI(dev) (dev->bus == &pci_bus_type)
  238. #else
  239. #define DFX_BUS_PCI(dev) 0
  240. #endif
  241. #ifdef CONFIG_EISA
  242. #define DFX_BUS_EISA(dev) (dev->bus == &eisa_bus_type)
  243. #else
  244. #define DFX_BUS_EISA(dev) 0
  245. #endif
  246. #ifdef CONFIG_TC
  247. #define DFX_BUS_TC(dev) (dev->bus == &tc_bus_type)
  248. #else
  249. #define DFX_BUS_TC(dev) 0
  250. #endif
  251. #ifdef CONFIG_DEFXX_MMIO
  252. #define DFX_MMIO 1
  253. #else
  254. #define DFX_MMIO 0
  255. #endif
  256. /* Define module-wide (static) routines */
  257. static void dfx_bus_init(struct net_device *dev);
  258. static void dfx_bus_uninit(struct net_device *dev);
  259. static void dfx_bus_config_check(DFX_board_t *bp);
  260. static int dfx_driver_init(struct net_device *dev,
  261. const char *print_name,
  262. resource_size_t bar_start);
  263. static int dfx_adap_init(DFX_board_t *bp, int get_buffers);
  264. static int dfx_open(struct net_device *dev);
  265. static int dfx_close(struct net_device *dev);
  266. static void dfx_int_pr_halt_id(DFX_board_t *bp);
  267. static void dfx_int_type_0_process(DFX_board_t *bp);
  268. static void dfx_int_common(struct net_device *dev);
  269. static irqreturn_t dfx_interrupt(int irq, void *dev_id);
  270. static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev);
  271. static void dfx_ctl_set_multicast_list(struct net_device *dev);
  272. static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr);
  273. static int dfx_ctl_update_cam(DFX_board_t *bp);
  274. static int dfx_ctl_update_filters(DFX_board_t *bp);
  275. static int dfx_hw_dma_cmd_req(DFX_board_t *bp);
  276. static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
  277. static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type);
  278. static int dfx_hw_adap_state_rd(DFX_board_t *bp);
  279. static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type);
  280. static int dfx_rcv_init(DFX_board_t *bp, int get_buffers);
  281. static void dfx_rcv_queue_process(DFX_board_t *bp);
  282. static void dfx_rcv_flush(DFX_board_t *bp);
  283. static int dfx_xmt_queue_pkt(struct sk_buff *skb, struct net_device *dev);
  284. static int dfx_xmt_done(DFX_board_t *bp);
  285. static void dfx_xmt_flush(DFX_board_t *bp);
  286. /* Define module-wide (static) variables */
  287. static struct pci_driver dfx_pci_driver;
  288. static struct eisa_driver dfx_eisa_driver;
  289. static struct tc_driver dfx_tc_driver;
  290. /*
  291. * =======================
  292. * = dfx_port_write_long =
  293. * = dfx_port_read_long =
  294. * =======================
  295. *
  296. * Overview:
  297. * Routines for reading and writing values from/to adapter
  298. *
  299. * Returns:
  300. * None
  301. *
  302. * Arguments:
  303. * bp - pointer to board information
  304. * offset - register offset from base I/O address
  305. * data - for dfx_port_write_long, this is a value to write;
  306. * for dfx_port_read_long, this is a pointer to store
  307. * the read value
  308. *
  309. * Functional Description:
  310. * These routines perform the correct operation to read or write
  311. * the adapter register.
  312. *
  313. * EISA port block base addresses are based on the slot number in which the
  314. * controller is installed. For example, if the EISA controller is installed
  315. * in slot 4, the port block base address is 0x4000. If the controller is
  316. * installed in slot 2, the port block base address is 0x2000, and so on.
  317. * This port block can be used to access PDQ, ESIC, and DEFEA on-board
  318. * registers using the register offsets defined in DEFXX.H.
  319. *
  320. * PCI port block base addresses are assigned by the PCI BIOS or system
  321. * firmware. There is one 128 byte port block which can be accessed. It
  322. * allows for I/O mapping of both PDQ and PFI registers using the register
  323. * offsets defined in DEFXX.H.
  324. *
  325. * Return Codes:
  326. * None
  327. *
  328. * Assumptions:
  329. * bp->base is a valid base I/O address for this adapter.
  330. * offset is a valid register offset for this adapter.
  331. *
  332. * Side Effects:
  333. * Rather than produce macros for these functions, these routines
  334. * are defined using "inline" to ensure that the compiler will
  335. * generate inline code and not waste a procedure call and return.
  336. * This provides all the benefits of macros, but with the
  337. * advantage of strict data type checking.
  338. */
  339. static inline void dfx_writel(DFX_board_t *bp, int offset, u32 data)
  340. {
  341. writel(data, bp->base.mem + offset);
  342. mb();
  343. }
  344. static inline void dfx_outl(DFX_board_t *bp, int offset, u32 data)
  345. {
  346. outl(data, bp->base.port + offset);
  347. }
  348. static void dfx_port_write_long(DFX_board_t *bp, int offset, u32 data)
  349. {
  350. struct device __unused *bdev = bp->bus_dev;
  351. int dfx_bus_tc = DFX_BUS_TC(bdev);
  352. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  353. if (dfx_use_mmio)
  354. dfx_writel(bp, offset, data);
  355. else
  356. dfx_outl(bp, offset, data);
  357. }
  358. static inline void dfx_readl(DFX_board_t *bp, int offset, u32 *data)
  359. {
  360. mb();
  361. *data = readl(bp->base.mem + offset);
  362. }
  363. static inline void dfx_inl(DFX_board_t *bp, int offset, u32 *data)
  364. {
  365. *data = inl(bp->base.port + offset);
  366. }
  367. static void dfx_port_read_long(DFX_board_t *bp, int offset, u32 *data)
  368. {
  369. struct device __unused *bdev = bp->bus_dev;
  370. int dfx_bus_tc = DFX_BUS_TC(bdev);
  371. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  372. if (dfx_use_mmio)
  373. dfx_readl(bp, offset, data);
  374. else
  375. dfx_inl(bp, offset, data);
  376. }
  377. /*
  378. * ================
  379. * = dfx_get_bars =
  380. * ================
  381. *
  382. * Overview:
  383. * Retrieves the address range used to access control and status
  384. * registers.
  385. *
  386. * Returns:
  387. * None
  388. *
  389. * Arguments:
  390. * bdev - pointer to device information
  391. * bar_start - pointer to store the start address
  392. * bar_len - pointer to store the length of the area
  393. *
  394. * Assumptions:
  395. * I am sure there are some.
  396. *
  397. * Side Effects:
  398. * None
  399. */
  400. static void dfx_get_bars(struct device *bdev,
  401. resource_size_t *bar_start, resource_size_t *bar_len)
  402. {
  403. int dfx_bus_pci = DFX_BUS_PCI(bdev);
  404. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  405. int dfx_bus_tc = DFX_BUS_TC(bdev);
  406. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  407. if (dfx_bus_pci) {
  408. int num = dfx_use_mmio ? 0 : 1;
  409. *bar_start = pci_resource_start(to_pci_dev(bdev), num);
  410. *bar_len = pci_resource_len(to_pci_dev(bdev), num);
  411. }
  412. if (dfx_bus_eisa) {
  413. unsigned long base_addr = to_eisa_device(bdev)->base_addr;
  414. resource_size_t bar;
  415. if (dfx_use_mmio) {
  416. bar = inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_2);
  417. bar <<= 8;
  418. bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_1);
  419. bar <<= 8;
  420. bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_0);
  421. bar <<= 16;
  422. *bar_start = bar;
  423. bar = inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_2);
  424. bar <<= 8;
  425. bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_1);
  426. bar <<= 8;
  427. bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_0);
  428. bar <<= 16;
  429. *bar_len = (bar | PI_MEM_ADD_MASK_M) + 1;
  430. } else {
  431. *bar_start = base_addr;
  432. *bar_len = PI_ESIC_K_CSR_IO_LEN;
  433. }
  434. }
  435. if (dfx_bus_tc) {
  436. *bar_start = to_tc_dev(bdev)->resource.start +
  437. PI_TC_K_CSR_OFFSET;
  438. *bar_len = PI_TC_K_CSR_LEN;
  439. }
  440. }
  441. /*
  442. * ================
  443. * = dfx_register =
  444. * ================
  445. *
  446. * Overview:
  447. * Initializes a supported FDDI controller
  448. *
  449. * Returns:
  450. * Condition code
  451. *
  452. * Arguments:
  453. * bdev - pointer to device information
  454. *
  455. * Functional Description:
  456. *
  457. * Return Codes:
  458. * 0 - This device (fddi0, fddi1, etc) configured successfully
  459. * -EBUSY - Failed to get resources, or dfx_driver_init failed.
  460. *
  461. * Assumptions:
  462. * It compiles so it should work :-( (PCI cards do :-)
  463. *
  464. * Side Effects:
  465. * Device structures for FDDI adapters (fddi0, fddi1, etc) are
  466. * initialized and the board resources are read and stored in
  467. * the device structure.
  468. */
  469. static int __devinit dfx_register(struct device *bdev)
  470. {
  471. static int version_disp;
  472. int dfx_bus_pci = DFX_BUS_PCI(bdev);
  473. int dfx_bus_tc = DFX_BUS_TC(bdev);
  474. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  475. char *print_name = bdev->bus_id;
  476. struct net_device *dev;
  477. DFX_board_t *bp; /* board pointer */
  478. resource_size_t bar_start = 0; /* pointer to port */
  479. resource_size_t bar_len = 0; /* resource length */
  480. int alloc_size; /* total buffer size used */
  481. struct resource *region;
  482. int err = 0;
  483. if (!version_disp) { /* display version info if adapter is found */
  484. version_disp = 1; /* set display flag to TRUE so that */
  485. printk(version); /* we only display this string ONCE */
  486. }
  487. dev = alloc_fddidev(sizeof(*bp));
  488. if (!dev) {
  489. printk(KERN_ERR "%s: Unable to allocate fddidev, aborting\n",
  490. print_name);
  491. return -ENOMEM;
  492. }
  493. /* Enable PCI device. */
  494. if (dfx_bus_pci && pci_enable_device(to_pci_dev(bdev))) {
  495. printk(KERN_ERR "%s: Cannot enable PCI device, aborting\n",
  496. print_name);
  497. goto err_out;
  498. }
  499. SET_MODULE_OWNER(dev);
  500. SET_NETDEV_DEV(dev, bdev);
  501. bp = netdev_priv(dev);
  502. bp->bus_dev = bdev;
  503. dev_set_drvdata(bdev, dev);
  504. dfx_get_bars(bdev, &bar_start, &bar_len);
  505. if (dfx_use_mmio)
  506. region = request_mem_region(bar_start, bar_len, print_name);
  507. else
  508. region = request_region(bar_start, bar_len, print_name);
  509. if (!region) {
  510. printk(KERN_ERR "%s: Cannot reserve I/O resource "
  511. "0x%lx @ 0x%lx, aborting\n",
  512. print_name, (long)bar_len, (long)bar_start);
  513. err = -EBUSY;
  514. goto err_out_disable;
  515. }
  516. /* Set up I/O base address. */
  517. if (dfx_use_mmio) {
  518. bp->base.mem = ioremap_nocache(bar_start, bar_len);
  519. if (!bp->base.mem) {
  520. printk(KERN_ERR "%s: Cannot map MMIO\n", print_name);
  521. goto err_out_region;
  522. }
  523. } else {
  524. bp->base.port = bar_start;
  525. dev->base_addr = bar_start;
  526. }
  527. /* Initialize new device structure */
  528. dev->get_stats = dfx_ctl_get_stats;
  529. dev->open = dfx_open;
  530. dev->stop = dfx_close;
  531. dev->hard_start_xmit = dfx_xmt_queue_pkt;
  532. dev->set_multicast_list = dfx_ctl_set_multicast_list;
  533. dev->set_mac_address = dfx_ctl_set_mac_address;
  534. if (dfx_bus_pci)
  535. pci_set_master(to_pci_dev(bdev));
  536. if (dfx_driver_init(dev, print_name, bar_start) != DFX_K_SUCCESS) {
  537. err = -ENODEV;
  538. goto err_out_unmap;
  539. }
  540. err = register_netdev(dev);
  541. if (err)
  542. goto err_out_kfree;
  543. printk("%s: registered as %s\n", print_name, dev->name);
  544. return 0;
  545. err_out_kfree:
  546. alloc_size = sizeof(PI_DESCR_BLOCK) +
  547. PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
  548. #ifndef DYNAMIC_BUFFERS
  549. (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
  550. #endif
  551. sizeof(PI_CONSUMER_BLOCK) +
  552. (PI_ALIGN_K_DESC_BLK - 1);
  553. if (bp->kmalloced)
  554. dma_free_coherent(bdev, alloc_size,
  555. bp->kmalloced, bp->kmalloced_dma);
  556. err_out_unmap:
  557. if (dfx_use_mmio)
  558. iounmap(bp->base.mem);
  559. err_out_region:
  560. if (dfx_use_mmio)
  561. release_mem_region(bar_start, bar_len);
  562. else
  563. release_region(bar_start, bar_len);
  564. err_out_disable:
  565. if (dfx_bus_pci)
  566. pci_disable_device(to_pci_dev(bdev));
  567. err_out:
  568. free_netdev(dev);
  569. return err;
  570. }
  571. /*
  572. * ================
  573. * = dfx_bus_init =
  574. * ================
  575. *
  576. * Overview:
  577. * Initializes the bus-specific controller logic.
  578. *
  579. * Returns:
  580. * None
  581. *
  582. * Arguments:
  583. * dev - pointer to device information
  584. *
  585. * Functional Description:
  586. * Determine and save adapter IRQ in device table,
  587. * then perform bus-specific logic initialization.
  588. *
  589. * Return Codes:
  590. * None
  591. *
  592. * Assumptions:
  593. * bp->base has already been set with the proper
  594. * base I/O address for this device.
  595. *
  596. * Side Effects:
  597. * Interrupts are enabled at the adapter bus-specific logic.
  598. * Note: Interrupts at the DMA engine (PDQ chip) are not
  599. * enabled yet.
  600. */
  601. static void __devinit dfx_bus_init(struct net_device *dev)
  602. {
  603. DFX_board_t *bp = netdev_priv(dev);
  604. struct device *bdev = bp->bus_dev;
  605. int dfx_bus_pci = DFX_BUS_PCI(bdev);
  606. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  607. int dfx_bus_tc = DFX_BUS_TC(bdev);
  608. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  609. u8 val;
  610. DBG_printk("In dfx_bus_init...\n");
  611. /* Initialize a pointer back to the net_device struct */
  612. bp->dev = dev;
  613. /* Initialize adapter based on bus type */
  614. if (dfx_bus_tc)
  615. dev->irq = to_tc_dev(bdev)->interrupt;
  616. if (dfx_bus_eisa) {
  617. unsigned long base_addr = to_eisa_device(bdev)->base_addr;
  618. /* Get the interrupt level from the ESIC chip. */
  619. val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  620. val &= PI_CONFIG_STAT_0_M_IRQ;
  621. val >>= PI_CONFIG_STAT_0_V_IRQ;
  622. switch (val) {
  623. case PI_CONFIG_STAT_0_IRQ_K_9:
  624. dev->irq = 9;
  625. break;
  626. case PI_CONFIG_STAT_0_IRQ_K_10:
  627. dev->irq = 10;
  628. break;
  629. case PI_CONFIG_STAT_0_IRQ_K_11:
  630. dev->irq = 11;
  631. break;
  632. case PI_CONFIG_STAT_0_IRQ_K_15:
  633. dev->irq = 15;
  634. break;
  635. }
  636. /*
  637. * Enable memory decoding (MEMCS0) and/or port decoding
  638. * (IOCS1/IOCS0) as appropriate in Function Control
  639. * Register. One of the port chip selects seems to be
  640. * used for the Burst Holdoff register, but this bit of
  641. * documentation is missing and as yet it has not been
  642. * determined which of the two. This is also the reason
  643. * the size of the decoded port range is twice as large
  644. * as one required by the PDQ.
  645. */
  646. /* Set the decode range of the board. */
  647. val = ((bp->base.port >> 12) << PI_IO_CMP_V_SLOT);
  648. outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_1, val);
  649. outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_0, 0);
  650. outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_1, val);
  651. outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_0, 0);
  652. val = PI_ESIC_K_CSR_IO_LEN - 1;
  653. outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_1, (val >> 8) & 0xff);
  654. outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_0, val & 0xff);
  655. outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_1, (val >> 8) & 0xff);
  656. outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_0, val & 0xff);
  657. /* Enable the decoders. */
  658. val = PI_FUNCTION_CNTRL_M_IOCS1 | PI_FUNCTION_CNTRL_M_IOCS0;
  659. if (dfx_use_mmio)
  660. val |= PI_FUNCTION_CNTRL_M_MEMCS0;
  661. outb(base_addr + PI_ESIC_K_FUNCTION_CNTRL, val);
  662. /*
  663. * Enable access to the rest of the module
  664. * (including PDQ and packet memory).
  665. */
  666. val = PI_SLOT_CNTRL_M_ENB;
  667. outb(base_addr + PI_ESIC_K_SLOT_CNTRL, val);
  668. /*
  669. * Map PDQ registers into memory or port space. This is
  670. * done with a bit in the Burst Holdoff register.
  671. */
  672. val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF);
  673. if (dfx_use_mmio)
  674. val |= PI_BURST_HOLDOFF_V_MEM_MAP;
  675. else
  676. val &= ~PI_BURST_HOLDOFF_V_MEM_MAP;
  677. outb(base_addr + PI_DEFEA_K_BURST_HOLDOFF, val);
  678. /* Enable interrupts at EISA bus interface chip (ESIC) */
  679. val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  680. val |= PI_CONFIG_STAT_0_M_INT_ENB;
  681. outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val);
  682. }
  683. if (dfx_bus_pci) {
  684. struct pci_dev *pdev = to_pci_dev(bdev);
  685. /* Get the interrupt level from the PCI Configuration Table */
  686. dev->irq = pdev->irq;
  687. /* Check Latency Timer and set if less than minimal */
  688. pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
  689. if (val < PFI_K_LAT_TIMER_MIN) {
  690. val = PFI_K_LAT_TIMER_DEF;
  691. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val);
  692. }
  693. /* Enable interrupts at PCI bus interface chip (PFI) */
  694. val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB;
  695. dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val);
  696. }
  697. }
  698. /*
  699. * ==================
  700. * = dfx_bus_uninit =
  701. * ==================
  702. *
  703. * Overview:
  704. * Uninitializes the bus-specific controller logic.
  705. *
  706. * Returns:
  707. * None
  708. *
  709. * Arguments:
  710. * dev - pointer to device information
  711. *
  712. * Functional Description:
  713. * Perform bus-specific logic uninitialization.
  714. *
  715. * Return Codes:
  716. * None
  717. *
  718. * Assumptions:
  719. * bp->base has already been set with the proper
  720. * base I/O address for this device.
  721. *
  722. * Side Effects:
  723. * Interrupts are disabled at the adapter bus-specific logic.
  724. */
  725. static void __devinit dfx_bus_uninit(struct net_device *dev)
  726. {
  727. DFX_board_t *bp = netdev_priv(dev);
  728. struct device *bdev = bp->bus_dev;
  729. int dfx_bus_pci = DFX_BUS_PCI(bdev);
  730. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  731. u8 val;
  732. DBG_printk("In dfx_bus_uninit...\n");
  733. /* Uninitialize adapter based on bus type */
  734. if (dfx_bus_eisa) {
  735. unsigned long base_addr = to_eisa_device(bdev)->base_addr;
  736. /* Disable interrupts at EISA bus interface chip (ESIC) */
  737. val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  738. val &= ~PI_CONFIG_STAT_0_M_INT_ENB;
  739. outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val);
  740. }
  741. if (dfx_bus_pci) {
  742. /* Disable interrupts at PCI bus interface chip (PFI) */
  743. dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 0);
  744. }
  745. }
  746. /*
  747. * ========================
  748. * = dfx_bus_config_check =
  749. * ========================
  750. *
  751. * Overview:
  752. * Checks the configuration (burst size, full-duplex, etc.) If any parameters
  753. * are illegal, then this routine will set new defaults.
  754. *
  755. * Returns:
  756. * None
  757. *
  758. * Arguments:
  759. * bp - pointer to board information
  760. *
  761. * Functional Description:
  762. * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
  763. * PDQ, and all FDDI PCI controllers, all values are legal.
  764. *
  765. * Return Codes:
  766. * None
  767. *
  768. * Assumptions:
  769. * dfx_adap_init has NOT been called yet so burst size and other items have
  770. * not been set.
  771. *
  772. * Side Effects:
  773. * None
  774. */
  775. static void __devinit dfx_bus_config_check(DFX_board_t *bp)
  776. {
  777. struct device __unused *bdev = bp->bus_dev;
  778. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  779. int status; /* return code from adapter port control call */
  780. u32 host_data; /* LW data returned from port control call */
  781. DBG_printk("In dfx_bus_config_check...\n");
  782. /* Configuration check only valid for EISA adapter */
  783. if (dfx_bus_eisa) {
  784. /*
  785. * First check if revision 2 EISA controller. Rev. 1 cards used
  786. * PDQ revision B, so no workaround needed in this case. Rev. 3
  787. * cards used PDQ revision E, so no workaround needed in this
  788. * case, either. Only Rev. 2 cards used either Rev. D or E
  789. * chips, so we must verify the chip revision on Rev. 2 cards.
  790. */
  791. if (to_eisa_device(bdev)->id.driver_data == DEFEA_PROD_ID_2) {
  792. /*
  793. * Revision 2 FDDI EISA controller found,
  794. * so let's check PDQ revision of adapter.
  795. */
  796. status = dfx_hw_port_ctrl_req(bp,
  797. PI_PCTRL_M_SUB_CMD,
  798. PI_SUB_CMD_K_PDQ_REV_GET,
  799. 0,
  800. &host_data);
  801. if ((status != DFX_K_SUCCESS) || (host_data == 2))
  802. {
  803. /*
  804. * Either we couldn't determine the PDQ revision, or
  805. * we determined that it is at revision D. In either case,
  806. * we need to implement the workaround.
  807. */
  808. /* Ensure that the burst size is set to 8 longwords or less */
  809. switch (bp->burst_size)
  810. {
  811. case PI_PDATA_B_DMA_BURST_SIZE_32:
  812. case PI_PDATA_B_DMA_BURST_SIZE_16:
  813. bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8;
  814. break;
  815. default:
  816. break;
  817. }
  818. /* Ensure that full-duplex mode is not enabled */
  819. bp->full_duplex_enb = PI_SNMP_K_FALSE;
  820. }
  821. }
  822. }
  823. }
  824. /*
  825. * ===================
  826. * = dfx_driver_init =
  827. * ===================
  828. *
  829. * Overview:
  830. * Initializes remaining adapter board structure information
  831. * and makes sure adapter is in a safe state prior to dfx_open().
  832. *
  833. * Returns:
  834. * Condition code
  835. *
  836. * Arguments:
  837. * dev - pointer to device information
  838. * print_name - printable device name
  839. *
  840. * Functional Description:
  841. * This function allocates additional resources such as the host memory
  842. * blocks needed by the adapter (eg. descriptor and consumer blocks).
  843. * Remaining bus initialization steps are also completed. The adapter
  844. * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
  845. * must call dfx_open() to open the adapter and bring it on-line.
  846. *
  847. * Return Codes:
  848. * DFX_K_SUCCESS - initialization succeeded
  849. * DFX_K_FAILURE - initialization failed - could not allocate memory
  850. * or read adapter MAC address
  851. *
  852. * Assumptions:
  853. * Memory allocated from pci_alloc_consistent() call is physically
  854. * contiguous, locked memory.
  855. *
  856. * Side Effects:
  857. * Adapter is reset and should be in DMA_UNAVAILABLE state before
  858. * returning from this routine.
  859. */
  860. static int __devinit dfx_driver_init(struct net_device *dev,
  861. const char *print_name,
  862. resource_size_t bar_start)
  863. {
  864. DFX_board_t *bp = netdev_priv(dev);
  865. struct device *bdev = bp->bus_dev;
  866. int dfx_bus_pci = DFX_BUS_PCI(bdev);
  867. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  868. int dfx_bus_tc = DFX_BUS_TC(bdev);
  869. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  870. int alloc_size; /* total buffer size needed */
  871. char *top_v, *curr_v; /* virtual addrs into memory block */
  872. dma_addr_t top_p, curr_p; /* physical addrs into memory block */
  873. u32 data, le32; /* host data register value */
  874. char *board_name = NULL;
  875. DBG_printk("In dfx_driver_init...\n");
  876. /* Initialize bus-specific hardware registers */
  877. dfx_bus_init(dev);
  878. /*
  879. * Initialize default values for configurable parameters
  880. *
  881. * Note: All of these parameters are ones that a user may
  882. * want to customize. It'd be nice to break these
  883. * out into Space.c or someplace else that's more
  884. * accessible/understandable than this file.
  885. */
  886. bp->full_duplex_enb = PI_SNMP_K_FALSE;
  887. bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */
  888. bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF;
  889. bp->rcv_bufs_to_post = RCV_BUFS_DEF;
  890. /*
  891. * Ensure that HW configuration is OK
  892. *
  893. * Note: Depending on the hardware revision, we may need to modify
  894. * some of the configurable parameters to workaround hardware
  895. * limitations. We'll perform this configuration check AFTER
  896. * setting the parameters to their default values.
  897. */
  898. dfx_bus_config_check(bp);
  899. /* Disable PDQ interrupts first */
  900. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
  901. /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
  902. (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
  903. /* Read the factory MAC address from the adapter then save it */
  904. if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0,
  905. &data) != DFX_K_SUCCESS) {
  906. printk("%s: Could not read adapter factory MAC address!\n",
  907. print_name);
  908. return(DFX_K_FAILURE);
  909. }
  910. le32 = cpu_to_le32(data);
  911. memcpy(&bp->factory_mac_addr[0], &le32, sizeof(u32));
  912. if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0,
  913. &data) != DFX_K_SUCCESS) {
  914. printk("%s: Could not read adapter factory MAC address!\n",
  915. print_name);
  916. return(DFX_K_FAILURE);
  917. }
  918. le32 = cpu_to_le32(data);
  919. memcpy(&bp->factory_mac_addr[4], &le32, sizeof(u16));
  920. /*
  921. * Set current address to factory address
  922. *
  923. * Note: Node address override support is handled through
  924. * dfx_ctl_set_mac_address.
  925. */
  926. memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
  927. if (dfx_bus_tc)
  928. board_name = "DEFTA";
  929. if (dfx_bus_eisa)
  930. board_name = "DEFEA";
  931. if (dfx_bus_pci)
  932. board_name = "DEFPA";
  933. pr_info("%s: %s at %saddr = 0x%llx, IRQ = %d, "
  934. "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
  935. print_name, board_name, dfx_use_mmio ? "" : "I/O ",
  936. (long long)bar_start, dev->irq,
  937. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  938. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  939. /*
  940. * Get memory for descriptor block, consumer block, and other buffers
  941. * that need to be DMA read or written to by the adapter.
  942. */
  943. alloc_size = sizeof(PI_DESCR_BLOCK) +
  944. PI_CMD_REQ_K_SIZE_MAX +
  945. PI_CMD_RSP_K_SIZE_MAX +
  946. #ifndef DYNAMIC_BUFFERS
  947. (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
  948. #endif
  949. sizeof(PI_CONSUMER_BLOCK) +
  950. (PI_ALIGN_K_DESC_BLK - 1);
  951. bp->kmalloced = top_v = dma_alloc_coherent(bp->bus_dev, alloc_size,
  952. &bp->kmalloced_dma,
  953. GFP_ATOMIC);
  954. if (top_v == NULL) {
  955. printk("%s: Could not allocate memory for host buffers "
  956. "and structures!\n", print_name);
  957. return(DFX_K_FAILURE);
  958. }
  959. memset(top_v, 0, alloc_size); /* zero out memory before continuing */
  960. top_p = bp->kmalloced_dma; /* get physical address of buffer */
  961. /*
  962. * To guarantee the 8K alignment required for the descriptor block, 8K - 1
  963. * plus the amount of memory needed was allocated. The physical address
  964. * is now 8K aligned. By carving up the memory in a specific order,
  965. * we'll guarantee the alignment requirements for all other structures.
  966. *
  967. * Note: If the assumptions change regarding the non-paged, non-cached,
  968. * physically contiguous nature of the memory block or the address
  969. * alignments, then we'll need to implement a different algorithm
  970. * for allocating the needed memory.
  971. */
  972. curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK);
  973. curr_v = top_v + (curr_p - top_p);
  974. /* Reserve space for descriptor block */
  975. bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v;
  976. bp->descr_block_phys = curr_p;
  977. curr_v += sizeof(PI_DESCR_BLOCK);
  978. curr_p += sizeof(PI_DESCR_BLOCK);
  979. /* Reserve space for command request buffer */
  980. bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v;
  981. bp->cmd_req_phys = curr_p;
  982. curr_v += PI_CMD_REQ_K_SIZE_MAX;
  983. curr_p += PI_CMD_REQ_K_SIZE_MAX;
  984. /* Reserve space for command response buffer */
  985. bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v;
  986. bp->cmd_rsp_phys = curr_p;
  987. curr_v += PI_CMD_RSP_K_SIZE_MAX;
  988. curr_p += PI_CMD_RSP_K_SIZE_MAX;
  989. /* Reserve space for the LLC host receive queue buffers */
  990. bp->rcv_block_virt = curr_v;
  991. bp->rcv_block_phys = curr_p;
  992. #ifndef DYNAMIC_BUFFERS
  993. curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
  994. curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
  995. #endif
  996. /* Reserve space for the consumer block */
  997. bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v;
  998. bp->cons_block_phys = curr_p;
  999. /* Display virtual and physical addresses if debug driver */
  1000. DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n",
  1001. print_name,
  1002. (long)bp->descr_block_virt, bp->descr_block_phys);
  1003. DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n",
  1004. print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
  1005. DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n",
  1006. print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
  1007. DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n",
  1008. print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
  1009. DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n",
  1010. print_name, (long)bp->cons_block_virt, bp->cons_block_phys);
  1011. return(DFX_K_SUCCESS);
  1012. }
  1013. /*
  1014. * =================
  1015. * = dfx_adap_init =
  1016. * =================
  1017. *
  1018. * Overview:
  1019. * Brings the adapter to the link avail/link unavailable state.
  1020. *
  1021. * Returns:
  1022. * Condition code
  1023. *
  1024. * Arguments:
  1025. * bp - pointer to board information
  1026. * get_buffers - non-zero if buffers to be allocated
  1027. *
  1028. * Functional Description:
  1029. * Issues the low-level firmware/hardware calls necessary to bring
  1030. * the adapter up, or to properly reset and restore adapter during
  1031. * run-time.
  1032. *
  1033. * Return Codes:
  1034. * DFX_K_SUCCESS - Adapter brought up successfully
  1035. * DFX_K_FAILURE - Adapter initialization failed
  1036. *
  1037. * Assumptions:
  1038. * bp->reset_type should be set to a valid reset type value before
  1039. * calling this routine.
  1040. *
  1041. * Side Effects:
  1042. * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
  1043. * upon a successful return of this routine.
  1044. */
  1045. static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
  1046. {
  1047. DBG_printk("In dfx_adap_init...\n");
  1048. /* Disable PDQ interrupts first */
  1049. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
  1050. /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
  1051. if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS)
  1052. {
  1053. printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name);
  1054. return(DFX_K_FAILURE);
  1055. }
  1056. /*
  1057. * When the PDQ is reset, some false Type 0 interrupts may be pending,
  1058. * so we'll acknowledge all Type 0 interrupts now before continuing.
  1059. */
  1060. dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0);
  1061. /*
  1062. * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
  1063. *
  1064. * Note: We only need to clear host copies of these registers. The PDQ reset
  1065. * takes care of the on-board register values.
  1066. */
  1067. bp->cmd_req_reg.lword = 0;
  1068. bp->cmd_rsp_reg.lword = 0;
  1069. bp->rcv_xmt_reg.lword = 0;
  1070. /* Clear consumer block before going to DMA_AVAILABLE state */
  1071. memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
  1072. /* Initialize the DMA Burst Size */
  1073. if (dfx_hw_port_ctrl_req(bp,
  1074. PI_PCTRL_M_SUB_CMD,
  1075. PI_SUB_CMD_K_BURST_SIZE_SET,
  1076. bp->burst_size,
  1077. NULL) != DFX_K_SUCCESS)
  1078. {
  1079. printk("%s: Could not set adapter burst size!\n", bp->dev->name);
  1080. return(DFX_K_FAILURE);
  1081. }
  1082. /*
  1083. * Set base address of Consumer Block
  1084. *
  1085. * Assumption: 32-bit physical address of consumer block is 64 byte
  1086. * aligned. That is, bits 0-5 of the address must be zero.
  1087. */
  1088. if (dfx_hw_port_ctrl_req(bp,
  1089. PI_PCTRL_M_CONS_BLOCK,
  1090. bp->cons_block_phys,
  1091. 0,
  1092. NULL) != DFX_K_SUCCESS)
  1093. {
  1094. printk("%s: Could not set consumer block address!\n", bp->dev->name);
  1095. return(DFX_K_FAILURE);
  1096. }
  1097. /*
  1098. * Set the base address of Descriptor Block and bring adapter
  1099. * to DMA_AVAILABLE state.
  1100. *
  1101. * Note: We also set the literal and data swapping requirements
  1102. * in this command.
  1103. *
  1104. * Assumption: 32-bit physical address of descriptor block
  1105. * is 8Kbyte aligned.
  1106. */
  1107. if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT,
  1108. (u32)(bp->descr_block_phys |
  1109. PI_PDATA_A_INIT_M_BSWAP_INIT),
  1110. 0, NULL) != DFX_K_SUCCESS) {
  1111. printk("%s: Could not set descriptor block address!\n",
  1112. bp->dev->name);
  1113. return DFX_K_FAILURE;
  1114. }
  1115. /* Set transmit flush timeout value */
  1116. bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET;
  1117. bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME;
  1118. bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */
  1119. bp->cmd_req_virt->char_set.item[0].item_index = 0;
  1120. bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL;
  1121. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  1122. {
  1123. printk("%s: DMA command request failed!\n", bp->dev->name);
  1124. return(DFX_K_FAILURE);
  1125. }
  1126. /* Set the initial values for eFDXEnable and MACTReq MIB objects */
  1127. bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET;
  1128. bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS;
  1129. bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb;
  1130. bp->cmd_req_virt->snmp_set.item[0].item_index = 0;
  1131. bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ;
  1132. bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt;
  1133. bp->cmd_req_virt->snmp_set.item[1].item_index = 0;
  1134. bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL;
  1135. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  1136. {
  1137. printk("%s: DMA command request failed!\n", bp->dev->name);
  1138. return(DFX_K_FAILURE);
  1139. }
  1140. /* Initialize adapter CAM */
  1141. if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
  1142. {
  1143. printk("%s: Adapter CAM update failed!\n", bp->dev->name);
  1144. return(DFX_K_FAILURE);
  1145. }
  1146. /* Initialize adapter filters */
  1147. if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
  1148. {
  1149. printk("%s: Adapter filters update failed!\n", bp->dev->name);
  1150. return(DFX_K_FAILURE);
  1151. }
  1152. /*
  1153. * Remove any existing dynamic buffers (i.e. if the adapter is being
  1154. * reinitialized)
  1155. */
  1156. if (get_buffers)
  1157. dfx_rcv_flush(bp);
  1158. /* Initialize receive descriptor block and produce buffers */
  1159. if (dfx_rcv_init(bp, get_buffers))
  1160. {
  1161. printk("%s: Receive buffer allocation failed\n", bp->dev->name);
  1162. if (get_buffers)
  1163. dfx_rcv_flush(bp);
  1164. return(DFX_K_FAILURE);
  1165. }
  1166. /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
  1167. bp->cmd_req_virt->cmd_type = PI_CMD_K_START;
  1168. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  1169. {
  1170. printk("%s: Start command failed\n", bp->dev->name);
  1171. if (get_buffers)
  1172. dfx_rcv_flush(bp);
  1173. return(DFX_K_FAILURE);
  1174. }
  1175. /* Initialization succeeded, reenable PDQ interrupts */
  1176. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS);
  1177. return(DFX_K_SUCCESS);
  1178. }
  1179. /*
  1180. * ============
  1181. * = dfx_open =
  1182. * ============
  1183. *
  1184. * Overview:
  1185. * Opens the adapter
  1186. *
  1187. * Returns:
  1188. * Condition code
  1189. *
  1190. * Arguments:
  1191. * dev - pointer to device information
  1192. *
  1193. * Functional Description:
  1194. * This function brings the adapter to an operational state.
  1195. *
  1196. * Return Codes:
  1197. * 0 - Adapter was successfully opened
  1198. * -EAGAIN - Could not register IRQ or adapter initialization failed
  1199. *
  1200. * Assumptions:
  1201. * This routine should only be called for a device that was
  1202. * initialized successfully.
  1203. *
  1204. * Side Effects:
  1205. * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
  1206. * if the open is successful.
  1207. */
  1208. static int dfx_open(struct net_device *dev)
  1209. {
  1210. DFX_board_t *bp = netdev_priv(dev);
  1211. int ret;
  1212. DBG_printk("In dfx_open...\n");
  1213. /* Register IRQ - support shared interrupts by passing device ptr */
  1214. ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name,
  1215. dev);
  1216. if (ret) {
  1217. printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq);
  1218. return ret;
  1219. }
  1220. /*
  1221. * Set current address to factory MAC address
  1222. *
  1223. * Note: We've already done this step in dfx_driver_init.
  1224. * However, it's possible that a user has set a node
  1225. * address override, then closed and reopened the
  1226. * adapter. Unless we reset the device address field
  1227. * now, we'll continue to use the existing modified
  1228. * address.
  1229. */
  1230. memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
  1231. /* Clear local unicast/multicast address tables and counts */
  1232. memset(bp->uc_table, 0, sizeof(bp->uc_table));
  1233. memset(bp->mc_table, 0, sizeof(bp->mc_table));
  1234. bp->uc_count = 0;
  1235. bp->mc_count = 0;
  1236. /* Disable promiscuous filter settings */
  1237. bp->ind_group_prom = PI_FSTATE_K_BLOCK;
  1238. bp->group_prom = PI_FSTATE_K_BLOCK;
  1239. spin_lock_init(&bp->lock);
  1240. /* Reset and initialize adapter */
  1241. bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */
  1242. if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS)
  1243. {
  1244. printk(KERN_ERR "%s: Adapter open failed!\n", dev->name);
  1245. free_irq(dev->irq, dev);
  1246. return -EAGAIN;
  1247. }
  1248. /* Set device structure info */
  1249. netif_start_queue(dev);
  1250. return(0);
  1251. }
  1252. /*
  1253. * =============
  1254. * = dfx_close =
  1255. * =============
  1256. *
  1257. * Overview:
  1258. * Closes the device/module.
  1259. *
  1260. * Returns:
  1261. * Condition code
  1262. *
  1263. * Arguments:
  1264. * dev - pointer to device information
  1265. *
  1266. * Functional Description:
  1267. * This routine closes the adapter and brings it to a safe state.
  1268. * The interrupt service routine is deregistered with the OS.
  1269. * The adapter can be opened again with another call to dfx_open().
  1270. *
  1271. * Return Codes:
  1272. * Always return 0.
  1273. *
  1274. * Assumptions:
  1275. * No further requests for this adapter are made after this routine is
  1276. * called. dfx_open() can be called to reset and reinitialize the
  1277. * adapter.
  1278. *
  1279. * Side Effects:
  1280. * Adapter should be in DMA_UNAVAILABLE state upon completion of this
  1281. * routine.
  1282. */
  1283. static int dfx_close(struct net_device *dev)
  1284. {
  1285. DFX_board_t *bp = netdev_priv(dev);
  1286. DBG_printk("In dfx_close...\n");
  1287. /* Disable PDQ interrupts first */
  1288. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
  1289. /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
  1290. (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
  1291. /*
  1292. * Flush any pending transmit buffers
  1293. *
  1294. * Note: It's important that we flush the transmit buffers
  1295. * BEFORE we clear our copy of the Type 2 register.
  1296. * Otherwise, we'll have no idea how many buffers
  1297. * we need to free.
  1298. */
  1299. dfx_xmt_flush(bp);
  1300. /*
  1301. * Clear Type 1 and Type 2 registers after adapter reset
  1302. *
  1303. * Note: Even though we're closing the adapter, it's
  1304. * possible that an interrupt will occur after
  1305. * dfx_close is called. Without some assurance to
  1306. * the contrary we want to make sure that we don't
  1307. * process receive and transmit LLC frames and update
  1308. * the Type 2 register with bad information.
  1309. */
  1310. bp->cmd_req_reg.lword = 0;
  1311. bp->cmd_rsp_reg.lword = 0;
  1312. bp->rcv_xmt_reg.lword = 0;
  1313. /* Clear consumer block for the same reason given above */
  1314. memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
  1315. /* Release all dynamically allocate skb in the receive ring. */
  1316. dfx_rcv_flush(bp);
  1317. /* Clear device structure flags */
  1318. netif_stop_queue(dev);
  1319. /* Deregister (free) IRQ */
  1320. free_irq(dev->irq, dev);
  1321. return(0);
  1322. }
  1323. /*
  1324. * ======================
  1325. * = dfx_int_pr_halt_id =
  1326. * ======================
  1327. *
  1328. * Overview:
  1329. * Displays halt id's in string form.
  1330. *
  1331. * Returns:
  1332. * None
  1333. *
  1334. * Arguments:
  1335. * bp - pointer to board information
  1336. *
  1337. * Functional Description:
  1338. * Determine current halt id and display appropriate string.
  1339. *
  1340. * Return Codes:
  1341. * None
  1342. *
  1343. * Assumptions:
  1344. * None
  1345. *
  1346. * Side Effects:
  1347. * None
  1348. */
  1349. static void dfx_int_pr_halt_id(DFX_board_t *bp)
  1350. {
  1351. PI_UINT32 port_status; /* PDQ port status register value */
  1352. PI_UINT32 halt_id; /* PDQ port status halt ID */
  1353. /* Read the latest port status */
  1354. dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
  1355. /* Display halt state transition information */
  1356. halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID;
  1357. switch (halt_id)
  1358. {
  1359. case PI_HALT_ID_K_SELFTEST_TIMEOUT:
  1360. printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name);
  1361. break;
  1362. case PI_HALT_ID_K_PARITY_ERROR:
  1363. printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name);
  1364. break;
  1365. case PI_HALT_ID_K_HOST_DIR_HALT:
  1366. printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name);
  1367. break;
  1368. case PI_HALT_ID_K_SW_FAULT:
  1369. printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name);
  1370. break;
  1371. case PI_HALT_ID_K_HW_FAULT:
  1372. printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name);
  1373. break;
  1374. case PI_HALT_ID_K_PC_TRACE:
  1375. printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name);
  1376. break;
  1377. case PI_HALT_ID_K_DMA_ERROR:
  1378. printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name);
  1379. break;
  1380. case PI_HALT_ID_K_IMAGE_CRC_ERROR:
  1381. printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name);
  1382. break;
  1383. case PI_HALT_ID_K_BUS_EXCEPTION:
  1384. printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name);
  1385. break;
  1386. default:
  1387. printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id);
  1388. break;
  1389. }
  1390. }
  1391. /*
  1392. * ==========================
  1393. * = dfx_int_type_0_process =
  1394. * ==========================
  1395. *
  1396. * Overview:
  1397. * Processes Type 0 interrupts.
  1398. *
  1399. * Returns:
  1400. * None
  1401. *
  1402. * Arguments:
  1403. * bp - pointer to board information
  1404. *
  1405. * Functional Description:
  1406. * Processes all enabled Type 0 interrupts. If the reason for the interrupt
  1407. * is a serious fault on the adapter, then an error message is displayed
  1408. * and the adapter is reset.
  1409. *
  1410. * One tricky potential timing window is the rapid succession of "link avail"
  1411. * "link unavail" state change interrupts. The acknowledgement of the Type 0
  1412. * interrupt must be done before reading the state from the Port Status
  1413. * register. This is true because a state change could occur after reading
  1414. * the data, but before acknowledging the interrupt. If this state change
  1415. * does happen, it would be lost because the driver is using the old state,
  1416. * and it will never know about the new state because it subsequently
  1417. * acknowledges the state change interrupt.
  1418. *
  1419. * INCORRECT CORRECT
  1420. * read type 0 int reasons read type 0 int reasons
  1421. * read adapter state ack type 0 interrupts
  1422. * ack type 0 interrupts read adapter state
  1423. * ... process interrupt ... ... process interrupt ...
  1424. *
  1425. * Return Codes:
  1426. * None
  1427. *
  1428. * Assumptions:
  1429. * None
  1430. *
  1431. * Side Effects:
  1432. * An adapter reset may occur if the adapter has any Type 0 error interrupts
  1433. * or if the port status indicates that the adapter is halted. The driver
  1434. * is responsible for reinitializing the adapter with the current CAM
  1435. * contents and adapter filter settings.
  1436. */
  1437. static void dfx_int_type_0_process(DFX_board_t *bp)
  1438. {
  1439. PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */
  1440. PI_UINT32 state; /* current adap state (from port status) */
  1441. /*
  1442. * Read host interrupt Type 0 register to determine which Type 0
  1443. * interrupts are pending. Immediately write it back out to clear
  1444. * those interrupts.
  1445. */
  1446. dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status);
  1447. dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status);
  1448. /* Check for Type 0 error interrupts */
  1449. if (type_0_status & (PI_TYPE_0_STAT_M_NXM |
  1450. PI_TYPE_0_STAT_M_PM_PAR_ERR |
  1451. PI_TYPE_0_STAT_M_BUS_PAR_ERR))
  1452. {
  1453. /* Check for Non-Existent Memory error */
  1454. if (type_0_status & PI_TYPE_0_STAT_M_NXM)
  1455. printk("%s: Non-Existent Memory Access Error\n", bp->dev->name);
  1456. /* Check for Packet Memory Parity error */
  1457. if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR)
  1458. printk("%s: Packet Memory Parity Error\n", bp->dev->name);
  1459. /* Check for Host Bus Parity error */
  1460. if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR)
  1461. printk("%s: Host Bus Parity Error\n", bp->dev->name);
  1462. /* Reset adapter and bring it back on-line */
  1463. bp->link_available = PI_K_FALSE; /* link is no longer available */
  1464. bp->reset_type = 0; /* rerun on-board diagnostics */
  1465. printk("%s: Resetting adapter...\n", bp->dev->name);
  1466. if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
  1467. {
  1468. printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
  1469. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
  1470. return;
  1471. }
  1472. printk("%s: Adapter reset successful!\n", bp->dev->name);
  1473. return;
  1474. }
  1475. /* Check for transmit flush interrupt */
  1476. if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH)
  1477. {
  1478. /* Flush any pending xmt's and acknowledge the flush interrupt */
  1479. bp->link_available = PI_K_FALSE; /* link is no longer available */
  1480. dfx_xmt_flush(bp); /* flush any outstanding packets */
  1481. (void) dfx_hw_port_ctrl_req(bp,
  1482. PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
  1483. 0,
  1484. 0,
  1485. NULL);
  1486. }
  1487. /* Check for adapter state change */
  1488. if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE)
  1489. {
  1490. /* Get latest adapter state */
  1491. state = dfx_hw_adap_state_rd(bp); /* get adapter state */
  1492. if (state == PI_STATE_K_HALTED)
  1493. {
  1494. /*
  1495. * Adapter has transitioned to HALTED state, try to reset
  1496. * adapter to bring it back on-line. If reset fails,
  1497. * leave the adapter in the broken state.
  1498. */
  1499. printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name);
  1500. dfx_int_pr_halt_id(bp); /* display halt id as string */
  1501. /* Reset adapter and bring it back on-line */
  1502. bp->link_available = PI_K_FALSE; /* link is no longer available */
  1503. bp->reset_type = 0; /* rerun on-board diagnostics */
  1504. printk("%s: Resetting adapter...\n", bp->dev->name);
  1505. if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
  1506. {
  1507. printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
  1508. dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
  1509. return;
  1510. }
  1511. printk("%s: Adapter reset successful!\n", bp->dev->name);
  1512. }
  1513. else if (state == PI_STATE_K_LINK_AVAIL)
  1514. {
  1515. bp->link_available = PI_K_TRUE; /* set link available flag */
  1516. }
  1517. }
  1518. }
  1519. /*
  1520. * ==================
  1521. * = dfx_int_common =
  1522. * ==================
  1523. *
  1524. * Overview:
  1525. * Interrupt service routine (ISR)
  1526. *
  1527. * Returns:
  1528. * None
  1529. *
  1530. * Arguments:
  1531. * bp - pointer to board information
  1532. *
  1533. * Functional Description:
  1534. * This is the ISR which processes incoming adapter interrupts.
  1535. *
  1536. * Return Codes:
  1537. * None
  1538. *
  1539. * Assumptions:
  1540. * This routine assumes PDQ interrupts have not been disabled.
  1541. * When interrupts are disabled at the PDQ, the Port Status register
  1542. * is automatically cleared. This routine uses the Port Status
  1543. * register value to determine whether a Type 0 interrupt occurred,
  1544. * so it's important that adapter interrupts are not normally
  1545. * enabled/disabled at the PDQ.
  1546. *
  1547. * It's vital that this routine is NOT reentered for the
  1548. * same board and that the OS is not in another section of
  1549. * code (eg. dfx_xmt_queue_pkt) for the same board on a
  1550. * different thread.
  1551. *
  1552. * Side Effects:
  1553. * Pending interrupts are serviced. Depending on the type of
  1554. * interrupt, acknowledging and clearing the interrupt at the
  1555. * PDQ involves writing a register to clear the interrupt bit
  1556. * or updating completion indices.
  1557. */
  1558. static void dfx_int_common(struct net_device *dev)
  1559. {
  1560. DFX_board_t *bp = netdev_priv(dev);
  1561. PI_UINT32 port_status; /* Port Status register */
  1562. /* Process xmt interrupts - frequent case, so always call this routine */
  1563. if(dfx_xmt_done(bp)) /* free consumed xmt packets */
  1564. netif_wake_queue(dev);
  1565. /* Process rcv interrupts - frequent case, so always call this routine */
  1566. dfx_rcv_queue_process(bp); /* service received LLC frames */
  1567. /*
  1568. * Transmit and receive producer and completion indices are updated on the
  1569. * adapter by writing to the Type 2 Producer register. Since the frequent
  1570. * case is that we'll be processing either LLC transmit or receive buffers,
  1571. * we'll optimize I/O writes by doing a single register write here.
  1572. */
  1573. dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
  1574. /* Read PDQ Port Status register to find out which interrupts need processing */
  1575. dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
  1576. /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
  1577. if (port_status & PI_PSTATUS_M_TYPE_0_PENDING)
  1578. dfx_int_type_0_process(bp); /* process Type 0 interrupts */
  1579. }
  1580. /*
  1581. * =================
  1582. * = dfx_interrupt =
  1583. * =================
  1584. *
  1585. * Overview:
  1586. * Interrupt processing routine
  1587. *
  1588. * Returns:
  1589. * Whether a valid interrupt was seen.
  1590. *
  1591. * Arguments:
  1592. * irq - interrupt vector
  1593. * dev_id - pointer to device information
  1594. *
  1595. * Functional Description:
  1596. * This routine calls the interrupt processing routine for this adapter. It
  1597. * disables and reenables adapter interrupts, as appropriate. We can support
  1598. * shared interrupts since the incoming dev_id pointer provides our device
  1599. * structure context.
  1600. *
  1601. * Return Codes:
  1602. * IRQ_HANDLED - an IRQ was handled.
  1603. * IRQ_NONE - no IRQ was handled.
  1604. *
  1605. * Assumptions:
  1606. * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
  1607. * on Intel-based systems) is done by the operating system outside this
  1608. * routine.
  1609. *
  1610. * System interrupts are enabled through this call.
  1611. *
  1612. * Side Effects:
  1613. * Interrupts are disabled, then reenabled at the adapter.
  1614. */
  1615. static irqreturn_t dfx_interrupt(int irq, void *dev_id)
  1616. {
  1617. struct net_device *dev = dev_id;
  1618. DFX_board_t *bp = netdev_priv(dev);
  1619. struct device *bdev = bp->bus_dev;
  1620. int dfx_bus_pci = DFX_BUS_PCI(bdev);
  1621. int dfx_bus_eisa = DFX_BUS_EISA(bdev);
  1622. int dfx_bus_tc = DFX_BUS_TC(bdev);
  1623. /* Service adapter interrupts */
  1624. if (dfx_bus_pci) {
  1625. u32 status;
  1626. dfx_port_read_long(bp, PFI_K_REG_STATUS, &status);
  1627. if (!(status & PFI_STATUS_M_PDQ_INT))
  1628. return IRQ_NONE;
  1629. spin_lock(&bp->lock);
  1630. /* Disable PDQ-PFI interrupts at PFI */
  1631. dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
  1632. PFI_MODE_M_DMA_ENB);
  1633. /* Call interrupt service routine for this adapter */
  1634. dfx_int_common(dev);
  1635. /* Clear PDQ interrupt status bit and reenable interrupts */
  1636. dfx_port_write_long(bp, PFI_K_REG_STATUS,
  1637. PFI_STATUS_M_PDQ_INT);
  1638. dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
  1639. (PFI_MODE_M_PDQ_INT_ENB |
  1640. PFI_MODE_M_DMA_ENB));
  1641. spin_unlock(&bp->lock);
  1642. }
  1643. if (dfx_bus_eisa) {
  1644. unsigned long base_addr = to_eisa_device(bdev)->base_addr;
  1645. u8 status;
  1646. status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  1647. if (!(status & PI_CONFIG_STAT_0_M_PEND))
  1648. return IRQ_NONE;
  1649. spin_lock(&bp->lock);
  1650. /* Disable interrupts at the ESIC */
  1651. status &= ~PI_CONFIG_STAT_0_M_INT_ENB;
  1652. outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status);
  1653. /* Call interrupt service routine for this adapter */
  1654. dfx_int_common(dev);
  1655. /* Reenable interrupts at the ESIC */
  1656. status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
  1657. status |= PI_CONFIG_STAT_0_M_INT_ENB;
  1658. outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status);
  1659. spin_unlock(&bp->lock);
  1660. }
  1661. if (dfx_bus_tc) {
  1662. u32 status;
  1663. dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &status);
  1664. if (!(status & (PI_PSTATUS_M_RCV_DATA_PENDING |
  1665. PI_PSTATUS_M_XMT_DATA_PENDING |
  1666. PI_PSTATUS_M_SMT_HOST_PENDING |
  1667. PI_PSTATUS_M_UNSOL_PENDING |
  1668. PI_PSTATUS_M_CMD_RSP_PENDING |
  1669. PI_PSTATUS_M_CMD_REQ_PENDING |
  1670. PI_PSTATUS_M_TYPE_0_PENDING)))
  1671. return IRQ_NONE;
  1672. spin_lock(&bp->lock);
  1673. /* Call interrupt service routine for this adapter */
  1674. dfx_int_common(dev);
  1675. spin_unlock(&bp->lock);
  1676. }
  1677. return IRQ_HANDLED;
  1678. }
  1679. /*
  1680. * =====================
  1681. * = dfx_ctl_get_stats =
  1682. * =====================
  1683. *
  1684. * Overview:
  1685. * Get statistics for FDDI adapter
  1686. *
  1687. * Returns:
  1688. * Pointer to FDDI statistics structure
  1689. *
  1690. * Arguments:
  1691. * dev - pointer to device information
  1692. *
  1693. * Functional Description:
  1694. * Gets current MIB objects from adapter, then
  1695. * returns FDDI statistics structure as defined
  1696. * in if_fddi.h.
  1697. *
  1698. * Note: Since the FDDI statistics structure is
  1699. * still new and the device structure doesn't
  1700. * have an FDDI-specific get statistics handler,
  1701. * we'll return the FDDI statistics structure as
  1702. * a pointer to an Ethernet statistics structure.
  1703. * That way, at least the first part of the statistics
  1704. * structure can be decoded properly, and it allows
  1705. * "smart" applications to perform a second cast to
  1706. * decode the FDDI-specific statistics.
  1707. *
  1708. * We'll have to pay attention to this routine as the
  1709. * device structure becomes more mature and LAN media
  1710. * independent.
  1711. *
  1712. * Return Codes:
  1713. * None
  1714. *
  1715. * Assumptions:
  1716. * None
  1717. *
  1718. * Side Effects:
  1719. * None
  1720. */
  1721. static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev)
  1722. {
  1723. DFX_board_t *bp = netdev_priv(dev);
  1724. /* Fill the bp->stats structure with driver-maintained counters */
  1725. bp->stats.gen.rx_packets = bp->rcv_total_frames;
  1726. bp->stats.gen.tx_packets = bp->xmt_total_frames;
  1727. bp->stats.gen.rx_bytes = bp->rcv_total_bytes;
  1728. bp->stats.gen.tx_bytes = bp->xmt_total_bytes;
  1729. bp->stats.gen.rx_errors = bp->rcv_crc_errors +
  1730. bp->rcv_frame_status_errors +
  1731. bp->rcv_length_errors;
  1732. bp->stats.gen.tx_errors = bp->xmt_length_errors;
  1733. bp->stats.gen.rx_dropped = bp->rcv_discards;
  1734. bp->stats.gen.tx_dropped = bp->xmt_discards;
  1735. bp->stats.gen.multicast = bp->rcv_multicast_frames;
  1736. bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */
  1737. /* Get FDDI SMT MIB objects */
  1738. bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET;
  1739. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  1740. return((struct net_device_stats *) &bp->stats);
  1741. /* Fill the bp->stats structure with the SMT MIB object values */
  1742. memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
  1743. bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id;
  1744. bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id;
  1745. bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id;
  1746. memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
  1747. bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id;
  1748. bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct;
  1749. bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct;
  1750. bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct;
  1751. bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths;
  1752. bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities;
  1753. bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy;
  1754. bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy;
  1755. bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify;
  1756. bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy;
  1757. bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration;
  1758. bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present;
  1759. bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state;
  1760. bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state;
  1761. bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
  1762. bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status;
  1763. bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag;
  1764. bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls;
  1765. bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
  1766. bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
  1767. bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability;
  1768. bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability;
  1769. bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths;
  1770. bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path;
  1771. memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
  1772. memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
  1773. memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
  1774. memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
  1775. bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test;
  1776. bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths;
  1777. bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type;
  1778. memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
  1779. bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req;
  1780. bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg;
  1781. bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max;
  1782. bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value;
  1783. bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold;
  1784. bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio;
  1785. bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state;
  1786. bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag;
  1787. bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag;
  1788. bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag;
  1789. bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available;
  1790. bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present;
  1791. bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable;
  1792. bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound;
  1793. bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound;
  1794. bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req;
  1795. memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
  1796. bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0];
  1797. bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1];
  1798. bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0];
  1799. bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1];
  1800. bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
  1801. bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
  1802. bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0];
  1803. bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1];
  1804. bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0];
  1805. bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1];
  1806. memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
  1807. memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
  1808. bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0];
  1809. bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1];
  1810. bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0];
  1811. bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1];
  1812. bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0];
  1813. bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1];
  1814. bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
  1815. bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
  1816. bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0];
  1817. bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1];
  1818. bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0];
  1819. bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1];
  1820. bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0];
  1821. bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1];
  1822. bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0];
  1823. bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1];
  1824. bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0];
  1825. bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1];
  1826. bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0];
  1827. bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1];
  1828. bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0];
  1829. bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1];
  1830. bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0];
  1831. bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1];
  1832. bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0];
  1833. bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1];
  1834. /* Get FDDI counters */
  1835. bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET;
  1836. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  1837. return((struct net_device_stats *) &bp->stats);
  1838. /* Fill the bp->stats structure with the FDDI counter values */
  1839. bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls;
  1840. bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls;
  1841. bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls;
  1842. bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls;
  1843. bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls;
  1844. bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls;
  1845. bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls;
  1846. bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls;
  1847. bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls;
  1848. bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls;
  1849. bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls;
  1850. return((struct net_device_stats *) &bp->stats);
  1851. }
  1852. /*
  1853. * ==============================
  1854. * = dfx_ctl_set_multicast_list =
  1855. * ==============================
  1856. *
  1857. * Overview:
  1858. * Enable/Disable LLC frame promiscuous mode reception
  1859. * on the adapter and/or update multicast address table.
  1860. *
  1861. * Returns:
  1862. * None
  1863. *
  1864. * Arguments:
  1865. * dev - pointer to device information
  1866. *
  1867. * Functional Description:
  1868. * This routine follows a fairly simple algorithm for setting the
  1869. * adapter filters and CAM:
  1870. *
  1871. * if IFF_PROMISC flag is set
  1872. * enable LLC individual/group promiscuous mode
  1873. * else
  1874. * disable LLC individual/group promiscuous mode
  1875. * if number of incoming multicast addresses >
  1876. * (CAM max size - number of unicast addresses in CAM)
  1877. * enable LLC group promiscuous mode
  1878. * set driver-maintained multicast address count to zero
  1879. * else
  1880. * disable LLC group promiscuous mode
  1881. * set driver-maintained multicast address count to incoming count
  1882. * update adapter CAM
  1883. * update adapter filters
  1884. *
  1885. * Return Codes:
  1886. * None
  1887. *
  1888. * Assumptions:
  1889. * Multicast addresses are presented in canonical (LSB) format.
  1890. *
  1891. * Side Effects:
  1892. * On-board adapter CAM and filters are updated.
  1893. */
  1894. static void dfx_ctl_set_multicast_list(struct net_device *dev)
  1895. {
  1896. DFX_board_t *bp = netdev_priv(dev);
  1897. int i; /* used as index in for loop */
  1898. struct dev_mc_list *dmi; /* ptr to multicast addr entry */
  1899. /* Enable LLC frame promiscuous mode, if necessary */
  1900. if (dev->flags & IFF_PROMISC)
  1901. bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */
  1902. /* Else, update multicast address table */
  1903. else
  1904. {
  1905. bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */
  1906. /*
  1907. * Check whether incoming multicast address count exceeds table size
  1908. *
  1909. * Note: The adapters utilize an on-board 64 entry CAM for
  1910. * supporting perfect filtering of multicast packets
  1911. * and bridge functions when adding unicast addresses.
  1912. * There is no hash function available. To support
  1913. * additional multicast addresses, the all multicast
  1914. * filter (LLC group promiscuous mode) must be enabled.
  1915. *
  1916. * The firmware reserves two CAM entries for SMT-related
  1917. * multicast addresses, which leaves 62 entries available.
  1918. * The following code ensures that we're not being asked
  1919. * to add more than 62 addresses to the CAM. If we are,
  1920. * the driver will enable the all multicast filter.
  1921. * Should the number of multicast addresses drop below
  1922. * the high water mark, the filter will be disabled and
  1923. * perfect filtering will be used.
  1924. */
  1925. if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count))
  1926. {
  1927. bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
  1928. bp->mc_count = 0; /* Don't add mc addrs to CAM */
  1929. }
  1930. else
  1931. {
  1932. bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */
  1933. bp->mc_count = dev->mc_count; /* Add mc addrs to CAM */
  1934. }
  1935. /* Copy addresses to multicast address table, then update adapter CAM */
  1936. dmi = dev->mc_list; /* point to first multicast addr */
  1937. for (i=0; i < bp->mc_count; i++)
  1938. {
  1939. memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN);
  1940. dmi = dmi->next; /* point to next multicast addr */
  1941. }
  1942. if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
  1943. {
  1944. DBG_printk("%s: Could not update multicast address table!\n", dev->name);
  1945. }
  1946. else
  1947. {
  1948. DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
  1949. }
  1950. }
  1951. /* Update adapter filters */
  1952. if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
  1953. {
  1954. DBG_printk("%s: Could not update adapter filters!\n", dev->name);
  1955. }
  1956. else
  1957. {
  1958. DBG_printk("%s: Adapter filters updated!\n", dev->name);
  1959. }
  1960. }
  1961. /*
  1962. * ===========================
  1963. * = dfx_ctl_set_mac_address =
  1964. * ===========================
  1965. *
  1966. * Overview:
  1967. * Add node address override (unicast address) to adapter
  1968. * CAM and update dev_addr field in device table.
  1969. *
  1970. * Returns:
  1971. * None
  1972. *
  1973. * Arguments:
  1974. * dev - pointer to device information
  1975. * addr - pointer to sockaddr structure containing unicast address to add
  1976. *
  1977. * Functional Description:
  1978. * The adapter supports node address overrides by adding one or more
  1979. * unicast addresses to the adapter CAM. This is similar to adding
  1980. * multicast addresses. In this routine we'll update the driver and
  1981. * device structures with the new address, then update the adapter CAM
  1982. * to ensure that the adapter will copy and strip frames destined and
  1983. * sourced by that address.
  1984. *
  1985. * Return Codes:
  1986. * Always returns zero.
  1987. *
  1988. * Assumptions:
  1989. * The address pointed to by addr->sa_data is a valid unicast
  1990. * address and is presented in canonical (LSB) format.
  1991. *
  1992. * Side Effects:
  1993. * On-board adapter CAM is updated. On-board adapter filters
  1994. * may be updated.
  1995. */
  1996. static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr)
  1997. {
  1998. struct sockaddr *p_sockaddr = (struct sockaddr *)addr;
  1999. DFX_board_t *bp = netdev_priv(dev);
  2000. /* Copy unicast address to driver-maintained structs and update count */
  2001. memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */
  2002. memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */
  2003. bp->uc_count = 1;
  2004. /*
  2005. * Verify we're not exceeding the CAM size by adding unicast address
  2006. *
  2007. * Note: It's possible that before entering this routine we've
  2008. * already filled the CAM with 62 multicast addresses.
  2009. * Since we need to place the node address override into
  2010. * the CAM, we have to check to see that we're not
  2011. * exceeding the CAM size. If we are, we have to enable
  2012. * the LLC group (multicast) promiscuous mode filter as
  2013. * in dfx_ctl_set_multicast_list.
  2014. */
  2015. if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE)
  2016. {
  2017. bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
  2018. bp->mc_count = 0; /* Don't add mc addrs to CAM */
  2019. /* Update adapter filters */
  2020. if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
  2021. {
  2022. DBG_printk("%s: Could not update adapter filters!\n", dev->name);
  2023. }
  2024. else
  2025. {
  2026. DBG_printk("%s: Adapter filters updated!\n", dev->name);
  2027. }
  2028. }
  2029. /* Update adapter CAM with new unicast address */
  2030. if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
  2031. {
  2032. DBG_printk("%s: Could not set new MAC address!\n", dev->name);
  2033. }
  2034. else
  2035. {
  2036. DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name);
  2037. }
  2038. return(0); /* always return zero */
  2039. }
  2040. /*
  2041. * ======================
  2042. * = dfx_ctl_update_cam =
  2043. * ======================
  2044. *
  2045. * Overview:
  2046. * Procedure to update adapter CAM (Content Addressable Memory)
  2047. * with desired unicast and multicast address entries.
  2048. *
  2049. * Returns:
  2050. * Condition code
  2051. *
  2052. * Arguments:
  2053. * bp - pointer to board information
  2054. *
  2055. * Functional Description:
  2056. * Updates adapter CAM with current contents of board structure
  2057. * unicast and multicast address tables. Since there are only 62
  2058. * free entries in CAM, this routine ensures that the command
  2059. * request buffer is not overrun.
  2060. *
  2061. * Return Codes:
  2062. * DFX_K_SUCCESS - Request succeeded
  2063. * DFX_K_FAILURE - Request failed
  2064. *
  2065. * Assumptions:
  2066. * All addresses being added (unicast and multicast) are in canonical
  2067. * order.
  2068. *
  2069. * Side Effects:
  2070. * On-board adapter CAM is updated.
  2071. */
  2072. static int dfx_ctl_update_cam(DFX_board_t *bp)
  2073. {
  2074. int i; /* used as index */
  2075. PI_LAN_ADDR *p_addr; /* pointer to CAM entry */
  2076. /*
  2077. * Fill in command request information
  2078. *
  2079. * Note: Even though both the unicast and multicast address
  2080. * table entries are stored as contiguous 6 byte entries,
  2081. * the firmware address filter set command expects each
  2082. * entry to be two longwords (8 bytes total). We must be
  2083. * careful to only copy the six bytes of each unicast and
  2084. * multicast table entry into each command entry. This
  2085. * is also why we must first clear the entire command
  2086. * request buffer.
  2087. */
  2088. memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */
  2089. bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET;
  2090. p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0];
  2091. /* Now add unicast addresses to command request buffer, if any */
  2092. for (i=0; i < (int)bp->uc_count; i++)
  2093. {
  2094. if (i < PI_CMD_ADDR_FILTER_K_SIZE)
  2095. {
  2096. memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
  2097. p_addr++; /* point to next command entry */
  2098. }
  2099. }
  2100. /* Now add multicast addresses to command request buffer, if any */
  2101. for (i=0; i < (int)bp->mc_count; i++)
  2102. {
  2103. if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE)
  2104. {
  2105. memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
  2106. p_addr++; /* point to next command entry */
  2107. }
  2108. }
  2109. /* Issue command to update adapter CAM, then return */
  2110. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  2111. return(DFX_K_FAILURE);
  2112. return(DFX_K_SUCCESS);
  2113. }
  2114. /*
  2115. * ==========================
  2116. * = dfx_ctl_update_filters =
  2117. * ==========================
  2118. *
  2119. * Overview:
  2120. * Procedure to update adapter filters with desired
  2121. * filter settings.
  2122. *
  2123. * Returns:
  2124. * Condition code
  2125. *
  2126. * Arguments:
  2127. * bp - pointer to board information
  2128. *
  2129. * Functional Description:
  2130. * Enables or disables filter using current filter settings.
  2131. *
  2132. * Return Codes:
  2133. * DFX_K_SUCCESS - Request succeeded.
  2134. * DFX_K_FAILURE - Request failed.
  2135. *
  2136. * Assumptions:
  2137. * We must always pass up packets destined to the broadcast
  2138. * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
  2139. * broadcast filter enabled.
  2140. *
  2141. * Side Effects:
  2142. * On-board adapter filters are updated.
  2143. */
  2144. static int dfx_ctl_update_filters(DFX_board_t *bp)
  2145. {
  2146. int i = 0; /* used as index */
  2147. /* Fill in command request information */
  2148. bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET;
  2149. /* Initialize Broadcast filter - * ALWAYS ENABLED * */
  2150. bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST;
  2151. bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS;
  2152. /* Initialize LLC Individual/Group Promiscuous filter */
  2153. bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM;
  2154. bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom;
  2155. /* Initialize LLC Group Promiscuous filter */
  2156. bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM;
  2157. bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom;
  2158. /* Terminate the item code list */
  2159. bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL;
  2160. /* Issue command to update adapter filters, then return */
  2161. if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
  2162. return(DFX_K_FAILURE);
  2163. return(DFX_K_SUCCESS);
  2164. }
  2165. /*
  2166. * ======================
  2167. * = dfx_hw_dma_cmd_req =
  2168. * ======================
  2169. *
  2170. * Overview:
  2171. * Sends PDQ DMA command to adapter firmware
  2172. *
  2173. * Returns:
  2174. * Condition code
  2175. *
  2176. * Arguments:
  2177. * bp - pointer to board information
  2178. *
  2179. * Functional Description:
  2180. * The command request and response buffers are posted to the adapter in the manner
  2181. * described in the PDQ Port Specification:
  2182. *
  2183. * 1. Command Response Buffer is posted to adapter.
  2184. * 2. Command Request Buffer is posted to adapter.
  2185. * 3. Command Request consumer index is polled until it indicates that request
  2186. * buffer has been DMA'd to adapter.
  2187. * 4. Command Response consumer index is polled until it indicates that response
  2188. * buffer has been DMA'd from adapter.
  2189. *
  2190. * This ordering ensures that a response buffer is already available for the firmware
  2191. * to use once it's done processing the request buffer.
  2192. *
  2193. * Return Codes:
  2194. * DFX_K_SUCCESS - DMA command succeeded
  2195. * DFX_K_OUTSTATE - Adapter is NOT in proper state
  2196. * DFX_K_HW_TIMEOUT - DMA command timed out
  2197. *
  2198. * Assumptions:
  2199. * Command request buffer has already been filled with desired DMA command.
  2200. *
  2201. * Side Effects:
  2202. * None
  2203. */
  2204. static int dfx_hw_dma_cmd_req(DFX_board_t *bp)
  2205. {
  2206. int status; /* adapter status */
  2207. int timeout_cnt; /* used in for loops */
  2208. /* Make sure the adapter is in a state that we can issue the DMA command in */
  2209. status = dfx_hw_adap_state_rd(bp);
  2210. if ((status == PI_STATE_K_RESET) ||
  2211. (status == PI_STATE_K_HALTED) ||
  2212. (status == PI_STATE_K_DMA_UNAVAIL) ||
  2213. (status == PI_STATE_K_UPGRADE))
  2214. return(DFX_K_OUTSTATE);
  2215. /* Put response buffer on the command response queue */
  2216. bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
  2217. ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
  2218. bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys;
  2219. /* Bump (and wrap) the producer index and write out to register */
  2220. bp->cmd_rsp_reg.index.prod += 1;
  2221. bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1;
  2222. dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
  2223. /* Put request buffer on the command request queue */
  2224. bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP |
  2225. PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN));
  2226. bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys;
  2227. /* Bump (and wrap) the producer index and write out to register */
  2228. bp->cmd_req_reg.index.prod += 1;
  2229. bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1;
  2230. dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
  2231. /*
  2232. * Here we wait for the command request consumer index to be equal
  2233. * to the producer, indicating that the adapter has DMAed the request.
  2234. */
  2235. for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
  2236. {
  2237. if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req))
  2238. break;
  2239. udelay(100); /* wait for 100 microseconds */
  2240. }
  2241. if (timeout_cnt == 0)
  2242. return(DFX_K_HW_TIMEOUT);
  2243. /* Bump (and wrap) the completion index and write out to register */
  2244. bp->cmd_req_reg.index.comp += 1;
  2245. bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1;
  2246. dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
  2247. /*
  2248. * Here we wait for the command response consumer index to be equal
  2249. * to the producer, indicating that the adapter has DMAed the response.
  2250. */
  2251. for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
  2252. {
  2253. if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp))
  2254. break;
  2255. udelay(100); /* wait for 100 microseconds */
  2256. }
  2257. if (timeout_cnt == 0)
  2258. return(DFX_K_HW_TIMEOUT);
  2259. /* Bump (and wrap) the completion index and write out to register */
  2260. bp->cmd_rsp_reg.index.comp += 1;
  2261. bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1;
  2262. dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
  2263. return(DFX_K_SUCCESS);
  2264. }
  2265. /*
  2266. * ========================
  2267. * = dfx_hw_port_ctrl_req =
  2268. * ========================
  2269. *
  2270. * Overview:
  2271. * Sends PDQ port control command to adapter firmware
  2272. *
  2273. * Returns:
  2274. * Host data register value in host_data if ptr is not NULL
  2275. *
  2276. * Arguments:
  2277. * bp - pointer to board information
  2278. * command - port control command
  2279. * data_a - port data A register value
  2280. * data_b - port data B register value
  2281. * host_data - ptr to host data register value
  2282. *
  2283. * Functional Description:
  2284. * Send generic port control command to adapter by writing
  2285. * to various PDQ port registers, then polling for completion.
  2286. *
  2287. * Return Codes:
  2288. * DFX_K_SUCCESS - port control command succeeded
  2289. * DFX_K_HW_TIMEOUT - port control command timed out
  2290. *
  2291. * Assumptions:
  2292. * None
  2293. *
  2294. * Side Effects:
  2295. * None
  2296. */
  2297. static int dfx_hw_port_ctrl_req(
  2298. DFX_board_t *bp,
  2299. PI_UINT32 command,
  2300. PI_UINT32 data_a,
  2301. PI_UINT32 data_b,
  2302. PI_UINT32 *host_data
  2303. )
  2304. {
  2305. PI_UINT32 port_cmd; /* Port Control command register value */
  2306. int timeout_cnt; /* used in for loops */
  2307. /* Set Command Error bit in command longword */
  2308. port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR);
  2309. /* Issue port command to the adapter */
  2310. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a);
  2311. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b);
  2312. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd);
  2313. /* Now wait for command to complete */
  2314. if (command == PI_PCTRL_M_BLAST_FLASH)
  2315. timeout_cnt = 600000; /* set command timeout count to 60 seconds */
  2316. else
  2317. timeout_cnt = 20000; /* set command timeout count to 2 seconds */
  2318. for (; timeout_cnt > 0; timeout_cnt--)
  2319. {
  2320. dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd);
  2321. if (!(port_cmd & PI_PCTRL_M_CMD_ERROR))
  2322. break;
  2323. udelay(100); /* wait for 100 microseconds */
  2324. }
  2325. if (timeout_cnt == 0)
  2326. return(DFX_K_HW_TIMEOUT);
  2327. /*
  2328. * If the address of host_data is non-zero, assume caller has supplied a
  2329. * non NULL pointer, and return the contents of the HOST_DATA register in
  2330. * it.
  2331. */
  2332. if (host_data != NULL)
  2333. dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data);
  2334. return(DFX_K_SUCCESS);
  2335. }
  2336. /*
  2337. * =====================
  2338. * = dfx_hw_adap_reset =
  2339. * =====================
  2340. *
  2341. * Overview:
  2342. * Resets adapter
  2343. *
  2344. * Returns:
  2345. * None
  2346. *
  2347. * Arguments:
  2348. * bp - pointer to board information
  2349. * type - type of reset to perform
  2350. *
  2351. * Functional Description:
  2352. * Issue soft reset to adapter by writing to PDQ Port Reset
  2353. * register. Use incoming reset type to tell adapter what
  2354. * kind of reset operation to perform.
  2355. *
  2356. * Return Codes:
  2357. * None
  2358. *
  2359. * Assumptions:
  2360. * This routine merely issues a soft reset to the adapter.
  2361. * It is expected that after this routine returns, the caller
  2362. * will appropriately poll the Port Status register for the
  2363. * adapter to enter the proper state.
  2364. *
  2365. * Side Effects:
  2366. * Internal adapter registers are cleared.
  2367. */
  2368. static void dfx_hw_adap_reset(
  2369. DFX_board_t *bp,
  2370. PI_UINT32 type
  2371. )
  2372. {
  2373. /* Set Reset type and assert reset */
  2374. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */
  2375. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET);
  2376. /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
  2377. udelay(20);
  2378. /* Deassert reset */
  2379. dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0);
  2380. }
  2381. /*
  2382. * ========================
  2383. * = dfx_hw_adap_state_rd =
  2384. * ========================
  2385. *
  2386. * Overview:
  2387. * Returns current adapter state
  2388. *
  2389. * Returns:
  2390. * Adapter state per PDQ Port Specification
  2391. *
  2392. * Arguments:
  2393. * bp - pointer to board information
  2394. *
  2395. * Functional Description:
  2396. * Reads PDQ Port Status register and returns adapter state.
  2397. *
  2398. * Return Codes:
  2399. * None
  2400. *
  2401. * Assumptions:
  2402. * None
  2403. *
  2404. * Side Effects:
  2405. * None
  2406. */
  2407. static int dfx_hw_adap_state_rd(DFX_board_t *bp)
  2408. {
  2409. PI_UINT32 port_status; /* Port Status register value */
  2410. dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
  2411. return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE);
  2412. }
  2413. /*
  2414. * =====================
  2415. * = dfx_hw_dma_uninit =
  2416. * =====================
  2417. *
  2418. * Overview:
  2419. * Brings adapter to DMA_UNAVAILABLE state
  2420. *
  2421. * Returns:
  2422. * Condition code
  2423. *
  2424. * Arguments:
  2425. * bp - pointer to board information
  2426. * type - type of reset to perform
  2427. *
  2428. * Functional Description:
  2429. * Bring adapter to DMA_UNAVAILABLE state by performing the following:
  2430. * 1. Set reset type bit in Port Data A Register then reset adapter.
  2431. * 2. Check that adapter is in DMA_UNAVAILABLE state.
  2432. *
  2433. * Return Codes:
  2434. * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
  2435. * DFX_K_HW_TIMEOUT - adapter did not reset properly
  2436. *
  2437. * Assumptions:
  2438. * None
  2439. *
  2440. * Side Effects:
  2441. * Internal adapter registers are cleared.
  2442. */
  2443. static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type)
  2444. {
  2445. int timeout_cnt; /* used in for loops */
  2446. /* Set reset type bit and reset adapter */
  2447. dfx_hw_adap_reset(bp, type);
  2448. /* Now wait for adapter to enter DMA_UNAVAILABLE state */
  2449. for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--)
  2450. {
  2451. if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL)
  2452. break;
  2453. udelay(100); /* wait for 100 microseconds */
  2454. }
  2455. if (timeout_cnt == 0)
  2456. return(DFX_K_HW_TIMEOUT);
  2457. return(DFX_K_SUCCESS);
  2458. }
  2459. /*
  2460. * Align an sk_buff to a boundary power of 2
  2461. *
  2462. */
  2463. static void my_skb_align(struct sk_buff *skb, int n)
  2464. {
  2465. unsigned long x = (unsigned long)skb->data;
  2466. unsigned long v;
  2467. v = ALIGN(x, n); /* Where we want to be */
  2468. skb_reserve(skb, v - x);
  2469. }
  2470. /*
  2471. * ================
  2472. * = dfx_rcv_init =
  2473. * ================
  2474. *
  2475. * Overview:
  2476. * Produces buffers to adapter LLC Host receive descriptor block
  2477. *
  2478. * Returns:
  2479. * None
  2480. *
  2481. * Arguments:
  2482. * bp - pointer to board information
  2483. * get_buffers - non-zero if buffers to be allocated
  2484. *
  2485. * Functional Description:
  2486. * This routine can be called during dfx_adap_init() or during an adapter
  2487. * reset. It initializes the descriptor block and produces all allocated
  2488. * LLC Host queue receive buffers.
  2489. *
  2490. * Return Codes:
  2491. * Return 0 on success or -ENOMEM if buffer allocation failed (when using
  2492. * dynamic buffer allocation). If the buffer allocation failed, the
  2493. * already allocated buffers will not be released and the caller should do
  2494. * this.
  2495. *
  2496. * Assumptions:
  2497. * The PDQ has been reset and the adapter and driver maintained Type 2
  2498. * register indices are cleared.
  2499. *
  2500. * Side Effects:
  2501. * Receive buffers are posted to the adapter LLC queue and the adapter
  2502. * is notified.
  2503. */
  2504. static int dfx_rcv_init(DFX_board_t *bp, int get_buffers)
  2505. {
  2506. int i, j; /* used in for loop */
  2507. /*
  2508. * Since each receive buffer is a single fragment of same length, initialize
  2509. * first longword in each receive descriptor for entire LLC Host descriptor
  2510. * block. Also initialize second longword in each receive descriptor with
  2511. * physical address of receive buffer. We'll always allocate receive
  2512. * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
  2513. * block and produce new receive buffers by simply updating the receive
  2514. * producer index.
  2515. *
  2516. * Assumptions:
  2517. * To support all shipping versions of PDQ, the receive buffer size
  2518. * must be mod 128 in length and the physical address must be 128 byte
  2519. * aligned. In other words, bits 0-6 of the length and address must
  2520. * be zero for the following descriptor field entries to be correct on
  2521. * all PDQ-based boards. We guaranteed both requirements during
  2522. * driver initialization when we allocated memory for the receive buffers.
  2523. */
  2524. if (get_buffers) {
  2525. #ifdef DYNAMIC_BUFFERS
  2526. for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
  2527. for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
  2528. {
  2529. struct sk_buff *newskb = __dev_alloc_skb(NEW_SKB_SIZE, GFP_NOIO);
  2530. if (!newskb)
  2531. return -ENOMEM;
  2532. bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
  2533. ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
  2534. /*
  2535. * align to 128 bytes for compatibility with
  2536. * the old EISA boards.
  2537. */
  2538. my_skb_align(newskb, 128);
  2539. bp->descr_block_virt->rcv_data[i + j].long_1 =
  2540. (u32)dma_map_single(bp->bus_dev, newskb->data,
  2541. NEW_SKB_SIZE,
  2542. DMA_FROM_DEVICE);
  2543. /*
  2544. * p_rcv_buff_va is only used inside the
  2545. * kernel so we put the skb pointer here.
  2546. */
  2547. bp->p_rcv_buff_va[i+j] = (char *) newskb;
  2548. }
  2549. #else
  2550. for (i=0; i < (int)(bp->rcv_bufs_to_post); i++)
  2551. for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
  2552. {
  2553. bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
  2554. ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
  2555. bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
  2556. bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX));
  2557. }
  2558. #endif
  2559. }
  2560. /* Update receive producer and Type 2 register */
  2561. bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post;
  2562. dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
  2563. return 0;
  2564. }
  2565. /*
  2566. * =========================
  2567. * = dfx_rcv_queue_process =
  2568. * =========================
  2569. *
  2570. * Overview:
  2571. * Process received LLC frames.
  2572. *
  2573. * Returns:
  2574. * None
  2575. *
  2576. * Arguments:
  2577. * bp - pointer to board information
  2578. *
  2579. * Functional Description:
  2580. * Received LLC frames are processed until there are no more consumed frames.
  2581. * Once all frames are processed, the receive buffers are returned to the
  2582. * adapter. Note that this algorithm fixes the length of time that can be spent
  2583. * in this routine, because there are a fixed number of receive buffers to
  2584. * process and buffers are not produced until this routine exits and returns
  2585. * to the ISR.
  2586. *
  2587. * Return Codes:
  2588. * None
  2589. *
  2590. * Assumptions:
  2591. * None
  2592. *
  2593. * Side Effects:
  2594. * None
  2595. */
  2596. static void dfx_rcv_queue_process(
  2597. DFX_board_t *bp
  2598. )
  2599. {
  2600. PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
  2601. char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */
  2602. u32 descr, pkt_len; /* FMC descriptor field and packet length */
  2603. struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */
  2604. /* Service all consumed LLC receive frames */
  2605. p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
  2606. while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons)
  2607. {
  2608. /* Process any errors */
  2609. int entry;
  2610. entry = bp->rcv_xmt_reg.index.rcv_comp;
  2611. #ifdef DYNAMIC_BUFFERS
  2612. p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data);
  2613. #else
  2614. p_buff = (char *) bp->p_rcv_buff_va[entry];
  2615. #endif
  2616. memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32));
  2617. if (descr & PI_FMC_DESCR_M_RCC_FLUSH)
  2618. {
  2619. if (descr & PI_FMC_DESCR_M_RCC_CRC)
  2620. bp->rcv_crc_errors++;
  2621. else
  2622. bp->rcv_frame_status_errors++;
  2623. }
  2624. else
  2625. {
  2626. int rx_in_place = 0;
  2627. /* The frame was received without errors - verify packet length */
  2628. pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN);
  2629. pkt_len -= 4; /* subtract 4 byte CRC */
  2630. if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
  2631. bp->rcv_length_errors++;
  2632. else{
  2633. #ifdef DYNAMIC_BUFFERS
  2634. if (pkt_len > SKBUFF_RX_COPYBREAK) {
  2635. struct sk_buff *newskb;
  2636. newskb = dev_alloc_skb(NEW_SKB_SIZE);
  2637. if (newskb){
  2638. rx_in_place = 1;
  2639. my_skb_align(newskb, 128);
  2640. skb = (struct sk_buff *)bp->p_rcv_buff_va[entry];
  2641. dma_unmap_single(bp->bus_dev,
  2642. bp->descr_block_virt->rcv_data[entry].long_1,
  2643. NEW_SKB_SIZE,
  2644. DMA_FROM_DEVICE);
  2645. skb_reserve(skb, RCV_BUFF_K_PADDING);
  2646. bp->p_rcv_buff_va[entry] = (char *)newskb;
  2647. bp->descr_block_virt->rcv_data[entry].long_1 =
  2648. (u32)dma_map_single(bp->bus_dev,
  2649. newskb->data,
  2650. NEW_SKB_SIZE,
  2651. DMA_FROM_DEVICE);
  2652. } else
  2653. skb = NULL;
  2654. } else
  2655. #endif
  2656. skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */
  2657. if (skb == NULL)
  2658. {
  2659. printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name);
  2660. bp->rcv_discards++;
  2661. break;
  2662. }
  2663. else {
  2664. #ifndef DYNAMIC_BUFFERS
  2665. if (! rx_in_place)
  2666. #endif
  2667. {
  2668. /* Receive buffer allocated, pass receive packet up */
  2669. memcpy(skb->data, p_buff + RCV_BUFF_K_PADDING, pkt_len+3);
  2670. }
  2671. skb_reserve(skb,3); /* adjust data field so that it points to FC byte */
  2672. skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */
  2673. skb->dev = bp->dev; /* pass up device pointer */
  2674. skb->protocol = fddi_type_trans(skb, bp->dev);
  2675. bp->rcv_total_bytes += skb->len;
  2676. netif_rx(skb);
  2677. /* Update the rcv counters */
  2678. bp->dev->last_rx = jiffies;
  2679. bp->rcv_total_frames++;
  2680. if (*(p_buff + RCV_BUFF_K_DA) & 0x01)
  2681. bp->rcv_multicast_frames++;
  2682. }
  2683. }
  2684. }
  2685. /*
  2686. * Advance the producer (for recycling) and advance the completion
  2687. * (for servicing received frames). Note that it is okay to
  2688. * advance the producer without checking that it passes the
  2689. * completion index because they are both advanced at the same
  2690. * rate.
  2691. */
  2692. bp->rcv_xmt_reg.index.rcv_prod += 1;
  2693. bp->rcv_xmt_reg.index.rcv_comp += 1;
  2694. }
  2695. }
  2696. /*
  2697. * =====================
  2698. * = dfx_xmt_queue_pkt =
  2699. * =====================
  2700. *
  2701. * Overview:
  2702. * Queues packets for transmission
  2703. *
  2704. * Returns:
  2705. * Condition code
  2706. *
  2707. * Arguments:
  2708. * skb - pointer to sk_buff to queue for transmission
  2709. * dev - pointer to device information
  2710. *
  2711. * Functional Description:
  2712. * Here we assume that an incoming skb transmit request
  2713. * is contained in a single physically contiguous buffer
  2714. * in which the virtual address of the start of packet
  2715. * (skb->data) can be converted to a physical address
  2716. * by using pci_map_single().
  2717. *
  2718. * Since the adapter architecture requires a three byte
  2719. * packet request header to prepend the start of packet,
  2720. * we'll write the three byte field immediately prior to
  2721. * the FC byte. This assumption is valid because we've
  2722. * ensured that dev->hard_header_len includes three pad
  2723. * bytes. By posting a single fragment to the adapter,
  2724. * we'll reduce the number of descriptor fetches and
  2725. * bus traffic needed to send the request.
  2726. *
  2727. * Also, we can't free the skb until after it's been DMA'd
  2728. * out by the adapter, so we'll queue it in the driver and
  2729. * return it in dfx_xmt_done.
  2730. *
  2731. * Return Codes:
  2732. * 0 - driver queued packet, link is unavailable, or skbuff was bad
  2733. * 1 - caller should requeue the sk_buff for later transmission
  2734. *
  2735. * Assumptions:
  2736. * First and foremost, we assume the incoming skb pointer
  2737. * is NOT NULL and is pointing to a valid sk_buff structure.
  2738. *
  2739. * The outgoing packet is complete, starting with the
  2740. * frame control byte including the last byte of data,
  2741. * but NOT including the 4 byte CRC. We'll let the
  2742. * adapter hardware generate and append the CRC.
  2743. *
  2744. * The entire packet is stored in one physically
  2745. * contiguous buffer which is not cached and whose
  2746. * 32-bit physical address can be determined.
  2747. *
  2748. * It's vital that this routine is NOT reentered for the
  2749. * same board and that the OS is not in another section of
  2750. * code (eg. dfx_int_common) for the same board on a
  2751. * different thread.
  2752. *
  2753. * Side Effects:
  2754. * None
  2755. */
  2756. static int dfx_xmt_queue_pkt(
  2757. struct sk_buff *skb,
  2758. struct net_device *dev
  2759. )
  2760. {
  2761. DFX_board_t *bp = netdev_priv(dev);
  2762. u8 prod; /* local transmit producer index */
  2763. PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */
  2764. XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
  2765. unsigned long flags;
  2766. netif_stop_queue(dev);
  2767. /*
  2768. * Verify that incoming transmit request is OK
  2769. *
  2770. * Note: The packet size check is consistent with other
  2771. * Linux device drivers, although the correct packet
  2772. * size should be verified before calling the
  2773. * transmit routine.
  2774. */
  2775. if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
  2776. {
  2777. printk("%s: Invalid packet length - %u bytes\n",
  2778. dev->name, skb->len);
  2779. bp->xmt_length_errors++; /* bump error counter */
  2780. netif_wake_queue(dev);
  2781. dev_kfree_skb(skb);
  2782. return(0); /* return "success" */
  2783. }
  2784. /*
  2785. * See if adapter link is available, if not, free buffer
  2786. *
  2787. * Note: If the link isn't available, free buffer and return 0
  2788. * rather than tell the upper layer to requeue the packet.
  2789. * The methodology here is that by the time the link
  2790. * becomes available, the packet to be sent will be
  2791. * fairly stale. By simply dropping the packet, the
  2792. * higher layer protocols will eventually time out
  2793. * waiting for response packets which it won't receive.
  2794. */
  2795. if (bp->link_available == PI_K_FALSE)
  2796. {
  2797. if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */
  2798. bp->link_available = PI_K_TRUE; /* if so, set flag and continue */
  2799. else
  2800. {
  2801. bp->xmt_discards++; /* bump error counter */
  2802. dev_kfree_skb(skb); /* free sk_buff now */
  2803. netif_wake_queue(dev);
  2804. return(0); /* return "success" */
  2805. }
  2806. }
  2807. spin_lock_irqsave(&bp->lock, flags);
  2808. /* Get the current producer and the next free xmt data descriptor */
  2809. prod = bp->rcv_xmt_reg.index.xmt_prod;
  2810. p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]);
  2811. /*
  2812. * Get pointer to auxiliary queue entry to contain information
  2813. * for this packet.
  2814. *
  2815. * Note: The current xmt producer index will become the
  2816. * current xmt completion index when we complete this
  2817. * packet later on. So, we'll get the pointer to the
  2818. * next auxiliary queue entry now before we bump the
  2819. * producer index.
  2820. */
  2821. p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */
  2822. /* Write the three PRH bytes immediately before the FC byte */
  2823. skb_push(skb,3);
  2824. skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */
  2825. skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */
  2826. skb->data[2] = DFX_PRH2_BYTE; /* specification */
  2827. /*
  2828. * Write the descriptor with buffer info and bump producer
  2829. *
  2830. * Note: Since we need to start DMA from the packet request
  2831. * header, we'll add 3 bytes to the DMA buffer length,
  2832. * and we'll determine the physical address of the
  2833. * buffer from the PRH, not skb->data.
  2834. *
  2835. * Assumptions:
  2836. * 1. Packet starts with the frame control (FC) byte
  2837. * at skb->data.
  2838. * 2. The 4-byte CRC is not appended to the buffer or
  2839. * included in the length.
  2840. * 3. Packet length (skb->len) is from FC to end of
  2841. * data, inclusive.
  2842. * 4. The packet length does not exceed the maximum
  2843. * FDDI LLC frame length of 4491 bytes.
  2844. * 5. The entire packet is contained in a physically
  2845. * contiguous, non-cached, locked memory space
  2846. * comprised of a single buffer pointed to by
  2847. * skb->data.
  2848. * 6. The physical address of the start of packet
  2849. * can be determined from the virtual address
  2850. * by using pci_map_single() and is only 32-bits
  2851. * wide.
  2852. */
  2853. p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
  2854. p_xmt_descr->long_1 = (u32)dma_map_single(bp->bus_dev, skb->data,
  2855. skb->len, DMA_TO_DEVICE);
  2856. /*
  2857. * Verify that descriptor is actually available
  2858. *
  2859. * Note: If descriptor isn't available, return 1 which tells
  2860. * the upper layer to requeue the packet for later
  2861. * transmission.
  2862. *
  2863. * We need to ensure that the producer never reaches the
  2864. * completion, except to indicate that the queue is empty.
  2865. */
  2866. if (prod == bp->rcv_xmt_reg.index.xmt_comp)
  2867. {
  2868. skb_pull(skb,3);
  2869. spin_unlock_irqrestore(&bp->lock, flags);
  2870. return(1); /* requeue packet for later */
  2871. }
  2872. /*
  2873. * Save info for this packet for xmt done indication routine
  2874. *
  2875. * Normally, we'd save the producer index in the p_xmt_drv_descr
  2876. * structure so that we'd have it handy when we complete this
  2877. * packet later (in dfx_xmt_done). However, since the current
  2878. * transmit architecture guarantees a single fragment for the
  2879. * entire packet, we can simply bump the completion index by
  2880. * one (1) for each completed packet.
  2881. *
  2882. * Note: If this assumption changes and we're presented with
  2883. * an inconsistent number of transmit fragments for packet
  2884. * data, we'll need to modify this code to save the current
  2885. * transmit producer index.
  2886. */
  2887. p_xmt_drv_descr->p_skb = skb;
  2888. /* Update Type 2 register */
  2889. bp->rcv_xmt_reg.index.xmt_prod = prod;
  2890. dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
  2891. spin_unlock_irqrestore(&bp->lock, flags);
  2892. netif_wake_queue(dev);
  2893. return(0); /* packet queued to adapter */
  2894. }
  2895. /*
  2896. * ================
  2897. * = dfx_xmt_done =
  2898. * ================
  2899. *
  2900. * Overview:
  2901. * Processes all frames that have been transmitted.
  2902. *
  2903. * Returns:
  2904. * None
  2905. *
  2906. * Arguments:
  2907. * bp - pointer to board information
  2908. *
  2909. * Functional Description:
  2910. * For all consumed transmit descriptors that have not
  2911. * yet been completed, we'll free the skb we were holding
  2912. * onto using dev_kfree_skb and bump the appropriate
  2913. * counters.
  2914. *
  2915. * Return Codes:
  2916. * None
  2917. *
  2918. * Assumptions:
  2919. * The Type 2 register is not updated in this routine. It is
  2920. * assumed that it will be updated in the ISR when dfx_xmt_done
  2921. * returns.
  2922. *
  2923. * Side Effects:
  2924. * None
  2925. */
  2926. static int dfx_xmt_done(DFX_board_t *bp)
  2927. {
  2928. XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
  2929. PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
  2930. u8 comp; /* local transmit completion index */
  2931. int freed = 0; /* buffers freed */
  2932. /* Service all consumed transmit frames */
  2933. p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
  2934. while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons)
  2935. {
  2936. /* Get pointer to the transmit driver descriptor block information */
  2937. p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
  2938. /* Increment transmit counters */
  2939. bp->xmt_total_frames++;
  2940. bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len;
  2941. /* Return skb to operating system */
  2942. comp = bp->rcv_xmt_reg.index.xmt_comp;
  2943. dma_unmap_single(bp->bus_dev,
  2944. bp->descr_block_virt->xmt_data[comp].long_1,
  2945. p_xmt_drv_descr->p_skb->len,
  2946. DMA_TO_DEVICE);
  2947. dev_kfree_skb_irq(p_xmt_drv_descr->p_skb);
  2948. /*
  2949. * Move to start of next packet by updating completion index
  2950. *
  2951. * Here we assume that a transmit packet request is always
  2952. * serviced by posting one fragment. We can therefore
  2953. * simplify the completion code by incrementing the
  2954. * completion index by one. This code will need to be
  2955. * modified if this assumption changes. See comments
  2956. * in dfx_xmt_queue_pkt for more details.
  2957. */
  2958. bp->rcv_xmt_reg.index.xmt_comp += 1;
  2959. freed++;
  2960. }
  2961. return freed;
  2962. }
  2963. /*
  2964. * =================
  2965. * = dfx_rcv_flush =
  2966. * =================
  2967. *
  2968. * Overview:
  2969. * Remove all skb's in the receive ring.
  2970. *
  2971. * Returns:
  2972. * None
  2973. *
  2974. * Arguments:
  2975. * bp - pointer to board information
  2976. *
  2977. * Functional Description:
  2978. * Free's all the dynamically allocated skb's that are
  2979. * currently attached to the device receive ring. This
  2980. * function is typically only used when the device is
  2981. * initialized or reinitialized.
  2982. *
  2983. * Return Codes:
  2984. * None
  2985. *
  2986. * Side Effects:
  2987. * None
  2988. */
  2989. #ifdef DYNAMIC_BUFFERS
  2990. static void dfx_rcv_flush( DFX_board_t *bp )
  2991. {
  2992. int i, j;
  2993. for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
  2994. for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
  2995. {
  2996. struct sk_buff *skb;
  2997. skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j];
  2998. if (skb)
  2999. dev_kfree_skb(skb);
  3000. bp->p_rcv_buff_va[i+j] = NULL;
  3001. }
  3002. }
  3003. #else
  3004. static inline void dfx_rcv_flush( DFX_board_t *bp )
  3005. {
  3006. }
  3007. #endif /* DYNAMIC_BUFFERS */
  3008. /*
  3009. * =================
  3010. * = dfx_xmt_flush =
  3011. * =================
  3012. *
  3013. * Overview:
  3014. * Processes all frames whether they've been transmitted
  3015. * or not.
  3016. *
  3017. * Returns:
  3018. * None
  3019. *
  3020. * Arguments:
  3021. * bp - pointer to board information
  3022. *
  3023. * Functional Description:
  3024. * For all produced transmit descriptors that have not
  3025. * yet been completed, we'll free the skb we were holding
  3026. * onto using dev_kfree_skb and bump the appropriate
  3027. * counters. Of course, it's possible that some of
  3028. * these transmit requests actually did go out, but we
  3029. * won't make that distinction here. Finally, we'll
  3030. * update the consumer index to match the producer.
  3031. *
  3032. * Return Codes:
  3033. * None
  3034. *
  3035. * Assumptions:
  3036. * This routine does NOT update the Type 2 register. It
  3037. * is assumed that this routine is being called during a
  3038. * transmit flush interrupt, or a shutdown or close routine.
  3039. *
  3040. * Side Effects:
  3041. * None
  3042. */
  3043. static void dfx_xmt_flush( DFX_board_t *bp )
  3044. {
  3045. u32 prod_cons; /* rcv/xmt consumer block longword */
  3046. XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
  3047. u8 comp; /* local transmit completion index */
  3048. /* Flush all outstanding transmit frames */
  3049. while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod)
  3050. {
  3051. /* Get pointer to the transmit driver descriptor block information */
  3052. p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
  3053. /* Return skb to operating system */
  3054. comp = bp->rcv_xmt_reg.index.xmt_comp;
  3055. dma_unmap_single(bp->bus_dev,
  3056. bp->descr_block_virt->xmt_data[comp].long_1,
  3057. p_xmt_drv_descr->p_skb->len,
  3058. DMA_TO_DEVICE);
  3059. dev_kfree_skb(p_xmt_drv_descr->p_skb);
  3060. /* Increment transmit error counter */
  3061. bp->xmt_discards++;
  3062. /*
  3063. * Move to start of next packet by updating completion index
  3064. *
  3065. * Here we assume that a transmit packet request is always
  3066. * serviced by posting one fragment. We can therefore
  3067. * simplify the completion code by incrementing the
  3068. * completion index by one. This code will need to be
  3069. * modified if this assumption changes. See comments
  3070. * in dfx_xmt_queue_pkt for more details.
  3071. */
  3072. bp->rcv_xmt_reg.index.xmt_comp += 1;
  3073. }
  3074. /* Update the transmit consumer index in the consumer block */
  3075. prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX);
  3076. prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX);
  3077. bp->cons_block_virt->xmt_rcv_data = prod_cons;
  3078. }
  3079. /*
  3080. * ==================
  3081. * = dfx_unregister =
  3082. * ==================
  3083. *
  3084. * Overview:
  3085. * Shuts down an FDDI controller
  3086. *
  3087. * Returns:
  3088. * Condition code
  3089. *
  3090. * Arguments:
  3091. * bdev - pointer to device information
  3092. *
  3093. * Functional Description:
  3094. *
  3095. * Return Codes:
  3096. * None
  3097. *
  3098. * Assumptions:
  3099. * It compiles so it should work :-( (PCI cards do :-)
  3100. *
  3101. * Side Effects:
  3102. * Device structures for FDDI adapters (fddi0, fddi1, etc) are
  3103. * freed.
  3104. */
  3105. static void __devexit dfx_unregister(struct device *bdev)
  3106. {
  3107. struct net_device *dev = dev_get_drvdata(bdev);
  3108. DFX_board_t *bp = netdev_priv(dev);
  3109. int dfx_bus_pci = DFX_BUS_PCI(bdev);
  3110. int dfx_bus_tc = DFX_BUS_TC(bdev);
  3111. int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
  3112. resource_size_t bar_start = 0; /* pointer to port */
  3113. resource_size_t bar_len = 0; /* resource length */
  3114. int alloc_size; /* total buffer size used */
  3115. unregister_netdev(dev);
  3116. alloc_size = sizeof(PI_DESCR_BLOCK) +
  3117. PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
  3118. #ifndef DYNAMIC_BUFFERS
  3119. (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
  3120. #endif
  3121. sizeof(PI_CONSUMER_BLOCK) +
  3122. (PI_ALIGN_K_DESC_BLK - 1);
  3123. if (bp->kmalloced)
  3124. dma_free_coherent(bdev, alloc_size,
  3125. bp->kmalloced, bp->kmalloced_dma);
  3126. dfx_bus_uninit(dev);
  3127. dfx_get_bars(bdev, &bar_start, &bar_len);
  3128. if (dfx_use_mmio) {
  3129. iounmap(bp->base.mem);
  3130. release_mem_region(bar_start, bar_len);
  3131. } else
  3132. release_region(bar_start, bar_len);
  3133. if (dfx_bus_pci)
  3134. pci_disable_device(to_pci_dev(bdev));
  3135. free_netdev(dev);
  3136. }
  3137. static int __devinit __unused dfx_dev_register(struct device *);
  3138. static int __devexit __unused dfx_dev_unregister(struct device *);
  3139. #ifdef CONFIG_PCI
  3140. static int __devinit dfx_pci_register(struct pci_dev *,
  3141. const struct pci_device_id *);
  3142. static void __devexit dfx_pci_unregister(struct pci_dev *);
  3143. static struct pci_device_id dfx_pci_table[] = {
  3144. { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI) },
  3145. { }
  3146. };
  3147. MODULE_DEVICE_TABLE(pci, dfx_pci_table);
  3148. static struct pci_driver dfx_pci_driver = {
  3149. .name = "defxx",
  3150. .id_table = dfx_pci_table,
  3151. .probe = dfx_pci_register,
  3152. .remove = __devexit_p(dfx_pci_unregister),
  3153. };
  3154. static __devinit int dfx_pci_register(struct pci_dev *pdev,
  3155. const struct pci_device_id *ent)
  3156. {
  3157. return dfx_register(&pdev->dev);
  3158. }
  3159. static void __devexit dfx_pci_unregister(struct pci_dev *pdev)
  3160. {
  3161. dfx_unregister(&pdev->dev);
  3162. }
  3163. #endif /* CONFIG_PCI */
  3164. #ifdef CONFIG_EISA
  3165. static struct eisa_device_id dfx_eisa_table[] = {
  3166. { "DEC3001", DEFEA_PROD_ID_1 },
  3167. { "DEC3002", DEFEA_PROD_ID_2 },
  3168. { "DEC3003", DEFEA_PROD_ID_3 },
  3169. { "DEC3004", DEFEA_PROD_ID_4 },
  3170. { }
  3171. };
  3172. MODULE_DEVICE_TABLE(eisa, dfx_eisa_table);
  3173. static struct eisa_driver dfx_eisa_driver = {
  3174. .id_table = dfx_eisa_table,
  3175. .driver = {
  3176. .name = "defxx",
  3177. .bus = &eisa_bus_type,
  3178. .probe = dfx_dev_register,
  3179. .remove = __devexit_p(dfx_dev_unregister),
  3180. },
  3181. };
  3182. #endif /* CONFIG_EISA */
  3183. #ifdef CONFIG_TC
  3184. static struct tc_device_id const dfx_tc_table[] = {
  3185. { "DEC ", "PMAF-FA " },
  3186. { "DEC ", "PMAF-FD " },
  3187. { "DEC ", "PMAF-FS " },
  3188. { "DEC ", "PMAF-FU " },
  3189. { }
  3190. };
  3191. MODULE_DEVICE_TABLE(tc, dfx_tc_table);
  3192. static struct tc_driver dfx_tc_driver = {
  3193. .id_table = dfx_tc_table,
  3194. .driver = {
  3195. .name = "defxx",
  3196. .bus = &tc_bus_type,
  3197. .probe = dfx_dev_register,
  3198. .remove = __devexit_p(dfx_dev_unregister),
  3199. },
  3200. };
  3201. #endif /* CONFIG_TC */
  3202. static int __devinit __unused dfx_dev_register(struct device *dev)
  3203. {
  3204. int status;
  3205. status = dfx_register(dev);
  3206. if (!status)
  3207. get_device(dev);
  3208. return status;
  3209. }
  3210. static int __devexit __unused dfx_dev_unregister(struct device *dev)
  3211. {
  3212. put_device(dev);
  3213. dfx_unregister(dev);
  3214. return 0;
  3215. }
  3216. static int __devinit dfx_init(void)
  3217. {
  3218. int status;
  3219. status = pci_register_driver(&dfx_pci_driver);
  3220. if (!status)
  3221. status = eisa_driver_register(&dfx_eisa_driver);
  3222. if (!status)
  3223. status = tc_register_driver(&dfx_tc_driver);
  3224. return status;
  3225. }
  3226. static void __devexit dfx_cleanup(void)
  3227. {
  3228. tc_unregister_driver(&dfx_tc_driver);
  3229. eisa_driver_unregister(&dfx_eisa_driver);
  3230. pci_unregister_driver(&dfx_pci_driver);
  3231. }
  3232. module_init(dfx_init);
  3233. module_exit(dfx_cleanup);
  3234. MODULE_AUTHOR("Lawrence V. Stefani");
  3235. MODULE_DESCRIPTION("DEC FDDIcontroller TC/EISA/PCI (DEFTA/DEFEA/DEFPA) driver "
  3236. DRV_VERSION " " DRV_RELDATE);
  3237. MODULE_LICENSE("GPL");
  3238. /*
  3239. * Local variables:
  3240. * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"
  3241. * End:
  3242. */