de620.h 4.9 KB

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  1. /*********************************************************
  2. * *
  3. * Definition of D-Link DE-620 Ethernet Pocket adapter *
  4. * *
  5. *********************************************************/
  6. /* DE-620's CMD port Command */
  7. #define CS0 0x08 /* 1->0 command strobe */
  8. #define ICEN 0x04 /* 0=enable DL3520 host interface */
  9. #define DS0 0x02 /* 1->0 data strobe 0 */
  10. #define DS1 0x01 /* 1->0 data strobe 1 */
  11. #define WDIR 0x20 /* general 0=read 1=write */
  12. #define RDIR 0x00 /* (not 100% confirm ) */
  13. #define PS2WDIR 0x00 /* ps/2 mode 1=read, 0=write */
  14. #define PS2RDIR 0x20
  15. #define IRQEN 0x10 /* 1 = enable printer IRQ line */
  16. #define SELECTIN 0x08 /* 1 = select printer */
  17. #define INITP 0x04 /* 0 = initial printer */
  18. #define AUTOFEED 0x02 /* 1 = printer auto form feed */
  19. #define STROBE 0x01 /* 0->1 data strobe */
  20. #define RESET 0x08
  21. #define NIS0 0x20 /* 0 = BNC, 1 = UTP */
  22. #define NCTL0 0x10
  23. /* DE-620 DIC Command */
  24. #define W_DUMMY 0x00 /* DIC reserved command */
  25. #define W_CR 0x20 /* DIC write command register */
  26. #define W_NPR 0x40 /* DIC write Next Page Register */
  27. #define W_TBR 0x60 /* DIC write Tx Byte Count 1 reg */
  28. #define W_RSA 0x80 /* DIC write Remote Start Addr 1 */
  29. /* DE-620's STAT port bits 7-4 */
  30. #define EMPTY 0x80 /* 1 = receive buffer empty */
  31. #define INTLEVEL 0x40 /* 1 = interrupt level is high */
  32. #define TXBF1 0x20 /* 1 = transmit buffer 1 is in use */
  33. #define TXBF0 0x10 /* 1 = transmit buffer 0 is in use */
  34. #define READY 0x08 /* 1 = h/w ready to accept cmd/data */
  35. /* IDC 1 Command */
  36. #define W_RSA1 0xa0 /* write remote start address 1 */
  37. #define W_RSA0 0xa1 /* write remote start address 0 */
  38. #define W_NPRF 0xa2 /* write next page register NPR15-NPR8 */
  39. #define W_DFR 0xa3 /* write delay factor register */
  40. #define W_CPR 0xa4 /* write current page register */
  41. #define W_SPR 0xa5 /* write start page register */
  42. #define W_EPR 0xa6 /* write end page register */
  43. #define W_SCR 0xa7 /* write system configuration register */
  44. #define W_TCR 0xa8 /* write Transceiver Configuration reg */
  45. #define W_EIP 0xa9 /* write EEPM Interface port */
  46. #define W_PAR0 0xaa /* write physical address register 0 */
  47. #define W_PAR1 0xab /* write physical address register 1 */
  48. #define W_PAR2 0xac /* write physical address register 2 */
  49. #define W_PAR3 0xad /* write physical address register 3 */
  50. #define W_PAR4 0xae /* write physical address register 4 */
  51. #define W_PAR5 0xaf /* write physical address register 5 */
  52. /* IDC 2 Command */
  53. #define R_STS 0xc0 /* read status register */
  54. #define R_CPR 0xc1 /* read current page register */
  55. #define R_BPR 0xc2 /* read boundary page register */
  56. #define R_TDR 0xc3 /* read time domain reflectometry reg */
  57. /* STATUS Register */
  58. #define EEDI 0x80 /* EEPM DO pin */
  59. #define TXSUC 0x40 /* tx success */
  60. #define T16 0x20 /* tx fail 16 times */
  61. #define TS1 0x40 /* 0=Tx success, 1=T16 */
  62. #define TS0 0x20 /* 0=Tx success, 1=T16 */
  63. #define RXGOOD 0x10 /* rx a good packet */
  64. #define RXCRC 0x08 /* rx a CRC error packet */
  65. #define RXSHORT 0x04 /* rx a short packet */
  66. #define COLS 0x02 /* coaxial collision status */
  67. #define LNKS 0x01 /* UTP link status */
  68. /* Command Register */
  69. #define CLEAR 0x10 /* reset part of hardware */
  70. #define NOPER 0x08 /* No Operation */
  71. #define RNOP 0x08
  72. #define RRA 0x06 /* After RR then auto-advance NPR & BPR(=NPR-1) */
  73. #define RRN 0x04 /* Normal Remote Read mode */
  74. #define RW1 0x02 /* Remote Write tx buffer 1 ( page 6 - 11 ) */
  75. #define RW0 0x00 /* Remote Write tx buffer 0 ( page 0 - 5 ) */
  76. #define TXEN 0x01 /* 0->1 tx enable */
  77. /* System Configuration Register */
  78. #define TESTON 0x80 /* test host data transfer reliability */
  79. #define SLEEP 0x40 /* sleep mode */
  80. #if 0
  81. #define FASTMODE 0x04 /* fast mode for intel 82360SL fast mode */
  82. #define BYTEMODE 0x02 /* byte mode */
  83. #else
  84. #define FASTMODE 0x20 /* fast mode for intel 82360SL fast mode */
  85. #define BYTEMODE 0x10 /* byte mode */
  86. #endif
  87. #define NIBBLEMODE 0x00 /* nibble mode */
  88. #define IRQINV 0x08 /* turn off IRQ line inverter */
  89. #define IRQNML 0x00 /* turn on IRQ line inverter */
  90. #define INTON 0x04
  91. #define AUTOFFSET 0x02 /* auto shift address to TPR+12 */
  92. #define AUTOTX 0x01 /* auto tx when leave RW mode */
  93. /* Transceiver Configuration Register */
  94. #define JABBER 0x80 /* generate jabber condition */
  95. #define TXSUCINT 0x40 /* enable tx success interrupt */
  96. #define T16INT 0x20 /* enable T16 interrupt */
  97. #define RXERRPKT 0x10 /* accept CRC error or short packet */
  98. #define EXTERNALB2 0x0C /* external loopback 2 */
  99. #define EXTERNALB1 0x08 /* external loopback 1 */
  100. #define INTERNALB 0x04 /* internal loopback */
  101. #define NMLOPERATE 0x00 /* normal operation */
  102. #define RXPBM 0x03 /* rx physical, broadcast, multicast */
  103. #define RXPB 0x02 /* rx physical, broadcast */
  104. #define RXALL 0x01 /* rx all packet */
  105. #define RXOFF 0x00 /* rx disable */