cassini.c 138 KB

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  1. /* cassini.c: Sun Microsystems Cassini(+) ethernet driver.
  2. *
  3. * Copyright (C) 2004 Sun Microsystems Inc.
  4. * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com)
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of the
  9. * License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  19. * 02111-1307, USA.
  20. *
  21. * This driver uses the sungem driver (c) David Miller
  22. * (davem@redhat.com) as its basis.
  23. *
  24. * The cassini chip has a number of features that distinguish it from
  25. * the gem chip:
  26. * 4 transmit descriptor rings that are used for either QoS (VLAN) or
  27. * load balancing (non-VLAN mode)
  28. * batching of multiple packets
  29. * multiple CPU dispatching
  30. * page-based RX descriptor engine with separate completion rings
  31. * Gigabit support (GMII and PCS interface)
  32. * MIF link up/down detection works
  33. *
  34. * RX is handled by page sized buffers that are attached as fragments to
  35. * the skb. here's what's done:
  36. * -- driver allocates pages at a time and keeps reference counts
  37. * on them.
  38. * -- the upper protocol layers assume that the header is in the skb
  39. * itself. as a result, cassini will copy a small amount (64 bytes)
  40. * to make them happy.
  41. * -- driver appends the rest of the data pages as frags to skbuffs
  42. * and increments the reference count
  43. * -- on page reclamation, the driver swaps the page with a spare page.
  44. * if that page is still in use, it frees its reference to that page,
  45. * and allocates a new page for use. otherwise, it just recycles the
  46. * the page.
  47. *
  48. * NOTE: cassini can parse the header. however, it's not worth it
  49. * as long as the network stack requires a header copy.
  50. *
  51. * TX has 4 queues. currently these queues are used in a round-robin
  52. * fashion for load balancing. They can also be used for QoS. for that
  53. * to work, however, QoS information needs to be exposed down to the driver
  54. * level so that subqueues get targetted to particular transmit rings.
  55. * alternatively, the queues can be configured via use of the all-purpose
  56. * ioctl.
  57. *
  58. * RX DATA: the rx completion ring has all the info, but the rx desc
  59. * ring has all of the data. RX can conceivably come in under multiple
  60. * interrupts, but the INT# assignment needs to be set up properly by
  61. * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do
  62. * that. also, the two descriptor rings are designed to distinguish between
  63. * encrypted and non-encrypted packets, but we use them for buffering
  64. * instead.
  65. *
  66. * by default, the selective clear mask is set up to process rx packets.
  67. */
  68. #include <linux/module.h>
  69. #include <linux/kernel.h>
  70. #include <linux/types.h>
  71. #include <linux/compiler.h>
  72. #include <linux/slab.h>
  73. #include <linux/delay.h>
  74. #include <linux/init.h>
  75. #include <linux/ioport.h>
  76. #include <linux/pci.h>
  77. #include <linux/mm.h>
  78. #include <linux/highmem.h>
  79. #include <linux/list.h>
  80. #include <linux/dma-mapping.h>
  81. #include <linux/netdevice.h>
  82. #include <linux/etherdevice.h>
  83. #include <linux/skbuff.h>
  84. #include <linux/ethtool.h>
  85. #include <linux/crc32.h>
  86. #include <linux/random.h>
  87. #include <linux/mii.h>
  88. #include <linux/ip.h>
  89. #include <linux/tcp.h>
  90. #include <linux/mutex.h>
  91. #include <net/checksum.h>
  92. #include <asm/atomic.h>
  93. #include <asm/system.h>
  94. #include <asm/io.h>
  95. #include <asm/byteorder.h>
  96. #include <asm/uaccess.h>
  97. #define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
  98. #define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ)
  99. #define CAS_NCPUS num_online_cpus()
  100. #if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL)
  101. #define USE_NAPI
  102. #define cas_skb_release(x) netif_receive_skb(x)
  103. #else
  104. #define cas_skb_release(x) netif_rx(x)
  105. #endif
  106. /* select which firmware to use */
  107. #define USE_HP_WORKAROUND
  108. #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */
  109. #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */
  110. #include "cassini.h"
  111. #define USE_TX_COMPWB /* use completion writeback registers */
  112. #define USE_CSMA_CD_PROTO /* standard CSMA/CD */
  113. #define USE_RX_BLANK /* hw interrupt mitigation */
  114. #undef USE_ENTROPY_DEV /* don't test for entropy device */
  115. /* NOTE: these aren't useable unless PCI interrupts can be assigned.
  116. * also, we need to make cp->lock finer-grained.
  117. */
  118. #undef USE_PCI_INTB
  119. #undef USE_PCI_INTC
  120. #undef USE_PCI_INTD
  121. #undef USE_QOS
  122. #undef USE_VPD_DEBUG /* debug vpd information if defined */
  123. /* rx processing options */
  124. #define USE_PAGE_ORDER /* specify to allocate large rx pages */
  125. #define RX_DONT_BATCH 0 /* if 1, don't batch flows */
  126. #define RX_COPY_ALWAYS 0 /* if 0, use frags */
  127. #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */
  128. #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */
  129. #define DRV_MODULE_NAME "cassini"
  130. #define PFX DRV_MODULE_NAME ": "
  131. #define DRV_MODULE_VERSION "1.4"
  132. #define DRV_MODULE_RELDATE "1 July 2004"
  133. #define CAS_DEF_MSG_ENABLE \
  134. (NETIF_MSG_DRV | \
  135. NETIF_MSG_PROBE | \
  136. NETIF_MSG_LINK | \
  137. NETIF_MSG_TIMER | \
  138. NETIF_MSG_IFDOWN | \
  139. NETIF_MSG_IFUP | \
  140. NETIF_MSG_RX_ERR | \
  141. NETIF_MSG_TX_ERR)
  142. /* length of time before we decide the hardware is borked,
  143. * and dev->tx_timeout() should be called to fix the problem
  144. */
  145. #define CAS_TX_TIMEOUT (HZ)
  146. #define CAS_LINK_TIMEOUT (22*HZ/10)
  147. #define CAS_LINK_FAST_TIMEOUT (1)
  148. /* timeout values for state changing. these specify the number
  149. * of 10us delays to be used before giving up.
  150. */
  151. #define STOP_TRIES_PHY 1000
  152. #define STOP_TRIES 5000
  153. /* specify a minimum frame size to deal with some fifo issues
  154. * max mtu == 2 * page size - ethernet header - 64 - swivel =
  155. * 2 * page_size - 0x50
  156. */
  157. #define CAS_MIN_FRAME 97
  158. #define CAS_1000MB_MIN_FRAME 255
  159. #define CAS_MIN_MTU 60
  160. #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000)
  161. #if 1
  162. /*
  163. * Eliminate these and use separate atomic counters for each, to
  164. * avoid a race condition.
  165. */
  166. #else
  167. #define CAS_RESET_MTU 1
  168. #define CAS_RESET_ALL 2
  169. #define CAS_RESET_SPARE 3
  170. #endif
  171. static char version[] __devinitdata =
  172. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  173. static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */
  174. static int link_mode;
  175. MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)");
  176. MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver");
  177. MODULE_LICENSE("GPL");
  178. module_param(cassini_debug, int, 0);
  179. MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value");
  180. module_param(link_mode, int, 0);
  181. MODULE_PARM_DESC(link_mode, "default link mode");
  182. /*
  183. * Work around for a PCS bug in which the link goes down due to the chip
  184. * being confused and never showing a link status of "up."
  185. */
  186. #define DEFAULT_LINKDOWN_TIMEOUT 5
  187. /*
  188. * Value in seconds, for user input.
  189. */
  190. static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT;
  191. module_param(linkdown_timeout, int, 0);
  192. MODULE_PARM_DESC(linkdown_timeout,
  193. "min reset interval in sec. for PCS linkdown issue; disabled if not positive");
  194. /*
  195. * value in 'ticks' (units used by jiffies). Set when we init the
  196. * module because 'HZ' in actually a function call on some flavors of
  197. * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ.
  198. */
  199. static int link_transition_timeout;
  200. static u16 link_modes[] __devinitdata = {
  201. BMCR_ANENABLE, /* 0 : autoneg */
  202. 0, /* 1 : 10bt half duplex */
  203. BMCR_SPEED100, /* 2 : 100bt half duplex */
  204. BMCR_FULLDPLX, /* 3 : 10bt full duplex */
  205. BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */
  206. CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */
  207. };
  208. static struct pci_device_id cas_pci_tbl[] __devinitdata = {
  209. { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI,
  210. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  211. { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN,
  212. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  213. { 0, }
  214. };
  215. MODULE_DEVICE_TABLE(pci, cas_pci_tbl);
  216. static void cas_set_link_modes(struct cas *cp);
  217. static inline void cas_lock_tx(struct cas *cp)
  218. {
  219. int i;
  220. for (i = 0; i < N_TX_RINGS; i++)
  221. spin_lock(&cp->tx_lock[i]);
  222. }
  223. static inline void cas_lock_all(struct cas *cp)
  224. {
  225. spin_lock_irq(&cp->lock);
  226. cas_lock_tx(cp);
  227. }
  228. /* WTZ: QA was finding deadlock problems with the previous
  229. * versions after long test runs with multiple cards per machine.
  230. * See if replacing cas_lock_all with safer versions helps. The
  231. * symptoms QA is reporting match those we'd expect if interrupts
  232. * aren't being properly restored, and we fixed a previous deadlock
  233. * with similar symptoms by using save/restore versions in other
  234. * places.
  235. */
  236. #define cas_lock_all_save(cp, flags) \
  237. do { \
  238. struct cas *xxxcp = (cp); \
  239. spin_lock_irqsave(&xxxcp->lock, flags); \
  240. cas_lock_tx(xxxcp); \
  241. } while (0)
  242. static inline void cas_unlock_tx(struct cas *cp)
  243. {
  244. int i;
  245. for (i = N_TX_RINGS; i > 0; i--)
  246. spin_unlock(&cp->tx_lock[i - 1]);
  247. }
  248. static inline void cas_unlock_all(struct cas *cp)
  249. {
  250. cas_unlock_tx(cp);
  251. spin_unlock_irq(&cp->lock);
  252. }
  253. #define cas_unlock_all_restore(cp, flags) \
  254. do { \
  255. struct cas *xxxcp = (cp); \
  256. cas_unlock_tx(xxxcp); \
  257. spin_unlock_irqrestore(&xxxcp->lock, flags); \
  258. } while (0)
  259. static void cas_disable_irq(struct cas *cp, const int ring)
  260. {
  261. /* Make sure we won't get any more interrupts */
  262. if (ring == 0) {
  263. writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);
  264. return;
  265. }
  266. /* disable completion interrupts and selectively mask */
  267. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  268. switch (ring) {
  269. #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
  270. #ifdef USE_PCI_INTB
  271. case 1:
  272. #endif
  273. #ifdef USE_PCI_INTC
  274. case 2:
  275. #endif
  276. #ifdef USE_PCI_INTD
  277. case 3:
  278. #endif
  279. writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,
  280. cp->regs + REG_PLUS_INTRN_MASK(ring));
  281. break;
  282. #endif
  283. default:
  284. writel(INTRN_MASK_CLEAR_ALL, cp->regs +
  285. REG_PLUS_INTRN_MASK(ring));
  286. break;
  287. }
  288. }
  289. }
  290. static inline void cas_mask_intr(struct cas *cp)
  291. {
  292. int i;
  293. for (i = 0; i < N_RX_COMP_RINGS; i++)
  294. cas_disable_irq(cp, i);
  295. }
  296. static inline void cas_buffer_init(cas_page_t *cp)
  297. {
  298. struct page *page = cp->buffer;
  299. atomic_set((atomic_t *)&page->lru.next, 1);
  300. }
  301. static inline int cas_buffer_count(cas_page_t *cp)
  302. {
  303. struct page *page = cp->buffer;
  304. return atomic_read((atomic_t *)&page->lru.next);
  305. }
  306. static inline void cas_buffer_inc(cas_page_t *cp)
  307. {
  308. struct page *page = cp->buffer;
  309. atomic_inc((atomic_t *)&page->lru.next);
  310. }
  311. static inline void cas_buffer_dec(cas_page_t *cp)
  312. {
  313. struct page *page = cp->buffer;
  314. atomic_dec((atomic_t *)&page->lru.next);
  315. }
  316. static void cas_enable_irq(struct cas *cp, const int ring)
  317. {
  318. if (ring == 0) { /* all but TX_DONE */
  319. writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);
  320. return;
  321. }
  322. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  323. switch (ring) {
  324. #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
  325. #ifdef USE_PCI_INTB
  326. case 1:
  327. #endif
  328. #ifdef USE_PCI_INTC
  329. case 2:
  330. #endif
  331. #ifdef USE_PCI_INTD
  332. case 3:
  333. #endif
  334. writel(INTRN_MASK_RX_EN, cp->regs +
  335. REG_PLUS_INTRN_MASK(ring));
  336. break;
  337. #endif
  338. default:
  339. break;
  340. }
  341. }
  342. }
  343. static inline void cas_unmask_intr(struct cas *cp)
  344. {
  345. int i;
  346. for (i = 0; i < N_RX_COMP_RINGS; i++)
  347. cas_enable_irq(cp, i);
  348. }
  349. static inline void cas_entropy_gather(struct cas *cp)
  350. {
  351. #ifdef USE_ENTROPY_DEV
  352. if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
  353. return;
  354. batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV),
  355. readl(cp->regs + REG_ENTROPY_IV),
  356. sizeof(uint64_t)*8);
  357. #endif
  358. }
  359. static inline void cas_entropy_reset(struct cas *cp)
  360. {
  361. #ifdef USE_ENTROPY_DEV
  362. if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0)
  363. return;
  364. writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,
  365. cp->regs + REG_BIM_LOCAL_DEV_EN);
  366. writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET);
  367. writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG);
  368. /* if we read back 0x0, we don't have an entropy device */
  369. if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0)
  370. cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV;
  371. #endif
  372. }
  373. /* access to the phy. the following assumes that we've initialized the MIF to
  374. * be in frame rather than bit-bang mode
  375. */
  376. static u16 cas_phy_read(struct cas *cp, int reg)
  377. {
  378. u32 cmd;
  379. int limit = STOP_TRIES_PHY;
  380. cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ;
  381. cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
  382. cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
  383. cmd |= MIF_FRAME_TURN_AROUND_MSB;
  384. writel(cmd, cp->regs + REG_MIF_FRAME);
  385. /* poll for completion */
  386. while (limit-- > 0) {
  387. udelay(10);
  388. cmd = readl(cp->regs + REG_MIF_FRAME);
  389. if (cmd & MIF_FRAME_TURN_AROUND_LSB)
  390. return (cmd & MIF_FRAME_DATA_MASK);
  391. }
  392. return 0xFFFF; /* -1 */
  393. }
  394. static int cas_phy_write(struct cas *cp, int reg, u16 val)
  395. {
  396. int limit = STOP_TRIES_PHY;
  397. u32 cmd;
  398. cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE;
  399. cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr);
  400. cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg);
  401. cmd |= MIF_FRAME_TURN_AROUND_MSB;
  402. cmd |= val & MIF_FRAME_DATA_MASK;
  403. writel(cmd, cp->regs + REG_MIF_FRAME);
  404. /* poll for completion */
  405. while (limit-- > 0) {
  406. udelay(10);
  407. cmd = readl(cp->regs + REG_MIF_FRAME);
  408. if (cmd & MIF_FRAME_TURN_AROUND_LSB)
  409. return 0;
  410. }
  411. return -1;
  412. }
  413. static void cas_phy_powerup(struct cas *cp)
  414. {
  415. u16 ctl = cas_phy_read(cp, MII_BMCR);
  416. if ((ctl & BMCR_PDOWN) == 0)
  417. return;
  418. ctl &= ~BMCR_PDOWN;
  419. cas_phy_write(cp, MII_BMCR, ctl);
  420. }
  421. static void cas_phy_powerdown(struct cas *cp)
  422. {
  423. u16 ctl = cas_phy_read(cp, MII_BMCR);
  424. if (ctl & BMCR_PDOWN)
  425. return;
  426. ctl |= BMCR_PDOWN;
  427. cas_phy_write(cp, MII_BMCR, ctl);
  428. }
  429. /* cp->lock held. note: the last put_page will free the buffer */
  430. static int cas_page_free(struct cas *cp, cas_page_t *page)
  431. {
  432. pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size,
  433. PCI_DMA_FROMDEVICE);
  434. cas_buffer_dec(page);
  435. __free_pages(page->buffer, cp->page_order);
  436. kfree(page);
  437. return 0;
  438. }
  439. #ifdef RX_COUNT_BUFFERS
  440. #define RX_USED_ADD(x, y) ((x)->used += (y))
  441. #define RX_USED_SET(x, y) ((x)->used = (y))
  442. #else
  443. #define RX_USED_ADD(x, y)
  444. #define RX_USED_SET(x, y)
  445. #endif
  446. /* local page allocation routines for the receive buffers. jumbo pages
  447. * require at least 8K contiguous and 8K aligned buffers.
  448. */
  449. static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags)
  450. {
  451. cas_page_t *page;
  452. page = kmalloc(sizeof(cas_page_t), flags);
  453. if (!page)
  454. return NULL;
  455. INIT_LIST_HEAD(&page->list);
  456. RX_USED_SET(page, 0);
  457. page->buffer = alloc_pages(flags, cp->page_order);
  458. if (!page->buffer)
  459. goto page_err;
  460. cas_buffer_init(page);
  461. page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0,
  462. cp->page_size, PCI_DMA_FROMDEVICE);
  463. return page;
  464. page_err:
  465. kfree(page);
  466. return NULL;
  467. }
  468. /* initialize spare pool of rx buffers, but allocate during the open */
  469. static void cas_spare_init(struct cas *cp)
  470. {
  471. spin_lock(&cp->rx_inuse_lock);
  472. INIT_LIST_HEAD(&cp->rx_inuse_list);
  473. spin_unlock(&cp->rx_inuse_lock);
  474. spin_lock(&cp->rx_spare_lock);
  475. INIT_LIST_HEAD(&cp->rx_spare_list);
  476. cp->rx_spares_needed = RX_SPARE_COUNT;
  477. spin_unlock(&cp->rx_spare_lock);
  478. }
  479. /* used on close. free all the spare buffers. */
  480. static void cas_spare_free(struct cas *cp)
  481. {
  482. struct list_head list, *elem, *tmp;
  483. /* free spare buffers */
  484. INIT_LIST_HEAD(&list);
  485. spin_lock(&cp->rx_spare_lock);
  486. list_splice(&cp->rx_spare_list, &list);
  487. INIT_LIST_HEAD(&cp->rx_spare_list);
  488. spin_unlock(&cp->rx_spare_lock);
  489. list_for_each_safe(elem, tmp, &list) {
  490. cas_page_free(cp, list_entry(elem, cas_page_t, list));
  491. }
  492. INIT_LIST_HEAD(&list);
  493. #if 1
  494. /*
  495. * Looks like Adrian had protected this with a different
  496. * lock than used everywhere else to manipulate this list.
  497. */
  498. spin_lock(&cp->rx_inuse_lock);
  499. list_splice(&cp->rx_inuse_list, &list);
  500. INIT_LIST_HEAD(&cp->rx_inuse_list);
  501. spin_unlock(&cp->rx_inuse_lock);
  502. #else
  503. spin_lock(&cp->rx_spare_lock);
  504. list_splice(&cp->rx_inuse_list, &list);
  505. INIT_LIST_HEAD(&cp->rx_inuse_list);
  506. spin_unlock(&cp->rx_spare_lock);
  507. #endif
  508. list_for_each_safe(elem, tmp, &list) {
  509. cas_page_free(cp, list_entry(elem, cas_page_t, list));
  510. }
  511. }
  512. /* replenish spares if needed */
  513. static void cas_spare_recover(struct cas *cp, const gfp_t flags)
  514. {
  515. struct list_head list, *elem, *tmp;
  516. int needed, i;
  517. /* check inuse list. if we don't need any more free buffers,
  518. * just free it
  519. */
  520. /* make a local copy of the list */
  521. INIT_LIST_HEAD(&list);
  522. spin_lock(&cp->rx_inuse_lock);
  523. list_splice(&cp->rx_inuse_list, &list);
  524. INIT_LIST_HEAD(&cp->rx_inuse_list);
  525. spin_unlock(&cp->rx_inuse_lock);
  526. list_for_each_safe(elem, tmp, &list) {
  527. cas_page_t *page = list_entry(elem, cas_page_t, list);
  528. if (cas_buffer_count(page) > 1)
  529. continue;
  530. list_del(elem);
  531. spin_lock(&cp->rx_spare_lock);
  532. if (cp->rx_spares_needed > 0) {
  533. list_add(elem, &cp->rx_spare_list);
  534. cp->rx_spares_needed--;
  535. spin_unlock(&cp->rx_spare_lock);
  536. } else {
  537. spin_unlock(&cp->rx_spare_lock);
  538. cas_page_free(cp, page);
  539. }
  540. }
  541. /* put any inuse buffers back on the list */
  542. if (!list_empty(&list)) {
  543. spin_lock(&cp->rx_inuse_lock);
  544. list_splice(&list, &cp->rx_inuse_list);
  545. spin_unlock(&cp->rx_inuse_lock);
  546. }
  547. spin_lock(&cp->rx_spare_lock);
  548. needed = cp->rx_spares_needed;
  549. spin_unlock(&cp->rx_spare_lock);
  550. if (!needed)
  551. return;
  552. /* we still need spares, so try to allocate some */
  553. INIT_LIST_HEAD(&list);
  554. i = 0;
  555. while (i < needed) {
  556. cas_page_t *spare = cas_page_alloc(cp, flags);
  557. if (!spare)
  558. break;
  559. list_add(&spare->list, &list);
  560. i++;
  561. }
  562. spin_lock(&cp->rx_spare_lock);
  563. list_splice(&list, &cp->rx_spare_list);
  564. cp->rx_spares_needed -= i;
  565. spin_unlock(&cp->rx_spare_lock);
  566. }
  567. /* pull a page from the list. */
  568. static cas_page_t *cas_page_dequeue(struct cas *cp)
  569. {
  570. struct list_head *entry;
  571. int recover;
  572. spin_lock(&cp->rx_spare_lock);
  573. if (list_empty(&cp->rx_spare_list)) {
  574. /* try to do a quick recovery */
  575. spin_unlock(&cp->rx_spare_lock);
  576. cas_spare_recover(cp, GFP_ATOMIC);
  577. spin_lock(&cp->rx_spare_lock);
  578. if (list_empty(&cp->rx_spare_list)) {
  579. if (netif_msg_rx_err(cp))
  580. printk(KERN_ERR "%s: no spare buffers "
  581. "available.\n", cp->dev->name);
  582. spin_unlock(&cp->rx_spare_lock);
  583. return NULL;
  584. }
  585. }
  586. entry = cp->rx_spare_list.next;
  587. list_del(entry);
  588. recover = ++cp->rx_spares_needed;
  589. spin_unlock(&cp->rx_spare_lock);
  590. /* trigger the timer to do the recovery */
  591. if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) {
  592. #if 1
  593. atomic_inc(&cp->reset_task_pending);
  594. atomic_inc(&cp->reset_task_pending_spare);
  595. schedule_work(&cp->reset_task);
  596. #else
  597. atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE);
  598. schedule_work(&cp->reset_task);
  599. #endif
  600. }
  601. return list_entry(entry, cas_page_t, list);
  602. }
  603. static void cas_mif_poll(struct cas *cp, const int enable)
  604. {
  605. u32 cfg;
  606. cfg = readl(cp->regs + REG_MIF_CFG);
  607. cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1);
  608. if (cp->phy_type & CAS_PHY_MII_MDIO1)
  609. cfg |= MIF_CFG_PHY_SELECT;
  610. /* poll and interrupt on link status change. */
  611. if (enable) {
  612. cfg |= MIF_CFG_POLL_EN;
  613. cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR);
  614. cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr);
  615. }
  616. writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,
  617. cp->regs + REG_MIF_MASK);
  618. writel(cfg, cp->regs + REG_MIF_CFG);
  619. }
  620. /* Must be invoked under cp->lock */
  621. static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep)
  622. {
  623. u16 ctl;
  624. #if 1
  625. int lcntl;
  626. int changed = 0;
  627. int oldstate = cp->lstate;
  628. int link_was_not_down = !(oldstate == link_down);
  629. #endif
  630. /* Setup link parameters */
  631. if (!ep)
  632. goto start_aneg;
  633. lcntl = cp->link_cntl;
  634. if (ep->autoneg == AUTONEG_ENABLE)
  635. cp->link_cntl = BMCR_ANENABLE;
  636. else {
  637. cp->link_cntl = 0;
  638. if (ep->speed == SPEED_100)
  639. cp->link_cntl |= BMCR_SPEED100;
  640. else if (ep->speed == SPEED_1000)
  641. cp->link_cntl |= CAS_BMCR_SPEED1000;
  642. if (ep->duplex == DUPLEX_FULL)
  643. cp->link_cntl |= BMCR_FULLDPLX;
  644. }
  645. #if 1
  646. changed = (lcntl != cp->link_cntl);
  647. #endif
  648. start_aneg:
  649. if (cp->lstate == link_up) {
  650. printk(KERN_INFO "%s: PCS link down.\n",
  651. cp->dev->name);
  652. } else {
  653. if (changed) {
  654. printk(KERN_INFO "%s: link configuration changed\n",
  655. cp->dev->name);
  656. }
  657. }
  658. cp->lstate = link_down;
  659. cp->link_transition = LINK_TRANSITION_LINK_DOWN;
  660. if (!cp->hw_running)
  661. return;
  662. #if 1
  663. /*
  664. * WTZ: If the old state was link_up, we turn off the carrier
  665. * to replicate everything we do elsewhere on a link-down
  666. * event when we were already in a link-up state..
  667. */
  668. if (oldstate == link_up)
  669. netif_carrier_off(cp->dev);
  670. if (changed && link_was_not_down) {
  671. /*
  672. * WTZ: This branch will simply schedule a full reset after
  673. * we explicitly changed link modes in an ioctl. See if this
  674. * fixes the link-problems we were having for forced mode.
  675. */
  676. atomic_inc(&cp->reset_task_pending);
  677. atomic_inc(&cp->reset_task_pending_all);
  678. schedule_work(&cp->reset_task);
  679. cp->timer_ticks = 0;
  680. mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
  681. return;
  682. }
  683. #endif
  684. if (cp->phy_type & CAS_PHY_SERDES) {
  685. u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
  686. if (cp->link_cntl & BMCR_ANENABLE) {
  687. val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
  688. cp->lstate = link_aneg;
  689. } else {
  690. if (cp->link_cntl & BMCR_FULLDPLX)
  691. val |= PCS_MII_CTRL_DUPLEX;
  692. val &= ~PCS_MII_AUTONEG_EN;
  693. cp->lstate = link_force_ok;
  694. }
  695. cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
  696. writel(val, cp->regs + REG_PCS_MII_CTRL);
  697. } else {
  698. cas_mif_poll(cp, 0);
  699. ctl = cas_phy_read(cp, MII_BMCR);
  700. ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
  701. CAS_BMCR_SPEED1000 | BMCR_ANENABLE);
  702. ctl |= cp->link_cntl;
  703. if (ctl & BMCR_ANENABLE) {
  704. ctl |= BMCR_ANRESTART;
  705. cp->lstate = link_aneg;
  706. } else {
  707. cp->lstate = link_force_ok;
  708. }
  709. cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
  710. cas_phy_write(cp, MII_BMCR, ctl);
  711. cas_mif_poll(cp, 1);
  712. }
  713. cp->timer_ticks = 0;
  714. mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
  715. }
  716. /* Must be invoked under cp->lock. */
  717. static int cas_reset_mii_phy(struct cas *cp)
  718. {
  719. int limit = STOP_TRIES_PHY;
  720. u16 val;
  721. cas_phy_write(cp, MII_BMCR, BMCR_RESET);
  722. udelay(100);
  723. while (limit--) {
  724. val = cas_phy_read(cp, MII_BMCR);
  725. if ((val & BMCR_RESET) == 0)
  726. break;
  727. udelay(10);
  728. }
  729. return (limit <= 0);
  730. }
  731. static void cas_saturn_firmware_load(struct cas *cp)
  732. {
  733. cas_saturn_patch_t *patch = cas_saturn_patch;
  734. cas_phy_powerdown(cp);
  735. /* expanded memory access mode */
  736. cas_phy_write(cp, DP83065_MII_MEM, 0x0);
  737. /* pointer configuration for new firmware */
  738. cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9);
  739. cas_phy_write(cp, DP83065_MII_REGD, 0xbd);
  740. cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa);
  741. cas_phy_write(cp, DP83065_MII_REGD, 0x82);
  742. cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb);
  743. cas_phy_write(cp, DP83065_MII_REGD, 0x0);
  744. cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc);
  745. cas_phy_write(cp, DP83065_MII_REGD, 0x39);
  746. /* download new firmware */
  747. cas_phy_write(cp, DP83065_MII_MEM, 0x1);
  748. cas_phy_write(cp, DP83065_MII_REGE, patch->addr);
  749. while (patch->addr) {
  750. cas_phy_write(cp, DP83065_MII_REGD, patch->val);
  751. patch++;
  752. }
  753. /* enable firmware */
  754. cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8);
  755. cas_phy_write(cp, DP83065_MII_REGD, 0x1);
  756. }
  757. /* phy initialization */
  758. static void cas_phy_init(struct cas *cp)
  759. {
  760. u16 val;
  761. /* if we're in MII/GMII mode, set up phy */
  762. if (CAS_PHY_MII(cp->phy_type)) {
  763. writel(PCS_DATAPATH_MODE_MII,
  764. cp->regs + REG_PCS_DATAPATH_MODE);
  765. cas_mif_poll(cp, 0);
  766. cas_reset_mii_phy(cp); /* take out of isolate mode */
  767. if (PHY_LUCENT_B0 == cp->phy_id) {
  768. /* workaround link up/down issue with lucent */
  769. cas_phy_write(cp, LUCENT_MII_REG, 0x8000);
  770. cas_phy_write(cp, MII_BMCR, 0x00f1);
  771. cas_phy_write(cp, LUCENT_MII_REG, 0x0);
  772. } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) {
  773. /* workarounds for broadcom phy */
  774. cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20);
  775. cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012);
  776. cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804);
  777. cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013);
  778. cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204);
  779. cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
  780. cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132);
  781. cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006);
  782. cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232);
  783. cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F);
  784. cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20);
  785. } else if (PHY_BROADCOM_5411 == cp->phy_id) {
  786. val = cas_phy_read(cp, BROADCOM_MII_REG4);
  787. val = cas_phy_read(cp, BROADCOM_MII_REG4);
  788. if (val & 0x0080) {
  789. /* link workaround */
  790. cas_phy_write(cp, BROADCOM_MII_REG4,
  791. val & ~0x0080);
  792. }
  793. } else if (cp->cas_flags & CAS_FLAG_SATURN) {
  794. writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?
  795. SATURN_PCFG_FSI : 0x0,
  796. cp->regs + REG_SATURN_PCFG);
  797. /* load firmware to address 10Mbps auto-negotiation
  798. * issue. NOTE: this will need to be changed if the
  799. * default firmware gets fixed.
  800. */
  801. if (PHY_NS_DP83065 == cp->phy_id) {
  802. cas_saturn_firmware_load(cp);
  803. }
  804. cas_phy_powerup(cp);
  805. }
  806. /* advertise capabilities */
  807. val = cas_phy_read(cp, MII_BMCR);
  808. val &= ~BMCR_ANENABLE;
  809. cas_phy_write(cp, MII_BMCR, val);
  810. udelay(10);
  811. cas_phy_write(cp, MII_ADVERTISE,
  812. cas_phy_read(cp, MII_ADVERTISE) |
  813. (ADVERTISE_10HALF | ADVERTISE_10FULL |
  814. ADVERTISE_100HALF | ADVERTISE_100FULL |
  815. CAS_ADVERTISE_PAUSE |
  816. CAS_ADVERTISE_ASYM_PAUSE));
  817. if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
  818. /* make sure that we don't advertise half
  819. * duplex to avoid a chip issue
  820. */
  821. val = cas_phy_read(cp, CAS_MII_1000_CTRL);
  822. val &= ~CAS_ADVERTISE_1000HALF;
  823. val |= CAS_ADVERTISE_1000FULL;
  824. cas_phy_write(cp, CAS_MII_1000_CTRL, val);
  825. }
  826. } else {
  827. /* reset pcs for serdes */
  828. u32 val;
  829. int limit;
  830. writel(PCS_DATAPATH_MODE_SERDES,
  831. cp->regs + REG_PCS_DATAPATH_MODE);
  832. /* enable serdes pins on saturn */
  833. if (cp->cas_flags & CAS_FLAG_SATURN)
  834. writel(0, cp->regs + REG_SATURN_PCFG);
  835. /* Reset PCS unit. */
  836. val = readl(cp->regs + REG_PCS_MII_CTRL);
  837. val |= PCS_MII_RESET;
  838. writel(val, cp->regs + REG_PCS_MII_CTRL);
  839. limit = STOP_TRIES;
  840. while (limit-- > 0) {
  841. udelay(10);
  842. if ((readl(cp->regs + REG_PCS_MII_CTRL) &
  843. PCS_MII_RESET) == 0)
  844. break;
  845. }
  846. if (limit <= 0)
  847. printk(KERN_WARNING "%s: PCS reset bit would not "
  848. "clear [%08x].\n", cp->dev->name,
  849. readl(cp->regs + REG_PCS_STATE_MACHINE));
  850. /* Make sure PCS is disabled while changing advertisement
  851. * configuration.
  852. */
  853. writel(0x0, cp->regs + REG_PCS_CFG);
  854. /* Advertise all capabilities except half-duplex. */
  855. val = readl(cp->regs + REG_PCS_MII_ADVERT);
  856. val &= ~PCS_MII_ADVERT_HD;
  857. val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
  858. PCS_MII_ADVERT_ASYM_PAUSE);
  859. writel(val, cp->regs + REG_PCS_MII_ADVERT);
  860. /* enable PCS */
  861. writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);
  862. /* pcs workaround: enable sync detect */
  863. writel(PCS_SERDES_CTRL_SYNCD_EN,
  864. cp->regs + REG_PCS_SERDES_CTRL);
  865. }
  866. }
  867. static int cas_pcs_link_check(struct cas *cp)
  868. {
  869. u32 stat, state_machine;
  870. int retval = 0;
  871. /* The link status bit latches on zero, so you must
  872. * read it twice in such a case to see a transition
  873. * to the link being up.
  874. */
  875. stat = readl(cp->regs + REG_PCS_MII_STATUS);
  876. if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
  877. stat = readl(cp->regs + REG_PCS_MII_STATUS);
  878. /* The remote-fault indication is only valid
  879. * when autoneg has completed.
  880. */
  881. if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
  882. PCS_MII_STATUS_REMOTE_FAULT)) ==
  883. (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) {
  884. if (netif_msg_link(cp))
  885. printk(KERN_INFO "%s: PCS RemoteFault\n",
  886. cp->dev->name);
  887. }
  888. /* work around link detection issue by querying the PCS state
  889. * machine directly.
  890. */
  891. state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE);
  892. if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) {
  893. stat &= ~PCS_MII_STATUS_LINK_STATUS;
  894. } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) {
  895. stat |= PCS_MII_STATUS_LINK_STATUS;
  896. }
  897. if (stat & PCS_MII_STATUS_LINK_STATUS) {
  898. if (cp->lstate != link_up) {
  899. if (cp->opened) {
  900. cp->lstate = link_up;
  901. cp->link_transition = LINK_TRANSITION_LINK_UP;
  902. cas_set_link_modes(cp);
  903. netif_carrier_on(cp->dev);
  904. }
  905. }
  906. } else if (cp->lstate == link_up) {
  907. cp->lstate = link_down;
  908. if (link_transition_timeout != 0 &&
  909. cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
  910. !cp->link_transition_jiffies_valid) {
  911. /*
  912. * force a reset, as a workaround for the
  913. * link-failure problem. May want to move this to a
  914. * point a bit earlier in the sequence. If we had
  915. * generated a reset a short time ago, we'll wait for
  916. * the link timer to check the status until a
  917. * timer expires (link_transistion_jiffies_valid is
  918. * true when the timer is running.) Instead of using
  919. * a system timer, we just do a check whenever the
  920. * link timer is running - this clears the flag after
  921. * a suitable delay.
  922. */
  923. retval = 1;
  924. cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
  925. cp->link_transition_jiffies = jiffies;
  926. cp->link_transition_jiffies_valid = 1;
  927. } else {
  928. cp->link_transition = LINK_TRANSITION_ON_FAILURE;
  929. }
  930. netif_carrier_off(cp->dev);
  931. if (cp->opened && netif_msg_link(cp)) {
  932. printk(KERN_INFO "%s: PCS link down.\n",
  933. cp->dev->name);
  934. }
  935. /* Cassini only: if you force a mode, there can be
  936. * sync problems on link down. to fix that, the following
  937. * things need to be checked:
  938. * 1) read serialink state register
  939. * 2) read pcs status register to verify link down.
  940. * 3) if link down and serial link == 0x03, then you need
  941. * to global reset the chip.
  942. */
  943. if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) {
  944. /* should check to see if we're in a forced mode */
  945. stat = readl(cp->regs + REG_PCS_SERDES_STATE);
  946. if (stat == 0x03)
  947. return 1;
  948. }
  949. } else if (cp->lstate == link_down) {
  950. if (link_transition_timeout != 0 &&
  951. cp->link_transition != LINK_TRANSITION_REQUESTED_RESET &&
  952. !cp->link_transition_jiffies_valid) {
  953. /* force a reset, as a workaround for the
  954. * link-failure problem. May want to move
  955. * this to a point a bit earlier in the
  956. * sequence.
  957. */
  958. retval = 1;
  959. cp->link_transition = LINK_TRANSITION_REQUESTED_RESET;
  960. cp->link_transition_jiffies = jiffies;
  961. cp->link_transition_jiffies_valid = 1;
  962. } else {
  963. cp->link_transition = LINK_TRANSITION_STILL_FAILED;
  964. }
  965. }
  966. return retval;
  967. }
  968. static int cas_pcs_interrupt(struct net_device *dev,
  969. struct cas *cp, u32 status)
  970. {
  971. u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
  972. if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
  973. return 0;
  974. return cas_pcs_link_check(cp);
  975. }
  976. static int cas_txmac_interrupt(struct net_device *dev,
  977. struct cas *cp, u32 status)
  978. {
  979. u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS);
  980. if (!txmac_stat)
  981. return 0;
  982. if (netif_msg_intr(cp))
  983. printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
  984. cp->dev->name, txmac_stat);
  985. /* Defer timer expiration is quite normal,
  986. * don't even log the event.
  987. */
  988. if ((txmac_stat & MAC_TX_DEFER_TIMER) &&
  989. !(txmac_stat & ~MAC_TX_DEFER_TIMER))
  990. return 0;
  991. spin_lock(&cp->stat_lock[0]);
  992. if (txmac_stat & MAC_TX_UNDERRUN) {
  993. printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
  994. dev->name);
  995. cp->net_stats[0].tx_fifo_errors++;
  996. }
  997. if (txmac_stat & MAC_TX_MAX_PACKET_ERR) {
  998. printk(KERN_ERR "%s: TX MAC max packet size error.\n",
  999. dev->name);
  1000. cp->net_stats[0].tx_errors++;
  1001. }
  1002. /* The rest are all cases of one of the 16-bit TX
  1003. * counters expiring.
  1004. */
  1005. if (txmac_stat & MAC_TX_COLL_NORMAL)
  1006. cp->net_stats[0].collisions += 0x10000;
  1007. if (txmac_stat & MAC_TX_COLL_EXCESS) {
  1008. cp->net_stats[0].tx_aborted_errors += 0x10000;
  1009. cp->net_stats[0].collisions += 0x10000;
  1010. }
  1011. if (txmac_stat & MAC_TX_COLL_LATE) {
  1012. cp->net_stats[0].tx_aborted_errors += 0x10000;
  1013. cp->net_stats[0].collisions += 0x10000;
  1014. }
  1015. spin_unlock(&cp->stat_lock[0]);
  1016. /* We do not keep track of MAC_TX_COLL_FIRST and
  1017. * MAC_TX_PEAK_ATTEMPTS events.
  1018. */
  1019. return 0;
  1020. }
  1021. static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware)
  1022. {
  1023. cas_hp_inst_t *inst;
  1024. u32 val;
  1025. int i;
  1026. i = 0;
  1027. while ((inst = firmware) && inst->note) {
  1028. writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);
  1029. val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
  1030. val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
  1031. writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
  1032. val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
  1033. val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
  1034. val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
  1035. val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
  1036. val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
  1037. val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
  1038. val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
  1039. writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
  1040. val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
  1041. val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
  1042. val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
  1043. val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
  1044. writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
  1045. ++firmware;
  1046. ++i;
  1047. }
  1048. }
  1049. static void cas_init_rx_dma(struct cas *cp)
  1050. {
  1051. u64 desc_dma = cp->block_dvma;
  1052. u32 val;
  1053. int i, size;
  1054. /* rx free descriptors */
  1055. val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
  1056. val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
  1057. val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
  1058. if ((N_RX_DESC_RINGS > 1) &&
  1059. (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */
  1060. val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
  1061. writel(val, cp->regs + REG_RX_CFG);
  1062. val = (unsigned long) cp->init_rxds[0] -
  1063. (unsigned long) cp->init_block;
  1064. writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
  1065. writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
  1066. writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
  1067. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  1068. /* rx desc 2 is for IPSEC packets. however,
  1069. * we don't it that for that purpose.
  1070. */
  1071. val = (unsigned long) cp->init_rxds[1] -
  1072. (unsigned long) cp->init_block;
  1073. writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
  1074. writel((desc_dma + val) & 0xffffffff, cp->regs +
  1075. REG_PLUS_RX_DB1_LOW);
  1076. writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +
  1077. REG_PLUS_RX_KICK1);
  1078. }
  1079. /* rx completion registers */
  1080. val = (unsigned long) cp->init_rxcs[0] -
  1081. (unsigned long) cp->init_block;
  1082. writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
  1083. writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
  1084. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  1085. /* rx comp 2-4 */
  1086. for (i = 1; i < MAX_RX_COMP_RINGS; i++) {
  1087. val = (unsigned long) cp->init_rxcs[i] -
  1088. (unsigned long) cp->init_block;
  1089. writel((desc_dma + val) >> 32, cp->regs +
  1090. REG_PLUS_RX_CBN_HI(i));
  1091. writel((desc_dma + val) & 0xffffffff, cp->regs +
  1092. REG_PLUS_RX_CBN_LOW(i));
  1093. }
  1094. }
  1095. /* read selective clear regs to prevent spurious interrupts
  1096. * on reset because complete == kick.
  1097. * selective clear set up to prevent interrupts on resets
  1098. */
  1099. readl(cp->regs + REG_INTR_STATUS_ALIAS);
  1100. writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);
  1101. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  1102. for (i = 1; i < N_RX_COMP_RINGS; i++)
  1103. readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i));
  1104. /* 2 is different from 3 and 4 */
  1105. if (N_RX_COMP_RINGS > 1)
  1106. writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,
  1107. cp->regs + REG_PLUS_ALIASN_CLEAR(1));
  1108. for (i = 2; i < N_RX_COMP_RINGS; i++)
  1109. writel(INTR_RX_DONE_ALT,
  1110. cp->regs + REG_PLUS_ALIASN_CLEAR(i));
  1111. }
  1112. /* set up pause thresholds */
  1113. val = CAS_BASE(RX_PAUSE_THRESH_OFF,
  1114. cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM);
  1115. val |= CAS_BASE(RX_PAUSE_THRESH_ON,
  1116. cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM);
  1117. writel(val, cp->regs + REG_RX_PAUSE_THRESH);
  1118. /* zero out dma reassembly buffers */
  1119. for (i = 0; i < 64; i++) {
  1120. writel(i, cp->regs + REG_RX_TABLE_ADDR);
  1121. writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);
  1122. writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);
  1123. writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);
  1124. }
  1125. /* make sure address register is 0 for normal operation */
  1126. writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);
  1127. writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);
  1128. /* interrupt mitigation */
  1129. #ifdef USE_RX_BLANK
  1130. val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
  1131. val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
  1132. writel(val, cp->regs + REG_RX_BLANK);
  1133. #else
  1134. writel(0x0, cp->regs + REG_RX_BLANK);
  1135. #endif
  1136. /* interrupt generation as a function of low water marks for
  1137. * free desc and completion entries. these are used to trigger
  1138. * housekeeping for rx descs. we don't use the free interrupt
  1139. * as it's not very useful
  1140. */
  1141. /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
  1142. val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
  1143. writel(val, cp->regs + REG_RX_AE_THRESH);
  1144. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  1145. val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
  1146. writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
  1147. }
  1148. /* Random early detect registers. useful for congestion avoidance.
  1149. * this should be tunable.
  1150. */
  1151. writel(0x0, cp->regs + REG_RX_RED);
  1152. /* receive page sizes. default == 2K (0x800) */
  1153. val = 0;
  1154. if (cp->page_size == 0x1000)
  1155. val = 0x1;
  1156. else if (cp->page_size == 0x2000)
  1157. val = 0x2;
  1158. else if (cp->page_size == 0x4000)
  1159. val = 0x3;
  1160. /* round mtu + offset. constrain to page size. */
  1161. size = cp->dev->mtu + 64;
  1162. if (size > cp->page_size)
  1163. size = cp->page_size;
  1164. if (size <= 0x400)
  1165. i = 0x0;
  1166. else if (size <= 0x800)
  1167. i = 0x1;
  1168. else if (size <= 0x1000)
  1169. i = 0x2;
  1170. else
  1171. i = 0x3;
  1172. cp->mtu_stride = 1 << (i + 10);
  1173. val = CAS_BASE(RX_PAGE_SIZE, val);
  1174. val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
  1175. val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
  1176. val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
  1177. writel(val, cp->regs + REG_RX_PAGE_SIZE);
  1178. /* enable the header parser if desired */
  1179. if (CAS_HP_FIRMWARE == cas_prog_null)
  1180. return;
  1181. val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
  1182. val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
  1183. val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
  1184. writel(val, cp->regs + REG_HP_CFG);
  1185. }
  1186. static inline void cas_rxc_init(struct cas_rx_comp *rxc)
  1187. {
  1188. memset(rxc, 0, sizeof(*rxc));
  1189. rxc->word4 = cpu_to_le64(RX_COMP4_ZERO);
  1190. }
  1191. /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1]
  1192. * flipping is protected by the fact that the chip will not
  1193. * hand back the same page index while it's being processed.
  1194. */
  1195. static inline cas_page_t *cas_page_spare(struct cas *cp, const int index)
  1196. {
  1197. cas_page_t *page = cp->rx_pages[1][index];
  1198. cas_page_t *new;
  1199. if (cas_buffer_count(page) == 1)
  1200. return page;
  1201. new = cas_page_dequeue(cp);
  1202. if (new) {
  1203. spin_lock(&cp->rx_inuse_lock);
  1204. list_add(&page->list, &cp->rx_inuse_list);
  1205. spin_unlock(&cp->rx_inuse_lock);
  1206. }
  1207. return new;
  1208. }
  1209. /* this needs to be changed if we actually use the ENC RX DESC ring */
  1210. static cas_page_t *cas_page_swap(struct cas *cp, const int ring,
  1211. const int index)
  1212. {
  1213. cas_page_t **page0 = cp->rx_pages[0];
  1214. cas_page_t **page1 = cp->rx_pages[1];
  1215. /* swap if buffer is in use */
  1216. if (cas_buffer_count(page0[index]) > 1) {
  1217. cas_page_t *new = cas_page_spare(cp, index);
  1218. if (new) {
  1219. page1[index] = page0[index];
  1220. page0[index] = new;
  1221. }
  1222. }
  1223. RX_USED_SET(page0[index], 0);
  1224. return page0[index];
  1225. }
  1226. static void cas_clean_rxds(struct cas *cp)
  1227. {
  1228. /* only clean ring 0 as ring 1 is used for spare buffers */
  1229. struct cas_rx_desc *rxd = cp->init_rxds[0];
  1230. int i, size;
  1231. /* release all rx flows */
  1232. for (i = 0; i < N_RX_FLOWS; i++) {
  1233. struct sk_buff *skb;
  1234. while ((skb = __skb_dequeue(&cp->rx_flows[i]))) {
  1235. cas_skb_release(skb);
  1236. }
  1237. }
  1238. /* initialize descriptors */
  1239. size = RX_DESC_RINGN_SIZE(0);
  1240. for (i = 0; i < size; i++) {
  1241. cas_page_t *page = cas_page_swap(cp, 0, i);
  1242. rxd[i].buffer = cpu_to_le64(page->dma_addr);
  1243. rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) |
  1244. CAS_BASE(RX_INDEX_RING, 0));
  1245. }
  1246. cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4;
  1247. cp->rx_last[0] = 0;
  1248. cp->cas_flags &= ~CAS_FLAG_RXD_POST(0);
  1249. }
  1250. static void cas_clean_rxcs(struct cas *cp)
  1251. {
  1252. int i, j;
  1253. /* take ownership of rx comp descriptors */
  1254. memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS);
  1255. memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS);
  1256. for (i = 0; i < N_RX_COMP_RINGS; i++) {
  1257. struct cas_rx_comp *rxc = cp->init_rxcs[i];
  1258. for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) {
  1259. cas_rxc_init(rxc + j);
  1260. }
  1261. }
  1262. }
  1263. #if 0
  1264. /* When we get a RX fifo overflow, the RX unit is probably hung
  1265. * so we do the following.
  1266. *
  1267. * If any part of the reset goes wrong, we return 1 and that causes the
  1268. * whole chip to be reset.
  1269. */
  1270. static int cas_rxmac_reset(struct cas *cp)
  1271. {
  1272. struct net_device *dev = cp->dev;
  1273. int limit;
  1274. u32 val;
  1275. /* First, reset MAC RX. */
  1276. writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
  1277. for (limit = 0; limit < STOP_TRIES; limit++) {
  1278. if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN))
  1279. break;
  1280. udelay(10);
  1281. }
  1282. if (limit == STOP_TRIES) {
  1283. printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
  1284. "chip.\n", dev->name);
  1285. return 1;
  1286. }
  1287. /* Second, disable RX DMA. */
  1288. writel(0, cp->regs + REG_RX_CFG);
  1289. for (limit = 0; limit < STOP_TRIES; limit++) {
  1290. if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN))
  1291. break;
  1292. udelay(10);
  1293. }
  1294. if (limit == STOP_TRIES) {
  1295. printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
  1296. "chip.\n", dev->name);
  1297. return 1;
  1298. }
  1299. mdelay(5);
  1300. /* Execute RX reset command. */
  1301. writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
  1302. for (limit = 0; limit < STOP_TRIES; limit++) {
  1303. if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX))
  1304. break;
  1305. udelay(10);
  1306. }
  1307. if (limit == STOP_TRIES) {
  1308. printk(KERN_ERR "%s: RX reset command will not execute, "
  1309. "resetting whole chip.\n", dev->name);
  1310. return 1;
  1311. }
  1312. /* reset driver rx state */
  1313. cas_clean_rxds(cp);
  1314. cas_clean_rxcs(cp);
  1315. /* Now, reprogram the rest of RX unit. */
  1316. cas_init_rx_dma(cp);
  1317. /* re-enable */
  1318. val = readl(cp->regs + REG_RX_CFG);
  1319. writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
  1320. writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
  1321. val = readl(cp->regs + REG_MAC_RX_CFG);
  1322. writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
  1323. return 0;
  1324. }
  1325. #endif
  1326. static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp,
  1327. u32 status)
  1328. {
  1329. u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
  1330. if (!stat)
  1331. return 0;
  1332. if (netif_msg_intr(cp))
  1333. printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n",
  1334. cp->dev->name, stat);
  1335. /* these are all rollovers */
  1336. spin_lock(&cp->stat_lock[0]);
  1337. if (stat & MAC_RX_ALIGN_ERR)
  1338. cp->net_stats[0].rx_frame_errors += 0x10000;
  1339. if (stat & MAC_RX_CRC_ERR)
  1340. cp->net_stats[0].rx_crc_errors += 0x10000;
  1341. if (stat & MAC_RX_LEN_ERR)
  1342. cp->net_stats[0].rx_length_errors += 0x10000;
  1343. if (stat & MAC_RX_OVERFLOW) {
  1344. cp->net_stats[0].rx_over_errors++;
  1345. cp->net_stats[0].rx_fifo_errors++;
  1346. }
  1347. /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR
  1348. * events.
  1349. */
  1350. spin_unlock(&cp->stat_lock[0]);
  1351. return 0;
  1352. }
  1353. static int cas_mac_interrupt(struct net_device *dev, struct cas *cp,
  1354. u32 status)
  1355. {
  1356. u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
  1357. if (!stat)
  1358. return 0;
  1359. if (netif_msg_intr(cp))
  1360. printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n",
  1361. cp->dev->name, stat);
  1362. /* This interrupt is just for pause frame and pause
  1363. * tracking. It is useful for diagnostics and debug
  1364. * but probably by default we will mask these events.
  1365. */
  1366. if (stat & MAC_CTRL_PAUSE_STATE)
  1367. cp->pause_entered++;
  1368. if (stat & MAC_CTRL_PAUSE_RECEIVED)
  1369. cp->pause_last_time_recvd = (stat >> 16);
  1370. return 0;
  1371. }
  1372. /* Must be invoked under cp->lock. */
  1373. static inline int cas_mdio_link_not_up(struct cas *cp)
  1374. {
  1375. u16 val;
  1376. switch (cp->lstate) {
  1377. case link_force_ret:
  1378. if (netif_msg_link(cp))
  1379. printk(KERN_INFO "%s: Autoneg failed again, keeping"
  1380. " forced mode\n", cp->dev->name);
  1381. cas_phy_write(cp, MII_BMCR, cp->link_fcntl);
  1382. cp->timer_ticks = 5;
  1383. cp->lstate = link_force_ok;
  1384. cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
  1385. break;
  1386. case link_aneg:
  1387. val = cas_phy_read(cp, MII_BMCR);
  1388. /* Try forced modes. we try things in the following order:
  1389. * 1000 full -> 100 full/half -> 10 half
  1390. */
  1391. val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
  1392. val |= BMCR_FULLDPLX;
  1393. val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
  1394. CAS_BMCR_SPEED1000 : BMCR_SPEED100;
  1395. cas_phy_write(cp, MII_BMCR, val);
  1396. cp->timer_ticks = 5;
  1397. cp->lstate = link_force_try;
  1398. cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
  1399. break;
  1400. case link_force_try:
  1401. /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */
  1402. val = cas_phy_read(cp, MII_BMCR);
  1403. cp->timer_ticks = 5;
  1404. if (val & CAS_BMCR_SPEED1000) { /* gigabit */
  1405. val &= ~CAS_BMCR_SPEED1000;
  1406. val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
  1407. cas_phy_write(cp, MII_BMCR, val);
  1408. break;
  1409. }
  1410. if (val & BMCR_SPEED100) {
  1411. if (val & BMCR_FULLDPLX) /* fd failed */
  1412. val &= ~BMCR_FULLDPLX;
  1413. else { /* 100Mbps failed */
  1414. val &= ~BMCR_SPEED100;
  1415. }
  1416. cas_phy_write(cp, MII_BMCR, val);
  1417. break;
  1418. }
  1419. default:
  1420. break;
  1421. }
  1422. return 0;
  1423. }
  1424. /* must be invoked with cp->lock held */
  1425. static int cas_mii_link_check(struct cas *cp, const u16 bmsr)
  1426. {
  1427. int restart;
  1428. if (bmsr & BMSR_LSTATUS) {
  1429. /* Ok, here we got a link. If we had it due to a forced
  1430. * fallback, and we were configured for autoneg, we
  1431. * retry a short autoneg pass. If you know your hub is
  1432. * broken, use ethtool ;)
  1433. */
  1434. if ((cp->lstate == link_force_try) &&
  1435. (cp->link_cntl & BMCR_ANENABLE)) {
  1436. cp->lstate = link_force_ret;
  1437. cp->link_transition = LINK_TRANSITION_LINK_CONFIG;
  1438. cas_mif_poll(cp, 0);
  1439. cp->link_fcntl = cas_phy_read(cp, MII_BMCR);
  1440. cp->timer_ticks = 5;
  1441. if (cp->opened && netif_msg_link(cp))
  1442. printk(KERN_INFO "%s: Got link after fallback, retrying"
  1443. " autoneg once...\n", cp->dev->name);
  1444. cas_phy_write(cp, MII_BMCR,
  1445. cp->link_fcntl | BMCR_ANENABLE |
  1446. BMCR_ANRESTART);
  1447. cas_mif_poll(cp, 1);
  1448. } else if (cp->lstate != link_up) {
  1449. cp->lstate = link_up;
  1450. cp->link_transition = LINK_TRANSITION_LINK_UP;
  1451. if (cp->opened) {
  1452. cas_set_link_modes(cp);
  1453. netif_carrier_on(cp->dev);
  1454. }
  1455. }
  1456. return 0;
  1457. }
  1458. /* link not up. if the link was previously up, we restart the
  1459. * whole process
  1460. */
  1461. restart = 0;
  1462. if (cp->lstate == link_up) {
  1463. cp->lstate = link_down;
  1464. cp->link_transition = LINK_TRANSITION_LINK_DOWN;
  1465. netif_carrier_off(cp->dev);
  1466. if (cp->opened && netif_msg_link(cp))
  1467. printk(KERN_INFO "%s: Link down\n",
  1468. cp->dev->name);
  1469. restart = 1;
  1470. } else if (++cp->timer_ticks > 10)
  1471. cas_mdio_link_not_up(cp);
  1472. return restart;
  1473. }
  1474. static int cas_mif_interrupt(struct net_device *dev, struct cas *cp,
  1475. u32 status)
  1476. {
  1477. u32 stat = readl(cp->regs + REG_MIF_STATUS);
  1478. u16 bmsr;
  1479. /* check for a link change */
  1480. if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
  1481. return 0;
  1482. bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
  1483. return cas_mii_link_check(cp, bmsr);
  1484. }
  1485. static int cas_pci_interrupt(struct net_device *dev, struct cas *cp,
  1486. u32 status)
  1487. {
  1488. u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
  1489. if (!stat)
  1490. return 0;
  1491. printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat,
  1492. readl(cp->regs + REG_BIM_DIAG));
  1493. /* cassini+ has this reserved */
  1494. if ((stat & PCI_ERR_BADACK) &&
  1495. ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0))
  1496. printk("<No ACK64# during ABS64 cycle> ");
  1497. if (stat & PCI_ERR_DTRTO)
  1498. printk("<Delayed transaction timeout> ");
  1499. if (stat & PCI_ERR_OTHER)
  1500. printk("<other> ");
  1501. if (stat & PCI_ERR_BIM_DMA_WRITE)
  1502. printk("<BIM DMA 0 write req> ");
  1503. if (stat & PCI_ERR_BIM_DMA_READ)
  1504. printk("<BIM DMA 0 read req> ");
  1505. printk("\n");
  1506. if (stat & PCI_ERR_OTHER) {
  1507. u16 cfg;
  1508. /* Interrogate PCI config space for the
  1509. * true cause.
  1510. */
  1511. pci_read_config_word(cp->pdev, PCI_STATUS, &cfg);
  1512. printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
  1513. dev->name, cfg);
  1514. if (cfg & PCI_STATUS_PARITY)
  1515. printk(KERN_ERR "%s: PCI parity error detected.\n",
  1516. dev->name);
  1517. if (cfg & PCI_STATUS_SIG_TARGET_ABORT)
  1518. printk(KERN_ERR "%s: PCI target abort.\n",
  1519. dev->name);
  1520. if (cfg & PCI_STATUS_REC_TARGET_ABORT)
  1521. printk(KERN_ERR "%s: PCI master acks target abort.\n",
  1522. dev->name);
  1523. if (cfg & PCI_STATUS_REC_MASTER_ABORT)
  1524. printk(KERN_ERR "%s: PCI master abort.\n", dev->name);
  1525. if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR)
  1526. printk(KERN_ERR "%s: PCI system error SERR#.\n",
  1527. dev->name);
  1528. if (cfg & PCI_STATUS_DETECTED_PARITY)
  1529. printk(KERN_ERR "%s: PCI parity error.\n",
  1530. dev->name);
  1531. /* Write the error bits back to clear them. */
  1532. cfg &= (PCI_STATUS_PARITY |
  1533. PCI_STATUS_SIG_TARGET_ABORT |
  1534. PCI_STATUS_REC_TARGET_ABORT |
  1535. PCI_STATUS_REC_MASTER_ABORT |
  1536. PCI_STATUS_SIG_SYSTEM_ERROR |
  1537. PCI_STATUS_DETECTED_PARITY);
  1538. pci_write_config_word(cp->pdev, PCI_STATUS, cfg);
  1539. }
  1540. /* For all PCI errors, we should reset the chip. */
  1541. return 1;
  1542. }
  1543. /* All non-normal interrupt conditions get serviced here.
  1544. * Returns non-zero if we should just exit the interrupt
  1545. * handler right now (ie. if we reset the card which invalidates
  1546. * all of the other original irq status bits).
  1547. */
  1548. static int cas_abnormal_irq(struct net_device *dev, struct cas *cp,
  1549. u32 status)
  1550. {
  1551. if (status & INTR_RX_TAG_ERROR) {
  1552. /* corrupt RX tag framing */
  1553. if (netif_msg_rx_err(cp))
  1554. printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
  1555. cp->dev->name);
  1556. spin_lock(&cp->stat_lock[0]);
  1557. cp->net_stats[0].rx_errors++;
  1558. spin_unlock(&cp->stat_lock[0]);
  1559. goto do_reset;
  1560. }
  1561. if (status & INTR_RX_LEN_MISMATCH) {
  1562. /* length mismatch. */
  1563. if (netif_msg_rx_err(cp))
  1564. printk(KERN_DEBUG "%s: length mismatch for rx frame\n",
  1565. cp->dev->name);
  1566. spin_lock(&cp->stat_lock[0]);
  1567. cp->net_stats[0].rx_errors++;
  1568. spin_unlock(&cp->stat_lock[0]);
  1569. goto do_reset;
  1570. }
  1571. if (status & INTR_PCS_STATUS) {
  1572. if (cas_pcs_interrupt(dev, cp, status))
  1573. goto do_reset;
  1574. }
  1575. if (status & INTR_TX_MAC_STATUS) {
  1576. if (cas_txmac_interrupt(dev, cp, status))
  1577. goto do_reset;
  1578. }
  1579. if (status & INTR_RX_MAC_STATUS) {
  1580. if (cas_rxmac_interrupt(dev, cp, status))
  1581. goto do_reset;
  1582. }
  1583. if (status & INTR_MAC_CTRL_STATUS) {
  1584. if (cas_mac_interrupt(dev, cp, status))
  1585. goto do_reset;
  1586. }
  1587. if (status & INTR_MIF_STATUS) {
  1588. if (cas_mif_interrupt(dev, cp, status))
  1589. goto do_reset;
  1590. }
  1591. if (status & INTR_PCI_ERROR_STATUS) {
  1592. if (cas_pci_interrupt(dev, cp, status))
  1593. goto do_reset;
  1594. }
  1595. return 0;
  1596. do_reset:
  1597. #if 1
  1598. atomic_inc(&cp->reset_task_pending);
  1599. atomic_inc(&cp->reset_task_pending_all);
  1600. printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n",
  1601. dev->name, status);
  1602. schedule_work(&cp->reset_task);
  1603. #else
  1604. atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
  1605. printk(KERN_ERR "reset called in cas_abnormal_irq\n");
  1606. schedule_work(&cp->reset_task);
  1607. #endif
  1608. return 1;
  1609. }
  1610. /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when
  1611. * determining whether to do a netif_stop/wakeup
  1612. */
  1613. #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1)
  1614. #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK)
  1615. static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr,
  1616. const int len)
  1617. {
  1618. unsigned long off = addr + len;
  1619. if (CAS_TABORT(cp) == 1)
  1620. return 0;
  1621. if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN)
  1622. return 0;
  1623. return TX_TARGET_ABORT_LEN;
  1624. }
  1625. static inline void cas_tx_ringN(struct cas *cp, int ring, int limit)
  1626. {
  1627. struct cas_tx_desc *txds;
  1628. struct sk_buff **skbs;
  1629. struct net_device *dev = cp->dev;
  1630. int entry, count;
  1631. spin_lock(&cp->tx_lock[ring]);
  1632. txds = cp->init_txds[ring];
  1633. skbs = cp->tx_skbs[ring];
  1634. entry = cp->tx_old[ring];
  1635. count = TX_BUFF_COUNT(ring, entry, limit);
  1636. while (entry != limit) {
  1637. struct sk_buff *skb = skbs[entry];
  1638. dma_addr_t daddr;
  1639. u32 dlen;
  1640. int frag;
  1641. if (!skb) {
  1642. /* this should never occur */
  1643. entry = TX_DESC_NEXT(ring, entry);
  1644. continue;
  1645. }
  1646. /* however, we might get only a partial skb release. */
  1647. count -= skb_shinfo(skb)->nr_frags +
  1648. + cp->tx_tiny_use[ring][entry].nbufs + 1;
  1649. if (count < 0)
  1650. break;
  1651. if (netif_msg_tx_done(cp))
  1652. printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n",
  1653. cp->dev->name, ring, entry);
  1654. skbs[entry] = NULL;
  1655. cp->tx_tiny_use[ring][entry].nbufs = 0;
  1656. for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
  1657. struct cas_tx_desc *txd = txds + entry;
  1658. daddr = le64_to_cpu(txd->buffer);
  1659. dlen = CAS_VAL(TX_DESC_BUFLEN,
  1660. le64_to_cpu(txd->control));
  1661. pci_unmap_page(cp->pdev, daddr, dlen,
  1662. PCI_DMA_TODEVICE);
  1663. entry = TX_DESC_NEXT(ring, entry);
  1664. /* tiny buffer may follow */
  1665. if (cp->tx_tiny_use[ring][entry].used) {
  1666. cp->tx_tiny_use[ring][entry].used = 0;
  1667. entry = TX_DESC_NEXT(ring, entry);
  1668. }
  1669. }
  1670. spin_lock(&cp->stat_lock[ring]);
  1671. cp->net_stats[ring].tx_packets++;
  1672. cp->net_stats[ring].tx_bytes += skb->len;
  1673. spin_unlock(&cp->stat_lock[ring]);
  1674. dev_kfree_skb_irq(skb);
  1675. }
  1676. cp->tx_old[ring] = entry;
  1677. /* this is wrong for multiple tx rings. the net device needs
  1678. * multiple queues for this to do the right thing. we wait
  1679. * for 2*packets to be available when using tiny buffers
  1680. */
  1681. if (netif_queue_stopped(dev) &&
  1682. (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)))
  1683. netif_wake_queue(dev);
  1684. spin_unlock(&cp->tx_lock[ring]);
  1685. }
  1686. static void cas_tx(struct net_device *dev, struct cas *cp,
  1687. u32 status)
  1688. {
  1689. int limit, ring;
  1690. #ifdef USE_TX_COMPWB
  1691. u64 compwb = le64_to_cpu(cp->init_block->tx_compwb);
  1692. #endif
  1693. if (netif_msg_intr(cp))
  1694. printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %llx\n",
  1695. cp->dev->name, status, (unsigned long long)compwb);
  1696. /* process all the rings */
  1697. for (ring = 0; ring < N_TX_RINGS; ring++) {
  1698. #ifdef USE_TX_COMPWB
  1699. /* use the completion writeback registers */
  1700. limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) |
  1701. CAS_VAL(TX_COMPWB_LSB, compwb);
  1702. compwb = TX_COMPWB_NEXT(compwb);
  1703. #else
  1704. limit = readl(cp->regs + REG_TX_COMPN(ring));
  1705. #endif
  1706. if (cp->tx_old[ring] != limit)
  1707. cas_tx_ringN(cp, ring, limit);
  1708. }
  1709. }
  1710. static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc,
  1711. int entry, const u64 *words,
  1712. struct sk_buff **skbref)
  1713. {
  1714. int dlen, hlen, len, i, alloclen;
  1715. int off, swivel = RX_SWIVEL_OFF_VAL;
  1716. struct cas_page *page;
  1717. struct sk_buff *skb;
  1718. void *addr, *crcaddr;
  1719. char *p;
  1720. hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]);
  1721. dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]);
  1722. len = hlen + dlen;
  1723. if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT))
  1724. alloclen = len;
  1725. else
  1726. alloclen = max(hlen, RX_COPY_MIN);
  1727. skb = dev_alloc_skb(alloclen + swivel + cp->crc_size);
  1728. if (skb == NULL)
  1729. return -1;
  1730. *skbref = skb;
  1731. skb->dev = cp->dev;
  1732. skb_reserve(skb, swivel);
  1733. p = skb->data;
  1734. addr = crcaddr = NULL;
  1735. if (hlen) { /* always copy header pages */
  1736. i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
  1737. page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
  1738. off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 +
  1739. swivel;
  1740. i = hlen;
  1741. if (!dlen) /* attach FCS */
  1742. i += cp->crc_size;
  1743. pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
  1744. PCI_DMA_FROMDEVICE);
  1745. addr = cas_page_map(page->buffer);
  1746. memcpy(p, addr + off, i);
  1747. pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
  1748. PCI_DMA_FROMDEVICE);
  1749. cas_page_unmap(addr);
  1750. RX_USED_ADD(page, 0x100);
  1751. p += hlen;
  1752. swivel = 0;
  1753. }
  1754. if (alloclen < (hlen + dlen)) {
  1755. skb_frag_t *frag = skb_shinfo(skb)->frags;
  1756. /* normal or jumbo packets. we use frags */
  1757. i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
  1758. page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
  1759. off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
  1760. hlen = min(cp->page_size - off, dlen);
  1761. if (hlen < 0) {
  1762. if (netif_msg_rx_err(cp)) {
  1763. printk(KERN_DEBUG "%s: rx page overflow: "
  1764. "%d\n", cp->dev->name, hlen);
  1765. }
  1766. dev_kfree_skb_irq(skb);
  1767. return -1;
  1768. }
  1769. i = hlen;
  1770. if (i == dlen) /* attach FCS */
  1771. i += cp->crc_size;
  1772. pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
  1773. PCI_DMA_FROMDEVICE);
  1774. /* make sure we always copy a header */
  1775. swivel = 0;
  1776. if (p == (char *) skb->data) { /* not split */
  1777. addr = cas_page_map(page->buffer);
  1778. memcpy(p, addr + off, RX_COPY_MIN);
  1779. pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
  1780. PCI_DMA_FROMDEVICE);
  1781. cas_page_unmap(addr);
  1782. off += RX_COPY_MIN;
  1783. swivel = RX_COPY_MIN;
  1784. RX_USED_ADD(page, cp->mtu_stride);
  1785. } else {
  1786. RX_USED_ADD(page, hlen);
  1787. }
  1788. skb_put(skb, alloclen);
  1789. skb_shinfo(skb)->nr_frags++;
  1790. skb->data_len += hlen - swivel;
  1791. skb->len += hlen - swivel;
  1792. get_page(page->buffer);
  1793. cas_buffer_inc(page);
  1794. frag->page = page->buffer;
  1795. frag->page_offset = off;
  1796. frag->size = hlen - swivel;
  1797. /* any more data? */
  1798. if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
  1799. hlen = dlen;
  1800. off = 0;
  1801. i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
  1802. page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
  1803. pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
  1804. hlen + cp->crc_size,
  1805. PCI_DMA_FROMDEVICE);
  1806. pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
  1807. hlen + cp->crc_size,
  1808. PCI_DMA_FROMDEVICE);
  1809. skb_shinfo(skb)->nr_frags++;
  1810. skb->data_len += hlen;
  1811. skb->len += hlen;
  1812. frag++;
  1813. get_page(page->buffer);
  1814. cas_buffer_inc(page);
  1815. frag->page = page->buffer;
  1816. frag->page_offset = 0;
  1817. frag->size = hlen;
  1818. RX_USED_ADD(page, hlen + cp->crc_size);
  1819. }
  1820. if (cp->crc_size) {
  1821. addr = cas_page_map(page->buffer);
  1822. crcaddr = addr + off + hlen;
  1823. }
  1824. } else {
  1825. /* copying packet */
  1826. if (!dlen)
  1827. goto end_copy_pkt;
  1828. i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
  1829. page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
  1830. off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel;
  1831. hlen = min(cp->page_size - off, dlen);
  1832. if (hlen < 0) {
  1833. if (netif_msg_rx_err(cp)) {
  1834. printk(KERN_DEBUG "%s: rx page overflow: "
  1835. "%d\n", cp->dev->name, hlen);
  1836. }
  1837. dev_kfree_skb_irq(skb);
  1838. return -1;
  1839. }
  1840. i = hlen;
  1841. if (i == dlen) /* attach FCS */
  1842. i += cp->crc_size;
  1843. pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i,
  1844. PCI_DMA_FROMDEVICE);
  1845. addr = cas_page_map(page->buffer);
  1846. memcpy(p, addr + off, i);
  1847. pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i,
  1848. PCI_DMA_FROMDEVICE);
  1849. cas_page_unmap(addr);
  1850. if (p == (char *) skb->data) /* not split */
  1851. RX_USED_ADD(page, cp->mtu_stride);
  1852. else
  1853. RX_USED_ADD(page, i);
  1854. /* any more data? */
  1855. if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) {
  1856. p += hlen;
  1857. i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
  1858. page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)];
  1859. pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr,
  1860. dlen + cp->crc_size,
  1861. PCI_DMA_FROMDEVICE);
  1862. addr = cas_page_map(page->buffer);
  1863. memcpy(p, addr, dlen + cp->crc_size);
  1864. pci_dma_sync_single_for_device(cp->pdev, page->dma_addr,
  1865. dlen + cp->crc_size,
  1866. PCI_DMA_FROMDEVICE);
  1867. cas_page_unmap(addr);
  1868. RX_USED_ADD(page, dlen + cp->crc_size);
  1869. }
  1870. end_copy_pkt:
  1871. if (cp->crc_size) {
  1872. addr = NULL;
  1873. crcaddr = skb->data + alloclen;
  1874. }
  1875. skb_put(skb, alloclen);
  1876. }
  1877. i = CAS_VAL(RX_COMP4_TCP_CSUM, words[3]);
  1878. if (cp->crc_size) {
  1879. /* checksum includes FCS. strip it out. */
  1880. i = csum_fold(csum_partial(crcaddr, cp->crc_size, i));
  1881. if (addr)
  1882. cas_page_unmap(addr);
  1883. }
  1884. skb->csum = ntohs(i ^ 0xffff);
  1885. skb->ip_summed = CHECKSUM_COMPLETE;
  1886. skb->protocol = eth_type_trans(skb, cp->dev);
  1887. return len;
  1888. }
  1889. /* we can handle up to 64 rx flows at a time. we do the same thing
  1890. * as nonreassm except that we batch up the buffers.
  1891. * NOTE: we currently just treat each flow as a bunch of packets that
  1892. * we pass up. a better way would be to coalesce the packets
  1893. * into a jumbo packet. to do that, we need to do the following:
  1894. * 1) the first packet will have a clean split between header and
  1895. * data. save both.
  1896. * 2) each time the next flow packet comes in, extend the
  1897. * data length and merge the checksums.
  1898. * 3) on flow release, fix up the header.
  1899. * 4) make sure the higher layer doesn't care.
  1900. * because packets get coalesced, we shouldn't run into fragment count
  1901. * issues.
  1902. */
  1903. static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words,
  1904. struct sk_buff *skb)
  1905. {
  1906. int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1);
  1907. struct sk_buff_head *flow = &cp->rx_flows[flowid];
  1908. /* this is protected at a higher layer, so no need to
  1909. * do any additional locking here. stick the buffer
  1910. * at the end.
  1911. */
  1912. __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow);
  1913. if (words[0] & RX_COMP1_RELEASE_FLOW) {
  1914. while ((skb = __skb_dequeue(flow))) {
  1915. cas_skb_release(skb);
  1916. }
  1917. }
  1918. }
  1919. /* put rx descriptor back on ring. if a buffer is in use by a higher
  1920. * layer, this will need to put in a replacement.
  1921. */
  1922. static void cas_post_page(struct cas *cp, const int ring, const int index)
  1923. {
  1924. cas_page_t *new;
  1925. int entry;
  1926. entry = cp->rx_old[ring];
  1927. new = cas_page_swap(cp, ring, index);
  1928. cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr);
  1929. cp->init_rxds[ring][entry].index =
  1930. cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) |
  1931. CAS_BASE(RX_INDEX_RING, ring));
  1932. entry = RX_DESC_ENTRY(ring, entry + 1);
  1933. cp->rx_old[ring] = entry;
  1934. if (entry % 4)
  1935. return;
  1936. if (ring == 0)
  1937. writel(entry, cp->regs + REG_RX_KICK);
  1938. else if ((N_RX_DESC_RINGS > 1) &&
  1939. (cp->cas_flags & CAS_FLAG_REG_PLUS))
  1940. writel(entry, cp->regs + REG_PLUS_RX_KICK1);
  1941. }
  1942. /* only when things are bad */
  1943. static int cas_post_rxds_ringN(struct cas *cp, int ring, int num)
  1944. {
  1945. unsigned int entry, last, count, released;
  1946. int cluster;
  1947. cas_page_t **page = cp->rx_pages[ring];
  1948. entry = cp->rx_old[ring];
  1949. if (netif_msg_intr(cp))
  1950. printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n",
  1951. cp->dev->name, ring, entry);
  1952. cluster = -1;
  1953. count = entry & 0x3;
  1954. last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4);
  1955. released = 0;
  1956. while (entry != last) {
  1957. /* make a new buffer if it's still in use */
  1958. if (cas_buffer_count(page[entry]) > 1) {
  1959. cas_page_t *new = cas_page_dequeue(cp);
  1960. if (!new) {
  1961. /* let the timer know that we need to
  1962. * do this again
  1963. */
  1964. cp->cas_flags |= CAS_FLAG_RXD_POST(ring);
  1965. if (!timer_pending(&cp->link_timer))
  1966. mod_timer(&cp->link_timer, jiffies +
  1967. CAS_LINK_FAST_TIMEOUT);
  1968. cp->rx_old[ring] = entry;
  1969. cp->rx_last[ring] = num ? num - released : 0;
  1970. return -ENOMEM;
  1971. }
  1972. spin_lock(&cp->rx_inuse_lock);
  1973. list_add(&page[entry]->list, &cp->rx_inuse_list);
  1974. spin_unlock(&cp->rx_inuse_lock);
  1975. cp->init_rxds[ring][entry].buffer =
  1976. cpu_to_le64(new->dma_addr);
  1977. page[entry] = new;
  1978. }
  1979. if (++count == 4) {
  1980. cluster = entry;
  1981. count = 0;
  1982. }
  1983. released++;
  1984. entry = RX_DESC_ENTRY(ring, entry + 1);
  1985. }
  1986. cp->rx_old[ring] = entry;
  1987. if (cluster < 0)
  1988. return 0;
  1989. if (ring == 0)
  1990. writel(cluster, cp->regs + REG_RX_KICK);
  1991. else if ((N_RX_DESC_RINGS > 1) &&
  1992. (cp->cas_flags & CAS_FLAG_REG_PLUS))
  1993. writel(cluster, cp->regs + REG_PLUS_RX_KICK1);
  1994. return 0;
  1995. }
  1996. /* process a completion ring. packets are set up in three basic ways:
  1997. * small packets: should be copied header + data in single buffer.
  1998. * large packets: header and data in a single buffer.
  1999. * split packets: header in a separate buffer from data.
  2000. * data may be in multiple pages. data may be > 256
  2001. * bytes but in a single page.
  2002. *
  2003. * NOTE: RX page posting is done in this routine as well. while there's
  2004. * the capability of using multiple RX completion rings, it isn't
  2005. * really worthwhile due to the fact that the page posting will
  2006. * force serialization on the single descriptor ring.
  2007. */
  2008. static int cas_rx_ringN(struct cas *cp, int ring, int budget)
  2009. {
  2010. struct cas_rx_comp *rxcs = cp->init_rxcs[ring];
  2011. int entry, drops;
  2012. int npackets = 0;
  2013. if (netif_msg_intr(cp))
  2014. printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n",
  2015. cp->dev->name, ring,
  2016. readl(cp->regs + REG_RX_COMP_HEAD),
  2017. cp->rx_new[ring]);
  2018. entry = cp->rx_new[ring];
  2019. drops = 0;
  2020. while (1) {
  2021. struct cas_rx_comp *rxc = rxcs + entry;
  2022. struct sk_buff *skb;
  2023. int type, len;
  2024. u64 words[4];
  2025. int i, dring;
  2026. words[0] = le64_to_cpu(rxc->word1);
  2027. words[1] = le64_to_cpu(rxc->word2);
  2028. words[2] = le64_to_cpu(rxc->word3);
  2029. words[3] = le64_to_cpu(rxc->word4);
  2030. /* don't touch if still owned by hw */
  2031. type = CAS_VAL(RX_COMP1_TYPE, words[0]);
  2032. if (type == 0)
  2033. break;
  2034. /* hw hasn't cleared the zero bit yet */
  2035. if (words[3] & RX_COMP4_ZERO) {
  2036. break;
  2037. }
  2038. /* get info on the packet */
  2039. if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) {
  2040. spin_lock(&cp->stat_lock[ring]);
  2041. cp->net_stats[ring].rx_errors++;
  2042. if (words[3] & RX_COMP4_LEN_MISMATCH)
  2043. cp->net_stats[ring].rx_length_errors++;
  2044. if (words[3] & RX_COMP4_BAD)
  2045. cp->net_stats[ring].rx_crc_errors++;
  2046. spin_unlock(&cp->stat_lock[ring]);
  2047. /* We'll just return it to Cassini. */
  2048. drop_it:
  2049. spin_lock(&cp->stat_lock[ring]);
  2050. ++cp->net_stats[ring].rx_dropped;
  2051. spin_unlock(&cp->stat_lock[ring]);
  2052. goto next;
  2053. }
  2054. len = cas_rx_process_pkt(cp, rxc, entry, words, &skb);
  2055. if (len < 0) {
  2056. ++drops;
  2057. goto drop_it;
  2058. }
  2059. /* see if it's a flow re-assembly or not. the driver
  2060. * itself handles release back up.
  2061. */
  2062. if (RX_DONT_BATCH || (type == 0x2)) {
  2063. /* non-reassm: these always get released */
  2064. cas_skb_release(skb);
  2065. } else {
  2066. cas_rx_flow_pkt(cp, words, skb);
  2067. }
  2068. spin_lock(&cp->stat_lock[ring]);
  2069. cp->net_stats[ring].rx_packets++;
  2070. cp->net_stats[ring].rx_bytes += len;
  2071. spin_unlock(&cp->stat_lock[ring]);
  2072. cp->dev->last_rx = jiffies;
  2073. next:
  2074. npackets++;
  2075. /* should it be released? */
  2076. if (words[0] & RX_COMP1_RELEASE_HDR) {
  2077. i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]);
  2078. dring = CAS_VAL(RX_INDEX_RING, i);
  2079. i = CAS_VAL(RX_INDEX_NUM, i);
  2080. cas_post_page(cp, dring, i);
  2081. }
  2082. if (words[0] & RX_COMP1_RELEASE_DATA) {
  2083. i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]);
  2084. dring = CAS_VAL(RX_INDEX_RING, i);
  2085. i = CAS_VAL(RX_INDEX_NUM, i);
  2086. cas_post_page(cp, dring, i);
  2087. }
  2088. if (words[0] & RX_COMP1_RELEASE_NEXT) {
  2089. i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]);
  2090. dring = CAS_VAL(RX_INDEX_RING, i);
  2091. i = CAS_VAL(RX_INDEX_NUM, i);
  2092. cas_post_page(cp, dring, i);
  2093. }
  2094. /* skip to the next entry */
  2095. entry = RX_COMP_ENTRY(ring, entry + 1 +
  2096. CAS_VAL(RX_COMP1_SKIP, words[0]));
  2097. #ifdef USE_NAPI
  2098. if (budget && (npackets >= budget))
  2099. break;
  2100. #endif
  2101. }
  2102. cp->rx_new[ring] = entry;
  2103. if (drops)
  2104. printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
  2105. cp->dev->name);
  2106. return npackets;
  2107. }
  2108. /* put completion entries back on the ring */
  2109. static void cas_post_rxcs_ringN(struct net_device *dev,
  2110. struct cas *cp, int ring)
  2111. {
  2112. struct cas_rx_comp *rxc = cp->init_rxcs[ring];
  2113. int last, entry;
  2114. last = cp->rx_cur[ring];
  2115. entry = cp->rx_new[ring];
  2116. if (netif_msg_intr(cp))
  2117. printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n",
  2118. dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD),
  2119. entry);
  2120. /* zero and re-mark descriptors */
  2121. while (last != entry) {
  2122. cas_rxc_init(rxc + last);
  2123. last = RX_COMP_ENTRY(ring, last + 1);
  2124. }
  2125. cp->rx_cur[ring] = last;
  2126. if (ring == 0)
  2127. writel(last, cp->regs + REG_RX_COMP_TAIL);
  2128. else if (cp->cas_flags & CAS_FLAG_REG_PLUS)
  2129. writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));
  2130. }
  2131. /* cassini can use all four PCI interrupts for the completion ring.
  2132. * rings 3 and 4 are identical
  2133. */
  2134. #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD)
  2135. static inline void cas_handle_irqN(struct net_device *dev,
  2136. struct cas *cp, const u32 status,
  2137. const int ring)
  2138. {
  2139. if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT))
  2140. cas_post_rxcs_ringN(dev, cp, ring);
  2141. }
  2142. static irqreturn_t cas_interruptN(int irq, void *dev_id)
  2143. {
  2144. struct net_device *dev = dev_id;
  2145. struct cas *cp = netdev_priv(dev);
  2146. unsigned long flags;
  2147. int ring;
  2148. u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring));
  2149. /* check for shared irq */
  2150. if (status == 0)
  2151. return IRQ_NONE;
  2152. ring = (irq == cp->pci_irq_INTC) ? 2 : 3;
  2153. spin_lock_irqsave(&cp->lock, flags);
  2154. if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
  2155. #ifdef USE_NAPI
  2156. cas_mask_intr(cp);
  2157. netif_rx_schedule(dev);
  2158. #else
  2159. cas_rx_ringN(cp, ring, 0);
  2160. #endif
  2161. status &= ~INTR_RX_DONE_ALT;
  2162. }
  2163. if (status)
  2164. cas_handle_irqN(dev, cp, status, ring);
  2165. spin_unlock_irqrestore(&cp->lock, flags);
  2166. return IRQ_HANDLED;
  2167. }
  2168. #endif
  2169. #ifdef USE_PCI_INTB
  2170. /* everything but rx packets */
  2171. static inline void cas_handle_irq1(struct cas *cp, const u32 status)
  2172. {
  2173. if (status & INTR_RX_BUF_UNAVAIL_1) {
  2174. /* Frame arrived, no free RX buffers available.
  2175. * NOTE: we can get this on a link transition. */
  2176. cas_post_rxds_ringN(cp, 1, 0);
  2177. spin_lock(&cp->stat_lock[1]);
  2178. cp->net_stats[1].rx_dropped++;
  2179. spin_unlock(&cp->stat_lock[1]);
  2180. }
  2181. if (status & INTR_RX_BUF_AE_1)
  2182. cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) -
  2183. RX_AE_FREEN_VAL(1));
  2184. if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
  2185. cas_post_rxcs_ringN(cp, 1);
  2186. }
  2187. /* ring 2 handles a few more events than 3 and 4 */
  2188. static irqreturn_t cas_interrupt1(int irq, void *dev_id)
  2189. {
  2190. struct net_device *dev = dev_id;
  2191. struct cas *cp = netdev_priv(dev);
  2192. unsigned long flags;
  2193. u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
  2194. /* check for shared interrupt */
  2195. if (status == 0)
  2196. return IRQ_NONE;
  2197. spin_lock_irqsave(&cp->lock, flags);
  2198. if (status & INTR_RX_DONE_ALT) { /* handle rx separately */
  2199. #ifdef USE_NAPI
  2200. cas_mask_intr(cp);
  2201. netif_rx_schedule(dev);
  2202. #else
  2203. cas_rx_ringN(cp, 1, 0);
  2204. #endif
  2205. status &= ~INTR_RX_DONE_ALT;
  2206. }
  2207. if (status)
  2208. cas_handle_irq1(cp, status);
  2209. spin_unlock_irqrestore(&cp->lock, flags);
  2210. return IRQ_HANDLED;
  2211. }
  2212. #endif
  2213. static inline void cas_handle_irq(struct net_device *dev,
  2214. struct cas *cp, const u32 status)
  2215. {
  2216. /* housekeeping interrupts */
  2217. if (status & INTR_ERROR_MASK)
  2218. cas_abnormal_irq(dev, cp, status);
  2219. if (status & INTR_RX_BUF_UNAVAIL) {
  2220. /* Frame arrived, no free RX buffers available.
  2221. * NOTE: we can get this on a link transition.
  2222. */
  2223. cas_post_rxds_ringN(cp, 0, 0);
  2224. spin_lock(&cp->stat_lock[0]);
  2225. cp->net_stats[0].rx_dropped++;
  2226. spin_unlock(&cp->stat_lock[0]);
  2227. } else if (status & INTR_RX_BUF_AE) {
  2228. cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) -
  2229. RX_AE_FREEN_VAL(0));
  2230. }
  2231. if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL))
  2232. cas_post_rxcs_ringN(dev, cp, 0);
  2233. }
  2234. static irqreturn_t cas_interrupt(int irq, void *dev_id)
  2235. {
  2236. struct net_device *dev = dev_id;
  2237. struct cas *cp = netdev_priv(dev);
  2238. unsigned long flags;
  2239. u32 status = readl(cp->regs + REG_INTR_STATUS);
  2240. if (status == 0)
  2241. return IRQ_NONE;
  2242. spin_lock_irqsave(&cp->lock, flags);
  2243. if (status & (INTR_TX_ALL | INTR_TX_INTME)) {
  2244. cas_tx(dev, cp, status);
  2245. status &= ~(INTR_TX_ALL | INTR_TX_INTME);
  2246. }
  2247. if (status & INTR_RX_DONE) {
  2248. #ifdef USE_NAPI
  2249. cas_mask_intr(cp);
  2250. netif_rx_schedule(dev);
  2251. #else
  2252. cas_rx_ringN(cp, 0, 0);
  2253. #endif
  2254. status &= ~INTR_RX_DONE;
  2255. }
  2256. if (status)
  2257. cas_handle_irq(dev, cp, status);
  2258. spin_unlock_irqrestore(&cp->lock, flags);
  2259. return IRQ_HANDLED;
  2260. }
  2261. #ifdef USE_NAPI
  2262. static int cas_poll(struct net_device *dev, int *budget)
  2263. {
  2264. struct cas *cp = netdev_priv(dev);
  2265. int i, enable_intr, todo, credits;
  2266. u32 status = readl(cp->regs + REG_INTR_STATUS);
  2267. unsigned long flags;
  2268. spin_lock_irqsave(&cp->lock, flags);
  2269. cas_tx(dev, cp, status);
  2270. spin_unlock_irqrestore(&cp->lock, flags);
  2271. /* NAPI rx packets. we spread the credits across all of the
  2272. * rxc rings
  2273. */
  2274. todo = min(*budget, dev->quota);
  2275. /* to make sure we're fair with the work we loop through each
  2276. * ring N_RX_COMP_RING times with a request of
  2277. * todo / N_RX_COMP_RINGS
  2278. */
  2279. enable_intr = 1;
  2280. credits = 0;
  2281. for (i = 0; i < N_RX_COMP_RINGS; i++) {
  2282. int j;
  2283. for (j = 0; j < N_RX_COMP_RINGS; j++) {
  2284. credits += cas_rx_ringN(cp, j, todo / N_RX_COMP_RINGS);
  2285. if (credits >= todo) {
  2286. enable_intr = 0;
  2287. goto rx_comp;
  2288. }
  2289. }
  2290. }
  2291. rx_comp:
  2292. *budget -= credits;
  2293. dev->quota -= credits;
  2294. /* final rx completion */
  2295. spin_lock_irqsave(&cp->lock, flags);
  2296. if (status)
  2297. cas_handle_irq(dev, cp, status);
  2298. #ifdef USE_PCI_INTB
  2299. if (N_RX_COMP_RINGS > 1) {
  2300. status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1));
  2301. if (status)
  2302. cas_handle_irq1(dev, cp, status);
  2303. }
  2304. #endif
  2305. #ifdef USE_PCI_INTC
  2306. if (N_RX_COMP_RINGS > 2) {
  2307. status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2));
  2308. if (status)
  2309. cas_handle_irqN(dev, cp, status, 2);
  2310. }
  2311. #endif
  2312. #ifdef USE_PCI_INTD
  2313. if (N_RX_COMP_RINGS > 3) {
  2314. status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3));
  2315. if (status)
  2316. cas_handle_irqN(dev, cp, status, 3);
  2317. }
  2318. #endif
  2319. spin_unlock_irqrestore(&cp->lock, flags);
  2320. if (enable_intr) {
  2321. netif_rx_complete(dev);
  2322. cas_unmask_intr(cp);
  2323. return 0;
  2324. }
  2325. return 1;
  2326. }
  2327. #endif
  2328. #ifdef CONFIG_NET_POLL_CONTROLLER
  2329. static void cas_netpoll(struct net_device *dev)
  2330. {
  2331. struct cas *cp = netdev_priv(dev);
  2332. cas_disable_irq(cp, 0);
  2333. cas_interrupt(cp->pdev->irq, dev);
  2334. cas_enable_irq(cp, 0);
  2335. #ifdef USE_PCI_INTB
  2336. if (N_RX_COMP_RINGS > 1) {
  2337. /* cas_interrupt1(); */
  2338. }
  2339. #endif
  2340. #ifdef USE_PCI_INTC
  2341. if (N_RX_COMP_RINGS > 2) {
  2342. /* cas_interruptN(); */
  2343. }
  2344. #endif
  2345. #ifdef USE_PCI_INTD
  2346. if (N_RX_COMP_RINGS > 3) {
  2347. /* cas_interruptN(); */
  2348. }
  2349. #endif
  2350. }
  2351. #endif
  2352. static void cas_tx_timeout(struct net_device *dev)
  2353. {
  2354. struct cas *cp = netdev_priv(dev);
  2355. printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
  2356. if (!cp->hw_running) {
  2357. printk("%s: hrm.. hw not running!\n", dev->name);
  2358. return;
  2359. }
  2360. printk(KERN_ERR "%s: MIF_STATE[%08x]\n",
  2361. dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE));
  2362. printk(KERN_ERR "%s: MAC_STATE[%08x]\n",
  2363. dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE));
  2364. printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] "
  2365. "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n",
  2366. dev->name,
  2367. readl(cp->regs + REG_TX_CFG),
  2368. readl(cp->regs + REG_MAC_TX_STATUS),
  2369. readl(cp->regs + REG_MAC_TX_CFG),
  2370. readl(cp->regs + REG_TX_FIFO_PKT_CNT),
  2371. readl(cp->regs + REG_TX_FIFO_WRITE_PTR),
  2372. readl(cp->regs + REG_TX_FIFO_READ_PTR),
  2373. readl(cp->regs + REG_TX_SM_1),
  2374. readl(cp->regs + REG_TX_SM_2));
  2375. printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
  2376. dev->name,
  2377. readl(cp->regs + REG_RX_CFG),
  2378. readl(cp->regs + REG_MAC_RX_STATUS),
  2379. readl(cp->regs + REG_MAC_RX_CFG));
  2380. printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n",
  2381. dev->name,
  2382. readl(cp->regs + REG_HP_STATE_MACHINE),
  2383. readl(cp->regs + REG_HP_STATUS0),
  2384. readl(cp->regs + REG_HP_STATUS1),
  2385. readl(cp->regs + REG_HP_STATUS2));
  2386. #if 1
  2387. atomic_inc(&cp->reset_task_pending);
  2388. atomic_inc(&cp->reset_task_pending_all);
  2389. schedule_work(&cp->reset_task);
  2390. #else
  2391. atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
  2392. schedule_work(&cp->reset_task);
  2393. #endif
  2394. }
  2395. static inline int cas_intme(int ring, int entry)
  2396. {
  2397. /* Algorithm: IRQ every 1/2 of descriptors. */
  2398. if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1)))
  2399. return 1;
  2400. return 0;
  2401. }
  2402. static void cas_write_txd(struct cas *cp, int ring, int entry,
  2403. dma_addr_t mapping, int len, u64 ctrl, int last)
  2404. {
  2405. struct cas_tx_desc *txd = cp->init_txds[ring] + entry;
  2406. ctrl |= CAS_BASE(TX_DESC_BUFLEN, len);
  2407. if (cas_intme(ring, entry))
  2408. ctrl |= TX_DESC_INTME;
  2409. if (last)
  2410. ctrl |= TX_DESC_EOF;
  2411. txd->control = cpu_to_le64(ctrl);
  2412. txd->buffer = cpu_to_le64(mapping);
  2413. }
  2414. static inline void *tx_tiny_buf(struct cas *cp, const int ring,
  2415. const int entry)
  2416. {
  2417. return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry;
  2418. }
  2419. static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring,
  2420. const int entry, const int tentry)
  2421. {
  2422. cp->tx_tiny_use[ring][tentry].nbufs++;
  2423. cp->tx_tiny_use[ring][entry].used = 1;
  2424. return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry;
  2425. }
  2426. static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
  2427. struct sk_buff *skb)
  2428. {
  2429. struct net_device *dev = cp->dev;
  2430. int entry, nr_frags, frag, tabort, tentry;
  2431. dma_addr_t mapping;
  2432. unsigned long flags;
  2433. u64 ctrl;
  2434. u32 len;
  2435. spin_lock_irqsave(&cp->tx_lock[ring], flags);
  2436. /* This is a hard error, log it. */
  2437. if (TX_BUFFS_AVAIL(cp, ring) <=
  2438. CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) {
  2439. netif_stop_queue(dev);
  2440. spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
  2441. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  2442. "queue awake!\n", dev->name);
  2443. return 1;
  2444. }
  2445. ctrl = 0;
  2446. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  2447. u64 csum_start_off, csum_stuff_off;
  2448. csum_start_off = (u64) (skb->h.raw - skb->data);
  2449. csum_stuff_off = csum_start_off + skb->csum_offset;
  2450. ctrl = TX_DESC_CSUM_EN |
  2451. CAS_BASE(TX_DESC_CSUM_START, csum_start_off) |
  2452. CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off);
  2453. }
  2454. entry = cp->tx_new[ring];
  2455. cp->tx_skbs[ring][entry] = skb;
  2456. nr_frags = skb_shinfo(skb)->nr_frags;
  2457. len = skb_headlen(skb);
  2458. mapping = pci_map_page(cp->pdev, virt_to_page(skb->data),
  2459. offset_in_page(skb->data), len,
  2460. PCI_DMA_TODEVICE);
  2461. tentry = entry;
  2462. tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len);
  2463. if (unlikely(tabort)) {
  2464. /* NOTE: len is always > tabort */
  2465. cas_write_txd(cp, ring, entry, mapping, len - tabort,
  2466. ctrl | TX_DESC_SOF, 0);
  2467. entry = TX_DESC_NEXT(ring, entry);
  2468. memcpy(tx_tiny_buf(cp, ring, entry), skb->data +
  2469. len - tabort, tabort);
  2470. mapping = tx_tiny_map(cp, ring, entry, tentry);
  2471. cas_write_txd(cp, ring, entry, mapping, tabort, ctrl,
  2472. (nr_frags == 0));
  2473. } else {
  2474. cas_write_txd(cp, ring, entry, mapping, len, ctrl |
  2475. TX_DESC_SOF, (nr_frags == 0));
  2476. }
  2477. entry = TX_DESC_NEXT(ring, entry);
  2478. for (frag = 0; frag < nr_frags; frag++) {
  2479. skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
  2480. len = fragp->size;
  2481. mapping = pci_map_page(cp->pdev, fragp->page,
  2482. fragp->page_offset, len,
  2483. PCI_DMA_TODEVICE);
  2484. tabort = cas_calc_tabort(cp, fragp->page_offset, len);
  2485. if (unlikely(tabort)) {
  2486. void *addr;
  2487. /* NOTE: len is always > tabort */
  2488. cas_write_txd(cp, ring, entry, mapping, len - tabort,
  2489. ctrl, 0);
  2490. entry = TX_DESC_NEXT(ring, entry);
  2491. addr = cas_page_map(fragp->page);
  2492. memcpy(tx_tiny_buf(cp, ring, entry),
  2493. addr + fragp->page_offset + len - tabort,
  2494. tabort);
  2495. cas_page_unmap(addr);
  2496. mapping = tx_tiny_map(cp, ring, entry, tentry);
  2497. len = tabort;
  2498. }
  2499. cas_write_txd(cp, ring, entry, mapping, len, ctrl,
  2500. (frag + 1 == nr_frags));
  2501. entry = TX_DESC_NEXT(ring, entry);
  2502. }
  2503. cp->tx_new[ring] = entry;
  2504. if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))
  2505. netif_stop_queue(dev);
  2506. if (netif_msg_tx_queued(cp))
  2507. printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, "
  2508. "avail %d\n",
  2509. dev->name, ring, entry, skb->len,
  2510. TX_BUFFS_AVAIL(cp, ring));
  2511. writel(entry, cp->regs + REG_TX_KICKN(ring));
  2512. spin_unlock_irqrestore(&cp->tx_lock[ring], flags);
  2513. return 0;
  2514. }
  2515. static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev)
  2516. {
  2517. struct cas *cp = netdev_priv(dev);
  2518. /* this is only used as a load-balancing hint, so it doesn't
  2519. * need to be SMP safe
  2520. */
  2521. static int ring;
  2522. if (skb_padto(skb, cp->min_frame_size))
  2523. return 0;
  2524. /* XXX: we need some higher-level QoS hooks to steer packets to
  2525. * individual queues.
  2526. */
  2527. if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb))
  2528. return 1;
  2529. dev->trans_start = jiffies;
  2530. return 0;
  2531. }
  2532. static void cas_init_tx_dma(struct cas *cp)
  2533. {
  2534. u64 desc_dma = cp->block_dvma;
  2535. unsigned long off;
  2536. u32 val;
  2537. int i;
  2538. /* set up tx completion writeback registers. must be 8-byte aligned */
  2539. #ifdef USE_TX_COMPWB
  2540. off = offsetof(struct cas_init_block, tx_compwb);
  2541. writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);
  2542. writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);
  2543. #endif
  2544. /* enable completion writebacks, enable paced mode,
  2545. * disable read pipe, and disable pre-interrupt compwbs
  2546. */
  2547. val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
  2548. TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 |
  2549. TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE |
  2550. TX_CFG_INTR_COMPWB_DIS;
  2551. /* write out tx ring info and tx desc bases */
  2552. for (i = 0; i < MAX_TX_RINGS; i++) {
  2553. off = (unsigned long) cp->init_txds[i] -
  2554. (unsigned long) cp->init_block;
  2555. val |= CAS_TX_RINGN_BASE(i);
  2556. writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));
  2557. writel((desc_dma + off) & 0xffffffff, cp->regs +
  2558. REG_TX_DBN_LOW(i));
  2559. /* don't zero out the kick register here as the system
  2560. * will wedge
  2561. */
  2562. }
  2563. writel(val, cp->regs + REG_TX_CFG);
  2564. /* program max burst sizes. these numbers should be different
  2565. * if doing QoS.
  2566. */
  2567. #ifdef USE_QOS
  2568. writel(0x800, cp->regs + REG_TX_MAXBURST_0);
  2569. writel(0x1600, cp->regs + REG_TX_MAXBURST_1);
  2570. writel(0x2400, cp->regs + REG_TX_MAXBURST_2);
  2571. writel(0x4800, cp->regs + REG_TX_MAXBURST_3);
  2572. #else
  2573. writel(0x800, cp->regs + REG_TX_MAXBURST_0);
  2574. writel(0x800, cp->regs + REG_TX_MAXBURST_1);
  2575. writel(0x800, cp->regs + REG_TX_MAXBURST_2);
  2576. writel(0x800, cp->regs + REG_TX_MAXBURST_3);
  2577. #endif
  2578. }
  2579. /* Must be invoked under cp->lock. */
  2580. static inline void cas_init_dma(struct cas *cp)
  2581. {
  2582. cas_init_tx_dma(cp);
  2583. cas_init_rx_dma(cp);
  2584. }
  2585. /* Must be invoked under cp->lock. */
  2586. static u32 cas_setup_multicast(struct cas *cp)
  2587. {
  2588. u32 rxcfg = 0;
  2589. int i;
  2590. if (cp->dev->flags & IFF_PROMISC) {
  2591. rxcfg |= MAC_RX_CFG_PROMISC_EN;
  2592. } else if (cp->dev->flags & IFF_ALLMULTI) {
  2593. for (i=0; i < 16; i++)
  2594. writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));
  2595. rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
  2596. } else {
  2597. u16 hash_table[16];
  2598. u32 crc;
  2599. struct dev_mc_list *dmi = cp->dev->mc_list;
  2600. int i;
  2601. /* use the alternate mac address registers for the
  2602. * first 15 multicast addresses
  2603. */
  2604. for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) {
  2605. if (!dmi) {
  2606. writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0));
  2607. writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1));
  2608. writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2));
  2609. continue;
  2610. }
  2611. writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5],
  2612. cp->regs + REG_MAC_ADDRN(i*3 + 0));
  2613. writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3],
  2614. cp->regs + REG_MAC_ADDRN(i*3 + 1));
  2615. writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1],
  2616. cp->regs + REG_MAC_ADDRN(i*3 + 2));
  2617. dmi = dmi->next;
  2618. }
  2619. /* use hw hash table for the next series of
  2620. * multicast addresses
  2621. */
  2622. memset(hash_table, 0, sizeof(hash_table));
  2623. while (dmi) {
  2624. crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr);
  2625. crc >>= 24;
  2626. hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
  2627. dmi = dmi->next;
  2628. }
  2629. for (i=0; i < 16; i++)
  2630. writel(hash_table[i], cp->regs +
  2631. REG_MAC_HASH_TABLEN(i));
  2632. rxcfg |= MAC_RX_CFG_HASH_FILTER_EN;
  2633. }
  2634. return rxcfg;
  2635. }
  2636. /* must be invoked under cp->stat_lock[N_TX_RINGS] */
  2637. static void cas_clear_mac_err(struct cas *cp)
  2638. {
  2639. writel(0, cp->regs + REG_MAC_COLL_NORMAL);
  2640. writel(0, cp->regs + REG_MAC_COLL_FIRST);
  2641. writel(0, cp->regs + REG_MAC_COLL_EXCESS);
  2642. writel(0, cp->regs + REG_MAC_COLL_LATE);
  2643. writel(0, cp->regs + REG_MAC_TIMER_DEFER);
  2644. writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);
  2645. writel(0, cp->regs + REG_MAC_RECV_FRAME);
  2646. writel(0, cp->regs + REG_MAC_LEN_ERR);
  2647. writel(0, cp->regs + REG_MAC_ALIGN_ERR);
  2648. writel(0, cp->regs + REG_MAC_FCS_ERR);
  2649. writel(0, cp->regs + REG_MAC_RX_CODE_ERR);
  2650. }
  2651. static void cas_mac_reset(struct cas *cp)
  2652. {
  2653. int i;
  2654. /* do both TX and RX reset */
  2655. writel(0x1, cp->regs + REG_MAC_TX_RESET);
  2656. writel(0x1, cp->regs + REG_MAC_RX_RESET);
  2657. /* wait for TX */
  2658. i = STOP_TRIES;
  2659. while (i-- > 0) {
  2660. if (readl(cp->regs + REG_MAC_TX_RESET) == 0)
  2661. break;
  2662. udelay(10);
  2663. }
  2664. /* wait for RX */
  2665. i = STOP_TRIES;
  2666. while (i-- > 0) {
  2667. if (readl(cp->regs + REG_MAC_RX_RESET) == 0)
  2668. break;
  2669. udelay(10);
  2670. }
  2671. if (readl(cp->regs + REG_MAC_TX_RESET) |
  2672. readl(cp->regs + REG_MAC_RX_RESET))
  2673. printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n",
  2674. cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET),
  2675. readl(cp->regs + REG_MAC_RX_RESET),
  2676. readl(cp->regs + REG_MAC_STATE_MACHINE));
  2677. }
  2678. /* Must be invoked under cp->lock. */
  2679. static void cas_init_mac(struct cas *cp)
  2680. {
  2681. unsigned char *e = &cp->dev->dev_addr[0];
  2682. int i;
  2683. #ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE
  2684. u32 rxcfg;
  2685. #endif
  2686. cas_mac_reset(cp);
  2687. /* setup core arbitration weight register */
  2688. writel(CAWR_RR_DIS, cp->regs + REG_CAWR);
  2689. /* XXX Use pci_dma_burst_advice() */
  2690. #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
  2691. /* set the infinite burst register for chips that don't have
  2692. * pci issues.
  2693. */
  2694. if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0)
  2695. writel(INF_BURST_EN, cp->regs + REG_INF_BURST);
  2696. #endif
  2697. writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);
  2698. writel(0x00, cp->regs + REG_MAC_IPG0);
  2699. writel(0x08, cp->regs + REG_MAC_IPG1);
  2700. writel(0x04, cp->regs + REG_MAC_IPG2);
  2701. /* change later for 802.3z */
  2702. writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
  2703. /* min frame + FCS */
  2704. writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);
  2705. /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we
  2706. * specify the maximum frame size to prevent RX tag errors on
  2707. * oversized frames.
  2708. */
  2709. writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |
  2710. CAS_BASE(MAC_FRAMESIZE_MAX_FRAME,
  2711. (CAS_MAX_MTU + ETH_HLEN + 4 + 4)),
  2712. cp->regs + REG_MAC_FRAMESIZE_MAX);
  2713. /* NOTE: crc_size is used as a surrogate for half-duplex.
  2714. * workaround saturn half-duplex issue by increasing preamble
  2715. * size to 65 bytes.
  2716. */
  2717. if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size)
  2718. writel(0x41, cp->regs + REG_MAC_PA_SIZE);
  2719. else
  2720. writel(0x07, cp->regs + REG_MAC_PA_SIZE);
  2721. writel(0x04, cp->regs + REG_MAC_JAM_SIZE);
  2722. writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);
  2723. writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);
  2724. writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);
  2725. writel(0, cp->regs + REG_MAC_ADDR_FILTER0);
  2726. writel(0, cp->regs + REG_MAC_ADDR_FILTER1);
  2727. writel(0, cp->regs + REG_MAC_ADDR_FILTER2);
  2728. writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);
  2729. writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);
  2730. /* setup mac address in perfect filter array */
  2731. for (i = 0; i < 45; i++)
  2732. writel(0x0, cp->regs + REG_MAC_ADDRN(i));
  2733. writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));
  2734. writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));
  2735. writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));
  2736. writel(0x0001, cp->regs + REG_MAC_ADDRN(42));
  2737. writel(0xc200, cp->regs + REG_MAC_ADDRN(43));
  2738. writel(0x0180, cp->regs + REG_MAC_ADDRN(44));
  2739. #ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE
  2740. cp->mac_rx_cfg = cas_setup_multicast(cp);
  2741. #else
  2742. /* WTZ: Do what Adrian did in cas_set_multicast. Doing
  2743. * a writel does not seem to be necessary because Cassini
  2744. * seems to preserve the configuration when we do the reset.
  2745. * If the chip is in trouble, though, it is not clear if we
  2746. * can really count on this behavior. cas_set_multicast uses
  2747. * spin_lock_irqsave, but we are called only in cas_init_hw and
  2748. * cas_init_hw is protected by cas_lock_all, which calls
  2749. * spin_lock_irq (so it doesn't need to save the flags, and
  2750. * we should be OK for the writel, as that is the only
  2751. * difference).
  2752. */
  2753. cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp);
  2754. writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
  2755. #endif
  2756. spin_lock(&cp->stat_lock[N_TX_RINGS]);
  2757. cas_clear_mac_err(cp);
  2758. spin_unlock(&cp->stat_lock[N_TX_RINGS]);
  2759. /* Setup MAC interrupts. We want to get all of the interesting
  2760. * counter expiration events, but we do not want to hear about
  2761. * normal rx/tx as the DMA engine tells us that.
  2762. */
  2763. writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);
  2764. writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
  2765. /* Don't enable even the PAUSE interrupts for now, we
  2766. * make no use of those events other than to record them.
  2767. */
  2768. writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);
  2769. }
  2770. /* Must be invoked under cp->lock. */
  2771. static void cas_init_pause_thresholds(struct cas *cp)
  2772. {
  2773. /* Calculate pause thresholds. Setting the OFF threshold to the
  2774. * full RX fifo size effectively disables PAUSE generation
  2775. */
  2776. if (cp->rx_fifo_size <= (2 * 1024)) {
  2777. cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size;
  2778. } else {
  2779. int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
  2780. if (max_frame * 3 > cp->rx_fifo_size) {
  2781. cp->rx_pause_off = 7104;
  2782. cp->rx_pause_on = 960;
  2783. } else {
  2784. int off = (cp->rx_fifo_size - (max_frame * 2));
  2785. int on = off - max_frame;
  2786. cp->rx_pause_off = off;
  2787. cp->rx_pause_on = on;
  2788. }
  2789. }
  2790. }
  2791. static int cas_vpd_match(const void __iomem *p, const char *str)
  2792. {
  2793. int len = strlen(str) + 1;
  2794. int i;
  2795. for (i = 0; i < len; i++) {
  2796. if (readb(p + i) != str[i])
  2797. return 0;
  2798. }
  2799. return 1;
  2800. }
  2801. /* get the mac address by reading the vpd information in the rom.
  2802. * also get the phy type and determine if there's an entropy generator.
  2803. * NOTE: this is a bit convoluted for the following reasons:
  2804. * 1) vpd info has order-dependent mac addresses for multinic cards
  2805. * 2) the only way to determine the nic order is to use the slot
  2806. * number.
  2807. * 3) fiber cards don't have bridges, so their slot numbers don't
  2808. * mean anything.
  2809. * 4) we don't actually know we have a fiber card until after
  2810. * the mac addresses are parsed.
  2811. */
  2812. static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
  2813. const int offset)
  2814. {
  2815. void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START;
  2816. void __iomem *base, *kstart;
  2817. int i, len;
  2818. int found = 0;
  2819. #define VPD_FOUND_MAC 0x01
  2820. #define VPD_FOUND_PHY 0x02
  2821. int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
  2822. int mac_off = 0;
  2823. /* give us access to the PROM */
  2824. writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
  2825. cp->regs + REG_BIM_LOCAL_DEV_EN);
  2826. /* check for an expansion rom */
  2827. if (readb(p) != 0x55 || readb(p + 1) != 0xaa)
  2828. goto use_random_mac_addr;
  2829. /* search for beginning of vpd */
  2830. base = NULL;
  2831. for (i = 2; i < EXPANSION_ROM_SIZE; i++) {
  2832. /* check for PCIR */
  2833. if ((readb(p + i + 0) == 0x50) &&
  2834. (readb(p + i + 1) == 0x43) &&
  2835. (readb(p + i + 2) == 0x49) &&
  2836. (readb(p + i + 3) == 0x52)) {
  2837. base = p + (readb(p + i + 8) |
  2838. (readb(p + i + 9) << 8));
  2839. break;
  2840. }
  2841. }
  2842. if (!base || (readb(base) != 0x82))
  2843. goto use_random_mac_addr;
  2844. i = (readb(base + 1) | (readb(base + 2) << 8)) + 3;
  2845. while (i < EXPANSION_ROM_SIZE) {
  2846. if (readb(base + i) != 0x90) /* no vpd found */
  2847. goto use_random_mac_addr;
  2848. /* found a vpd field */
  2849. len = readb(base + i + 1) | (readb(base + i + 2) << 8);
  2850. /* extract keywords */
  2851. kstart = base + i + 3;
  2852. p = kstart;
  2853. while ((p - kstart) < len) {
  2854. int klen = readb(p + 2);
  2855. int j;
  2856. char type;
  2857. p += 3;
  2858. /* look for the following things:
  2859. * -- correct length == 29
  2860. * 3 (type) + 2 (size) +
  2861. * 18 (strlen("local-mac-address") + 1) +
  2862. * 6 (mac addr)
  2863. * -- VPD Instance 'I'
  2864. * -- VPD Type Bytes 'B'
  2865. * -- VPD data length == 6
  2866. * -- property string == local-mac-address
  2867. *
  2868. * -- correct length == 24
  2869. * 3 (type) + 2 (size) +
  2870. * 12 (strlen("entropy-dev") + 1) +
  2871. * 7 (strlen("vms110") + 1)
  2872. * -- VPD Instance 'I'
  2873. * -- VPD Type String 'B'
  2874. * -- VPD data length == 7
  2875. * -- property string == entropy-dev
  2876. *
  2877. * -- correct length == 18
  2878. * 3 (type) + 2 (size) +
  2879. * 9 (strlen("phy-type") + 1) +
  2880. * 4 (strlen("pcs") + 1)
  2881. * -- VPD Instance 'I'
  2882. * -- VPD Type String 'S'
  2883. * -- VPD data length == 4
  2884. * -- property string == phy-type
  2885. *
  2886. * -- correct length == 23
  2887. * 3 (type) + 2 (size) +
  2888. * 14 (strlen("phy-interface") + 1) +
  2889. * 4 (strlen("pcs") + 1)
  2890. * -- VPD Instance 'I'
  2891. * -- VPD Type String 'S'
  2892. * -- VPD data length == 4
  2893. * -- property string == phy-interface
  2894. */
  2895. if (readb(p) != 'I')
  2896. goto next;
  2897. /* finally, check string and length */
  2898. type = readb(p + 3);
  2899. if (type == 'B') {
  2900. if ((klen == 29) && readb(p + 4) == 6 &&
  2901. cas_vpd_match(p + 5,
  2902. "local-mac-address")) {
  2903. if (mac_off++ > offset)
  2904. goto next;
  2905. /* set mac address */
  2906. for (j = 0; j < 6; j++)
  2907. dev_addr[j] =
  2908. readb(p + 23 + j);
  2909. goto found_mac;
  2910. }
  2911. }
  2912. if (type != 'S')
  2913. goto next;
  2914. #ifdef USE_ENTROPY_DEV
  2915. if ((klen == 24) &&
  2916. cas_vpd_match(p + 5, "entropy-dev") &&
  2917. cas_vpd_match(p + 17, "vms110")) {
  2918. cp->cas_flags |= CAS_FLAG_ENTROPY_DEV;
  2919. goto next;
  2920. }
  2921. #endif
  2922. if (found & VPD_FOUND_PHY)
  2923. goto next;
  2924. if ((klen == 18) && readb(p + 4) == 4 &&
  2925. cas_vpd_match(p + 5, "phy-type")) {
  2926. if (cas_vpd_match(p + 14, "pcs")) {
  2927. phy_type = CAS_PHY_SERDES;
  2928. goto found_phy;
  2929. }
  2930. }
  2931. if ((klen == 23) && readb(p + 4) == 4 &&
  2932. cas_vpd_match(p + 5, "phy-interface")) {
  2933. if (cas_vpd_match(p + 19, "pcs")) {
  2934. phy_type = CAS_PHY_SERDES;
  2935. goto found_phy;
  2936. }
  2937. }
  2938. found_mac:
  2939. found |= VPD_FOUND_MAC;
  2940. goto next;
  2941. found_phy:
  2942. found |= VPD_FOUND_PHY;
  2943. next:
  2944. p += klen;
  2945. }
  2946. i += len + 3;
  2947. }
  2948. use_random_mac_addr:
  2949. if (found & VPD_FOUND_MAC)
  2950. goto done;
  2951. /* Sun MAC prefix then 3 random bytes. */
  2952. printk(PFX "MAC address not found in ROM VPD\n");
  2953. dev_addr[0] = 0x08;
  2954. dev_addr[1] = 0x00;
  2955. dev_addr[2] = 0x20;
  2956. get_random_bytes(dev_addr + 3, 3);
  2957. done:
  2958. writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);
  2959. return phy_type;
  2960. }
  2961. /* check pci invariants */
  2962. static void cas_check_pci_invariants(struct cas *cp)
  2963. {
  2964. struct pci_dev *pdev = cp->pdev;
  2965. u8 rev;
  2966. cp->cas_flags = 0;
  2967. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  2968. if ((pdev->vendor == PCI_VENDOR_ID_SUN) &&
  2969. (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) {
  2970. if (rev >= CAS_ID_REVPLUS)
  2971. cp->cas_flags |= CAS_FLAG_REG_PLUS;
  2972. if (rev < CAS_ID_REVPLUS02u)
  2973. cp->cas_flags |= CAS_FLAG_TARGET_ABORT;
  2974. /* Original Cassini supports HW CSUM, but it's not
  2975. * enabled by default as it can trigger TX hangs.
  2976. */
  2977. if (rev < CAS_ID_REV2)
  2978. cp->cas_flags |= CAS_FLAG_NO_HW_CSUM;
  2979. } else {
  2980. /* Only sun has original cassini chips. */
  2981. cp->cas_flags |= CAS_FLAG_REG_PLUS;
  2982. /* We use a flag because the same phy might be externally
  2983. * connected.
  2984. */
  2985. if ((pdev->vendor == PCI_VENDOR_ID_NS) &&
  2986. (pdev->device == PCI_DEVICE_ID_NS_SATURN))
  2987. cp->cas_flags |= CAS_FLAG_SATURN;
  2988. }
  2989. }
  2990. static int cas_check_invariants(struct cas *cp)
  2991. {
  2992. struct pci_dev *pdev = cp->pdev;
  2993. u32 cfg;
  2994. int i;
  2995. /* get page size for rx buffers. */
  2996. cp->page_order = 0;
  2997. #ifdef USE_PAGE_ORDER
  2998. if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) {
  2999. /* see if we can allocate larger pages */
  3000. struct page *page = alloc_pages(GFP_ATOMIC,
  3001. CAS_JUMBO_PAGE_SHIFT -
  3002. PAGE_SHIFT);
  3003. if (page) {
  3004. __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT);
  3005. cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT;
  3006. } else {
  3007. printk(PFX "MTU limited to %d bytes\n", CAS_MAX_MTU);
  3008. }
  3009. }
  3010. #endif
  3011. cp->page_size = (PAGE_SIZE << cp->page_order);
  3012. /* Fetch the FIFO configurations. */
  3013. cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64;
  3014. cp->rx_fifo_size = RX_FIFO_SIZE;
  3015. /* finish phy determination. MDIO1 takes precedence over MDIO0 if
  3016. * they're both connected.
  3017. */
  3018. cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr,
  3019. PCI_SLOT(pdev->devfn));
  3020. if (cp->phy_type & CAS_PHY_SERDES) {
  3021. cp->cas_flags |= CAS_FLAG_1000MB_CAP;
  3022. return 0; /* no more checking needed */
  3023. }
  3024. /* MII */
  3025. cfg = readl(cp->regs + REG_MIF_CFG);
  3026. if (cfg & MIF_CFG_MDIO_1) {
  3027. cp->phy_type = CAS_PHY_MII_MDIO1;
  3028. } else if (cfg & MIF_CFG_MDIO_0) {
  3029. cp->phy_type = CAS_PHY_MII_MDIO0;
  3030. }
  3031. cas_mif_poll(cp, 0);
  3032. writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
  3033. for (i = 0; i < 32; i++) {
  3034. u32 phy_id;
  3035. int j;
  3036. for (j = 0; j < 3; j++) {
  3037. cp->phy_addr = i;
  3038. phy_id = cas_phy_read(cp, MII_PHYSID1) << 16;
  3039. phy_id |= cas_phy_read(cp, MII_PHYSID2);
  3040. if (phy_id && (phy_id != 0xFFFFFFFF)) {
  3041. cp->phy_id = phy_id;
  3042. goto done;
  3043. }
  3044. }
  3045. }
  3046. printk(KERN_ERR PFX "MII phy did not respond [%08x]\n",
  3047. readl(cp->regs + REG_MIF_STATE_MACHINE));
  3048. return -1;
  3049. done:
  3050. /* see if we can do gigabit */
  3051. cfg = cas_phy_read(cp, MII_BMSR);
  3052. if ((cfg & CAS_BMSR_1000_EXTEND) &&
  3053. cas_phy_read(cp, CAS_MII_1000_EXTEND))
  3054. cp->cas_flags |= CAS_FLAG_1000MB_CAP;
  3055. return 0;
  3056. }
  3057. /* Must be invoked under cp->lock. */
  3058. static inline void cas_start_dma(struct cas *cp)
  3059. {
  3060. int i;
  3061. u32 val;
  3062. int txfailed = 0;
  3063. /* enable dma */
  3064. val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
  3065. writel(val, cp->regs + REG_TX_CFG);
  3066. val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
  3067. writel(val, cp->regs + REG_RX_CFG);
  3068. /* enable the mac */
  3069. val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
  3070. writel(val, cp->regs + REG_MAC_TX_CFG);
  3071. val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
  3072. writel(val, cp->regs + REG_MAC_RX_CFG);
  3073. i = STOP_TRIES;
  3074. while (i-- > 0) {
  3075. val = readl(cp->regs + REG_MAC_TX_CFG);
  3076. if ((val & MAC_TX_CFG_EN))
  3077. break;
  3078. udelay(10);
  3079. }
  3080. if (i < 0) txfailed = 1;
  3081. i = STOP_TRIES;
  3082. while (i-- > 0) {
  3083. val = readl(cp->regs + REG_MAC_RX_CFG);
  3084. if ((val & MAC_RX_CFG_EN)) {
  3085. if (txfailed) {
  3086. printk(KERN_ERR
  3087. "%s: enabling mac failed [tx:%08x:%08x].\n",
  3088. cp->dev->name,
  3089. readl(cp->regs + REG_MIF_STATE_MACHINE),
  3090. readl(cp->regs + REG_MAC_STATE_MACHINE));
  3091. }
  3092. goto enable_rx_done;
  3093. }
  3094. udelay(10);
  3095. }
  3096. printk(KERN_ERR "%s: enabling mac failed [%s:%08x:%08x].\n",
  3097. cp->dev->name,
  3098. (txfailed? "tx,rx":"rx"),
  3099. readl(cp->regs + REG_MIF_STATE_MACHINE),
  3100. readl(cp->regs + REG_MAC_STATE_MACHINE));
  3101. enable_rx_done:
  3102. cas_unmask_intr(cp); /* enable interrupts */
  3103. writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);
  3104. writel(0, cp->regs + REG_RX_COMP_TAIL);
  3105. if (cp->cas_flags & CAS_FLAG_REG_PLUS) {
  3106. if (N_RX_DESC_RINGS > 1)
  3107. writel(RX_DESC_RINGN_SIZE(1) - 4,
  3108. cp->regs + REG_PLUS_RX_KICK1);
  3109. for (i = 1; i < N_RX_COMP_RINGS; i++)
  3110. writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));
  3111. }
  3112. }
  3113. /* Must be invoked under cp->lock. */
  3114. static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd,
  3115. int *pause)
  3116. {
  3117. u32 val = readl(cp->regs + REG_PCS_MII_LPA);
  3118. *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
  3119. *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
  3120. if (val & PCS_MII_LPA_ASYM_PAUSE)
  3121. *pause |= 0x10;
  3122. *spd = 1000;
  3123. }
  3124. /* Must be invoked under cp->lock. */
  3125. static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd,
  3126. int *pause)
  3127. {
  3128. u32 val;
  3129. *fd = 0;
  3130. *spd = 10;
  3131. *pause = 0;
  3132. /* use GMII registers */
  3133. val = cas_phy_read(cp, MII_LPA);
  3134. if (val & CAS_LPA_PAUSE)
  3135. *pause = 0x01;
  3136. if (val & CAS_LPA_ASYM_PAUSE)
  3137. *pause |= 0x10;
  3138. if (val & LPA_DUPLEX)
  3139. *fd = 1;
  3140. if (val & LPA_100)
  3141. *spd = 100;
  3142. if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
  3143. val = cas_phy_read(cp, CAS_MII_1000_STATUS);
  3144. if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
  3145. *spd = 1000;
  3146. if (val & CAS_LPA_1000FULL)
  3147. *fd = 1;
  3148. }
  3149. }
  3150. /* A link-up condition has occurred, initialize and enable the
  3151. * rest of the chip.
  3152. *
  3153. * Must be invoked under cp->lock.
  3154. */
  3155. static void cas_set_link_modes(struct cas *cp)
  3156. {
  3157. u32 val;
  3158. int full_duplex, speed, pause;
  3159. full_duplex = 0;
  3160. speed = 10;
  3161. pause = 0;
  3162. if (CAS_PHY_MII(cp->phy_type)) {
  3163. cas_mif_poll(cp, 0);
  3164. val = cas_phy_read(cp, MII_BMCR);
  3165. if (val & BMCR_ANENABLE) {
  3166. cas_read_mii_link_mode(cp, &full_duplex, &speed,
  3167. &pause);
  3168. } else {
  3169. if (val & BMCR_FULLDPLX)
  3170. full_duplex = 1;
  3171. if (val & BMCR_SPEED100)
  3172. speed = 100;
  3173. else if (val & CAS_BMCR_SPEED1000)
  3174. speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
  3175. 1000 : 100;
  3176. }
  3177. cas_mif_poll(cp, 1);
  3178. } else {
  3179. val = readl(cp->regs + REG_PCS_MII_CTRL);
  3180. cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause);
  3181. if ((val & PCS_MII_AUTONEG_EN) == 0) {
  3182. if (val & PCS_MII_CTRL_DUPLEX)
  3183. full_duplex = 1;
  3184. }
  3185. }
  3186. if (netif_msg_link(cp))
  3187. printk(KERN_INFO "%s: Link up at %d Mbps, %s-duplex.\n",
  3188. cp->dev->name, speed, (full_duplex ? "full" : "half"));
  3189. val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
  3190. if (CAS_PHY_MII(cp->phy_type)) {
  3191. val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
  3192. if (!full_duplex)
  3193. val |= MAC_XIF_DISABLE_ECHO;
  3194. }
  3195. if (full_duplex)
  3196. val |= MAC_XIF_FDPLX_LED;
  3197. if (speed == 1000)
  3198. val |= MAC_XIF_GMII_MODE;
  3199. writel(val, cp->regs + REG_MAC_XIF_CFG);
  3200. /* deal with carrier and collision detect. */
  3201. val = MAC_TX_CFG_IPG_EN;
  3202. if (full_duplex) {
  3203. val |= MAC_TX_CFG_IGNORE_CARRIER;
  3204. val |= MAC_TX_CFG_IGNORE_COLL;
  3205. } else {
  3206. #ifndef USE_CSMA_CD_PROTO
  3207. val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
  3208. val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
  3209. #endif
  3210. }
  3211. /* val now set up for REG_MAC_TX_CFG */
  3212. /* If gigabit and half-duplex, enable carrier extension
  3213. * mode. increase slot time to 512 bytes as well.
  3214. * else, disable it and make sure slot time is 64 bytes.
  3215. * also activate checksum bug workaround
  3216. */
  3217. if ((speed == 1000) && !full_duplex) {
  3218. writel(val | MAC_TX_CFG_CARRIER_EXTEND,
  3219. cp->regs + REG_MAC_TX_CFG);
  3220. val = readl(cp->regs + REG_MAC_RX_CFG);
  3221. val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
  3222. writel(val | MAC_RX_CFG_CARRIER_EXTEND,
  3223. cp->regs + REG_MAC_RX_CFG);
  3224. writel(0x200, cp->regs + REG_MAC_SLOT_TIME);
  3225. cp->crc_size = 4;
  3226. /* minimum size gigabit frame at half duplex */
  3227. cp->min_frame_size = CAS_1000MB_MIN_FRAME;
  3228. } else {
  3229. writel(val, cp->regs + REG_MAC_TX_CFG);
  3230. /* checksum bug workaround. don't strip FCS when in
  3231. * half-duplex mode
  3232. */
  3233. val = readl(cp->regs + REG_MAC_RX_CFG);
  3234. if (full_duplex) {
  3235. val |= MAC_RX_CFG_STRIP_FCS;
  3236. cp->crc_size = 0;
  3237. cp->min_frame_size = CAS_MIN_MTU;
  3238. } else {
  3239. val &= ~MAC_RX_CFG_STRIP_FCS;
  3240. cp->crc_size = 4;
  3241. cp->min_frame_size = CAS_MIN_FRAME;
  3242. }
  3243. writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
  3244. cp->regs + REG_MAC_RX_CFG);
  3245. writel(0x40, cp->regs + REG_MAC_SLOT_TIME);
  3246. }
  3247. if (netif_msg_link(cp)) {
  3248. if (pause & 0x01) {
  3249. printk(KERN_INFO "%s: Pause is enabled "
  3250. "(rxfifo: %d off: %d on: %d)\n",
  3251. cp->dev->name,
  3252. cp->rx_fifo_size,
  3253. cp->rx_pause_off,
  3254. cp->rx_pause_on);
  3255. } else if (pause & 0x10) {
  3256. printk(KERN_INFO "%s: TX pause enabled\n",
  3257. cp->dev->name);
  3258. } else {
  3259. printk(KERN_INFO "%s: Pause is disabled\n",
  3260. cp->dev->name);
  3261. }
  3262. }
  3263. val = readl(cp->regs + REG_MAC_CTRL_CFG);
  3264. val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
  3265. if (pause) { /* symmetric or asymmetric pause */
  3266. val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
  3267. if (pause & 0x01) { /* symmetric pause */
  3268. val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
  3269. }
  3270. }
  3271. writel(val, cp->regs + REG_MAC_CTRL_CFG);
  3272. cas_start_dma(cp);
  3273. }
  3274. /* Must be invoked under cp->lock. */
  3275. static void cas_init_hw(struct cas *cp, int restart_link)
  3276. {
  3277. if (restart_link)
  3278. cas_phy_init(cp);
  3279. cas_init_pause_thresholds(cp);
  3280. cas_init_mac(cp);
  3281. cas_init_dma(cp);
  3282. if (restart_link) {
  3283. /* Default aneg parameters */
  3284. cp->timer_ticks = 0;
  3285. cas_begin_auto_negotiation(cp, NULL);
  3286. } else if (cp->lstate == link_up) {
  3287. cas_set_link_modes(cp);
  3288. netif_carrier_on(cp->dev);
  3289. }
  3290. }
  3291. /* Must be invoked under cp->lock. on earlier cassini boards,
  3292. * SOFT_0 is tied to PCI reset. we use this to force a pci reset,
  3293. * let it settle out, and then restore pci state.
  3294. */
  3295. static void cas_hard_reset(struct cas *cp)
  3296. {
  3297. writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);
  3298. udelay(20);
  3299. pci_restore_state(cp->pdev);
  3300. }
  3301. static void cas_global_reset(struct cas *cp, int blkflag)
  3302. {
  3303. int limit;
  3304. /* issue a global reset. don't use RSTOUT. */
  3305. if (blkflag && !CAS_PHY_MII(cp->phy_type)) {
  3306. /* For PCS, when the blkflag is set, we should set the
  3307. * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of
  3308. * the last autonegotiation from being cleared. We'll
  3309. * need some special handling if the chip is set into a
  3310. * loopback mode.
  3311. */
  3312. writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),
  3313. cp->regs + REG_SW_RESET);
  3314. } else {
  3315. writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);
  3316. }
  3317. /* need to wait at least 3ms before polling register */
  3318. mdelay(3);
  3319. limit = STOP_TRIES;
  3320. while (limit-- > 0) {
  3321. u32 val = readl(cp->regs + REG_SW_RESET);
  3322. if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
  3323. goto done;
  3324. udelay(10);
  3325. }
  3326. printk(KERN_ERR "%s: sw reset failed.\n", cp->dev->name);
  3327. done:
  3328. /* enable various BIM interrupts */
  3329. writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |
  3330. BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG);
  3331. /* clear out pci error status mask for handled errors.
  3332. * we don't deal with DMA counter overflows as they happen
  3333. * all the time.
  3334. */
  3335. writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |
  3336. PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE |
  3337. PCI_ERR_BIM_DMA_READ), cp->regs +
  3338. REG_PCI_ERR_STATUS_MASK);
  3339. /* set up for MII by default to address mac rx reset timeout
  3340. * issue
  3341. */
  3342. writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);
  3343. }
  3344. static void cas_reset(struct cas *cp, int blkflag)
  3345. {
  3346. u32 val;
  3347. cas_mask_intr(cp);
  3348. cas_global_reset(cp, blkflag);
  3349. cas_mac_reset(cp);
  3350. cas_entropy_reset(cp);
  3351. /* disable dma engines. */
  3352. val = readl(cp->regs + REG_TX_CFG);
  3353. val &= ~TX_CFG_DMA_EN;
  3354. writel(val, cp->regs + REG_TX_CFG);
  3355. val = readl(cp->regs + REG_RX_CFG);
  3356. val &= ~RX_CFG_DMA_EN;
  3357. writel(val, cp->regs + REG_RX_CFG);
  3358. /* program header parser */
  3359. if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) ||
  3360. (CAS_HP_ALT_FIRMWARE == cas_prog_null)) {
  3361. cas_load_firmware(cp, CAS_HP_FIRMWARE);
  3362. } else {
  3363. cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE);
  3364. }
  3365. /* clear out error registers */
  3366. spin_lock(&cp->stat_lock[N_TX_RINGS]);
  3367. cas_clear_mac_err(cp);
  3368. spin_unlock(&cp->stat_lock[N_TX_RINGS]);
  3369. }
  3370. /* Shut down the chip, must be called with pm_mutex held. */
  3371. static void cas_shutdown(struct cas *cp)
  3372. {
  3373. unsigned long flags;
  3374. /* Make us not-running to avoid timers respawning */
  3375. cp->hw_running = 0;
  3376. del_timer_sync(&cp->link_timer);
  3377. /* Stop the reset task */
  3378. #if 0
  3379. while (atomic_read(&cp->reset_task_pending_mtu) ||
  3380. atomic_read(&cp->reset_task_pending_spare) ||
  3381. atomic_read(&cp->reset_task_pending_all))
  3382. schedule();
  3383. #else
  3384. while (atomic_read(&cp->reset_task_pending))
  3385. schedule();
  3386. #endif
  3387. /* Actually stop the chip */
  3388. cas_lock_all_save(cp, flags);
  3389. cas_reset(cp, 0);
  3390. if (cp->cas_flags & CAS_FLAG_SATURN)
  3391. cas_phy_powerdown(cp);
  3392. cas_unlock_all_restore(cp, flags);
  3393. }
  3394. static int cas_change_mtu(struct net_device *dev, int new_mtu)
  3395. {
  3396. struct cas *cp = netdev_priv(dev);
  3397. if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU)
  3398. return -EINVAL;
  3399. dev->mtu = new_mtu;
  3400. if (!netif_running(dev) || !netif_device_present(dev))
  3401. return 0;
  3402. /* let the reset task handle it */
  3403. #if 1
  3404. atomic_inc(&cp->reset_task_pending);
  3405. if ((cp->phy_type & CAS_PHY_SERDES)) {
  3406. atomic_inc(&cp->reset_task_pending_all);
  3407. } else {
  3408. atomic_inc(&cp->reset_task_pending_mtu);
  3409. }
  3410. schedule_work(&cp->reset_task);
  3411. #else
  3412. atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ?
  3413. CAS_RESET_ALL : CAS_RESET_MTU);
  3414. printk(KERN_ERR "reset called in cas_change_mtu\n");
  3415. schedule_work(&cp->reset_task);
  3416. #endif
  3417. flush_scheduled_work();
  3418. return 0;
  3419. }
  3420. static void cas_clean_txd(struct cas *cp, int ring)
  3421. {
  3422. struct cas_tx_desc *txd = cp->init_txds[ring];
  3423. struct sk_buff *skb, **skbs = cp->tx_skbs[ring];
  3424. u64 daddr, dlen;
  3425. int i, size;
  3426. size = TX_DESC_RINGN_SIZE(ring);
  3427. for (i = 0; i < size; i++) {
  3428. int frag;
  3429. if (skbs[i] == NULL)
  3430. continue;
  3431. skb = skbs[i];
  3432. skbs[i] = NULL;
  3433. for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
  3434. int ent = i & (size - 1);
  3435. /* first buffer is never a tiny buffer and so
  3436. * needs to be unmapped.
  3437. */
  3438. daddr = le64_to_cpu(txd[ent].buffer);
  3439. dlen = CAS_VAL(TX_DESC_BUFLEN,
  3440. le64_to_cpu(txd[ent].control));
  3441. pci_unmap_page(cp->pdev, daddr, dlen,
  3442. PCI_DMA_TODEVICE);
  3443. if (frag != skb_shinfo(skb)->nr_frags) {
  3444. i++;
  3445. /* next buffer might by a tiny buffer.
  3446. * skip past it.
  3447. */
  3448. ent = i & (size - 1);
  3449. if (cp->tx_tiny_use[ring][ent].used)
  3450. i++;
  3451. }
  3452. }
  3453. dev_kfree_skb_any(skb);
  3454. }
  3455. /* zero out tiny buf usage */
  3456. memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring]));
  3457. }
  3458. /* freed on close */
  3459. static inline void cas_free_rx_desc(struct cas *cp, int ring)
  3460. {
  3461. cas_page_t **page = cp->rx_pages[ring];
  3462. int i, size;
  3463. size = RX_DESC_RINGN_SIZE(ring);
  3464. for (i = 0; i < size; i++) {
  3465. if (page[i]) {
  3466. cas_page_free(cp, page[i]);
  3467. page[i] = NULL;
  3468. }
  3469. }
  3470. }
  3471. static void cas_free_rxds(struct cas *cp)
  3472. {
  3473. int i;
  3474. for (i = 0; i < N_RX_DESC_RINGS; i++)
  3475. cas_free_rx_desc(cp, i);
  3476. }
  3477. /* Must be invoked under cp->lock. */
  3478. static void cas_clean_rings(struct cas *cp)
  3479. {
  3480. int i;
  3481. /* need to clean all tx rings */
  3482. memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS);
  3483. memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS);
  3484. for (i = 0; i < N_TX_RINGS; i++)
  3485. cas_clean_txd(cp, i);
  3486. /* zero out init block */
  3487. memset(cp->init_block, 0, sizeof(struct cas_init_block));
  3488. cas_clean_rxds(cp);
  3489. cas_clean_rxcs(cp);
  3490. }
  3491. /* allocated on open */
  3492. static inline int cas_alloc_rx_desc(struct cas *cp, int ring)
  3493. {
  3494. cas_page_t **page = cp->rx_pages[ring];
  3495. int size, i = 0;
  3496. size = RX_DESC_RINGN_SIZE(ring);
  3497. for (i = 0; i < size; i++) {
  3498. if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL)
  3499. return -1;
  3500. }
  3501. return 0;
  3502. }
  3503. static int cas_alloc_rxds(struct cas *cp)
  3504. {
  3505. int i;
  3506. for (i = 0; i < N_RX_DESC_RINGS; i++) {
  3507. if (cas_alloc_rx_desc(cp, i) < 0) {
  3508. cas_free_rxds(cp);
  3509. return -1;
  3510. }
  3511. }
  3512. return 0;
  3513. }
  3514. static void cas_reset_task(struct work_struct *work)
  3515. {
  3516. struct cas *cp = container_of(work, struct cas, reset_task);
  3517. #if 0
  3518. int pending = atomic_read(&cp->reset_task_pending);
  3519. #else
  3520. int pending_all = atomic_read(&cp->reset_task_pending_all);
  3521. int pending_spare = atomic_read(&cp->reset_task_pending_spare);
  3522. int pending_mtu = atomic_read(&cp->reset_task_pending_mtu);
  3523. if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) {
  3524. /* We can have more tasks scheduled than actually
  3525. * needed.
  3526. */
  3527. atomic_dec(&cp->reset_task_pending);
  3528. return;
  3529. }
  3530. #endif
  3531. /* The link went down, we reset the ring, but keep
  3532. * DMA stopped. Use this function for reset
  3533. * on error as well.
  3534. */
  3535. if (cp->hw_running) {
  3536. unsigned long flags;
  3537. /* Make sure we don't get interrupts or tx packets */
  3538. netif_device_detach(cp->dev);
  3539. cas_lock_all_save(cp, flags);
  3540. if (cp->opened) {
  3541. /* We call cas_spare_recover when we call cas_open.
  3542. * but we do not initialize the lists cas_spare_recover
  3543. * uses until cas_open is called.
  3544. */
  3545. cas_spare_recover(cp, GFP_ATOMIC);
  3546. }
  3547. #if 1
  3548. /* test => only pending_spare set */
  3549. if (!pending_all && !pending_mtu)
  3550. goto done;
  3551. #else
  3552. if (pending == CAS_RESET_SPARE)
  3553. goto done;
  3554. #endif
  3555. /* when pending == CAS_RESET_ALL, the following
  3556. * call to cas_init_hw will restart auto negotiation.
  3557. * Setting the second argument of cas_reset to
  3558. * !(pending == CAS_RESET_ALL) will set this argument
  3559. * to 1 (avoiding reinitializing the PHY for the normal
  3560. * PCS case) when auto negotiation is not restarted.
  3561. */
  3562. #if 1
  3563. cas_reset(cp, !(pending_all > 0));
  3564. if (cp->opened)
  3565. cas_clean_rings(cp);
  3566. cas_init_hw(cp, (pending_all > 0));
  3567. #else
  3568. cas_reset(cp, !(pending == CAS_RESET_ALL));
  3569. if (cp->opened)
  3570. cas_clean_rings(cp);
  3571. cas_init_hw(cp, pending == CAS_RESET_ALL);
  3572. #endif
  3573. done:
  3574. cas_unlock_all_restore(cp, flags);
  3575. netif_device_attach(cp->dev);
  3576. }
  3577. #if 1
  3578. atomic_sub(pending_all, &cp->reset_task_pending_all);
  3579. atomic_sub(pending_spare, &cp->reset_task_pending_spare);
  3580. atomic_sub(pending_mtu, &cp->reset_task_pending_mtu);
  3581. atomic_dec(&cp->reset_task_pending);
  3582. #else
  3583. atomic_set(&cp->reset_task_pending, 0);
  3584. #endif
  3585. }
  3586. static void cas_link_timer(unsigned long data)
  3587. {
  3588. struct cas *cp = (struct cas *) data;
  3589. int mask, pending = 0, reset = 0;
  3590. unsigned long flags;
  3591. if (link_transition_timeout != 0 &&
  3592. cp->link_transition_jiffies_valid &&
  3593. ((jiffies - cp->link_transition_jiffies) >
  3594. (link_transition_timeout))) {
  3595. /* One-second counter so link-down workaround doesn't
  3596. * cause resets to occur so fast as to fool the switch
  3597. * into thinking the link is down.
  3598. */
  3599. cp->link_transition_jiffies_valid = 0;
  3600. }
  3601. if (!cp->hw_running)
  3602. return;
  3603. spin_lock_irqsave(&cp->lock, flags);
  3604. cas_lock_tx(cp);
  3605. cas_entropy_gather(cp);
  3606. /* If the link task is still pending, we just
  3607. * reschedule the link timer
  3608. */
  3609. #if 1
  3610. if (atomic_read(&cp->reset_task_pending_all) ||
  3611. atomic_read(&cp->reset_task_pending_spare) ||
  3612. atomic_read(&cp->reset_task_pending_mtu))
  3613. goto done;
  3614. #else
  3615. if (atomic_read(&cp->reset_task_pending))
  3616. goto done;
  3617. #endif
  3618. /* check for rx cleaning */
  3619. if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) {
  3620. int i, rmask;
  3621. for (i = 0; i < MAX_RX_DESC_RINGS; i++) {
  3622. rmask = CAS_FLAG_RXD_POST(i);
  3623. if ((mask & rmask) == 0)
  3624. continue;
  3625. /* post_rxds will do a mod_timer */
  3626. if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) {
  3627. pending = 1;
  3628. continue;
  3629. }
  3630. cp->cas_flags &= ~rmask;
  3631. }
  3632. }
  3633. if (CAS_PHY_MII(cp->phy_type)) {
  3634. u16 bmsr;
  3635. cas_mif_poll(cp, 0);
  3636. bmsr = cas_phy_read(cp, MII_BMSR);
  3637. /* WTZ: Solaris driver reads this twice, but that
  3638. * may be due to the PCS case and the use of a
  3639. * common implementation. Read it twice here to be
  3640. * safe.
  3641. */
  3642. bmsr = cas_phy_read(cp, MII_BMSR);
  3643. cas_mif_poll(cp, 1);
  3644. readl(cp->regs + REG_MIF_STATUS); /* avoid dups */
  3645. reset = cas_mii_link_check(cp, bmsr);
  3646. } else {
  3647. reset = cas_pcs_link_check(cp);
  3648. }
  3649. if (reset)
  3650. goto done;
  3651. /* check for tx state machine confusion */
  3652. if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) {
  3653. u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
  3654. u32 wptr, rptr;
  3655. int tlm = CAS_VAL(MAC_SM_TLM, val);
  3656. if (((tlm == 0x5) || (tlm == 0x3)) &&
  3657. (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
  3658. if (netif_msg_tx_err(cp))
  3659. printk(KERN_DEBUG "%s: tx err: "
  3660. "MAC_STATE[%08x]\n",
  3661. cp->dev->name, val);
  3662. reset = 1;
  3663. goto done;
  3664. }
  3665. val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
  3666. wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
  3667. rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR);
  3668. if ((val == 0) && (wptr != rptr)) {
  3669. if (netif_msg_tx_err(cp))
  3670. printk(KERN_DEBUG "%s: tx err: "
  3671. "TX_FIFO[%08x:%08x:%08x]\n",
  3672. cp->dev->name, val, wptr, rptr);
  3673. reset = 1;
  3674. }
  3675. if (reset)
  3676. cas_hard_reset(cp);
  3677. }
  3678. done:
  3679. if (reset) {
  3680. #if 1
  3681. atomic_inc(&cp->reset_task_pending);
  3682. atomic_inc(&cp->reset_task_pending_all);
  3683. schedule_work(&cp->reset_task);
  3684. #else
  3685. atomic_set(&cp->reset_task_pending, CAS_RESET_ALL);
  3686. printk(KERN_ERR "reset called in cas_link_timer\n");
  3687. schedule_work(&cp->reset_task);
  3688. #endif
  3689. }
  3690. if (!pending)
  3691. mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT);
  3692. cas_unlock_tx(cp);
  3693. spin_unlock_irqrestore(&cp->lock, flags);
  3694. }
  3695. /* tiny buffers are used to avoid target abort issues with
  3696. * older cassini's
  3697. */
  3698. static void cas_tx_tiny_free(struct cas *cp)
  3699. {
  3700. struct pci_dev *pdev = cp->pdev;
  3701. int i;
  3702. for (i = 0; i < N_TX_RINGS; i++) {
  3703. if (!cp->tx_tiny_bufs[i])
  3704. continue;
  3705. pci_free_consistent(pdev, TX_TINY_BUF_BLOCK,
  3706. cp->tx_tiny_bufs[i],
  3707. cp->tx_tiny_dvma[i]);
  3708. cp->tx_tiny_bufs[i] = NULL;
  3709. }
  3710. }
  3711. static int cas_tx_tiny_alloc(struct cas *cp)
  3712. {
  3713. struct pci_dev *pdev = cp->pdev;
  3714. int i;
  3715. for (i = 0; i < N_TX_RINGS; i++) {
  3716. cp->tx_tiny_bufs[i] =
  3717. pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK,
  3718. &cp->tx_tiny_dvma[i]);
  3719. if (!cp->tx_tiny_bufs[i]) {
  3720. cas_tx_tiny_free(cp);
  3721. return -1;
  3722. }
  3723. }
  3724. return 0;
  3725. }
  3726. static int cas_open(struct net_device *dev)
  3727. {
  3728. struct cas *cp = netdev_priv(dev);
  3729. int hw_was_up, err;
  3730. unsigned long flags;
  3731. mutex_lock(&cp->pm_mutex);
  3732. hw_was_up = cp->hw_running;
  3733. /* The power-management mutex protects the hw_running
  3734. * etc. state so it is safe to do this bit without cp->lock
  3735. */
  3736. if (!cp->hw_running) {
  3737. /* Reset the chip */
  3738. cas_lock_all_save(cp, flags);
  3739. /* We set the second arg to cas_reset to zero
  3740. * because cas_init_hw below will have its second
  3741. * argument set to non-zero, which will force
  3742. * autonegotiation to start.
  3743. */
  3744. cas_reset(cp, 0);
  3745. cp->hw_running = 1;
  3746. cas_unlock_all_restore(cp, flags);
  3747. }
  3748. if (cas_tx_tiny_alloc(cp) < 0)
  3749. return -ENOMEM;
  3750. /* alloc rx descriptors */
  3751. err = -ENOMEM;
  3752. if (cas_alloc_rxds(cp) < 0)
  3753. goto err_tx_tiny;
  3754. /* allocate spares */
  3755. cas_spare_init(cp);
  3756. cas_spare_recover(cp, GFP_KERNEL);
  3757. /* We can now request the interrupt as we know it's masked
  3758. * on the controller. cassini+ has up to 4 interrupts
  3759. * that can be used, but you need to do explicit pci interrupt
  3760. * mapping to expose them
  3761. */
  3762. if (request_irq(cp->pdev->irq, cas_interrupt,
  3763. IRQF_SHARED, dev->name, (void *) dev)) {
  3764. printk(KERN_ERR "%s: failed to request irq !\n",
  3765. cp->dev->name);
  3766. err = -EAGAIN;
  3767. goto err_spare;
  3768. }
  3769. /* init hw */
  3770. cas_lock_all_save(cp, flags);
  3771. cas_clean_rings(cp);
  3772. cas_init_hw(cp, !hw_was_up);
  3773. cp->opened = 1;
  3774. cas_unlock_all_restore(cp, flags);
  3775. netif_start_queue(dev);
  3776. mutex_unlock(&cp->pm_mutex);
  3777. return 0;
  3778. err_spare:
  3779. cas_spare_free(cp);
  3780. cas_free_rxds(cp);
  3781. err_tx_tiny:
  3782. cas_tx_tiny_free(cp);
  3783. mutex_unlock(&cp->pm_mutex);
  3784. return err;
  3785. }
  3786. static int cas_close(struct net_device *dev)
  3787. {
  3788. unsigned long flags;
  3789. struct cas *cp = netdev_priv(dev);
  3790. /* Make sure we don't get distracted by suspend/resume */
  3791. mutex_lock(&cp->pm_mutex);
  3792. netif_stop_queue(dev);
  3793. /* Stop traffic, mark us closed */
  3794. cas_lock_all_save(cp, flags);
  3795. cp->opened = 0;
  3796. cas_reset(cp, 0);
  3797. cas_phy_init(cp);
  3798. cas_begin_auto_negotiation(cp, NULL);
  3799. cas_clean_rings(cp);
  3800. cas_unlock_all_restore(cp, flags);
  3801. free_irq(cp->pdev->irq, (void *) dev);
  3802. cas_spare_free(cp);
  3803. cas_free_rxds(cp);
  3804. cas_tx_tiny_free(cp);
  3805. mutex_unlock(&cp->pm_mutex);
  3806. return 0;
  3807. }
  3808. static struct {
  3809. const char name[ETH_GSTRING_LEN];
  3810. } ethtool_cassini_statnames[] = {
  3811. {"collisions"},
  3812. {"rx_bytes"},
  3813. {"rx_crc_errors"},
  3814. {"rx_dropped"},
  3815. {"rx_errors"},
  3816. {"rx_fifo_errors"},
  3817. {"rx_frame_errors"},
  3818. {"rx_length_errors"},
  3819. {"rx_over_errors"},
  3820. {"rx_packets"},
  3821. {"tx_aborted_errors"},
  3822. {"tx_bytes"},
  3823. {"tx_dropped"},
  3824. {"tx_errors"},
  3825. {"tx_fifo_errors"},
  3826. {"tx_packets"}
  3827. };
  3828. #define CAS_NUM_STAT_KEYS (sizeof(ethtool_cassini_statnames)/ETH_GSTRING_LEN)
  3829. static struct {
  3830. const int offsets; /* neg. values for 2nd arg to cas_read_phy */
  3831. } ethtool_register_table[] = {
  3832. {-MII_BMSR},
  3833. {-MII_BMCR},
  3834. {REG_CAWR},
  3835. {REG_INF_BURST},
  3836. {REG_BIM_CFG},
  3837. {REG_RX_CFG},
  3838. {REG_HP_CFG},
  3839. {REG_MAC_TX_CFG},
  3840. {REG_MAC_RX_CFG},
  3841. {REG_MAC_CTRL_CFG},
  3842. {REG_MAC_XIF_CFG},
  3843. {REG_MIF_CFG},
  3844. {REG_PCS_CFG},
  3845. {REG_SATURN_PCFG},
  3846. {REG_PCS_MII_STATUS},
  3847. {REG_PCS_STATE_MACHINE},
  3848. {REG_MAC_COLL_EXCESS},
  3849. {REG_MAC_COLL_LATE}
  3850. };
  3851. #define CAS_REG_LEN (sizeof(ethtool_register_table)/sizeof(int))
  3852. #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN)
  3853. static void cas_read_regs(struct cas *cp, u8 *ptr, int len)
  3854. {
  3855. u8 *p;
  3856. int i;
  3857. unsigned long flags;
  3858. spin_lock_irqsave(&cp->lock, flags);
  3859. for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) {
  3860. u16 hval;
  3861. u32 val;
  3862. if (ethtool_register_table[i].offsets < 0) {
  3863. hval = cas_phy_read(cp,
  3864. -ethtool_register_table[i].offsets);
  3865. val = hval;
  3866. } else {
  3867. val= readl(cp->regs+ethtool_register_table[i].offsets);
  3868. }
  3869. memcpy(p, (u8 *)&val, sizeof(u32));
  3870. }
  3871. spin_unlock_irqrestore(&cp->lock, flags);
  3872. }
  3873. static struct net_device_stats *cas_get_stats(struct net_device *dev)
  3874. {
  3875. struct cas *cp = netdev_priv(dev);
  3876. struct net_device_stats *stats = cp->net_stats;
  3877. unsigned long flags;
  3878. int i;
  3879. unsigned long tmp;
  3880. /* we collate all of the stats into net_stats[N_TX_RING] */
  3881. if (!cp->hw_running)
  3882. return stats + N_TX_RINGS;
  3883. /* collect outstanding stats */
  3884. /* WTZ: the Cassini spec gives these as 16 bit counters but
  3885. * stored in 32-bit words. Added a mask of 0xffff to be safe,
  3886. * in case the chip somehow puts any garbage in the other bits.
  3887. * Also, counter usage didn't seem to mach what Adrian did
  3888. * in the parts of the code that set these quantities. Made
  3889. * that consistent.
  3890. */
  3891. spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags);
  3892. stats[N_TX_RINGS].rx_crc_errors +=
  3893. readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff;
  3894. stats[N_TX_RINGS].rx_frame_errors +=
  3895. readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff;
  3896. stats[N_TX_RINGS].rx_length_errors +=
  3897. readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff;
  3898. #if 1
  3899. tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) +
  3900. (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff);
  3901. stats[N_TX_RINGS].tx_aborted_errors += tmp;
  3902. stats[N_TX_RINGS].collisions +=
  3903. tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff);
  3904. #else
  3905. stats[N_TX_RINGS].tx_aborted_errors +=
  3906. readl(cp->regs + REG_MAC_COLL_EXCESS);
  3907. stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) +
  3908. readl(cp->regs + REG_MAC_COLL_LATE);
  3909. #endif
  3910. cas_clear_mac_err(cp);
  3911. /* saved bits that are unique to ring 0 */
  3912. spin_lock(&cp->stat_lock[0]);
  3913. stats[N_TX_RINGS].collisions += stats[0].collisions;
  3914. stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors;
  3915. stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors;
  3916. stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors;
  3917. stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors;
  3918. stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors;
  3919. spin_unlock(&cp->stat_lock[0]);
  3920. for (i = 0; i < N_TX_RINGS; i++) {
  3921. spin_lock(&cp->stat_lock[i]);
  3922. stats[N_TX_RINGS].rx_length_errors +=
  3923. stats[i].rx_length_errors;
  3924. stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors;
  3925. stats[N_TX_RINGS].rx_packets += stats[i].rx_packets;
  3926. stats[N_TX_RINGS].tx_packets += stats[i].tx_packets;
  3927. stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes;
  3928. stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes;
  3929. stats[N_TX_RINGS].rx_errors += stats[i].rx_errors;
  3930. stats[N_TX_RINGS].tx_errors += stats[i].tx_errors;
  3931. stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped;
  3932. stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped;
  3933. memset(stats + i, 0, sizeof(struct net_device_stats));
  3934. spin_unlock(&cp->stat_lock[i]);
  3935. }
  3936. spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags);
  3937. return stats + N_TX_RINGS;
  3938. }
  3939. static void cas_set_multicast(struct net_device *dev)
  3940. {
  3941. struct cas *cp = netdev_priv(dev);
  3942. u32 rxcfg, rxcfg_new;
  3943. unsigned long flags;
  3944. int limit = STOP_TRIES;
  3945. if (!cp->hw_running)
  3946. return;
  3947. spin_lock_irqsave(&cp->lock, flags);
  3948. rxcfg = readl(cp->regs + REG_MAC_RX_CFG);
  3949. /* disable RX MAC and wait for completion */
  3950. writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
  3951. while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) {
  3952. if (!limit--)
  3953. break;
  3954. udelay(10);
  3955. }
  3956. /* disable hash filter and wait for completion */
  3957. limit = STOP_TRIES;
  3958. rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN);
  3959. writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
  3960. while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) {
  3961. if (!limit--)
  3962. break;
  3963. udelay(10);
  3964. }
  3965. /* program hash filters */
  3966. cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp);
  3967. rxcfg |= rxcfg_new;
  3968. writel(rxcfg, cp->regs + REG_MAC_RX_CFG);
  3969. spin_unlock_irqrestore(&cp->lock, flags);
  3970. }
  3971. static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  3972. {
  3973. struct cas *cp = netdev_priv(dev);
  3974. strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN);
  3975. strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN);
  3976. info->fw_version[0] = '\0';
  3977. strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN);
  3978. info->regdump_len = cp->casreg_len < CAS_MAX_REGS ?
  3979. cp->casreg_len : CAS_MAX_REGS;
  3980. info->n_stats = CAS_NUM_STAT_KEYS;
  3981. }
  3982. static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  3983. {
  3984. struct cas *cp = netdev_priv(dev);
  3985. u16 bmcr;
  3986. int full_duplex, speed, pause;
  3987. unsigned long flags;
  3988. enum link_state linkstate = link_up;
  3989. cmd->advertising = 0;
  3990. cmd->supported = SUPPORTED_Autoneg;
  3991. if (cp->cas_flags & CAS_FLAG_1000MB_CAP) {
  3992. cmd->supported |= SUPPORTED_1000baseT_Full;
  3993. cmd->advertising |= ADVERTISED_1000baseT_Full;
  3994. }
  3995. /* Record PHY settings if HW is on. */
  3996. spin_lock_irqsave(&cp->lock, flags);
  3997. bmcr = 0;
  3998. linkstate = cp->lstate;
  3999. if (CAS_PHY_MII(cp->phy_type)) {
  4000. cmd->port = PORT_MII;
  4001. cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ?
  4002. XCVR_INTERNAL : XCVR_EXTERNAL;
  4003. cmd->phy_address = cp->phy_addr;
  4004. cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII |
  4005. ADVERTISED_10baseT_Half |
  4006. ADVERTISED_10baseT_Full |
  4007. ADVERTISED_100baseT_Half |
  4008. ADVERTISED_100baseT_Full;
  4009. cmd->supported |=
  4010. (SUPPORTED_10baseT_Half |
  4011. SUPPORTED_10baseT_Full |
  4012. SUPPORTED_100baseT_Half |
  4013. SUPPORTED_100baseT_Full |
  4014. SUPPORTED_TP | SUPPORTED_MII);
  4015. if (cp->hw_running) {
  4016. cas_mif_poll(cp, 0);
  4017. bmcr = cas_phy_read(cp, MII_BMCR);
  4018. cas_read_mii_link_mode(cp, &full_duplex,
  4019. &speed, &pause);
  4020. cas_mif_poll(cp, 1);
  4021. }
  4022. } else {
  4023. cmd->port = PORT_FIBRE;
  4024. cmd->transceiver = XCVR_INTERNAL;
  4025. cmd->phy_address = 0;
  4026. cmd->supported |= SUPPORTED_FIBRE;
  4027. cmd->advertising |= ADVERTISED_FIBRE;
  4028. if (cp->hw_running) {
  4029. /* pcs uses the same bits as mii */
  4030. bmcr = readl(cp->regs + REG_PCS_MII_CTRL);
  4031. cas_read_pcs_link_mode(cp, &full_duplex,
  4032. &speed, &pause);
  4033. }
  4034. }
  4035. spin_unlock_irqrestore(&cp->lock, flags);
  4036. if (bmcr & BMCR_ANENABLE) {
  4037. cmd->advertising |= ADVERTISED_Autoneg;
  4038. cmd->autoneg = AUTONEG_ENABLE;
  4039. cmd->speed = ((speed == 10) ?
  4040. SPEED_10 :
  4041. ((speed == 1000) ?
  4042. SPEED_1000 : SPEED_100));
  4043. cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  4044. } else {
  4045. cmd->autoneg = AUTONEG_DISABLE;
  4046. cmd->speed =
  4047. (bmcr & CAS_BMCR_SPEED1000) ?
  4048. SPEED_1000 :
  4049. ((bmcr & BMCR_SPEED100) ? SPEED_100:
  4050. SPEED_10);
  4051. cmd->duplex =
  4052. (bmcr & BMCR_FULLDPLX) ?
  4053. DUPLEX_FULL : DUPLEX_HALF;
  4054. }
  4055. if (linkstate != link_up) {
  4056. /* Force these to "unknown" if the link is not up and
  4057. * autonogotiation in enabled. We can set the link
  4058. * speed to 0, but not cmd->duplex,
  4059. * because its legal values are 0 and 1. Ethtool will
  4060. * print the value reported in parentheses after the
  4061. * word "Unknown" for unrecognized values.
  4062. *
  4063. * If in forced mode, we report the speed and duplex
  4064. * settings that we configured.
  4065. */
  4066. if (cp->link_cntl & BMCR_ANENABLE) {
  4067. cmd->speed = 0;
  4068. cmd->duplex = 0xff;
  4069. } else {
  4070. cmd->speed = SPEED_10;
  4071. if (cp->link_cntl & BMCR_SPEED100) {
  4072. cmd->speed = SPEED_100;
  4073. } else if (cp->link_cntl & CAS_BMCR_SPEED1000) {
  4074. cmd->speed = SPEED_1000;
  4075. }
  4076. cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)?
  4077. DUPLEX_FULL : DUPLEX_HALF;
  4078. }
  4079. }
  4080. return 0;
  4081. }
  4082. static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  4083. {
  4084. struct cas *cp = netdev_priv(dev);
  4085. unsigned long flags;
  4086. /* Verify the settings we care about. */
  4087. if (cmd->autoneg != AUTONEG_ENABLE &&
  4088. cmd->autoneg != AUTONEG_DISABLE)
  4089. return -EINVAL;
  4090. if (cmd->autoneg == AUTONEG_DISABLE &&
  4091. ((cmd->speed != SPEED_1000 &&
  4092. cmd->speed != SPEED_100 &&
  4093. cmd->speed != SPEED_10) ||
  4094. (cmd->duplex != DUPLEX_HALF &&
  4095. cmd->duplex != DUPLEX_FULL)))
  4096. return -EINVAL;
  4097. /* Apply settings and restart link process. */
  4098. spin_lock_irqsave(&cp->lock, flags);
  4099. cas_begin_auto_negotiation(cp, cmd);
  4100. spin_unlock_irqrestore(&cp->lock, flags);
  4101. return 0;
  4102. }
  4103. static int cas_nway_reset(struct net_device *dev)
  4104. {
  4105. struct cas *cp = netdev_priv(dev);
  4106. unsigned long flags;
  4107. if ((cp->link_cntl & BMCR_ANENABLE) == 0)
  4108. return -EINVAL;
  4109. /* Restart link process. */
  4110. spin_lock_irqsave(&cp->lock, flags);
  4111. cas_begin_auto_negotiation(cp, NULL);
  4112. spin_unlock_irqrestore(&cp->lock, flags);
  4113. return 0;
  4114. }
  4115. static u32 cas_get_link(struct net_device *dev)
  4116. {
  4117. struct cas *cp = netdev_priv(dev);
  4118. return cp->lstate == link_up;
  4119. }
  4120. static u32 cas_get_msglevel(struct net_device *dev)
  4121. {
  4122. struct cas *cp = netdev_priv(dev);
  4123. return cp->msg_enable;
  4124. }
  4125. static void cas_set_msglevel(struct net_device *dev, u32 value)
  4126. {
  4127. struct cas *cp = netdev_priv(dev);
  4128. cp->msg_enable = value;
  4129. }
  4130. static int cas_get_regs_len(struct net_device *dev)
  4131. {
  4132. struct cas *cp = netdev_priv(dev);
  4133. return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS;
  4134. }
  4135. static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  4136. void *p)
  4137. {
  4138. struct cas *cp = netdev_priv(dev);
  4139. regs->version = 0;
  4140. /* cas_read_regs handles locks (cp->lock). */
  4141. cas_read_regs(cp, p, regs->len / sizeof(u32));
  4142. }
  4143. static int cas_get_stats_count(struct net_device *dev)
  4144. {
  4145. return CAS_NUM_STAT_KEYS;
  4146. }
  4147. static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4148. {
  4149. memcpy(data, &ethtool_cassini_statnames,
  4150. CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN);
  4151. }
  4152. static void cas_get_ethtool_stats(struct net_device *dev,
  4153. struct ethtool_stats *estats, u64 *data)
  4154. {
  4155. struct cas *cp = netdev_priv(dev);
  4156. struct net_device_stats *stats = cas_get_stats(cp->dev);
  4157. int i = 0;
  4158. data[i++] = stats->collisions;
  4159. data[i++] = stats->rx_bytes;
  4160. data[i++] = stats->rx_crc_errors;
  4161. data[i++] = stats->rx_dropped;
  4162. data[i++] = stats->rx_errors;
  4163. data[i++] = stats->rx_fifo_errors;
  4164. data[i++] = stats->rx_frame_errors;
  4165. data[i++] = stats->rx_length_errors;
  4166. data[i++] = stats->rx_over_errors;
  4167. data[i++] = stats->rx_packets;
  4168. data[i++] = stats->tx_aborted_errors;
  4169. data[i++] = stats->tx_bytes;
  4170. data[i++] = stats->tx_dropped;
  4171. data[i++] = stats->tx_errors;
  4172. data[i++] = stats->tx_fifo_errors;
  4173. data[i++] = stats->tx_packets;
  4174. BUG_ON(i != CAS_NUM_STAT_KEYS);
  4175. }
  4176. static const struct ethtool_ops cas_ethtool_ops = {
  4177. .get_drvinfo = cas_get_drvinfo,
  4178. .get_settings = cas_get_settings,
  4179. .set_settings = cas_set_settings,
  4180. .nway_reset = cas_nway_reset,
  4181. .get_link = cas_get_link,
  4182. .get_msglevel = cas_get_msglevel,
  4183. .set_msglevel = cas_set_msglevel,
  4184. .get_regs_len = cas_get_regs_len,
  4185. .get_regs = cas_get_regs,
  4186. .get_stats_count = cas_get_stats_count,
  4187. .get_strings = cas_get_strings,
  4188. .get_ethtool_stats = cas_get_ethtool_stats,
  4189. };
  4190. static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  4191. {
  4192. struct cas *cp = netdev_priv(dev);
  4193. struct mii_ioctl_data *data = if_mii(ifr);
  4194. unsigned long flags;
  4195. int rc = -EOPNOTSUPP;
  4196. /* Hold the PM mutex while doing ioctl's or we may collide
  4197. * with open/close and power management and oops.
  4198. */
  4199. mutex_lock(&cp->pm_mutex);
  4200. switch (cmd) {
  4201. case SIOCGMIIPHY: /* Get address of MII PHY in use. */
  4202. data->phy_id = cp->phy_addr;
  4203. /* Fallthrough... */
  4204. case SIOCGMIIREG: /* Read MII PHY register. */
  4205. spin_lock_irqsave(&cp->lock, flags);
  4206. cas_mif_poll(cp, 0);
  4207. data->val_out = cas_phy_read(cp, data->reg_num & 0x1f);
  4208. cas_mif_poll(cp, 1);
  4209. spin_unlock_irqrestore(&cp->lock, flags);
  4210. rc = 0;
  4211. break;
  4212. case SIOCSMIIREG: /* Write MII PHY register. */
  4213. if (!capable(CAP_NET_ADMIN)) {
  4214. rc = -EPERM;
  4215. break;
  4216. }
  4217. spin_lock_irqsave(&cp->lock, flags);
  4218. cas_mif_poll(cp, 0);
  4219. rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in);
  4220. cas_mif_poll(cp, 1);
  4221. spin_unlock_irqrestore(&cp->lock, flags);
  4222. break;
  4223. default:
  4224. break;
  4225. };
  4226. mutex_unlock(&cp->pm_mutex);
  4227. return rc;
  4228. }
  4229. static int __devinit cas_init_one(struct pci_dev *pdev,
  4230. const struct pci_device_id *ent)
  4231. {
  4232. static int cas_version_printed = 0;
  4233. unsigned long casreg_len;
  4234. struct net_device *dev;
  4235. struct cas *cp;
  4236. int i, err, pci_using_dac;
  4237. u16 pci_cmd;
  4238. u8 orig_cacheline_size = 0, cas_cacheline_size = 0;
  4239. if (cas_version_printed++ == 0)
  4240. printk(KERN_INFO "%s", version);
  4241. err = pci_enable_device(pdev);
  4242. if (err) {
  4243. dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
  4244. return err;
  4245. }
  4246. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  4247. dev_err(&pdev->dev, "Cannot find proper PCI device "
  4248. "base address, aborting.\n");
  4249. err = -ENODEV;
  4250. goto err_out_disable_pdev;
  4251. }
  4252. dev = alloc_etherdev(sizeof(*cp));
  4253. if (!dev) {
  4254. dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n");
  4255. err = -ENOMEM;
  4256. goto err_out_disable_pdev;
  4257. }
  4258. SET_MODULE_OWNER(dev);
  4259. SET_NETDEV_DEV(dev, &pdev->dev);
  4260. err = pci_request_regions(pdev, dev->name);
  4261. if (err) {
  4262. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
  4263. goto err_out_free_netdev;
  4264. }
  4265. pci_set_master(pdev);
  4266. /* we must always turn on parity response or else parity
  4267. * doesn't get generated properly. disable SERR/PERR as well.
  4268. * in addition, we want to turn MWI on.
  4269. */
  4270. pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
  4271. pci_cmd &= ~PCI_COMMAND_SERR;
  4272. pci_cmd |= PCI_COMMAND_PARITY;
  4273. pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
  4274. pci_set_mwi(pdev);
  4275. /*
  4276. * On some architectures, the default cache line size set
  4277. * by pci_set_mwi reduces perforamnce. We have to increase
  4278. * it for this case. To start, we'll print some configuration
  4279. * data.
  4280. */
  4281. #if 1
  4282. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE,
  4283. &orig_cacheline_size);
  4284. if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) {
  4285. cas_cacheline_size =
  4286. (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ?
  4287. CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES;
  4288. if (pci_write_config_byte(pdev,
  4289. PCI_CACHE_LINE_SIZE,
  4290. cas_cacheline_size)) {
  4291. dev_err(&pdev->dev, "Could not set PCI cache "
  4292. "line size\n");
  4293. goto err_write_cacheline;
  4294. }
  4295. }
  4296. #endif
  4297. /* Configure DMA attributes. */
  4298. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  4299. pci_using_dac = 1;
  4300. err = pci_set_consistent_dma_mask(pdev,
  4301. DMA_64BIT_MASK);
  4302. if (err < 0) {
  4303. dev_err(&pdev->dev, "Unable to obtain 64-bit DMA "
  4304. "for consistent allocations\n");
  4305. goto err_out_free_res;
  4306. }
  4307. } else {
  4308. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  4309. if (err) {
  4310. dev_err(&pdev->dev, "No usable DMA configuration, "
  4311. "aborting.\n");
  4312. goto err_out_free_res;
  4313. }
  4314. pci_using_dac = 0;
  4315. }
  4316. casreg_len = pci_resource_len(pdev, 0);
  4317. cp = netdev_priv(dev);
  4318. cp->pdev = pdev;
  4319. #if 1
  4320. /* A value of 0 indicates we never explicitly set it */
  4321. cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0;
  4322. #endif
  4323. cp->dev = dev;
  4324. cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
  4325. cassini_debug;
  4326. cp->link_transition = LINK_TRANSITION_UNKNOWN;
  4327. cp->link_transition_jiffies_valid = 0;
  4328. spin_lock_init(&cp->lock);
  4329. spin_lock_init(&cp->rx_inuse_lock);
  4330. spin_lock_init(&cp->rx_spare_lock);
  4331. for (i = 0; i < N_TX_RINGS; i++) {
  4332. spin_lock_init(&cp->stat_lock[i]);
  4333. spin_lock_init(&cp->tx_lock[i]);
  4334. }
  4335. spin_lock_init(&cp->stat_lock[N_TX_RINGS]);
  4336. mutex_init(&cp->pm_mutex);
  4337. init_timer(&cp->link_timer);
  4338. cp->link_timer.function = cas_link_timer;
  4339. cp->link_timer.data = (unsigned long) cp;
  4340. #if 1
  4341. /* Just in case the implementation of atomic operations
  4342. * change so that an explicit initialization is necessary.
  4343. */
  4344. atomic_set(&cp->reset_task_pending, 0);
  4345. atomic_set(&cp->reset_task_pending_all, 0);
  4346. atomic_set(&cp->reset_task_pending_spare, 0);
  4347. atomic_set(&cp->reset_task_pending_mtu, 0);
  4348. #endif
  4349. INIT_WORK(&cp->reset_task, cas_reset_task);
  4350. /* Default link parameters */
  4351. if (link_mode >= 0 && link_mode <= 6)
  4352. cp->link_cntl = link_modes[link_mode];
  4353. else
  4354. cp->link_cntl = BMCR_ANENABLE;
  4355. cp->lstate = link_down;
  4356. cp->link_transition = LINK_TRANSITION_LINK_DOWN;
  4357. netif_carrier_off(cp->dev);
  4358. cp->timer_ticks = 0;
  4359. /* give us access to cassini registers */
  4360. cp->regs = pci_iomap(pdev, 0, casreg_len);
  4361. if (cp->regs == 0UL) {
  4362. dev_err(&pdev->dev, "Cannot map device registers, aborting.\n");
  4363. goto err_out_free_res;
  4364. }
  4365. cp->casreg_len = casreg_len;
  4366. pci_save_state(pdev);
  4367. cas_check_pci_invariants(cp);
  4368. cas_hard_reset(cp);
  4369. cas_reset(cp, 0);
  4370. if (cas_check_invariants(cp))
  4371. goto err_out_iounmap;
  4372. cp->init_block = (struct cas_init_block *)
  4373. pci_alloc_consistent(pdev, sizeof(struct cas_init_block),
  4374. &cp->block_dvma);
  4375. if (!cp->init_block) {
  4376. dev_err(&pdev->dev, "Cannot allocate init block, aborting.\n");
  4377. goto err_out_iounmap;
  4378. }
  4379. for (i = 0; i < N_TX_RINGS; i++)
  4380. cp->init_txds[i] = cp->init_block->txds[i];
  4381. for (i = 0; i < N_RX_DESC_RINGS; i++)
  4382. cp->init_rxds[i] = cp->init_block->rxds[i];
  4383. for (i = 0; i < N_RX_COMP_RINGS; i++)
  4384. cp->init_rxcs[i] = cp->init_block->rxcs[i];
  4385. for (i = 0; i < N_RX_FLOWS; i++)
  4386. skb_queue_head_init(&cp->rx_flows[i]);
  4387. dev->open = cas_open;
  4388. dev->stop = cas_close;
  4389. dev->hard_start_xmit = cas_start_xmit;
  4390. dev->get_stats = cas_get_stats;
  4391. dev->set_multicast_list = cas_set_multicast;
  4392. dev->do_ioctl = cas_ioctl;
  4393. dev->ethtool_ops = &cas_ethtool_ops;
  4394. dev->tx_timeout = cas_tx_timeout;
  4395. dev->watchdog_timeo = CAS_TX_TIMEOUT;
  4396. dev->change_mtu = cas_change_mtu;
  4397. #ifdef USE_NAPI
  4398. dev->poll = cas_poll;
  4399. dev->weight = 64;
  4400. #endif
  4401. #ifdef CONFIG_NET_POLL_CONTROLLER
  4402. dev->poll_controller = cas_netpoll;
  4403. #endif
  4404. dev->irq = pdev->irq;
  4405. dev->dma = 0;
  4406. /* Cassini features. */
  4407. if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0)
  4408. dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
  4409. if (pci_using_dac)
  4410. dev->features |= NETIF_F_HIGHDMA;
  4411. if (register_netdev(dev)) {
  4412. dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
  4413. goto err_out_free_consistent;
  4414. }
  4415. i = readl(cp->regs + REG_BIM_CFG);
  4416. printk(KERN_INFO "%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) "
  4417. "Ethernet[%d] ", dev->name,
  4418. (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "",
  4419. (i & BIM_CFG_32BIT) ? "32" : "64",
  4420. (i & BIM_CFG_66MHZ) ? "66" : "33",
  4421. (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq);
  4422. for (i = 0; i < 6; i++)
  4423. printk("%2.2x%c", dev->dev_addr[i],
  4424. i == 5 ? ' ' : ':');
  4425. printk("\n");
  4426. pci_set_drvdata(pdev, dev);
  4427. cp->hw_running = 1;
  4428. cas_entropy_reset(cp);
  4429. cas_phy_init(cp);
  4430. cas_begin_auto_negotiation(cp, NULL);
  4431. return 0;
  4432. err_out_free_consistent:
  4433. pci_free_consistent(pdev, sizeof(struct cas_init_block),
  4434. cp->init_block, cp->block_dvma);
  4435. err_out_iounmap:
  4436. mutex_lock(&cp->pm_mutex);
  4437. if (cp->hw_running)
  4438. cas_shutdown(cp);
  4439. mutex_unlock(&cp->pm_mutex);
  4440. pci_iounmap(pdev, cp->regs);
  4441. err_out_free_res:
  4442. pci_release_regions(pdev);
  4443. err_write_cacheline:
  4444. /* Try to restore it in case the error occured after we
  4445. * set it.
  4446. */
  4447. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size);
  4448. err_out_free_netdev:
  4449. free_netdev(dev);
  4450. err_out_disable_pdev:
  4451. pci_disable_device(pdev);
  4452. pci_set_drvdata(pdev, NULL);
  4453. return -ENODEV;
  4454. }
  4455. static void __devexit cas_remove_one(struct pci_dev *pdev)
  4456. {
  4457. struct net_device *dev = pci_get_drvdata(pdev);
  4458. struct cas *cp;
  4459. if (!dev)
  4460. return;
  4461. cp = netdev_priv(dev);
  4462. unregister_netdev(dev);
  4463. mutex_lock(&cp->pm_mutex);
  4464. flush_scheduled_work();
  4465. if (cp->hw_running)
  4466. cas_shutdown(cp);
  4467. mutex_unlock(&cp->pm_mutex);
  4468. #if 1
  4469. if (cp->orig_cacheline_size) {
  4470. /* Restore the cache line size if we had modified
  4471. * it.
  4472. */
  4473. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
  4474. cp->orig_cacheline_size);
  4475. }
  4476. #endif
  4477. pci_free_consistent(pdev, sizeof(struct cas_init_block),
  4478. cp->init_block, cp->block_dvma);
  4479. pci_iounmap(pdev, cp->regs);
  4480. free_netdev(dev);
  4481. pci_release_regions(pdev);
  4482. pci_disable_device(pdev);
  4483. pci_set_drvdata(pdev, NULL);
  4484. }
  4485. #ifdef CONFIG_PM
  4486. static int cas_suspend(struct pci_dev *pdev, pm_message_t state)
  4487. {
  4488. struct net_device *dev = pci_get_drvdata(pdev);
  4489. struct cas *cp = netdev_priv(dev);
  4490. unsigned long flags;
  4491. mutex_lock(&cp->pm_mutex);
  4492. /* If the driver is opened, we stop the DMA */
  4493. if (cp->opened) {
  4494. netif_device_detach(dev);
  4495. cas_lock_all_save(cp, flags);
  4496. /* We can set the second arg of cas_reset to 0
  4497. * because on resume, we'll call cas_init_hw with
  4498. * its second arg set so that autonegotiation is
  4499. * restarted.
  4500. */
  4501. cas_reset(cp, 0);
  4502. cas_clean_rings(cp);
  4503. cas_unlock_all_restore(cp, flags);
  4504. }
  4505. if (cp->hw_running)
  4506. cas_shutdown(cp);
  4507. mutex_unlock(&cp->pm_mutex);
  4508. return 0;
  4509. }
  4510. static int cas_resume(struct pci_dev *pdev)
  4511. {
  4512. struct net_device *dev = pci_get_drvdata(pdev);
  4513. struct cas *cp = netdev_priv(dev);
  4514. printk(KERN_INFO "%s: resuming\n", dev->name);
  4515. mutex_lock(&cp->pm_mutex);
  4516. cas_hard_reset(cp);
  4517. if (cp->opened) {
  4518. unsigned long flags;
  4519. cas_lock_all_save(cp, flags);
  4520. cas_reset(cp, 0);
  4521. cp->hw_running = 1;
  4522. cas_clean_rings(cp);
  4523. cas_init_hw(cp, 1);
  4524. cas_unlock_all_restore(cp, flags);
  4525. netif_device_attach(dev);
  4526. }
  4527. mutex_unlock(&cp->pm_mutex);
  4528. return 0;
  4529. }
  4530. #endif /* CONFIG_PM */
  4531. static struct pci_driver cas_driver = {
  4532. .name = DRV_MODULE_NAME,
  4533. .id_table = cas_pci_tbl,
  4534. .probe = cas_init_one,
  4535. .remove = __devexit_p(cas_remove_one),
  4536. #ifdef CONFIG_PM
  4537. .suspend = cas_suspend,
  4538. .resume = cas_resume
  4539. #endif
  4540. };
  4541. static int __init cas_init(void)
  4542. {
  4543. if (linkdown_timeout > 0)
  4544. link_transition_timeout = linkdown_timeout * HZ;
  4545. else
  4546. link_transition_timeout = 0;
  4547. return pci_register_driver(&cas_driver);
  4548. }
  4549. static void __exit cas_cleanup(void)
  4550. {
  4551. pci_unregister_driver(&cas_driver);
  4552. }
  4553. module_init(cas_init);
  4554. module_exit(cas_cleanup);