bnx2.h 308 KB

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  1. /* bnx2.h: Broadcom NX2 network driver.
  2. *
  3. * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Written by: Michael Chan (mchan@broadcom.com)
  10. */
  11. #ifndef BNX2_H
  12. #define BNX2_H
  13. /* Hardware data structures and register definitions automatically
  14. * generated from RTL code. Do not modify.
  15. */
  16. /*
  17. * tx_bd definition
  18. */
  19. struct tx_bd {
  20. u32 tx_bd_haddr_hi;
  21. u32 tx_bd_haddr_lo;
  22. u32 tx_bd_mss_nbytes;
  23. u32 tx_bd_vlan_tag_flags;
  24. #define TX_BD_FLAGS_CONN_FAULT (1<<0)
  25. #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
  26. #define TX_BD_FLAGS_IP_CKSUM (1<<2)
  27. #define TX_BD_FLAGS_VLAN_TAG (1<<3)
  28. #define TX_BD_FLAGS_COAL_NOW (1<<4)
  29. #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
  30. #define TX_BD_FLAGS_END (1<<6)
  31. #define TX_BD_FLAGS_START (1<<7)
  32. #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
  33. #define TX_BD_FLAGS_SW_FLAGS (1<<13)
  34. #define TX_BD_FLAGS_SW_SNAP (1<<14)
  35. #define TX_BD_FLAGS_SW_LSO (1<<15)
  36. };
  37. /*
  38. * rx_bd definition
  39. */
  40. struct rx_bd {
  41. u32 rx_bd_haddr_hi;
  42. u32 rx_bd_haddr_lo;
  43. u32 rx_bd_len;
  44. u32 rx_bd_flags;
  45. #define RX_BD_FLAGS_NOPUSH (1<<0)
  46. #define RX_BD_FLAGS_DUMMY (1<<1)
  47. #define RX_BD_FLAGS_END (1<<2)
  48. #define RX_BD_FLAGS_START (1<<3)
  49. };
  50. #define BNX2_RX_ALIGN 16
  51. /*
  52. * status_block definition
  53. */
  54. struct status_block {
  55. u32 status_attn_bits;
  56. #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
  57. #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
  58. #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
  59. #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
  60. #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
  61. #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
  62. #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
  63. #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
  64. #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
  65. #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
  66. #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
  67. #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
  68. #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
  69. #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
  70. #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
  71. #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
  72. #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
  73. #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
  74. #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
  75. #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
  76. #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
  77. #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
  78. #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
  79. #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
  80. #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
  81. #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
  82. #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
  83. #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
  84. #define STATUS_ATTN_BITS_EPB_ERROR (1L<<30)
  85. #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
  86. u32 status_attn_bits_ack;
  87. #if defined(__BIG_ENDIAN)
  88. u16 status_tx_quick_consumer_index0;
  89. u16 status_tx_quick_consumer_index1;
  90. u16 status_tx_quick_consumer_index2;
  91. u16 status_tx_quick_consumer_index3;
  92. u16 status_rx_quick_consumer_index0;
  93. u16 status_rx_quick_consumer_index1;
  94. u16 status_rx_quick_consumer_index2;
  95. u16 status_rx_quick_consumer_index3;
  96. u16 status_rx_quick_consumer_index4;
  97. u16 status_rx_quick_consumer_index5;
  98. u16 status_rx_quick_consumer_index6;
  99. u16 status_rx_quick_consumer_index7;
  100. u16 status_rx_quick_consumer_index8;
  101. u16 status_rx_quick_consumer_index9;
  102. u16 status_rx_quick_consumer_index10;
  103. u16 status_rx_quick_consumer_index11;
  104. u16 status_rx_quick_consumer_index12;
  105. u16 status_rx_quick_consumer_index13;
  106. u16 status_rx_quick_consumer_index14;
  107. u16 status_rx_quick_consumer_index15;
  108. u16 status_completion_producer_index;
  109. u16 status_cmd_consumer_index;
  110. u16 status_idx;
  111. u8 status_unused;
  112. u8 status_blk_num;
  113. #elif defined(__LITTLE_ENDIAN)
  114. u16 status_tx_quick_consumer_index1;
  115. u16 status_tx_quick_consumer_index0;
  116. u16 status_tx_quick_consumer_index3;
  117. u16 status_tx_quick_consumer_index2;
  118. u16 status_rx_quick_consumer_index1;
  119. u16 status_rx_quick_consumer_index0;
  120. u16 status_rx_quick_consumer_index3;
  121. u16 status_rx_quick_consumer_index2;
  122. u16 status_rx_quick_consumer_index5;
  123. u16 status_rx_quick_consumer_index4;
  124. u16 status_rx_quick_consumer_index7;
  125. u16 status_rx_quick_consumer_index6;
  126. u16 status_rx_quick_consumer_index9;
  127. u16 status_rx_quick_consumer_index8;
  128. u16 status_rx_quick_consumer_index11;
  129. u16 status_rx_quick_consumer_index10;
  130. u16 status_rx_quick_consumer_index13;
  131. u16 status_rx_quick_consumer_index12;
  132. u16 status_rx_quick_consumer_index15;
  133. u16 status_rx_quick_consumer_index14;
  134. u16 status_cmd_consumer_index;
  135. u16 status_completion_producer_index;
  136. u8 status_blk_num;
  137. u8 status_unused;
  138. u16 status_idx;
  139. #endif
  140. };
  141. /*
  142. * statistics_block definition
  143. */
  144. struct statistics_block {
  145. u32 stat_IfHCInOctets_hi;
  146. u32 stat_IfHCInOctets_lo;
  147. u32 stat_IfHCInBadOctets_hi;
  148. u32 stat_IfHCInBadOctets_lo;
  149. u32 stat_IfHCOutOctets_hi;
  150. u32 stat_IfHCOutOctets_lo;
  151. u32 stat_IfHCOutBadOctets_hi;
  152. u32 stat_IfHCOutBadOctets_lo;
  153. u32 stat_IfHCInUcastPkts_hi;
  154. u32 stat_IfHCInUcastPkts_lo;
  155. u32 stat_IfHCInMulticastPkts_hi;
  156. u32 stat_IfHCInMulticastPkts_lo;
  157. u32 stat_IfHCInBroadcastPkts_hi;
  158. u32 stat_IfHCInBroadcastPkts_lo;
  159. u32 stat_IfHCOutUcastPkts_hi;
  160. u32 stat_IfHCOutUcastPkts_lo;
  161. u32 stat_IfHCOutMulticastPkts_hi;
  162. u32 stat_IfHCOutMulticastPkts_lo;
  163. u32 stat_IfHCOutBroadcastPkts_hi;
  164. u32 stat_IfHCOutBroadcastPkts_lo;
  165. u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
  166. u32 stat_Dot3StatsCarrierSenseErrors;
  167. u32 stat_Dot3StatsFCSErrors;
  168. u32 stat_Dot3StatsAlignmentErrors;
  169. u32 stat_Dot3StatsSingleCollisionFrames;
  170. u32 stat_Dot3StatsMultipleCollisionFrames;
  171. u32 stat_Dot3StatsDeferredTransmissions;
  172. u32 stat_Dot3StatsExcessiveCollisions;
  173. u32 stat_Dot3StatsLateCollisions;
  174. u32 stat_EtherStatsCollisions;
  175. u32 stat_EtherStatsFragments;
  176. u32 stat_EtherStatsJabbers;
  177. u32 stat_EtherStatsUndersizePkts;
  178. u32 stat_EtherStatsOverrsizePkts;
  179. u32 stat_EtherStatsPktsRx64Octets;
  180. u32 stat_EtherStatsPktsRx65Octetsto127Octets;
  181. u32 stat_EtherStatsPktsRx128Octetsto255Octets;
  182. u32 stat_EtherStatsPktsRx256Octetsto511Octets;
  183. u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
  184. u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
  185. u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
  186. u32 stat_EtherStatsPktsTx64Octets;
  187. u32 stat_EtherStatsPktsTx65Octetsto127Octets;
  188. u32 stat_EtherStatsPktsTx128Octetsto255Octets;
  189. u32 stat_EtherStatsPktsTx256Octetsto511Octets;
  190. u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
  191. u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
  192. u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
  193. u32 stat_XonPauseFramesReceived;
  194. u32 stat_XoffPauseFramesReceived;
  195. u32 stat_OutXonSent;
  196. u32 stat_OutXoffSent;
  197. u32 stat_FlowControlDone;
  198. u32 stat_MacControlFramesReceived;
  199. u32 stat_XoffStateEntered;
  200. u32 stat_IfInFramesL2FilterDiscards;
  201. u32 stat_IfInRuleCheckerDiscards;
  202. u32 stat_IfInFTQDiscards;
  203. u32 stat_IfInMBUFDiscards;
  204. u32 stat_IfInRuleCheckerP4Hit;
  205. u32 stat_CatchupInRuleCheckerDiscards;
  206. u32 stat_CatchupInFTQDiscards;
  207. u32 stat_CatchupInMBUFDiscards;
  208. u32 stat_CatchupInRuleCheckerP4Hit;
  209. u32 stat_GenStat00;
  210. u32 stat_GenStat01;
  211. u32 stat_GenStat02;
  212. u32 stat_GenStat03;
  213. u32 stat_GenStat04;
  214. u32 stat_GenStat05;
  215. u32 stat_GenStat06;
  216. u32 stat_GenStat07;
  217. u32 stat_GenStat08;
  218. u32 stat_GenStat09;
  219. u32 stat_GenStat10;
  220. u32 stat_GenStat11;
  221. u32 stat_GenStat12;
  222. u32 stat_GenStat13;
  223. u32 stat_GenStat14;
  224. u32 stat_GenStat15;
  225. u32 stat_FwRxDrop;
  226. };
  227. /*
  228. * l2_fhdr definition
  229. */
  230. struct l2_fhdr {
  231. u32 l2_fhdr_status;
  232. #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
  233. #define L2_FHDR_STATUS_RULE_P2 (1<<3)
  234. #define L2_FHDR_STATUS_RULE_P3 (1<<4)
  235. #define L2_FHDR_STATUS_RULE_P4 (1<<5)
  236. #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
  237. #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
  238. #define L2_FHDR_STATUS_RSS_HASH (1<<8)
  239. #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
  240. #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
  241. #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
  242. #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
  243. #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
  244. #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
  245. #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
  246. #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
  247. #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
  248. #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
  249. u32 l2_fhdr_hash;
  250. #if defined(__BIG_ENDIAN)
  251. u16 l2_fhdr_pkt_len;
  252. u16 l2_fhdr_vlan_tag;
  253. u16 l2_fhdr_ip_xsum;
  254. u16 l2_fhdr_tcp_udp_xsum;
  255. #elif defined(__LITTLE_ENDIAN)
  256. u16 l2_fhdr_vlan_tag;
  257. u16 l2_fhdr_pkt_len;
  258. u16 l2_fhdr_tcp_udp_xsum;
  259. u16 l2_fhdr_ip_xsum;
  260. #endif
  261. };
  262. /*
  263. * l2_context definition
  264. */
  265. #define BNX2_L2CTX_TYPE 0x00000000
  266. #define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
  267. #define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
  268. #define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
  269. #define BNX2_L2CTX_TYPE_TYPE_L2 (1<<28)
  270. #define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
  271. #define BNX2_L2CTX_EST_NBD 0x00000088
  272. #define BNX2_L2CTX_CMD_TYPE 0x00000088
  273. #define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24)
  274. #define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
  275. #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
  276. #define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090
  277. #define BNX2_L2CTX_TSCH_BSEQ 0x00000094
  278. #define BNX2_L2CTX_TBDR_BSEQ 0x00000098
  279. #define BNX2_L2CTX_TBDR_BOFF 0x0000009c
  280. #define BNX2_L2CTX_TBDR_BIDX 0x0000009c
  281. #define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0
  282. #define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4
  283. #define BNX2_L2CTX_TXP_BOFF 0x000000a8
  284. #define BNX2_L2CTX_TXP_BIDX 0x000000a8
  285. #define BNX2_L2CTX_TXP_BSEQ 0x000000ac
  286. #define BNX2_L2CTX_TYPE_XI 0x00000080
  287. #define BNX2_L2CTX_CMD_TYPE_XI 0x00000240
  288. #define BNX2_L2CTX_TBDR_BHADDR_HI_XI 0x00000258
  289. #define BNX2_L2CTX_TBDR_BHADDR_LO_XI 0x0000025c
  290. /*
  291. * l2_bd_chain_context definition
  292. */
  293. #define BNX2_L2CTX_BD_PRE_READ 0x00000000
  294. #define BNX2_L2CTX_CTX_SIZE 0x00000000
  295. #define BNX2_L2CTX_CTX_TYPE 0x00000000
  296. #define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
  297. #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
  298. #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
  299. #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
  300. #define BNX2_L2CTX_HOST_BDIDX 0x00000004
  301. #define BNX2_L2CTX_HOST_BSEQ 0x00000008
  302. #define BNX2_L2CTX_NX_BSEQ 0x0000000c
  303. #define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010
  304. #define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014
  305. #define BNX2_L2CTX_NX_BDIDX 0x00000018
  306. /*
  307. * pci_config_l definition
  308. * offset: 0000
  309. */
  310. #define BNX2_PCICFG_MISC_CONFIG 0x00000068
  311. #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
  312. #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
  313. #define BNX2_PCICFG_MISC_CONFIG_RESERVED1 (1L<<4)
  314. #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
  315. #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
  316. #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
  317. #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
  318. #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
  319. #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN (1L<<10)
  320. #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN (1L<<11)
  321. #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN (1L<<12)
  322. #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
  323. #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
  324. #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
  325. #define BNX2_PCICFG_MISC_STATUS 0x0000006c
  326. #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
  327. #define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
  328. #define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2)
  329. #define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
  330. #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
  331. #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
  332. #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
  333. #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
  334. #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
  335. #define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE (1L<<8)
  336. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
  337. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
  338. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
  339. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
  340. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
  341. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
  342. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
  343. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
  344. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
  345. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
  346. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
  347. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
  348. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
  349. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
  350. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
  351. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
  352. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
  353. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
  354. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
  355. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
  356. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
  357. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
  358. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
  359. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
  360. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
  361. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
  362. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17 (1L<<17)
  363. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
  364. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19 (1L<<19)
  365. #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
  366. #define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078
  367. #define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL (0xfffffL<<2)
  368. #define BNX2_PCICFG_REG_WINDOW 0x00000080
  369. #define BNX2_PCICFG_INT_ACK_CMD 0x00000084
  370. #define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
  371. #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
  372. #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
  373. #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
  374. #define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM (0xfL<<24)
  375. #define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
  376. #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
  377. #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
  378. #define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
  379. /*
  380. * pci_reg definition
  381. * offset: 0x400
  382. */
  383. #define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400
  384. #define BNX2_PCI_GRC_WINDOW_ADDR_VALUE (0x1ffL<<13)
  385. #define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN (1L<<31)
  386. #define BNX2_PCI_CONFIG_1 0x00000404
  387. #define BNX2_PCI_CONFIG_1_RESERVED0 (0xffL<<0)
  388. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
  389. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
  390. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
  391. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
  392. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
  393. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
  394. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
  395. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
  396. #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
  397. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
  398. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
  399. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
  400. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
  401. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
  402. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
  403. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
  404. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
  405. #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
  406. #define BNX2_PCI_CONFIG_1_RESERVED1 (0x3ffffL<<14)
  407. #define BNX2_PCI_CONFIG_2 0x00000408
  408. #define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
  409. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
  410. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
  411. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
  412. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
  413. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
  414. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
  415. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
  416. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
  417. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
  418. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
  419. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
  420. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
  421. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
  422. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
  423. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
  424. #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
  425. #define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
  426. #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
  427. #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
  428. #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
  429. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
  430. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
  431. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
  432. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
  433. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
  434. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
  435. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
  436. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
  437. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
  438. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
  439. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
  440. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
  441. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
  442. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
  443. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
  444. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
  445. #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
  446. #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
  447. #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
  448. #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
  449. #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
  450. #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
  451. #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
  452. #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
  453. #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
  454. #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
  455. #define BNX2_PCI_CONFIG_2_RESERVED0 (0x3fL<<26)
  456. #define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI (1L<<16)
  457. #define BNX2_PCI_CONFIG_2_RESERVED0_XI (0x7fffL<<17)
  458. #define BNX2_PCI_CONFIG_3 0x0000040c
  459. #define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
  460. #define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE (0xffL<<8)
  461. #define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24)
  462. #define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25)
  463. #define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26)
  464. #define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27)
  465. #define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
  466. #define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31)
  467. #define BNX2_PCI_PM_DATA_A 0x00000410
  468. #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
  469. #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
  470. #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
  471. #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
  472. #define BNX2_PCI_PM_DATA_B 0x00000414
  473. #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
  474. #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
  475. #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
  476. #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
  477. #define BNX2_PCI_SWAP_DIAG0 0x00000418
  478. #define BNX2_PCI_SWAP_DIAG1 0x0000041c
  479. #define BNX2_PCI_EXP_ROM_ADDR 0x00000420
  480. #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
  481. #define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31)
  482. #define BNX2_PCI_EXP_ROM_DATA 0x00000424
  483. #define BNX2_PCI_VPD_INTF 0x00000428
  484. #define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
  485. #define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c
  486. #define BNX2_PCI_VPD_ADDR_FLAG_MSK 0x0000ffff
  487. #define BNX2_PCI_VPD_ADDR_FLAG_SL 0L
  488. #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fffL<<2)
  489. #define BNX2_PCI_VPD_ADDR_FLAG_WR (1L<<15)
  490. #define BNX2_PCI_VPD_DATA 0x00000430
  491. #define BNX2_PCI_ID_VAL1 0x00000434
  492. #define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
  493. #define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
  494. #define BNX2_PCI_ID_VAL2 0x00000438
  495. #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
  496. #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
  497. #define BNX2_PCI_ID_VAL3 0x0000043c
  498. #define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
  499. #define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
  500. #define BNX2_PCI_ID_VAL4 0x00000440
  501. #define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
  502. #define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
  503. #define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
  504. #define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
  505. #define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
  506. #define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
  507. #define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
  508. #define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
  509. #define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
  510. #define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
  511. #define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
  512. #define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
  513. #define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
  514. #define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
  515. #define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
  516. #define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
  517. #define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
  518. #define BNX2_PCI_ID_VAL4_RESERVED0 (0x3L<<4)
  519. #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
  520. #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
  521. #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
  522. #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
  523. #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
  524. #define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP (1L<<8)
  525. #define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
  526. #define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP (0x7L<<12)
  527. #define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
  528. #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
  529. #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
  530. #define BNX2_PCI_ID_VAL4_RESERVED2 (0x7L<<18)
  531. #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21 (0x3L<<21)
  532. #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21 (0x3L<<23)
  533. #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0 (1L<<25)
  534. #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10 (0x3L<<26)
  535. #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0 (1L<<28)
  536. #define BNX2_PCI_ID_VAL4_RESERVED3 (0x7L<<29)
  537. #define BNX2_PCI_ID_VAL4_RESERVED3_XI (0xffffL<<16)
  538. #define BNX2_PCI_ID_VAL5 0x00000444
  539. #define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
  540. #define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
  541. #define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
  542. #define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
  543. #define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
  544. #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
  545. #define BNX2_PCI_ID_VAL5_RESERVED0_TE (0x3ffffffL<<6)
  546. #define BNX2_PCI_ID_VAL5_PM_VERSION_XI (0x7L<<6)
  547. #define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI (1L<<9)
  548. #define BNX2_PCI_ID_VAL5_RESERVED0_XI (0x3fffffL<<10)
  549. #define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448
  550. #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
  551. #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
  552. #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
  553. #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
  554. #define BNX2_PCI_ID_VAL6 0x0000044c
  555. #define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
  556. #define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
  557. #define BNX2_PCI_ID_VAL6_BIST (0xffL<<16)
  558. #define BNX2_PCI_ID_VAL6_RESERVED0 (0xffL<<24)
  559. #define BNX2_PCI_MSI_DATA 0x00000450
  560. #define BNX2_PCI_MSI_DATA_MSI_DATA (0xffffL<<0)
  561. #define BNX2_PCI_MSI_ADDR_H 0x00000454
  562. #define BNX2_PCI_MSI_ADDR_L 0x00000458
  563. #define BNX2_PCI_MSI_ADDR_L_VAL (0x3fffffffL<<2)
  564. #define BNX2_PCI_CFG_ACCESS_CMD 0x0000045c
  565. #define BNX2_PCI_CFG_ACCESS_CMD_ADR (0x3fL<<2)
  566. #define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ (1L<<27)
  567. #define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ (0xfL<<28)
  568. #define BNX2_PCI_CFG_ACCESS_DATA 0x00000460
  569. #define BNX2_PCI_MSI_MASK 0x00000464
  570. #define BNX2_PCI_MSI_MASK_MSI_MASK (0xffffffffL<<0)
  571. #define BNX2_PCI_MSI_PEND 0x00000468
  572. #define BNX2_PCI_MSI_PEND_MSI_PEND (0xffffffffL<<0)
  573. #define BNX2_PCI_PM_DATA_C 0x0000046c
  574. #define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG (0xffL<<0)
  575. #define BNX2_PCI_PM_DATA_C_RESERVED0 (0xffffffL<<8)
  576. #define BNX2_PCI_MSIX_CONTROL 0x000004c0
  577. #define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ (0x7ffL<<0)
  578. #define BNX2_PCI_MSIX_CONTROL_RESERVED0 (0x1fffffL<<11)
  579. #define BNX2_PCI_MSIX_TBL_OFF_BIR 0x000004c4
  580. #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR (0x7L<<0)
  581. #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF (0x1fffffffL<<3)
  582. #define BNX2_PCI_MSIX_PBA_OFF_BIT 0x000004c8
  583. #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR (0x7L<<0)
  584. #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF (0x1fffffffL<<3)
  585. #define BNX2_PCI_PCIE_CAPABILITY 0x000004d0
  586. #define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM (0x1fL<<0)
  587. #define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1 (1L<<5)
  588. #define BNX2_PCI_DEVICE_CAPABILITY 0x000004d4
  589. #define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED (0x7L<<0)
  590. #define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (1L<<5)
  591. #define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY (0x7L<<6)
  592. #define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY (0x7L<<9)
  593. #define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (1L<<15)
  594. #define BNX2_PCI_LINK_CAPABILITY 0x000004dc
  595. #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED (0xfL<<0)
  596. #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001 (1L<<0)
  597. #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010 (1L<<0)
  598. #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH (0x1fL<<4)
  599. #define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT (1L<<9)
  600. #define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT (0x3L<<10)
  601. #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT (0x7L<<12)
  602. #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101 (5L<<12)
  603. #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110 (6L<<12)
  604. #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT (0x7L<<15)
  605. #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001 (1L<<15)
  606. #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010 (2L<<15)
  607. #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT (0x7L<<18)
  608. #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101 (5L<<18)
  609. #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110 (6L<<18)
  610. #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT (0x7L<<21)
  611. #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001 (1L<<21)
  612. #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010 (2L<<21)
  613. #define BNX2_PCI_LINK_CAPABILITY_PORT_NUM (0xffL<<24)
  614. #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2 0x000004e4
  615. #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfL<<0)
  616. #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1L<<4)
  617. #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED (0x7ffffffL<<5)
  618. #define BNX2_PCI_PCIE_LINK_CAPABILITY_2 0x000004e8
  619. #define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED (0xffffffffL<<0)
  620. #define BNX2_PCI_GRC_WINDOW1_ADDR 0x00000610
  621. #define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE (0x1ffL<<13)
  622. #define BNX2_PCI_GRC_WINDOW2_ADDR 0x00000614
  623. #define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE (0x1ffL<<13)
  624. #define BNX2_PCI_GRC_WINDOW3_ADDR 0x00000618
  625. #define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE (0x1ffL<<13)
  626. /*
  627. * misc_reg definition
  628. * offset: 0x800
  629. */
  630. #define BNX2_MISC_COMMAND 0x00000800
  631. #define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
  632. #define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1)
  633. #define BNX2_MISC_COMMAND_SW_RESET (1L<<4)
  634. #define BNX2_MISC_COMMAND_POR_RESET (1L<<5)
  635. #define BNX2_MISC_COMMAND_HD_RESET (1L<<6)
  636. #define BNX2_MISC_COMMAND_CMN_SW_RESET (1L<<7)
  637. #define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8)
  638. #define BNX2_MISC_COMMAND_CS16_ERR (1L<<9)
  639. #define BNX2_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12)
  640. #define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
  641. #define BNX2_MISC_COMMAND_POWERDOWN_EVENT (1L<<23)
  642. #define BNX2_MISC_COMMAND_SW_SHUTDOWN (1L<<24)
  643. #define BNX2_MISC_COMMAND_SHUTDOWN_EN (1L<<25)
  644. #define BNX2_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26)
  645. #define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27)
  646. #define BNX2_MISC_COMMAND_PCIE_DIS (1L<<28)
  647. #define BNX2_MISC_CFG 0x00000804
  648. #define BNX2_MISC_CFG_GRC_TMOUT (1L<<0)
  649. #define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1)
  650. #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
  651. #define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
  652. #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
  653. #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
  654. #define BNX2_MISC_CFG_BIST_EN (1L<<3)
  655. #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
  656. #define BNX2_MISC_CFG_RESERVED5_TE (1L<<5)
  657. #define BNX2_MISC_CFG_RESERVED6_TE (1L<<6)
  658. #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
  659. #define BNX2_MISC_CFG_LEDMODE (0x7L<<8)
  660. #define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
  661. #define BNX2_MISC_CFG_LEDMODE_PHY1_TE (1L<<8)
  662. #define BNX2_MISC_CFG_LEDMODE_PHY2_TE (2L<<8)
  663. #define BNX2_MISC_CFG_LEDMODE_PHY3_TE (3L<<8)
  664. #define BNX2_MISC_CFG_LEDMODE_PHY4_TE (4L<<8)
  665. #define BNX2_MISC_CFG_LEDMODE_PHY5_TE (5L<<8)
  666. #define BNX2_MISC_CFG_LEDMODE_PHY6_TE (6L<<8)
  667. #define BNX2_MISC_CFG_LEDMODE_PHY7_TE (7L<<8)
  668. #define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11)
  669. #define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12)
  670. #define BNX2_MISC_CFG_LEDMODE_XI (0xfL<<8)
  671. #define BNX2_MISC_CFG_LEDMODE_MAC_XI (0L<<8)
  672. #define BNX2_MISC_CFG_LEDMODE_PHY1_XI (1L<<8)
  673. #define BNX2_MISC_CFG_LEDMODE_PHY2_XI (2L<<8)
  674. #define BNX2_MISC_CFG_LEDMODE_PHY3_XI (3L<<8)
  675. #define BNX2_MISC_CFG_LEDMODE_MAC2_XI (4L<<8)
  676. #define BNX2_MISC_CFG_LEDMODE_PHY4_XI (5L<<8)
  677. #define BNX2_MISC_CFG_LEDMODE_PHY5_XI (6L<<8)
  678. #define BNX2_MISC_CFG_LEDMODE_PHY6_XI (7L<<8)
  679. #define BNX2_MISC_CFG_LEDMODE_MAC3_XI (8L<<8)
  680. #define BNX2_MISC_CFG_LEDMODE_PHY7_XI (9L<<8)
  681. #define BNX2_MISC_CFG_LEDMODE_PHY8_XI (10L<<8)
  682. #define BNX2_MISC_CFG_LEDMODE_PHY9_XI (11L<<8)
  683. #define BNX2_MISC_CFG_LEDMODE_MAC4_XI (12L<<8)
  684. #define BNX2_MISC_CFG_LEDMODE_PHY10_XI (13L<<8)
  685. #define BNX2_MISC_CFG_LEDMODE_PHY11_XI (14L<<8)
  686. #define BNX2_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8)
  687. #define BNX2_MISC_CFG_PORT_SELECT_XI (1L<<13)
  688. #define BNX2_MISC_CFG_PARITY_MODE_XI (1L<<14)
  689. #define BNX2_MISC_ID 0x00000808
  690. #define BNX2_MISC_ID_BOND_ID (0xfL<<0)
  691. #define BNX2_MISC_ID_BOND_ID_X (0L<<0)
  692. #define BNX2_MISC_ID_BOND_ID_C (3L<<0)
  693. #define BNX2_MISC_ID_BOND_ID_S (12L<<0)
  694. #define BNX2_MISC_ID_CHIP_METAL (0xffL<<4)
  695. #define BNX2_MISC_ID_CHIP_REV (0xfL<<12)
  696. #define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16)
  697. #define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c
  698. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
  699. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
  700. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
  701. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
  702. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
  703. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
  704. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
  705. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
  706. #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
  707. #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
  708. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
  709. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
  710. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
  711. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
  712. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
  713. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
  714. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
  715. #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
  716. #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
  717. #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
  718. #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
  719. #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
  720. #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
  721. #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
  722. #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
  723. #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
  724. #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
  725. #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
  726. #define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
  727. #define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
  728. #define BNX2_MISC_ENABLE_SET_BITS 0x00000810
  729. #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
  730. #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
  731. #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
  732. #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
  733. #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
  734. #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
  735. #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
  736. #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
  737. #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
  738. #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
  739. #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
  740. #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
  741. #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
  742. #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
  743. #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
  744. #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
  745. #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
  746. #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
  747. #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
  748. #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
  749. #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
  750. #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
  751. #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
  752. #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
  753. #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
  754. #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
  755. #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
  756. #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
  757. #define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
  758. #define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
  759. #define BNX2_MISC_ENABLE_CLR_BITS 0x00000814
  760. #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
  761. #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
  762. #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
  763. #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
  764. #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
  765. #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
  766. #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
  767. #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
  768. #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
  769. #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
  770. #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
  771. #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
  772. #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
  773. #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
  774. #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
  775. #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
  776. #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
  777. #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
  778. #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
  779. #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
  780. #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
  781. #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
  782. #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
  783. #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
  784. #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
  785. #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
  786. #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
  787. #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
  788. #define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
  789. #define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
  790. #define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818
  791. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
  792. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
  793. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
  794. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
  795. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
  796. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
  797. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
  798. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
  799. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
  800. #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
  801. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
  802. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
  803. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
  804. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
  805. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
  806. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
  807. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
  808. #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7L<<8)
  809. #define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
  810. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
  811. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
  812. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
  813. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
  814. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
  815. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
  816. #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfL<<12)
  817. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
  818. #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17)
  819. #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18)
  820. #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19)
  821. #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffL<<20)
  822. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17)
  823. #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fL<<18)
  824. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7L<<24)
  825. #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27)
  826. #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfL<<28)
  827. #define BNX2_MISC_SPIO 0x0000081c
  828. #define BNX2_MISC_SPIO_VALUE (0xffL<<0)
  829. #define BNX2_MISC_SPIO_SET (0xffL<<8)
  830. #define BNX2_MISC_SPIO_CLR (0xffL<<16)
  831. #define BNX2_MISC_SPIO_FLOAT (0xffL<<24)
  832. #define BNX2_MISC_SPIO_INT 0x00000820
  833. #define BNX2_MISC_SPIO_INT_INT_STATE_TE (0xfL<<0)
  834. #define BNX2_MISC_SPIO_INT_OLD_VALUE_TE (0xfL<<8)
  835. #define BNX2_MISC_SPIO_INT_OLD_SET_TE (0xfL<<16)
  836. #define BNX2_MISC_SPIO_INT_OLD_CLR_TE (0xfL<<24)
  837. #define BNX2_MISC_SPIO_INT_INT_STATE_XI (0xffL<<0)
  838. #define BNX2_MISC_SPIO_INT_OLD_VALUE_XI (0xffL<<8)
  839. #define BNX2_MISC_SPIO_INT_OLD_SET_XI (0xffL<<16)
  840. #define BNX2_MISC_SPIO_INT_OLD_CLR_XI (0xffL<<24)
  841. #define BNX2_MISC_CONFIG_LFSR 0x00000824
  842. #define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
  843. #define BNX2_MISC_LFSR_MASK_BITS 0x00000828
  844. #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
  845. #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
  846. #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
  847. #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
  848. #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
  849. #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
  850. #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
  851. #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
  852. #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
  853. #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
  854. #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
  855. #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
  856. #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
  857. #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
  858. #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
  859. #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
  860. #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
  861. #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
  862. #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
  863. #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
  864. #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
  865. #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
  866. #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
  867. #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
  868. #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
  869. #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
  870. #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
  871. #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
  872. #define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
  873. #define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
  874. #define BNX2_MISC_ARB_REQ0 0x0000082c
  875. #define BNX2_MISC_ARB_REQ1 0x00000830
  876. #define BNX2_MISC_ARB_REQ2 0x00000834
  877. #define BNX2_MISC_ARB_REQ3 0x00000838
  878. #define BNX2_MISC_ARB_REQ4 0x0000083c
  879. #define BNX2_MISC_ARB_FREE0 0x00000840
  880. #define BNX2_MISC_ARB_FREE1 0x00000844
  881. #define BNX2_MISC_ARB_FREE2 0x00000848
  882. #define BNX2_MISC_ARB_FREE3 0x0000084c
  883. #define BNX2_MISC_ARB_FREE4 0x00000850
  884. #define BNX2_MISC_ARB_REQ_STATUS0 0x00000854
  885. #define BNX2_MISC_ARB_REQ_STATUS1 0x00000858
  886. #define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c
  887. #define BNX2_MISC_ARB_REQ_STATUS3 0x00000860
  888. #define BNX2_MISC_ARB_REQ_STATUS4 0x00000864
  889. #define BNX2_MISC_ARB_GNT0 0x00000868
  890. #define BNX2_MISC_ARB_GNT0_0 (0x7L<<0)
  891. #define BNX2_MISC_ARB_GNT0_1 (0x7L<<4)
  892. #define BNX2_MISC_ARB_GNT0_2 (0x7L<<8)
  893. #define BNX2_MISC_ARB_GNT0_3 (0x7L<<12)
  894. #define BNX2_MISC_ARB_GNT0_4 (0x7L<<16)
  895. #define BNX2_MISC_ARB_GNT0_5 (0x7L<<20)
  896. #define BNX2_MISC_ARB_GNT0_6 (0x7L<<24)
  897. #define BNX2_MISC_ARB_GNT0_7 (0x7L<<28)
  898. #define BNX2_MISC_ARB_GNT1 0x0000086c
  899. #define BNX2_MISC_ARB_GNT1_8 (0x7L<<0)
  900. #define BNX2_MISC_ARB_GNT1_9 (0x7L<<4)
  901. #define BNX2_MISC_ARB_GNT1_10 (0x7L<<8)
  902. #define BNX2_MISC_ARB_GNT1_11 (0x7L<<12)
  903. #define BNX2_MISC_ARB_GNT1_12 (0x7L<<16)
  904. #define BNX2_MISC_ARB_GNT1_13 (0x7L<<20)
  905. #define BNX2_MISC_ARB_GNT1_14 (0x7L<<24)
  906. #define BNX2_MISC_ARB_GNT1_15 (0x7L<<28)
  907. #define BNX2_MISC_ARB_GNT2 0x00000870
  908. #define BNX2_MISC_ARB_GNT2_16 (0x7L<<0)
  909. #define BNX2_MISC_ARB_GNT2_17 (0x7L<<4)
  910. #define BNX2_MISC_ARB_GNT2_18 (0x7L<<8)
  911. #define BNX2_MISC_ARB_GNT2_19 (0x7L<<12)
  912. #define BNX2_MISC_ARB_GNT2_20 (0x7L<<16)
  913. #define BNX2_MISC_ARB_GNT2_21 (0x7L<<20)
  914. #define BNX2_MISC_ARB_GNT2_22 (0x7L<<24)
  915. #define BNX2_MISC_ARB_GNT2_23 (0x7L<<28)
  916. #define BNX2_MISC_ARB_GNT3 0x00000874
  917. #define BNX2_MISC_ARB_GNT3_24 (0x7L<<0)
  918. #define BNX2_MISC_ARB_GNT3_25 (0x7L<<4)
  919. #define BNX2_MISC_ARB_GNT3_26 (0x7L<<8)
  920. #define BNX2_MISC_ARB_GNT3_27 (0x7L<<12)
  921. #define BNX2_MISC_ARB_GNT3_28 (0x7L<<16)
  922. #define BNX2_MISC_ARB_GNT3_29 (0x7L<<20)
  923. #define BNX2_MISC_ARB_GNT3_30 (0x7L<<24)
  924. #define BNX2_MISC_ARB_GNT3_31 (0x7L<<28)
  925. #define BNX2_MISC_RESERVED1 0x00000878
  926. #define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fL<<0)
  927. #define BNX2_MISC_RESERVED2 0x0000087c
  928. #define BNX2_MISC_RESERVED2_PCIE_DIS (1L<<0)
  929. #define BNX2_MISC_RESERVED2_LINK_IN_L23 (1L<<1)
  930. #define BNX2_MISC_SM_ASF_CONTROL 0x00000880
  931. #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
  932. #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
  933. #define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
  934. #define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
  935. #define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
  936. #define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
  937. #define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
  938. #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
  939. #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8)
  940. #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9)
  941. #define BNX2_MISC_SM_ASF_CONTROL_RES (0x3L<<10)
  942. #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
  943. #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
  944. #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
  945. #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
  946. #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fL<<16)
  947. #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fL<<23)
  948. #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
  949. #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
  950. #define BNX2_MISC_SMB_IN 0x00000884
  951. #define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0)
  952. #define BNX2_MISC_SMB_IN_RDY (1L<<8)
  953. #define BNX2_MISC_SMB_IN_DONE (1L<<9)
  954. #define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10)
  955. #define BNX2_MISC_SMB_IN_STATUS (0x7L<<11)
  956. #define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11)
  957. #define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
  958. #define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
  959. #define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
  960. #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
  961. #define BNX2_MISC_SMB_OUT 0x00000888
  962. #define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
  963. #define BNX2_MISC_SMB_OUT_RDY (1L<<8)
  964. #define BNX2_MISC_SMB_OUT_START (1L<<9)
  965. #define BNX2_MISC_SMB_OUT_LAST (1L<<10)
  966. #define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11)
  967. #define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12)
  968. #define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
  969. #define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
  970. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
  971. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
  972. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
  973. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
  974. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
  975. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
  976. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
  977. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20)
  978. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
  979. #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
  980. #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
  981. #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
  982. #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
  983. #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
  984. #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
  985. #define BNX2_MISC_SMB_WATCHDOG 0x0000088c
  986. #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
  987. #define BNX2_MISC_SMB_HEARTBEAT 0x00000890
  988. #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
  989. #define BNX2_MISC_SMB_POLL_ASF 0x00000894
  990. #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
  991. #define BNX2_MISC_SMB_POLL_LEGACY 0x00000898
  992. #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
  993. #define BNX2_MISC_SMB_RETRAN 0x0000089c
  994. #define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
  995. #define BNX2_MISC_SMB_TIMESTAMP 0x000008a0
  996. #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
  997. #define BNX2_MISC_PERR_ENA0 0x000008a4
  998. #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
  999. #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
  1000. #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
  1001. #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
  1002. #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
  1003. #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
  1004. #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
  1005. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
  1006. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
  1007. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
  1008. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
  1009. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
  1010. #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
  1011. #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
  1012. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
  1013. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
  1014. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
  1015. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
  1016. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
  1017. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
  1018. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
  1019. #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
  1020. #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
  1021. #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
  1022. #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
  1023. #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
  1024. #define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
  1025. #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
  1026. #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
  1027. #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
  1028. #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
  1029. #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
  1030. #define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0)
  1031. #define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1)
  1032. #define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2)
  1033. #define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3)
  1034. #define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4)
  1035. #define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5)
  1036. #define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6)
  1037. #define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7)
  1038. #define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8)
  1039. #define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9)
  1040. #define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10)
  1041. #define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11)
  1042. #define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12)
  1043. #define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13)
  1044. #define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14)
  1045. #define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15)
  1046. #define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16)
  1047. #define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17)
  1048. #define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18)
  1049. #define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19)
  1050. #define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20)
  1051. #define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21)
  1052. #define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22)
  1053. #define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23)
  1054. #define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24)
  1055. #define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25)
  1056. #define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26)
  1057. #define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27)
  1058. #define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28)
  1059. #define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29)
  1060. #define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30)
  1061. #define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31)
  1062. #define BNX2_MISC_PERR_ENA1 0x000008a8
  1063. #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
  1064. #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
  1065. #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
  1066. #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
  1067. #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
  1068. #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
  1069. #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
  1070. #define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
  1071. #define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
  1072. #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
  1073. #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
  1074. #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
  1075. #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
  1076. #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
  1077. #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
  1078. #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
  1079. #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
  1080. #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
  1081. #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
  1082. #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
  1083. #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
  1084. #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
  1085. #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
  1086. #define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
  1087. #define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
  1088. #define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
  1089. #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
  1090. #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
  1091. #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
  1092. #define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
  1093. #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
  1094. #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
  1095. #define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0)
  1096. #define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2)
  1097. #define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3)
  1098. #define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4)
  1099. #define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5)
  1100. #define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6)
  1101. #define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7)
  1102. #define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8)
  1103. #define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9)
  1104. #define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10)
  1105. #define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11)
  1106. #define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12)
  1107. #define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13)
  1108. #define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14)
  1109. #define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15)
  1110. #define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16)
  1111. #define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17)
  1112. #define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18)
  1113. #define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19)
  1114. #define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20)
  1115. #define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21)
  1116. #define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22)
  1117. #define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23)
  1118. #define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24)
  1119. #define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25)
  1120. #define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26)
  1121. #define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27)
  1122. #define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28)
  1123. #define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29)
  1124. #define BNX2_MISC_PERR_ENA2 0x000008ac
  1125. #define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
  1126. #define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
  1127. #define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
  1128. #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
  1129. #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
  1130. #define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
  1131. #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
  1132. #define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
  1133. #define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
  1134. #define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0)
  1135. #define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1)
  1136. #define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2)
  1137. #define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3)
  1138. #define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4)
  1139. #define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5)
  1140. #define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6)
  1141. #define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0
  1142. #define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
  1143. #define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
  1144. #define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI (0xfffL<<15)
  1145. #define BNX2_MISC_VREG_CONTROL 0x000008b4
  1146. #define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0)
  1147. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0)
  1148. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0)
  1149. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0)
  1150. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0)
  1151. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0)
  1152. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0)
  1153. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0)
  1154. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0)
  1155. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0)
  1156. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0)
  1157. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0)
  1158. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0)
  1159. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0)
  1160. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0)
  1161. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0)
  1162. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0)
  1163. #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0)
  1164. #define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4)
  1165. #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4)
  1166. #define BNX2_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4)
  1167. #define BNX2_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4)
  1168. #define BNX2_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4)
  1169. #define BNX2_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4)
  1170. #define BNX2_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4)
  1171. #define BNX2_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4)
  1172. #define BNX2_MISC_VREG_CONTROL_2_5_NOM (7L<<4)
  1173. #define BNX2_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4)
  1174. #define BNX2_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4)
  1175. #define BNX2_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4)
  1176. #define BNX2_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4)
  1177. #define BNX2_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4)
  1178. #define BNX2_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4)
  1179. #define BNX2_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4)
  1180. #define BNX2_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4)
  1181. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8)
  1182. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8)
  1183. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8)
  1184. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8)
  1185. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8)
  1186. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8)
  1187. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8)
  1188. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8)
  1189. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8)
  1190. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8)
  1191. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8)
  1192. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8)
  1193. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8)
  1194. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8)
  1195. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8)
  1196. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8)
  1197. #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8)
  1198. #define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8
  1199. #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
  1200. #define BNX2_MISC_GP_HW_CTL0 0x000008bc
  1201. #define BNX2_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0)
  1202. #define BNX2_MISC_GP_HW_CTL0_RMII_MODE (1L<<1)
  1203. #define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2)
  1204. #define BNX2_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3)
  1205. #define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4)
  1206. #define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5)
  1207. #define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6)
  1208. #define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI (0x7L<<4)
  1209. #define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7)
  1210. #define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8)
  1211. #define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9)
  1212. #define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10)
  1213. #define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI (0x7L<<8)
  1214. #define BNX2_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11)
  1215. #define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12)
  1216. #define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13)
  1217. #define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14)
  1218. #define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15)
  1219. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfL<<16)
  1220. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16)
  1221. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16)
  1222. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16)
  1223. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16)
  1224. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16)
  1225. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16)
  1226. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20)
  1227. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21)
  1228. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3L<<22)
  1229. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22)
  1230. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22)
  1231. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22)
  1232. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22)
  1233. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3L<<24)
  1234. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24)
  1235. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24)
  1236. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24)
  1237. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24)
  1238. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3L<<26)
  1239. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26)
  1240. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26)
  1241. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26)
  1242. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26)
  1243. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3L<<28)
  1244. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28)
  1245. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28)
  1246. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28)
  1247. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28)
  1248. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3L<<30)
  1249. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30)
  1250. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30)
  1251. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30)
  1252. #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30)
  1253. #define BNX2_MISC_GP_HW_CTL1 0x000008c0
  1254. #define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0)
  1255. #define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1)
  1256. #define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2)
  1257. #define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3)
  1258. #define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffL<<0)
  1259. #define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffL<<16)
  1260. #define BNX2_MISC_NEW_HW_CTL 0x000008c4
  1261. #define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0)
  1262. #define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1)
  1263. #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2)
  1264. #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3)
  1265. #define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED (0xfffL<<4)
  1266. #define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffL<<16)
  1267. #define BNX2_MISC_NEW_CORE_CTL 0x000008c8
  1268. #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
  1269. #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
  1270. #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
  1271. #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
  1272. #define BNX2_MISC_ECO_HW_CTL 0x000008cc
  1273. #define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0)
  1274. #define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffL<<1)
  1275. #define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD (0xffffL<<16)
  1276. #define BNX2_MISC_ECO_CORE_CTL 0x000008d0
  1277. #define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffL<<0)
  1278. #define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffL<<16)
  1279. #define BNX2_MISC_PPIO 0x000008d4
  1280. #define BNX2_MISC_PPIO_VALUE (0xfL<<0)
  1281. #define BNX2_MISC_PPIO_SET (0xfL<<8)
  1282. #define BNX2_MISC_PPIO_CLR (0xfL<<16)
  1283. #define BNX2_MISC_PPIO_FLOAT (0xfL<<24)
  1284. #define BNX2_MISC_PPIO_INT 0x000008d8
  1285. #define BNX2_MISC_PPIO_INT_INT_STATE (0xfL<<0)
  1286. #define BNX2_MISC_PPIO_INT_OLD_VALUE (0xfL<<8)
  1287. #define BNX2_MISC_PPIO_INT_OLD_SET (0xfL<<16)
  1288. #define BNX2_MISC_PPIO_INT_OLD_CLR (0xfL<<24)
  1289. #define BNX2_MISC_RESET_NUMS 0x000008dc
  1290. #define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS (0x7L<<0)
  1291. #define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7L<<4)
  1292. #define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7L<<8)
  1293. #define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS (0x7L<<12)
  1294. #define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS (0x7L<<16)
  1295. #define BNX2_MISC_CS16_ERR 0x000008e0
  1296. #define BNX2_MISC_CS16_ERR_ENA_PCI (1L<<0)
  1297. #define BNX2_MISC_CS16_ERR_ENA_RDMA (1L<<1)
  1298. #define BNX2_MISC_CS16_ERR_ENA_TDMA (1L<<2)
  1299. #define BNX2_MISC_CS16_ERR_ENA_EMAC (1L<<3)
  1300. #define BNX2_MISC_CS16_ERR_ENA_CTX (1L<<4)
  1301. #define BNX2_MISC_CS16_ERR_ENA_TBDR (1L<<5)
  1302. #define BNX2_MISC_CS16_ERR_ENA_RBDC (1L<<6)
  1303. #define BNX2_MISC_CS16_ERR_ENA_COM (1L<<7)
  1304. #define BNX2_MISC_CS16_ERR_ENA_CP (1L<<8)
  1305. #define BNX2_MISC_CS16_ERR_STA_PCI (1L<<16)
  1306. #define BNX2_MISC_CS16_ERR_STA_RDMA (1L<<17)
  1307. #define BNX2_MISC_CS16_ERR_STA_TDMA (1L<<18)
  1308. #define BNX2_MISC_CS16_ERR_STA_EMAC (1L<<19)
  1309. #define BNX2_MISC_CS16_ERR_STA_CTX (1L<<20)
  1310. #define BNX2_MISC_CS16_ERR_STA_TBDR (1L<<21)
  1311. #define BNX2_MISC_CS16_ERR_STA_RBDC (1L<<22)
  1312. #define BNX2_MISC_CS16_ERR_STA_COM (1L<<23)
  1313. #define BNX2_MISC_CS16_ERR_STA_CP (1L<<24)
  1314. #define BNX2_MISC_SPIO_EVENT 0x000008e4
  1315. #define BNX2_MISC_SPIO_EVENT_ENABLE (0xffL<<0)
  1316. #define BNX2_MISC_PPIO_EVENT 0x000008e8
  1317. #define BNX2_MISC_PPIO_EVENT_ENABLE (0xfL<<0)
  1318. #define BNX2_MISC_DUAL_MEDIA_CTRL 0x000008ec
  1319. #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0)
  1320. #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0)
  1321. #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0)
  1322. #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0)
  1323. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8)
  1324. #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11)
  1325. #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12)
  1326. #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13)
  1327. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14)
  1328. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15)
  1329. #define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16)
  1330. #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17)
  1331. #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18)
  1332. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19)
  1333. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20)
  1334. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21)
  1335. #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24)
  1336. #define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25)
  1337. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26)
  1338. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26)
  1339. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26)
  1340. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26)
  1341. #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26)
  1342. #define BNX2_MISC_OTP_CMD1 0x000008f0
  1343. #define BNX2_MISC_OTP_CMD1_FMODE (0x7L<<0)
  1344. #define BNX2_MISC_OTP_CMD1_FMODE_IDLE (0L<<0)
  1345. #define BNX2_MISC_OTP_CMD1_FMODE_WRITE (1L<<0)
  1346. #define BNX2_MISC_OTP_CMD1_FMODE_INIT (2L<<0)
  1347. #define BNX2_MISC_OTP_CMD1_FMODE_SET (3L<<0)
  1348. #define BNX2_MISC_OTP_CMD1_FMODE_RST (4L<<0)
  1349. #define BNX2_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0)
  1350. #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0)
  1351. #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0)
  1352. #define BNX2_MISC_OTP_CMD1_USEPINS (1L<<8)
  1353. #define BNX2_MISC_OTP_CMD1_PROGSEL (1L<<9)
  1354. #define BNX2_MISC_OTP_CMD1_PROGSTART (1L<<10)
  1355. #define BNX2_MISC_OTP_CMD1_PCOUNT (0x7L<<16)
  1356. #define BNX2_MISC_OTP_CMD1_PBYP (1L<<19)
  1357. #define BNX2_MISC_OTP_CMD1_VSEL (0xfL<<20)
  1358. #define BNX2_MISC_OTP_CMD1_TM (0x7L<<27)
  1359. #define BNX2_MISC_OTP_CMD1_SADBYP (1L<<30)
  1360. #define BNX2_MISC_OTP_CMD1_DEBUG (1L<<31)
  1361. #define BNX2_MISC_OTP_CMD2 0x000008f4
  1362. #define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffL<<0)
  1363. #define BNX2_MISC_OTP_CMD2_DOSEL (0x7fL<<16)
  1364. #define BNX2_MISC_OTP_CMD2_DOSEL_0 (0L<<16)
  1365. #define BNX2_MISC_OTP_CMD2_DOSEL_1 (1L<<16)
  1366. #define BNX2_MISC_OTP_CMD2_DOSEL_127 (127L<<16)
  1367. #define BNX2_MISC_OTP_STATUS 0x000008f8
  1368. #define BNX2_MISC_OTP_STATUS_DATA (0xffL<<0)
  1369. #define BNX2_MISC_OTP_STATUS_VALID (1L<<8)
  1370. #define BNX2_MISC_OTP_STATUS_BUSY (1L<<9)
  1371. #define BNX2_MISC_OTP_STATUS_BUSYSM (1L<<10)
  1372. #define BNX2_MISC_OTP_STATUS_DONE (1L<<11)
  1373. #define BNX2_MISC_OTP_SHIFT1_CMD 0x000008fc
  1374. #define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0)
  1375. #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1)
  1376. #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2)
  1377. #define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3)
  1378. #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fL<<8)
  1379. #define BNX2_MISC_OTP_SHIFT1_DATA 0x00000900
  1380. #define BNX2_MISC_OTP_SHIFT2_CMD 0x00000904
  1381. #define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0)
  1382. #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1)
  1383. #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2)
  1384. #define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3)
  1385. #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fL<<8)
  1386. #define BNX2_MISC_OTP_SHIFT2_DATA 0x00000908
  1387. #define BNX2_MISC_BIST_CS0 0x0000090c
  1388. #define BNX2_MISC_BIST_CS0_MBIST_EN (1L<<0)
  1389. #define BNX2_MISC_BIST_CS0_BIST_SETUP (0x3L<<1)
  1390. #define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3)
  1391. #define BNX2_MISC_BIST_CS0_MBIST_DONE (1L<<8)
  1392. #define BNX2_MISC_BIST_CS0_MBIST_GO (1L<<9)
  1393. #define BNX2_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31)
  1394. #define BNX2_MISC_BIST_MEMSTATUS0 0x00000910
  1395. #define BNX2_MISC_BIST_CS1 0x00000914
  1396. #define BNX2_MISC_BIST_CS1_MBIST_EN (1L<<0)
  1397. #define BNX2_MISC_BIST_CS1_BIST_SETUP (0x3L<<1)
  1398. #define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3)
  1399. #define BNX2_MISC_BIST_CS1_MBIST_DONE (1L<<8)
  1400. #define BNX2_MISC_BIST_CS1_MBIST_GO (1L<<9)
  1401. #define BNX2_MISC_BIST_MEMSTATUS1 0x00000918
  1402. #define BNX2_MISC_BIST_CS2 0x0000091c
  1403. #define BNX2_MISC_BIST_CS2_MBIST_EN (1L<<0)
  1404. #define BNX2_MISC_BIST_CS2_BIST_SETUP (0x3L<<1)
  1405. #define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3)
  1406. #define BNX2_MISC_BIST_CS2_MBIST_DONE (1L<<8)
  1407. #define BNX2_MISC_BIST_CS2_MBIST_GO (1L<<9)
  1408. #define BNX2_MISC_BIST_MEMSTATUS2 0x00000920
  1409. #define BNX2_MISC_BIST_CS3 0x00000924
  1410. #define BNX2_MISC_BIST_CS3_MBIST_EN (1L<<0)
  1411. #define BNX2_MISC_BIST_CS3_BIST_SETUP (0x3L<<1)
  1412. #define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3)
  1413. #define BNX2_MISC_BIST_CS3_MBIST_DONE (1L<<8)
  1414. #define BNX2_MISC_BIST_CS3_MBIST_GO (1L<<9)
  1415. #define BNX2_MISC_BIST_MEMSTATUS3 0x00000928
  1416. #define BNX2_MISC_BIST_CS4 0x0000092c
  1417. #define BNX2_MISC_BIST_CS4_MBIST_EN (1L<<0)
  1418. #define BNX2_MISC_BIST_CS4_BIST_SETUP (0x3L<<1)
  1419. #define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3)
  1420. #define BNX2_MISC_BIST_CS4_MBIST_DONE (1L<<8)
  1421. #define BNX2_MISC_BIST_CS4_MBIST_GO (1L<<9)
  1422. #define BNX2_MISC_BIST_MEMSTATUS4 0x00000930
  1423. #define BNX2_MISC_BIST_CS5 0x00000934
  1424. #define BNX2_MISC_BIST_CS5_MBIST_EN (1L<<0)
  1425. #define BNX2_MISC_BIST_CS5_BIST_SETUP (0x3L<<1)
  1426. #define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3)
  1427. #define BNX2_MISC_BIST_CS5_MBIST_DONE (1L<<8)
  1428. #define BNX2_MISC_BIST_CS5_MBIST_GO (1L<<9)
  1429. #define BNX2_MISC_BIST_MEMSTATUS5 0x00000938
  1430. #define BNX2_MISC_MEM_TM0 0x0000093c
  1431. #define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM (0xfL<<0)
  1432. #define BNX2_MISC_MEM_TM0_MCP_SCPAD (0xfL<<8)
  1433. #define BNX2_MISC_MEM_TM0_UMP_TM (0xffL<<16)
  1434. #define BNX2_MISC_MEM_TM0_HB_MEM_TM (0xfL<<24)
  1435. #define BNX2_MISC_USPLL_CTRL 0x00000940
  1436. #define BNX2_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0)
  1437. #define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1)
  1438. #define BNX2_MISC_USPLL_CTRL_LCPX (0x3fL<<2)
  1439. #define BNX2_MISC_USPLL_CTRL_RX (0x3L<<8)
  1440. #define BNX2_MISC_USPLL_CTRL_VC_EN (1L<<10)
  1441. #define BNX2_MISC_USPLL_CTRL_VCO_MG (0x3L<<11)
  1442. #define BNX2_MISC_USPLL_CTRL_KVCO_XF (0x7L<<13)
  1443. #define BNX2_MISC_USPLL_CTRL_KVCO_XS (0x7L<<16)
  1444. #define BNX2_MISC_USPLL_CTRL_TESTD_EN (1L<<19)
  1445. #define BNX2_MISC_USPLL_CTRL_TESTD_SEL (0x7L<<20)
  1446. #define BNX2_MISC_USPLL_CTRL_TESTA_EN (1L<<23)
  1447. #define BNX2_MISC_USPLL_CTRL_TESTA_SEL (0x3L<<24)
  1448. #define BNX2_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26)
  1449. #define BNX2_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27)
  1450. #define BNX2_MISC_USPLL_CTRL_ANALOG_RST (1L<<28)
  1451. #define BNX2_MISC_USPLL_CTRL_LOCK (1L<<29)
  1452. #define BNX2_MISC_PERR_STATUS0 0x00000944
  1453. #define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0)
  1454. #define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1)
  1455. #define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2)
  1456. #define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3)
  1457. #define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4)
  1458. #define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5)
  1459. #define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6)
  1460. #define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7)
  1461. #define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8)
  1462. #define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9)
  1463. #define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10)
  1464. #define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11)
  1465. #define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12)
  1466. #define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13)
  1467. #define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14)
  1468. #define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15)
  1469. #define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16)
  1470. #define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17)
  1471. #define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18)
  1472. #define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19)
  1473. #define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20)
  1474. #define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21)
  1475. #define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22)
  1476. #define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23)
  1477. #define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24)
  1478. #define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25)
  1479. #define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26)
  1480. #define BNX2_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27)
  1481. #define BNX2_MISC_PERR_STATUS0_THBUF_PERR (1L<<28)
  1482. #define BNX2_MISC_PERR_STATUS0_TDMA_PERR (1L<<29)
  1483. #define BNX2_MISC_PERR_STATUS0_TBDC_PERR (1L<<30)
  1484. #define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31)
  1485. #define BNX2_MISC_PERR_STATUS1 0x00000948
  1486. #define BNX2_MISC_PERR_STATUS1_RBDC_PERR (1L<<0)
  1487. #define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2)
  1488. #define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3)
  1489. #define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4)
  1490. #define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5)
  1491. #define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6)
  1492. #define BNX2_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7)
  1493. #define BNX2_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8)
  1494. #define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9)
  1495. #define BNX2_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10)
  1496. #define BNX2_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11)
  1497. #define BNX2_MISC_PERR_STATUS1_COMQ_PERR (1L<<12)
  1498. #define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13)
  1499. #define BNX2_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14)
  1500. #define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15)
  1501. #define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16)
  1502. #define BNX2_MISC_PERR_STATUS1_TASQ_PERR (1L<<17)
  1503. #define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18)
  1504. #define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19)
  1505. #define BNX2_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20)
  1506. #define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21)
  1507. #define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22)
  1508. #define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23)
  1509. #define BNX2_MISC_PERR_STATUS1_CPQ_PERR (1L<<24)
  1510. #define BNX2_MISC_PERR_STATUS1_CSQ_PERR (1L<<25)
  1511. #define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26)
  1512. #define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27)
  1513. #define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28)
  1514. #define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29)
  1515. #define BNX2_MISC_PERR_STATUS2 0x0000094c
  1516. #define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0)
  1517. #define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1)
  1518. #define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2)
  1519. #define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3)
  1520. #define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4)
  1521. #define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5)
  1522. #define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6)
  1523. #define BNX2_MISC_LCPLL_CTRL0 0x00000950
  1524. #define BNX2_MISC_LCPLL_CTRL0_OAC (0x7L<<0)
  1525. #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0)
  1526. #define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0)
  1527. #define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0)
  1528. #define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0)
  1529. #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL (0x7L<<3)
  1530. #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3)
  1531. #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3)
  1532. #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3)
  1533. #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3)
  1534. #define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL (0x3L<<6)
  1535. #define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7L<<8)
  1536. #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL (0x3L<<11)
  1537. #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11)
  1538. #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11)
  1539. #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11)
  1540. #define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13)
  1541. #define BNX2_MISC_LCPLL_CTRL0_RESERVED (1L<<14)
  1542. #define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15)
  1543. #define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16)
  1544. #define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17)
  1545. #define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18)
  1546. #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19)
  1547. #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20)
  1548. #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21)
  1549. #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22)
  1550. #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23)
  1551. #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24)
  1552. #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25)
  1553. #define BNX2_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26)
  1554. #define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27)
  1555. #define BNX2_MISC_LCPLL_CTRL1 0x00000954
  1556. #define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM (0x1fL<<0)
  1557. #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5)
  1558. #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6)
  1559. #define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7)
  1560. #define BNX2_MISC_LCPLL_STATUS 0x00000958
  1561. #define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0)
  1562. #define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1)
  1563. #define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2)
  1564. #define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3)
  1565. #define BNX2_MISC_LCPLL_STATUS_PLLSTATE (0x7L<<4)
  1566. #define BNX2_MISC_LCPLL_STATUS_CAPSTATE (0x7L<<7)
  1567. #define BNX2_MISC_LCPLL_STATUS_CAPSELECT (0x1fL<<10)
  1568. #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15)
  1569. #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15)
  1570. #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15)
  1571. #define BNX2_MISC_OSCFUNDS_CTRL 0x0000095c
  1572. #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5)
  1573. #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5)
  1574. #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5)
  1575. #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3L<<6)
  1576. #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6)
  1577. #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6)
  1578. #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6)
  1579. #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6)
  1580. #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3L<<8)
  1581. #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8)
  1582. #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8)
  1583. #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8)
  1584. #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8)
  1585. #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3L<<10)
  1586. #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10)
  1587. #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10)
  1588. #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10)
  1589. #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10)
  1590. /*
  1591. * nvm_reg definition
  1592. * offset: 0x6400
  1593. */
  1594. #define BNX2_NVM_COMMAND 0x00006400
  1595. #define BNX2_NVM_COMMAND_RST (1L<<0)
  1596. #define BNX2_NVM_COMMAND_DONE (1L<<3)
  1597. #define BNX2_NVM_COMMAND_DOIT (1L<<4)
  1598. #define BNX2_NVM_COMMAND_WR (1L<<5)
  1599. #define BNX2_NVM_COMMAND_ERASE (1L<<6)
  1600. #define BNX2_NVM_COMMAND_FIRST (1L<<7)
  1601. #define BNX2_NVM_COMMAND_LAST (1L<<8)
  1602. #define BNX2_NVM_COMMAND_WREN (1L<<16)
  1603. #define BNX2_NVM_COMMAND_WRDI (1L<<17)
  1604. #define BNX2_NVM_COMMAND_EWSR (1L<<18)
  1605. #define BNX2_NVM_COMMAND_WRSR (1L<<19)
  1606. #define BNX2_NVM_COMMAND_RD_ID (1L<<20)
  1607. #define BNX2_NVM_COMMAND_RD_STATUS (1L<<21)
  1608. #define BNX2_NVM_COMMAND_MODE_256 (1L<<22)
  1609. #define BNX2_NVM_STATUS 0x00006404
  1610. #define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
  1611. #define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
  1612. #define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
  1613. #define BNX2_NVM_STATUS_SPI_FSM_STATE_XI (0x1fL<<0)
  1614. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI (0L<<0)
  1615. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI (1L<<0)
  1616. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI (2L<<0)
  1617. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI (3L<<0)
  1618. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI (4L<<0)
  1619. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI (5L<<0)
  1620. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI (6L<<0)
  1621. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI (7L<<0)
  1622. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI (8L<<0)
  1623. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI (9L<<0)
  1624. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI (10L<<0)
  1625. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI (11L<<0)
  1626. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI (12L<<0)
  1627. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI (13L<<0)
  1628. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI (14L<<0)
  1629. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI (15L<<0)
  1630. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI (16L<<0)
  1631. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI (17L<<0)
  1632. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI (18L<<0)
  1633. #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI (19L<<0)
  1634. #define BNX2_NVM_WRITE 0x00006408
  1635. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
  1636. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
  1637. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
  1638. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
  1639. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
  1640. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
  1641. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
  1642. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
  1643. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI (1L<<0)
  1644. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI (2L<<0)
  1645. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI (4L<<0)
  1646. #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI (8L<<0)
  1647. #define BNX2_NVM_ADDR 0x0000640c
  1648. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
  1649. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
  1650. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
  1651. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
  1652. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
  1653. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
  1654. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
  1655. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
  1656. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI (1L<<0)
  1657. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI (2L<<0)
  1658. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI (4L<<0)
  1659. #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI (8L<<0)
  1660. #define BNX2_NVM_READ 0x00006410
  1661. #define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
  1662. #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
  1663. #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
  1664. #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
  1665. #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
  1666. #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
  1667. #define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
  1668. #define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
  1669. #define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI (1L<<0)
  1670. #define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI (2L<<0)
  1671. #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI (4L<<0)
  1672. #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI (8L<<0)
  1673. #define BNX2_NVM_CFG1 0x00006414
  1674. #define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
  1675. #define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1)
  1676. #define BNX2_NVM_CFG1_PASS_MODE (1L<<2)
  1677. #define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3)
  1678. #define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4)
  1679. #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
  1680. #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
  1681. #define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
  1682. #define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
  1683. #define BNX2_NVM_CFG1_STRAP_CONTROL_0 (1L<<23)
  1684. #define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24)
  1685. #define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25)
  1686. #define BNX2_NVM_CFG1_FW_USTRAP_1 (1L<<26)
  1687. #define BNX2_NVM_CFG1_FW_USTRAP_0 (1L<<27)
  1688. #define BNX2_NVM_CFG1_FW_USTRAP_2 (1L<<28)
  1689. #define BNX2_NVM_CFG1_FW_USTRAP_3 (1L<<29)
  1690. #define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN (1L<<30)
  1691. #define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
  1692. #define BNX2_NVM_CFG2 0x00006418
  1693. #define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0)
  1694. #define BNX2_NVM_CFG2_DUMMY (0xffL<<8)
  1695. #define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16)
  1696. #define BNX2_NVM_CFG2_READ_ID (0xffL<<24)
  1697. #define BNX2_NVM_CFG3 0x0000641c
  1698. #define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
  1699. #define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8)
  1700. #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
  1701. #define BNX2_NVM_CFG3_READ_CMD (0xffL<<24)
  1702. #define BNX2_NVM_SW_ARB 0x00006420
  1703. #define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
  1704. #define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
  1705. #define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
  1706. #define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
  1707. #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
  1708. #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
  1709. #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
  1710. #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
  1711. #define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8)
  1712. #define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9)
  1713. #define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10)
  1714. #define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11)
  1715. #define BNX2_NVM_SW_ARB_REQ0 (1L<<12)
  1716. #define BNX2_NVM_SW_ARB_REQ1 (1L<<13)
  1717. #define BNX2_NVM_SW_ARB_REQ2 (1L<<14)
  1718. #define BNX2_NVM_SW_ARB_REQ3 (1L<<15)
  1719. #define BNX2_NVM_ACCESS_ENABLE 0x00006424
  1720. #define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0)
  1721. #define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
  1722. #define BNX2_NVM_WRITE1 0x00006428
  1723. #define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0)
  1724. #define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8)
  1725. #define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16)
  1726. #define BNX2_NVM_CFG4 0x0000642c
  1727. #define BNX2_NVM_CFG4_FLASH_SIZE (0x7L<<0)
  1728. #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0)
  1729. #define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT (1L<<0)
  1730. #define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT (2L<<0)
  1731. #define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT (3L<<0)
  1732. #define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT (4L<<0)
  1733. #define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT (5L<<0)
  1734. #define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT (6L<<0)
  1735. #define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT (7L<<0)
  1736. #define BNX2_NVM_CFG4_FLASH_VENDOR (1L<<3)
  1737. #define BNX2_NVM_CFG4_FLASH_VENDOR_ST (0L<<3)
  1738. #define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL (1L<<3)
  1739. #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3L<<4)
  1740. #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0L<<4)
  1741. #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1L<<4)
  1742. #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2L<<4)
  1743. #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3L<<4)
  1744. #define BNX2_NVM_CFG4_STATUS_BIT_POLARITY (1L<<6)
  1745. #define BNX2_NVM_CFG4_RESERVED (0x1ffffffL<<7)
  1746. #define BNX2_NVM_RECONFIG 0x00006430
  1747. #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfL<<0)
  1748. #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0L<<0)
  1749. #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1L<<0)
  1750. #define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfL<<4)
  1751. #define BNX2_NVM_RECONFIG_RESERVED (0x7fffffL<<8)
  1752. #define BNX2_NVM_RECONFIG_RECONFIG_DONE (1L<<31)
  1753. /*
  1754. * dma_reg definition
  1755. * offset: 0xc00
  1756. */
  1757. #define BNX2_DMA_COMMAND 0x00000c00
  1758. #define BNX2_DMA_COMMAND_ENABLE (1L<<0)
  1759. #define BNX2_DMA_STATUS 0x00000c04
  1760. #define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
  1761. #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
  1762. #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
  1763. #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
  1764. #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
  1765. #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
  1766. #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
  1767. #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
  1768. #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
  1769. #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
  1770. #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
  1771. #define BNX2_DMA_STATUS_GLOBAL_ERR_XI (1L<<0)
  1772. #define BNX2_DMA_STATUS_BME_XI (1L<<4)
  1773. #define BNX2_DMA_CONFIG 0x00000c08
  1774. #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
  1775. #define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
  1776. #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
  1777. #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
  1778. #define BNX2_DMA_CONFIG_ONE_DMA (1L<<6)
  1779. #define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
  1780. #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
  1781. #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
  1782. #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
  1783. #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
  1784. #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
  1785. #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
  1786. #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
  1787. #define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24)
  1788. #define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
  1789. #define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
  1790. #define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
  1791. #define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
  1792. #define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
  1793. #define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI (0x3L<<0)
  1794. #define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI (0x3L<<4)
  1795. #define BNX2_DMA_CONFIG_MAX_PL_XI (0x7L<<12)
  1796. #define BNX2_DMA_CONFIG_MAX_PL_128B_XI (0L<<12)
  1797. #define BNX2_DMA_CONFIG_MAX_PL_256B_XI (1L<<12)
  1798. #define BNX2_DMA_CONFIG_MAX_PL_512B_XI (2L<<12)
  1799. #define BNX2_DMA_CONFIG_MAX_PL_EN_XI (1L<<15)
  1800. #define BNX2_DMA_CONFIG_MAX_RRS_XI (0x7L<<16)
  1801. #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI (0L<<16)
  1802. #define BNX2_DMA_CONFIG_MAX_RRS_256B_XI (1L<<16)
  1803. #define BNX2_DMA_CONFIG_MAX_RRS_512B_XI (2L<<16)
  1804. #define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI (3L<<16)
  1805. #define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI (4L<<16)
  1806. #define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI (5L<<16)
  1807. #define BNX2_DMA_CONFIG_MAX_RRS_EN_XI (1L<<19)
  1808. #define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI (1L<<31)
  1809. #define BNX2_DMA_BLACKOUT 0x00000c0c
  1810. #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
  1811. #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
  1812. #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
  1813. #define BNX2_DMA_READ_MASTER_SETTING_0 0x00000c10
  1814. #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP (1L<<0)
  1815. #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER (1L<<1)
  1816. #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY (1L<<2)
  1817. #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS (0x7L<<4)
  1818. #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN (1L<<7)
  1819. #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP (1L<<8)
  1820. #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER (1L<<9)
  1821. #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY (1L<<10)
  1822. #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS (0x7L<<12)
  1823. #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN (1L<<15)
  1824. #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP (1L<<16)
  1825. #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER (1L<<17)
  1826. #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY (1L<<18)
  1827. #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS (0x7L<<20)
  1828. #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN (1L<<23)
  1829. #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP (1L<<24)
  1830. #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER (1L<<25)
  1831. #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY (1L<<26)
  1832. #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7L<<28)
  1833. #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN (1L<<31)
  1834. #define BNX2_DMA_READ_MASTER_SETTING_1 0x00000c14
  1835. #define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0)
  1836. #define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER (1L<<1)
  1837. #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY (1L<<2)
  1838. #define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7L<<4)
  1839. #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN (1L<<7)
  1840. #define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP (1L<<8)
  1841. #define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER (1L<<9)
  1842. #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY (1L<<10)
  1843. #define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7L<<12)
  1844. #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN (1L<<15)
  1845. #define BNX2_DMA_WRITE_MASTER_SETTING_0 0x00000c18
  1846. #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP (1L<<0)
  1847. #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER (1L<<1)
  1848. #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY (1L<<2)
  1849. #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD (1L<<3)
  1850. #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS (0x7L<<4)
  1851. #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN (1L<<7)
  1852. #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP (1L<<8)
  1853. #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER (1L<<9)
  1854. #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY (1L<<10)
  1855. #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD (1L<<11)
  1856. #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS (0x7L<<12)
  1857. #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN (1L<<15)
  1858. #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP (1L<<24)
  1859. #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER (1L<<25)
  1860. #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY (1L<<26)
  1861. #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD (1L<<27)
  1862. #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7L<<28)
  1863. #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN (1L<<31)
  1864. #define BNX2_DMA_WRITE_MASTER_SETTING_1 0x00000c1c
  1865. #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0)
  1866. #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER (1L<<1)
  1867. #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY (1L<<2)
  1868. #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD (1L<<3)
  1869. #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7L<<4)
  1870. #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN (1L<<7)
  1871. #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP (1L<<8)
  1872. #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER (1L<<9)
  1873. #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY (1L<<10)
  1874. #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD (1L<<11)
  1875. #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7L<<12)
  1876. #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN (1L<<15)
  1877. #define BNX2_DMA_ARBITER 0x00000c20
  1878. #define BNX2_DMA_ARBITER_NUM_READS (0x7L<<0)
  1879. #define BNX2_DMA_ARBITER_WR_ARB_MODE (1L<<4)
  1880. #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT (0L<<4)
  1881. #define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN (1L<<4)
  1882. #define BNX2_DMA_ARBITER_RD_ARB_MODE (0x3L<<5)
  1883. #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT (0L<<5)
  1884. #define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN (1L<<5)
  1885. #define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN (2L<<5)
  1886. #define BNX2_DMA_ARBITER_ALT_MODE_EN (1L<<8)
  1887. #define BNX2_DMA_ARBITER_RR_MODE (1L<<9)
  1888. #define BNX2_DMA_ARBITER_TIMER_MODE (1L<<10)
  1889. #define BNX2_DMA_ARBITER_OUSTD_READ_REQ (0xfL<<12)
  1890. #define BNX2_DMA_ARB_TIMERS 0x00000c24
  1891. #define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME (0xffL<<0)
  1892. #define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT (0xffL<<12)
  1893. #define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT (0xfffL<<20)
  1894. #define BNX2_DMA_DEBUG_VECT_PEEK 0x00000c2c
  1895. #define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  1896. #define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  1897. #define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  1898. #define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  1899. #define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  1900. #define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  1901. #define BNX2_DMA_TAG_RAM_00 0x00000c30
  1902. #define BNX2_DMA_TAG_RAM_00_CHANNEL (0xfL<<0)
  1903. #define BNX2_DMA_TAG_RAM_00_MASTER (0x7L<<4)
  1904. #define BNX2_DMA_TAG_RAM_00_MASTER_CTX (0L<<4)
  1905. #define BNX2_DMA_TAG_RAM_00_MASTER_RBDC (1L<<4)
  1906. #define BNX2_DMA_TAG_RAM_00_MASTER_TBDC (2L<<4)
  1907. #define BNX2_DMA_TAG_RAM_00_MASTER_COM (3L<<4)
  1908. #define BNX2_DMA_TAG_RAM_00_MASTER_CP (4L<<4)
  1909. #define BNX2_DMA_TAG_RAM_00_MASTER_TDMA (5L<<4)
  1910. #define BNX2_DMA_TAG_RAM_00_SWAP (0x3L<<7)
  1911. #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG (0L<<7)
  1912. #define BNX2_DMA_TAG_RAM_00_SWAP_DATA (1L<<7)
  1913. #define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL (2L<<7)
  1914. #define BNX2_DMA_TAG_RAM_00_FUNCTION (1L<<9)
  1915. #define BNX2_DMA_TAG_RAM_00_VALID (1L<<10)
  1916. #define BNX2_DMA_TAG_RAM_01 0x00000c34
  1917. #define BNX2_DMA_TAG_RAM_01_CHANNEL (0xfL<<0)
  1918. #define BNX2_DMA_TAG_RAM_01_MASTER (0x7L<<4)
  1919. #define BNX2_DMA_TAG_RAM_01_MASTER_CTX (0L<<4)
  1920. #define BNX2_DMA_TAG_RAM_01_MASTER_RBDC (1L<<4)
  1921. #define BNX2_DMA_TAG_RAM_01_MASTER_TBDC (2L<<4)
  1922. #define BNX2_DMA_TAG_RAM_01_MASTER_COM (3L<<4)
  1923. #define BNX2_DMA_TAG_RAM_01_MASTER_CP (4L<<4)
  1924. #define BNX2_DMA_TAG_RAM_01_MASTER_TDMA (5L<<4)
  1925. #define BNX2_DMA_TAG_RAM_01_SWAP (0x3L<<7)
  1926. #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG (0L<<7)
  1927. #define BNX2_DMA_TAG_RAM_01_SWAP_DATA (1L<<7)
  1928. #define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL (2L<<7)
  1929. #define BNX2_DMA_TAG_RAM_01_FUNCTION (1L<<9)
  1930. #define BNX2_DMA_TAG_RAM_01_VALID (1L<<10)
  1931. #define BNX2_DMA_TAG_RAM_02 0x00000c38
  1932. #define BNX2_DMA_TAG_RAM_02_CHANNEL (0xfL<<0)
  1933. #define BNX2_DMA_TAG_RAM_02_MASTER (0x7L<<4)
  1934. #define BNX2_DMA_TAG_RAM_02_MASTER_CTX (0L<<4)
  1935. #define BNX2_DMA_TAG_RAM_02_MASTER_RBDC (1L<<4)
  1936. #define BNX2_DMA_TAG_RAM_02_MASTER_TBDC (2L<<4)
  1937. #define BNX2_DMA_TAG_RAM_02_MASTER_COM (3L<<4)
  1938. #define BNX2_DMA_TAG_RAM_02_MASTER_CP (4L<<4)
  1939. #define BNX2_DMA_TAG_RAM_02_MASTER_TDMA (5L<<4)
  1940. #define BNX2_DMA_TAG_RAM_02_SWAP (0x3L<<7)
  1941. #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG (0L<<7)
  1942. #define BNX2_DMA_TAG_RAM_02_SWAP_DATA (1L<<7)
  1943. #define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL (2L<<7)
  1944. #define BNX2_DMA_TAG_RAM_02_FUNCTION (1L<<9)
  1945. #define BNX2_DMA_TAG_RAM_02_VALID (1L<<10)
  1946. #define BNX2_DMA_TAG_RAM_03 0x00000c3c
  1947. #define BNX2_DMA_TAG_RAM_03_CHANNEL (0xfL<<0)
  1948. #define BNX2_DMA_TAG_RAM_03_MASTER (0x7L<<4)
  1949. #define BNX2_DMA_TAG_RAM_03_MASTER_CTX (0L<<4)
  1950. #define BNX2_DMA_TAG_RAM_03_MASTER_RBDC (1L<<4)
  1951. #define BNX2_DMA_TAG_RAM_03_MASTER_TBDC (2L<<4)
  1952. #define BNX2_DMA_TAG_RAM_03_MASTER_COM (3L<<4)
  1953. #define BNX2_DMA_TAG_RAM_03_MASTER_CP (4L<<4)
  1954. #define BNX2_DMA_TAG_RAM_03_MASTER_TDMA (5L<<4)
  1955. #define BNX2_DMA_TAG_RAM_03_SWAP (0x3L<<7)
  1956. #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG (0L<<7)
  1957. #define BNX2_DMA_TAG_RAM_03_SWAP_DATA (1L<<7)
  1958. #define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL (2L<<7)
  1959. #define BNX2_DMA_TAG_RAM_03_FUNCTION (1L<<9)
  1960. #define BNX2_DMA_TAG_RAM_03_VALID (1L<<10)
  1961. #define BNX2_DMA_TAG_RAM_04 0x00000c40
  1962. #define BNX2_DMA_TAG_RAM_04_CHANNEL (0xfL<<0)
  1963. #define BNX2_DMA_TAG_RAM_04_MASTER (0x7L<<4)
  1964. #define BNX2_DMA_TAG_RAM_04_MASTER_CTX (0L<<4)
  1965. #define BNX2_DMA_TAG_RAM_04_MASTER_RBDC (1L<<4)
  1966. #define BNX2_DMA_TAG_RAM_04_MASTER_TBDC (2L<<4)
  1967. #define BNX2_DMA_TAG_RAM_04_MASTER_COM (3L<<4)
  1968. #define BNX2_DMA_TAG_RAM_04_MASTER_CP (4L<<4)
  1969. #define BNX2_DMA_TAG_RAM_04_MASTER_TDMA (5L<<4)
  1970. #define BNX2_DMA_TAG_RAM_04_SWAP (0x3L<<7)
  1971. #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG (0L<<7)
  1972. #define BNX2_DMA_TAG_RAM_04_SWAP_DATA (1L<<7)
  1973. #define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL (2L<<7)
  1974. #define BNX2_DMA_TAG_RAM_04_FUNCTION (1L<<9)
  1975. #define BNX2_DMA_TAG_RAM_04_VALID (1L<<10)
  1976. #define BNX2_DMA_TAG_RAM_05 0x00000c44
  1977. #define BNX2_DMA_TAG_RAM_05_CHANNEL (0xfL<<0)
  1978. #define BNX2_DMA_TAG_RAM_05_MASTER (0x7L<<4)
  1979. #define BNX2_DMA_TAG_RAM_05_MASTER_CTX (0L<<4)
  1980. #define BNX2_DMA_TAG_RAM_05_MASTER_RBDC (1L<<4)
  1981. #define BNX2_DMA_TAG_RAM_05_MASTER_TBDC (2L<<4)
  1982. #define BNX2_DMA_TAG_RAM_05_MASTER_COM (3L<<4)
  1983. #define BNX2_DMA_TAG_RAM_05_MASTER_CP (4L<<4)
  1984. #define BNX2_DMA_TAG_RAM_05_MASTER_TDMA (5L<<4)
  1985. #define BNX2_DMA_TAG_RAM_05_SWAP (0x3L<<7)
  1986. #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG (0L<<7)
  1987. #define BNX2_DMA_TAG_RAM_05_SWAP_DATA (1L<<7)
  1988. #define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL (2L<<7)
  1989. #define BNX2_DMA_TAG_RAM_05_FUNCTION (1L<<9)
  1990. #define BNX2_DMA_TAG_RAM_05_VALID (1L<<10)
  1991. #define BNX2_DMA_TAG_RAM_06 0x00000c48
  1992. #define BNX2_DMA_TAG_RAM_06_CHANNEL (0xfL<<0)
  1993. #define BNX2_DMA_TAG_RAM_06_MASTER (0x7L<<4)
  1994. #define BNX2_DMA_TAG_RAM_06_MASTER_CTX (0L<<4)
  1995. #define BNX2_DMA_TAG_RAM_06_MASTER_RBDC (1L<<4)
  1996. #define BNX2_DMA_TAG_RAM_06_MASTER_TBDC (2L<<4)
  1997. #define BNX2_DMA_TAG_RAM_06_MASTER_COM (3L<<4)
  1998. #define BNX2_DMA_TAG_RAM_06_MASTER_CP (4L<<4)
  1999. #define BNX2_DMA_TAG_RAM_06_MASTER_TDMA (5L<<4)
  2000. #define BNX2_DMA_TAG_RAM_06_SWAP (0x3L<<7)
  2001. #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG (0L<<7)
  2002. #define BNX2_DMA_TAG_RAM_06_SWAP_DATA (1L<<7)
  2003. #define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL (2L<<7)
  2004. #define BNX2_DMA_TAG_RAM_06_FUNCTION (1L<<9)
  2005. #define BNX2_DMA_TAG_RAM_06_VALID (1L<<10)
  2006. #define BNX2_DMA_TAG_RAM_07 0x00000c4c
  2007. #define BNX2_DMA_TAG_RAM_07_CHANNEL (0xfL<<0)
  2008. #define BNX2_DMA_TAG_RAM_07_MASTER (0x7L<<4)
  2009. #define BNX2_DMA_TAG_RAM_07_MASTER_CTX (0L<<4)
  2010. #define BNX2_DMA_TAG_RAM_07_MASTER_RBDC (1L<<4)
  2011. #define BNX2_DMA_TAG_RAM_07_MASTER_TBDC (2L<<4)
  2012. #define BNX2_DMA_TAG_RAM_07_MASTER_COM (3L<<4)
  2013. #define BNX2_DMA_TAG_RAM_07_MASTER_CP (4L<<4)
  2014. #define BNX2_DMA_TAG_RAM_07_MASTER_TDMA (5L<<4)
  2015. #define BNX2_DMA_TAG_RAM_07_SWAP (0x3L<<7)
  2016. #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG (0L<<7)
  2017. #define BNX2_DMA_TAG_RAM_07_SWAP_DATA (1L<<7)
  2018. #define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL (2L<<7)
  2019. #define BNX2_DMA_TAG_RAM_07_FUNCTION (1L<<9)
  2020. #define BNX2_DMA_TAG_RAM_07_VALID (1L<<10)
  2021. #define BNX2_DMA_TAG_RAM_08 0x00000c50
  2022. #define BNX2_DMA_TAG_RAM_08_CHANNEL (0xfL<<0)
  2023. #define BNX2_DMA_TAG_RAM_08_MASTER (0x7L<<4)
  2024. #define BNX2_DMA_TAG_RAM_08_MASTER_CTX (0L<<4)
  2025. #define BNX2_DMA_TAG_RAM_08_MASTER_RBDC (1L<<4)
  2026. #define BNX2_DMA_TAG_RAM_08_MASTER_TBDC (2L<<4)
  2027. #define BNX2_DMA_TAG_RAM_08_MASTER_COM (3L<<4)
  2028. #define BNX2_DMA_TAG_RAM_08_MASTER_CP (4L<<4)
  2029. #define BNX2_DMA_TAG_RAM_08_MASTER_TDMA (5L<<4)
  2030. #define BNX2_DMA_TAG_RAM_08_SWAP (0x3L<<7)
  2031. #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG (0L<<7)
  2032. #define BNX2_DMA_TAG_RAM_08_SWAP_DATA (1L<<7)
  2033. #define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL (2L<<7)
  2034. #define BNX2_DMA_TAG_RAM_08_FUNCTION (1L<<9)
  2035. #define BNX2_DMA_TAG_RAM_08_VALID (1L<<10)
  2036. #define BNX2_DMA_TAG_RAM_09 0x00000c54
  2037. #define BNX2_DMA_TAG_RAM_09_CHANNEL (0xfL<<0)
  2038. #define BNX2_DMA_TAG_RAM_09_MASTER (0x7L<<4)
  2039. #define BNX2_DMA_TAG_RAM_09_MASTER_CTX (0L<<4)
  2040. #define BNX2_DMA_TAG_RAM_09_MASTER_RBDC (1L<<4)
  2041. #define BNX2_DMA_TAG_RAM_09_MASTER_TBDC (2L<<4)
  2042. #define BNX2_DMA_TAG_RAM_09_MASTER_COM (3L<<4)
  2043. #define BNX2_DMA_TAG_RAM_09_MASTER_CP (4L<<4)
  2044. #define BNX2_DMA_TAG_RAM_09_MASTER_TDMA (5L<<4)
  2045. #define BNX2_DMA_TAG_RAM_09_SWAP (0x3L<<7)
  2046. #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG (0L<<7)
  2047. #define BNX2_DMA_TAG_RAM_09_SWAP_DATA (1L<<7)
  2048. #define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL (2L<<7)
  2049. #define BNX2_DMA_TAG_RAM_09_FUNCTION (1L<<9)
  2050. #define BNX2_DMA_TAG_RAM_09_VALID (1L<<10)
  2051. #define BNX2_DMA_TAG_RAM_10 0x00000c58
  2052. #define BNX2_DMA_TAG_RAM_10_CHANNEL (0xfL<<0)
  2053. #define BNX2_DMA_TAG_RAM_10_MASTER (0x7L<<4)
  2054. #define BNX2_DMA_TAG_RAM_10_MASTER_CTX (0L<<4)
  2055. #define BNX2_DMA_TAG_RAM_10_MASTER_RBDC (1L<<4)
  2056. #define BNX2_DMA_TAG_RAM_10_MASTER_TBDC (2L<<4)
  2057. #define BNX2_DMA_TAG_RAM_10_MASTER_COM (3L<<4)
  2058. #define BNX2_DMA_TAG_RAM_10_MASTER_CP (4L<<4)
  2059. #define BNX2_DMA_TAG_RAM_10_MASTER_TDMA (5L<<4)
  2060. #define BNX2_DMA_TAG_RAM_10_SWAP (0x3L<<7)
  2061. #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG (0L<<7)
  2062. #define BNX2_DMA_TAG_RAM_10_SWAP_DATA (1L<<7)
  2063. #define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL (2L<<7)
  2064. #define BNX2_DMA_TAG_RAM_10_FUNCTION (1L<<9)
  2065. #define BNX2_DMA_TAG_RAM_10_VALID (1L<<10)
  2066. #define BNX2_DMA_TAG_RAM_11 0x00000c5c
  2067. #define BNX2_DMA_TAG_RAM_11_CHANNEL (0xfL<<0)
  2068. #define BNX2_DMA_TAG_RAM_11_MASTER (0x7L<<4)
  2069. #define BNX2_DMA_TAG_RAM_11_MASTER_CTX (0L<<4)
  2070. #define BNX2_DMA_TAG_RAM_11_MASTER_RBDC (1L<<4)
  2071. #define BNX2_DMA_TAG_RAM_11_MASTER_TBDC (2L<<4)
  2072. #define BNX2_DMA_TAG_RAM_11_MASTER_COM (3L<<4)
  2073. #define BNX2_DMA_TAG_RAM_11_MASTER_CP (4L<<4)
  2074. #define BNX2_DMA_TAG_RAM_11_MASTER_TDMA (5L<<4)
  2075. #define BNX2_DMA_TAG_RAM_11_SWAP (0x3L<<7)
  2076. #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG (0L<<7)
  2077. #define BNX2_DMA_TAG_RAM_11_SWAP_DATA (1L<<7)
  2078. #define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL (2L<<7)
  2079. #define BNX2_DMA_TAG_RAM_11_FUNCTION (1L<<9)
  2080. #define BNX2_DMA_TAG_RAM_11_VALID (1L<<10)
  2081. #define BNX2_DMA_RCHAN_STAT_22 0x00000c60
  2082. #define BNX2_DMA_RCHAN_STAT_30 0x00000c64
  2083. #define BNX2_DMA_RCHAN_STAT_31 0x00000c68
  2084. #define BNX2_DMA_RCHAN_STAT_32 0x00000c6c
  2085. #define BNX2_DMA_RCHAN_STAT_40 0x00000c70
  2086. #define BNX2_DMA_RCHAN_STAT_41 0x00000c74
  2087. #define BNX2_DMA_RCHAN_STAT_42 0x00000c78
  2088. #define BNX2_DMA_RCHAN_STAT_50 0x00000c7c
  2089. #define BNX2_DMA_RCHAN_STAT_51 0x00000c80
  2090. #define BNX2_DMA_RCHAN_STAT_52 0x00000c84
  2091. #define BNX2_DMA_RCHAN_STAT_60 0x00000c88
  2092. #define BNX2_DMA_RCHAN_STAT_61 0x00000c8c
  2093. #define BNX2_DMA_RCHAN_STAT_62 0x00000c90
  2094. #define BNX2_DMA_RCHAN_STAT_70 0x00000c94
  2095. #define BNX2_DMA_RCHAN_STAT_71 0x00000c98
  2096. #define BNX2_DMA_RCHAN_STAT_72 0x00000c9c
  2097. #define BNX2_DMA_WCHAN_STAT_00 0x00000ca0
  2098. #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
  2099. #define BNX2_DMA_WCHAN_STAT_01 0x00000ca4
  2100. #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
  2101. #define BNX2_DMA_WCHAN_STAT_02 0x00000ca8
  2102. #define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
  2103. #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
  2104. #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
  2105. #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
  2106. #define BNX2_DMA_WCHAN_STAT_10 0x00000cac
  2107. #define BNX2_DMA_WCHAN_STAT_11 0x00000cb0
  2108. #define BNX2_DMA_WCHAN_STAT_12 0x00000cb4
  2109. #define BNX2_DMA_WCHAN_STAT_20 0x00000cb8
  2110. #define BNX2_DMA_WCHAN_STAT_21 0x00000cbc
  2111. #define BNX2_DMA_WCHAN_STAT_22 0x00000cc0
  2112. #define BNX2_DMA_WCHAN_STAT_30 0x00000cc4
  2113. #define BNX2_DMA_WCHAN_STAT_31 0x00000cc8
  2114. #define BNX2_DMA_WCHAN_STAT_32 0x00000ccc
  2115. #define BNX2_DMA_WCHAN_STAT_40 0x00000cd0
  2116. #define BNX2_DMA_WCHAN_STAT_41 0x00000cd4
  2117. #define BNX2_DMA_WCHAN_STAT_42 0x00000cd8
  2118. #define BNX2_DMA_WCHAN_STAT_50 0x00000cdc
  2119. #define BNX2_DMA_WCHAN_STAT_51 0x00000ce0
  2120. #define BNX2_DMA_WCHAN_STAT_52 0x00000ce4
  2121. #define BNX2_DMA_WCHAN_STAT_60 0x00000ce8
  2122. #define BNX2_DMA_WCHAN_STAT_61 0x00000cec
  2123. #define BNX2_DMA_WCHAN_STAT_62 0x00000cf0
  2124. #define BNX2_DMA_WCHAN_STAT_70 0x00000cf4
  2125. #define BNX2_DMA_WCHAN_STAT_71 0x00000cf8
  2126. #define BNX2_DMA_WCHAN_STAT_72 0x00000cfc
  2127. #define BNX2_DMA_ARB_STAT_00 0x00000d00
  2128. #define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
  2129. #define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
  2130. #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
  2131. #define BNX2_DMA_ARB_STAT_01 0x00000d04
  2132. #define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
  2133. #define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
  2134. #define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
  2135. #define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
  2136. #define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
  2137. #define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
  2138. #define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
  2139. #define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
  2140. #define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00
  2141. #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
  2142. #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
  2143. #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
  2144. #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
  2145. #define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
  2146. #define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04
  2147. #define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08
  2148. #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
  2149. #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
  2150. #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
  2151. #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
  2152. #define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
  2153. #define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c
  2154. #define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10
  2155. #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
  2156. #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
  2157. #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
  2158. #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
  2159. #define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
  2160. #define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14
  2161. /*
  2162. * context_reg definition
  2163. * offset: 0x1000
  2164. */
  2165. #define BNX2_CTX_COMMAND 0x00001000
  2166. #define BNX2_CTX_COMMAND_ENABLED (1L<<0)
  2167. #define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1)
  2168. #define BNX2_CTX_COMMAND_DISABLE_PLRU (1L<<2)
  2169. #define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3)
  2170. #define BNX2_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8)
  2171. #define BNX2_CTX_COMMAND_MEM_INIT (1L<<13)
  2172. #define BNX2_CTX_COMMAND_PAGE_SIZE (0xfL<<16)
  2173. #define BNX2_CTX_COMMAND_PAGE_SIZE_256 (0L<<16)
  2174. #define BNX2_CTX_COMMAND_PAGE_SIZE_512 (1L<<16)
  2175. #define BNX2_CTX_COMMAND_PAGE_SIZE_1K (2L<<16)
  2176. #define BNX2_CTX_COMMAND_PAGE_SIZE_2K (3L<<16)
  2177. #define BNX2_CTX_COMMAND_PAGE_SIZE_4K (4L<<16)
  2178. #define BNX2_CTX_COMMAND_PAGE_SIZE_8K (5L<<16)
  2179. #define BNX2_CTX_COMMAND_PAGE_SIZE_16K (6L<<16)
  2180. #define BNX2_CTX_COMMAND_PAGE_SIZE_32K (7L<<16)
  2181. #define BNX2_CTX_COMMAND_PAGE_SIZE_64K (8L<<16)
  2182. #define BNX2_CTX_COMMAND_PAGE_SIZE_128K (9L<<16)
  2183. #define BNX2_CTX_COMMAND_PAGE_SIZE_256K (10L<<16)
  2184. #define BNX2_CTX_COMMAND_PAGE_SIZE_512K (11L<<16)
  2185. #define BNX2_CTX_COMMAND_PAGE_SIZE_1M (12L<<16)
  2186. #define BNX2_CTX_STATUS 0x00001004
  2187. #define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
  2188. #define BNX2_CTX_STATUS_READ_STAT (1L<<16)
  2189. #define BNX2_CTX_STATUS_WRITE_STAT (1L<<17)
  2190. #define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18)
  2191. #define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
  2192. #define BNX2_CTX_STATUS_EXT_READ_STAT (1L<<20)
  2193. #define BNX2_CTX_STATUS_EXT_WRITE_STAT (1L<<21)
  2194. #define BNX2_CTX_STATUS_MISS_STAT (1L<<22)
  2195. #define BNX2_CTX_STATUS_HIT_STAT (1L<<23)
  2196. #define BNX2_CTX_STATUS_DEAD_LOCK (1L<<24)
  2197. #define BNX2_CTX_STATUS_USAGE_CNT_ERR (1L<<25)
  2198. #define BNX2_CTX_STATUS_INVALID_PAGE (1L<<26)
  2199. #define BNX2_CTX_VIRT_ADDR 0x00001008
  2200. #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
  2201. #define BNX2_CTX_PAGE_TBL 0x0000100c
  2202. #define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
  2203. #define BNX2_CTX_DATA_ADR 0x00001010
  2204. #define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
  2205. #define BNX2_CTX_DATA 0x00001014
  2206. #define BNX2_CTX_LOCK 0x00001018
  2207. #define BNX2_CTX_LOCK_TYPE (0x7L<<0)
  2208. #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
  2209. #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
  2210. #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
  2211. #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
  2212. #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
  2213. #define BNX2_CTX_LOCK_TYPE_VOID_XI (0L<<0)
  2214. #define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0)
  2215. #define BNX2_CTX_LOCK_TYPE_TX_XI (2L<<0)
  2216. #define BNX2_CTX_LOCK_TYPE_TIMER_XI (4L<<0)
  2217. #define BNX2_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0)
  2218. #define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7)
  2219. #define BNX2_CTX_LOCK_GRANTED (1L<<26)
  2220. #define BNX2_CTX_LOCK_MODE (0x7L<<27)
  2221. #define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
  2222. #define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
  2223. #define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27)
  2224. #define BNX2_CTX_LOCK_STATUS (1L<<30)
  2225. #define BNX2_CTX_LOCK_REQ (1L<<31)
  2226. #define BNX2_CTX_CTX_CTRL 0x0000101c
  2227. #define BNX2_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2)
  2228. #define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21)
  2229. #define BNX2_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23)
  2230. #define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24)
  2231. #define BNX2_CTX_CTX_CTRL_ATTR (1L<<26)
  2232. #define BNX2_CTX_CTX_CTRL_WRITE_REQ (1L<<30)
  2233. #define BNX2_CTX_CTX_CTRL_READ_REQ (1L<<31)
  2234. #define BNX2_CTX_CTX_DATA 0x00001020
  2235. #define BNX2_CTX_ACCESS_STATUS 0x00001040
  2236. #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
  2237. #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
  2238. #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
  2239. #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
  2240. #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
  2241. #define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0)
  2242. #define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5)
  2243. #define BNX2_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10)
  2244. #define BNX2_CTX_DBG_LOCK_STATUS 0x00001044
  2245. #define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
  2246. #define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
  2247. #define BNX2_CTX_CACHE_CTRL_STATUS 0x00001048
  2248. #define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0)
  2249. #define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1)
  2250. #define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6)
  2251. #define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fL<<7)
  2252. #define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fL<<13)
  2253. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19)
  2254. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20)
  2255. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21)
  2256. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22)
  2257. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23)
  2258. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24)
  2259. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25)
  2260. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26)
  2261. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27)
  2262. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28)
  2263. #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29)
  2264. #define BNX2_CTX_CACHE_CTRL_SM_STATUS 0x0000104c
  2265. #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7L<<0)
  2266. #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7L<<3)
  2267. #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7L<<6)
  2268. #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7L<<9)
  2269. #define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffL<<16)
  2270. #define BNX2_CTX_CACHE_STATUS 0x00001050
  2271. #define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffL<<0)
  2272. #define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffL<<16)
  2273. #define BNX2_CTX_DMA_STATUS 0x00001054
  2274. #define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3L<<0)
  2275. #define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3L<<2)
  2276. #define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3L<<4)
  2277. #define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3L<<6)
  2278. #define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3L<<8)
  2279. #define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3L<<10)
  2280. #define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3L<<12)
  2281. #define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3L<<14)
  2282. #define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3L<<16)
  2283. #define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3L<<18)
  2284. #define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3L<<20)
  2285. #define BNX2_CTX_REP_STATUS 0x00001058
  2286. #define BNX2_CTX_REP_STATUS_ERROR_ENTRY (0x3ffL<<0)
  2287. #define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fL<<10)
  2288. #define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16)
  2289. #define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17)
  2290. #define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18)
  2291. #define BNX2_CTX_CKSUM_ERROR_STATUS 0x0000105c
  2292. #define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
  2293. #define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
  2294. #define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080
  2295. #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
  2296. #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
  2297. #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
  2298. #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14)
  2299. #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7L<<15)
  2300. #define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084
  2301. #define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088
  2302. #define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c
  2303. #define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090
  2304. #define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094
  2305. #define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098
  2306. #define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c
  2307. #define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0
  2308. #define BNX2_CTX_CHNL_LOCK_STATUS_9 0x000010a4
  2309. #define BNX2_CTX_CACHE_DATA 0x000010c4
  2310. #define BNX2_CTX_HOST_PAGE_TBL_CTRL 0x000010c8
  2311. #define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0)
  2312. #define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30)
  2313. #define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31)
  2314. #define BNX2_CTX_HOST_PAGE_TBL_DATA0 0x000010cc
  2315. #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0)
  2316. #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8)
  2317. #define BNX2_CTX_HOST_PAGE_TBL_DATA1 0x000010d0
  2318. #define BNX2_CTX_CAM_CTRL 0x000010d4
  2319. #define BNX2_CTX_CAM_CTRL_CAM_ADDR (0x3ffL<<0)
  2320. #define BNX2_CTX_CAM_CTRL_RESET (1L<<27)
  2321. #define BNX2_CTX_CAM_CTRL_INVALIDATE (1L<<28)
  2322. #define BNX2_CTX_CAM_CTRL_SEARCH (1L<<29)
  2323. #define BNX2_CTX_CAM_CTRL_WRITE_REQ (1L<<30)
  2324. #define BNX2_CTX_CAM_CTRL_READ_REQ (1L<<31)
  2325. /*
  2326. * emac_reg definition
  2327. * offset: 0x1400
  2328. */
  2329. #define BNX2_EMAC_MODE 0x00001400
  2330. #define BNX2_EMAC_MODE_RESET (1L<<0)
  2331. #define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1)
  2332. #define BNX2_EMAC_MODE_PORT (0x3L<<2)
  2333. #define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
  2334. #define BNX2_EMAC_MODE_PORT_MII (1L<<2)
  2335. #define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
  2336. #define BNX2_EMAC_MODE_PORT_MII_10M (3L<<2)
  2337. #define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
  2338. #define BNX2_EMAC_MODE_25G_MODE (1L<<5)
  2339. #define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
  2340. #define BNX2_EMAC_MODE_TX_BURST (1L<<8)
  2341. #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
  2342. #define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10)
  2343. #define BNX2_EMAC_MODE_FORCE_LINK (1L<<11)
  2344. #define BNX2_EMAC_MODE_SERDES_MODE (1L<<12)
  2345. #define BNX2_EMAC_MODE_BOND_OVRD (1L<<13)
  2346. #define BNX2_EMAC_MODE_MPKT (1L<<18)
  2347. #define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19)
  2348. #define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20)
  2349. #define BNX2_EMAC_STATUS 0x00001404
  2350. #define BNX2_EMAC_STATUS_LINK (1L<<11)
  2351. #define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12)
  2352. #define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE (1L<<13)
  2353. #define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE (1L<<14)
  2354. #define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE (1L<<16)
  2355. #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0 (1L<<17)
  2356. #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
  2357. #define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22)
  2358. #define BNX2_EMAC_STATUS_MI_INT (1L<<23)
  2359. #define BNX2_EMAC_STATUS_AP_ERROR (1L<<24)
  2360. #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
  2361. #define BNX2_EMAC_ATTENTION_ENA 0x00001408
  2362. #define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11)
  2363. #define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE (1L<<14)
  2364. #define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE (1L<<16)
  2365. #define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
  2366. #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
  2367. #define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
  2368. #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
  2369. #define BNX2_EMAC_LED 0x0000140c
  2370. #define BNX2_EMAC_LED_OVERRIDE (1L<<0)
  2371. #define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1)
  2372. #define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2)
  2373. #define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3)
  2374. #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
  2375. #define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5)
  2376. #define BNX2_EMAC_LED_TRAFFIC (1L<<6)
  2377. #define BNX2_EMAC_LED_1000MB (1L<<7)
  2378. #define BNX2_EMAC_LED_100MB (1L<<8)
  2379. #define BNX2_EMAC_LED_10MB (1L<<9)
  2380. #define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10)
  2381. #define BNX2_EMAC_LED_2500MB (1L<<11)
  2382. #define BNX2_EMAC_LED_2500MB_OVERRIDE (1L<<12)
  2383. #define BNX2_EMAC_LED_ACTIVITY_SEL (0x3L<<17)
  2384. #define BNX2_EMAC_LED_ACTIVITY_SEL_0 (0L<<17)
  2385. #define BNX2_EMAC_LED_ACTIVITY_SEL_1 (1L<<17)
  2386. #define BNX2_EMAC_LED_ACTIVITY_SEL_2 (2L<<17)
  2387. #define BNX2_EMAC_LED_ACTIVITY_SEL_3 (3L<<17)
  2388. #define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19)
  2389. #define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31)
  2390. #define BNX2_EMAC_MAC_MATCH0 0x00001410
  2391. #define BNX2_EMAC_MAC_MATCH1 0x00001414
  2392. #define BNX2_EMAC_MAC_MATCH2 0x00001418
  2393. #define BNX2_EMAC_MAC_MATCH3 0x0000141c
  2394. #define BNX2_EMAC_MAC_MATCH4 0x00001420
  2395. #define BNX2_EMAC_MAC_MATCH5 0x00001424
  2396. #define BNX2_EMAC_MAC_MATCH6 0x00001428
  2397. #define BNX2_EMAC_MAC_MATCH7 0x0000142c
  2398. #define BNX2_EMAC_MAC_MATCH8 0x00001430
  2399. #define BNX2_EMAC_MAC_MATCH9 0x00001434
  2400. #define BNX2_EMAC_MAC_MATCH10 0x00001438
  2401. #define BNX2_EMAC_MAC_MATCH11 0x0000143c
  2402. #define BNX2_EMAC_MAC_MATCH12 0x00001440
  2403. #define BNX2_EMAC_MAC_MATCH13 0x00001444
  2404. #define BNX2_EMAC_MAC_MATCH14 0x00001448
  2405. #define BNX2_EMAC_MAC_MATCH15 0x0000144c
  2406. #define BNX2_EMAC_MAC_MATCH16 0x00001450
  2407. #define BNX2_EMAC_MAC_MATCH17 0x00001454
  2408. #define BNX2_EMAC_MAC_MATCH18 0x00001458
  2409. #define BNX2_EMAC_MAC_MATCH19 0x0000145c
  2410. #define BNX2_EMAC_MAC_MATCH20 0x00001460
  2411. #define BNX2_EMAC_MAC_MATCH21 0x00001464
  2412. #define BNX2_EMAC_MAC_MATCH22 0x00001468
  2413. #define BNX2_EMAC_MAC_MATCH23 0x0000146c
  2414. #define BNX2_EMAC_MAC_MATCH24 0x00001470
  2415. #define BNX2_EMAC_MAC_MATCH25 0x00001474
  2416. #define BNX2_EMAC_MAC_MATCH26 0x00001478
  2417. #define BNX2_EMAC_MAC_MATCH27 0x0000147c
  2418. #define BNX2_EMAC_MAC_MATCH28 0x00001480
  2419. #define BNX2_EMAC_MAC_MATCH29 0x00001484
  2420. #define BNX2_EMAC_MAC_MATCH30 0x00001488
  2421. #define BNX2_EMAC_MAC_MATCH31 0x0000148c
  2422. #define BNX2_EMAC_BACKOFF_SEED 0x00001498
  2423. #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
  2424. #define BNX2_EMAC_RX_MTU_SIZE 0x0000149c
  2425. #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
  2426. #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
  2427. #define BNX2_EMAC_SERDES_CNTL 0x000014a4
  2428. #define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0)
  2429. #define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3)
  2430. #define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
  2431. #define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
  2432. #define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10)
  2433. #define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11)
  2434. #define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12)
  2435. #define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
  2436. #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
  2437. #define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
  2438. #define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
  2439. #define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
  2440. #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
  2441. #define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
  2442. #define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
  2443. #define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
  2444. #define BNX2_EMAC_SERDES_STATUS 0x000014a8
  2445. #define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
  2446. #define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
  2447. #define BNX2_EMAC_MDIO_COMM 0x000014ac
  2448. #define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0)
  2449. #define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
  2450. #define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
  2451. #define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
  2452. #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
  2453. #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
  2454. #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
  2455. #define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
  2456. #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI (1L<<26)
  2457. #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI (1L<<26)
  2458. #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI (2L<<26)
  2459. #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI (2L<<26)
  2460. #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
  2461. #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
  2462. #define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28)
  2463. #define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29)
  2464. #define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30)
  2465. #define BNX2_EMAC_MDIO_STATUS 0x000014b0
  2466. #define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0)
  2467. #define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1)
  2468. #define BNX2_EMAC_MDIO_MODE 0x000014b4
  2469. #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
  2470. #define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
  2471. #define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
  2472. #define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9)
  2473. #define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
  2474. #define BNX2_EMAC_MDIO_MODE_MDC (1L<<11)
  2475. #define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12)
  2476. #define BNX2_EMAC_MDIO_MODE_EXT_MDINT (1L<<13)
  2477. #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
  2478. #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI (0x3fL<<16)
  2479. #define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI (1L<<31)
  2480. #define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8
  2481. #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
  2482. #define BNX2_EMAC_TX_MODE 0x000014bc
  2483. #define BNX2_EMAC_TX_MODE_RESET (1L<<0)
  2484. #define BNX2_EMAC_TX_MODE_CS16_TEST (1L<<2)
  2485. #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
  2486. #define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4)
  2487. #define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
  2488. #define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
  2489. #define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7)
  2490. #define BNX2_EMAC_TX_STATUS 0x000014c0
  2491. #define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0)
  2492. #define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
  2493. #define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2)
  2494. #define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3)
  2495. #define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4)
  2496. #define BNX2_EMAC_TX_STATUS_CS16_ERROR (1L<<5)
  2497. #define BNX2_EMAC_TX_LENGTHS 0x000014c4
  2498. #define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
  2499. #define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8)
  2500. #define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
  2501. #define BNX2_EMAC_RX_MODE 0x000014c8
  2502. #define BNX2_EMAC_RX_MODE_RESET (1L<<0)
  2503. #define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2)
  2504. #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
  2505. #define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
  2506. #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
  2507. #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
  2508. #define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7)
  2509. #define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
  2510. #define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
  2511. #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
  2512. #define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
  2513. #define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12)
  2514. #define BNX2_EMAC_RX_STATUS 0x000014cc
  2515. #define BNX2_EMAC_RX_STATUS_FFED (1L<<0)
  2516. #define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
  2517. #define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
  2518. #define BNX2_EMAC_MULTICAST_HASH0 0x000014d0
  2519. #define BNX2_EMAC_MULTICAST_HASH1 0x000014d4
  2520. #define BNX2_EMAC_MULTICAST_HASH2 0x000014d8
  2521. #define BNX2_EMAC_MULTICAST_HASH3 0x000014dc
  2522. #define BNX2_EMAC_MULTICAST_HASH4 0x000014e0
  2523. #define BNX2_EMAC_MULTICAST_HASH5 0x000014e4
  2524. #define BNX2_EMAC_MULTICAST_HASH6 0x000014e8
  2525. #define BNX2_EMAC_MULTICAST_HASH7 0x000014ec
  2526. #define BNX2_EMAC_CKSUM_ERROR_STATUS 0x000014f0
  2527. #define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
  2528. #define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
  2529. #define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
  2530. #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
  2531. #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
  2532. #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
  2533. #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
  2534. #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
  2535. #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
  2536. #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
  2537. #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
  2538. #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
  2539. #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
  2540. #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
  2541. #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
  2542. #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
  2543. #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
  2544. #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
  2545. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
  2546. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
  2547. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
  2548. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
  2549. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
  2550. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
  2551. #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x00001558
  2552. #define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c
  2553. #define BNX2_EMAC_RXMAC_DEBUG1 0x00001560
  2554. #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
  2555. #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
  2556. #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
  2557. #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
  2558. #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
  2559. #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
  2560. #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
  2561. #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
  2562. #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
  2563. #define BNX2_EMAC_RXMAC_DEBUG2 0x00001564
  2564. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
  2565. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
  2566. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
  2567. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
  2568. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
  2569. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
  2570. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
  2571. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
  2572. #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
  2573. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
  2574. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
  2575. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
  2576. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
  2577. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
  2578. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
  2579. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
  2580. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
  2581. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
  2582. #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
  2583. #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
  2584. #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
  2585. #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
  2586. #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
  2587. #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
  2588. #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
  2589. #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
  2590. #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
  2591. #define BNX2_EMAC_RXMAC_DEBUG3 0x00001568
  2592. #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
  2593. #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
  2594. #define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c
  2595. #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
  2596. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
  2597. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
  2598. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
  2599. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
  2600. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
  2601. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
  2602. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
  2603. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
  2604. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
  2605. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
  2606. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
  2607. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
  2608. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
  2609. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
  2610. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
  2611. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
  2612. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
  2613. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
  2614. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
  2615. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
  2616. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
  2617. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
  2618. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
  2619. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
  2620. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
  2621. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
  2622. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
  2623. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
  2624. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
  2625. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
  2626. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
  2627. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
  2628. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
  2629. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
  2630. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
  2631. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
  2632. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
  2633. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
  2634. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
  2635. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
  2636. #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
  2637. #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
  2638. #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
  2639. #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
  2640. #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
  2641. #define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND (1L<<26)
  2642. #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
  2643. #define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28)
  2644. #define BNX2_EMAC_RXMAC_DEBUG5 0x00001570
  2645. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
  2646. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
  2647. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
  2648. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
  2649. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
  2650. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
  2651. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
  2652. #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
  2653. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
  2654. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
  2655. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
  2656. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
  2657. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
  2658. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
  2659. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
  2660. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
  2661. #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
  2662. #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
  2663. #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
  2664. #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
  2665. #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
  2666. #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
  2667. #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
  2668. #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
  2669. #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
  2670. #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
  2671. #define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS 0x00001574
  2672. #define BNX2_EMAC_RX_STAT_AC0 0x00001580
  2673. #define BNX2_EMAC_RX_STAT_AC1 0x00001584
  2674. #define BNX2_EMAC_RX_STAT_AC2 0x00001588
  2675. #define BNX2_EMAC_RX_STAT_AC3 0x0000158c
  2676. #define BNX2_EMAC_RX_STAT_AC4 0x00001590
  2677. #define BNX2_EMAC_RX_STAT_AC5 0x00001594
  2678. #define BNX2_EMAC_RX_STAT_AC6 0x00001598
  2679. #define BNX2_EMAC_RX_STAT_AC7 0x0000159c
  2680. #define BNX2_EMAC_RX_STAT_AC8 0x000015a0
  2681. #define BNX2_EMAC_RX_STAT_AC9 0x000015a4
  2682. #define BNX2_EMAC_RX_STAT_AC10 0x000015a8
  2683. #define BNX2_EMAC_RX_STAT_AC11 0x000015ac
  2684. #define BNX2_EMAC_RX_STAT_AC12 0x000015b0
  2685. #define BNX2_EMAC_RX_STAT_AC13 0x000015b4
  2686. #define BNX2_EMAC_RX_STAT_AC14 0x000015b8
  2687. #define BNX2_EMAC_RX_STAT_AC15 0x000015bc
  2688. #define BNX2_EMAC_RX_STAT_AC16 0x000015c0
  2689. #define BNX2_EMAC_RX_STAT_AC17 0x000015c4
  2690. #define BNX2_EMAC_RX_STAT_AC18 0x000015c8
  2691. #define BNX2_EMAC_RX_STAT_AC19 0x000015cc
  2692. #define BNX2_EMAC_RX_STAT_AC20 0x000015d0
  2693. #define BNX2_EMAC_RX_STAT_AC21 0x000015d4
  2694. #define BNX2_EMAC_RX_STAT_AC22 0x000015d8
  2695. #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
  2696. #define BNX2_EMAC_RX_STAT_AC_28 0x000015f4
  2697. #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
  2698. #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
  2699. #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
  2700. #define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c
  2701. #define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
  2702. #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
  2703. #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
  2704. #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
  2705. #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
  2706. #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
  2707. #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
  2708. #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
  2709. #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
  2710. #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
  2711. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
  2712. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
  2713. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
  2714. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
  2715. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
  2716. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
  2717. #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x00001650
  2718. #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
  2719. #define BNX2_EMAC_TXMAC_DEBUG0 0x00001658
  2720. #define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c
  2721. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
  2722. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
  2723. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
  2724. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
  2725. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
  2726. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
  2727. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
  2728. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
  2729. #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
  2730. #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
  2731. #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
  2732. #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
  2733. #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
  2734. #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
  2735. #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
  2736. #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
  2737. #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
  2738. #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
  2739. #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
  2740. #define BNX2_EMAC_TXMAC_DEBUG2 0x00001660
  2741. #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
  2742. #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
  2743. #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
  2744. #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
  2745. #define BNX2_EMAC_TXMAC_DEBUG3 0x00001664
  2746. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
  2747. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
  2748. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
  2749. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
  2750. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
  2751. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
  2752. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
  2753. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
  2754. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
  2755. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
  2756. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
  2757. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
  2758. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
  2759. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
  2760. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
  2761. #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
  2762. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
  2763. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
  2764. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
  2765. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
  2766. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
  2767. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
  2768. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
  2769. #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
  2770. #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
  2771. #define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
  2772. #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
  2773. #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
  2774. #define BNX2_EMAC_TXMAC_DEBUG4 0x00001668
  2775. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
  2776. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
  2777. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
  2778. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
  2779. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
  2780. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
  2781. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
  2782. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
  2783. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
  2784. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
  2785. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
  2786. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
  2787. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
  2788. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
  2789. #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
  2790. #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
  2791. #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
  2792. #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
  2793. #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
  2794. #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
  2795. #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
  2796. #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
  2797. #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
  2798. #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
  2799. #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
  2800. #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
  2801. #define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31)
  2802. #define BNX2_EMAC_TX_STAT_AC0 0x00001680
  2803. #define BNX2_EMAC_TX_STAT_AC1 0x00001684
  2804. #define BNX2_EMAC_TX_STAT_AC2 0x00001688
  2805. #define BNX2_EMAC_TX_STAT_AC3 0x0000168c
  2806. #define BNX2_EMAC_TX_STAT_AC4 0x00001690
  2807. #define BNX2_EMAC_TX_STAT_AC5 0x00001694
  2808. #define BNX2_EMAC_TX_STAT_AC6 0x00001698
  2809. #define BNX2_EMAC_TX_STAT_AC7 0x0000169c
  2810. #define BNX2_EMAC_TX_STAT_AC8 0x000016a0
  2811. #define BNX2_EMAC_TX_STAT_AC9 0x000016a4
  2812. #define BNX2_EMAC_TX_STAT_AC10 0x000016a8
  2813. #define BNX2_EMAC_TX_STAT_AC11 0x000016ac
  2814. #define BNX2_EMAC_TX_STAT_AC12 0x000016b0
  2815. #define BNX2_EMAC_TX_STAT_AC13 0x000016b4
  2816. #define BNX2_EMAC_TX_STAT_AC14 0x000016b8
  2817. #define BNX2_EMAC_TX_STAT_AC15 0x000016bc
  2818. #define BNX2_EMAC_TX_STAT_AC16 0x000016c0
  2819. #define BNX2_EMAC_TX_STAT_AC17 0x000016c4
  2820. #define BNX2_EMAC_TX_STAT_AC18 0x000016c8
  2821. #define BNX2_EMAC_TX_STAT_AC19 0x000016cc
  2822. #define BNX2_EMAC_TX_STAT_AC20 0x000016d0
  2823. #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
  2824. #define BNX2_EMAC_TX_RATE_LIMIT_CTRL 0x000016fc
  2825. #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC (0x7fL<<0)
  2826. #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM (0x7fL<<16)
  2827. #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN (1L<<31)
  2828. /*
  2829. * rpm_reg definition
  2830. * offset: 0x1800
  2831. */
  2832. #define BNX2_RPM_COMMAND 0x00001800
  2833. #define BNX2_RPM_COMMAND_ENABLED (1L<<0)
  2834. #define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
  2835. #define BNX2_RPM_STATUS 0x00001804
  2836. #define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0)
  2837. #define BNX2_RPM_STATUS_FREE_WAIT (1L<<1)
  2838. #define BNX2_RPM_CONFIG 0x00001808
  2839. #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
  2840. #define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1)
  2841. #define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2)
  2842. #define BNX2_RPM_CONFIG_MP_KEEP (1L<<3)
  2843. #define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
  2844. #define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT (1L<<30)
  2845. #define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31)
  2846. #define BNX2_RPM_MGMT_PKT_CTRL 0x0000180c
  2847. #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT (0xfL<<0)
  2848. #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE (0xfL<<4)
  2849. #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN (1L<<30)
  2850. #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN (1L<<31)
  2851. #define BNX2_RPM_VLAN_MATCH0 0x00001810
  2852. #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
  2853. #define BNX2_RPM_VLAN_MATCH1 0x00001814
  2854. #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
  2855. #define BNX2_RPM_VLAN_MATCH2 0x00001818
  2856. #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
  2857. #define BNX2_RPM_VLAN_MATCH3 0x0000181c
  2858. #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
  2859. #define BNX2_RPM_SORT_USER0 0x00001820
  2860. #define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0)
  2861. #define BNX2_RPM_SORT_USER0_BC_EN (1L<<16)
  2862. #define BNX2_RPM_SORT_USER0_MC_EN (1L<<17)
  2863. #define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
  2864. #define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19)
  2865. #define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
  2866. #define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24)
  2867. #define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH (1L<<25)
  2868. #define BNX2_RPM_SORT_USER0_ENA (1L<<31)
  2869. #define BNX2_RPM_SORT_USER1 0x00001824
  2870. #define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0)
  2871. #define BNX2_RPM_SORT_USER1_BC_EN (1L<<16)
  2872. #define BNX2_RPM_SORT_USER1_MC_EN (1L<<17)
  2873. #define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
  2874. #define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19)
  2875. #define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
  2876. #define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24)
  2877. #define BNX2_RPM_SORT_USER1_ENA (1L<<31)
  2878. #define BNX2_RPM_SORT_USER2 0x00001828
  2879. #define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0)
  2880. #define BNX2_RPM_SORT_USER2_BC_EN (1L<<16)
  2881. #define BNX2_RPM_SORT_USER2_MC_EN (1L<<17)
  2882. #define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
  2883. #define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19)
  2884. #define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
  2885. #define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24)
  2886. #define BNX2_RPM_SORT_USER2_ENA (1L<<31)
  2887. #define BNX2_RPM_SORT_USER3 0x0000182c
  2888. #define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0)
  2889. #define BNX2_RPM_SORT_USER3_BC_EN (1L<<16)
  2890. #define BNX2_RPM_SORT_USER3_MC_EN (1L<<17)
  2891. #define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
  2892. #define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19)
  2893. #define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
  2894. #define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24)
  2895. #define BNX2_RPM_SORT_USER3_ENA (1L<<31)
  2896. #define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
  2897. #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
  2898. #define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848
  2899. #define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c
  2900. #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
  2901. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0 0x00001854
  2902. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN (0xffL<<0)
  2903. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER (0xffL<<16)
  2904. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE (1L<<30)
  2905. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN (1L<<31)
  2906. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1 0x00001858
  2907. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN (0xffL<<0)
  2908. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER (0xffL<<16)
  2909. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE (1L<<30)
  2910. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN (1L<<31)
  2911. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2 0x0000185c
  2912. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN (0xffL<<0)
  2913. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER (0xffL<<16)
  2914. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE (1L<<30)
  2915. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN (1L<<31)
  2916. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3 0x00001860
  2917. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN (0xffL<<0)
  2918. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER (0xffL<<16)
  2919. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE (1L<<30)
  2920. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN (1L<<31)
  2921. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4 0x00001864
  2922. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN (0xffL<<0)
  2923. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER (0xffL<<16)
  2924. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE (1L<<30)
  2925. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN (1L<<31)
  2926. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5 0x00001868
  2927. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN (0xffL<<0)
  2928. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER (0xffL<<16)
  2929. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE (1L<<30)
  2930. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN (1L<<31)
  2931. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6 0x0000186c
  2932. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN (0xffL<<0)
  2933. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER (0xffL<<16)
  2934. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE (1L<<30)
  2935. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN (1L<<31)
  2936. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7 0x00001870
  2937. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN (0xffL<<0)
  2938. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER (0xffL<<16)
  2939. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE (1L<<30)
  2940. #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN (1L<<31)
  2941. #define BNX2_RPM_STAT_AC0 0x00001880
  2942. #define BNX2_RPM_STAT_AC1 0x00001884
  2943. #define BNX2_RPM_STAT_AC2 0x00001888
  2944. #define BNX2_RPM_STAT_AC3 0x0000188c
  2945. #define BNX2_RPM_STAT_AC4 0x00001890
  2946. #define BNX2_RPM_RC_CNTL_16 0x000018e0
  2947. #define BNX2_RPM_RC_CNTL_16_OFFSET (0xffL<<0)
  2948. #define BNX2_RPM_RC_CNTL_16_CLASS (0x7L<<8)
  2949. #define BNX2_RPM_RC_CNTL_16_PRIORITY (1L<<11)
  2950. #define BNX2_RPM_RC_CNTL_16_P4 (1L<<12)
  2951. #define BNX2_RPM_RC_CNTL_16_HDR_TYPE (0x7L<<13)
  2952. #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START (0L<<13)
  2953. #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP (1L<<13)
  2954. #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP (2L<<13)
  2955. #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP (3L<<13)
  2956. #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA (4L<<13)
  2957. #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP (5L<<13)
  2958. #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6 (6L<<13)
  2959. #define BNX2_RPM_RC_CNTL_16_COMP (0x3L<<16)
  2960. #define BNX2_RPM_RC_CNTL_16_COMP_EQUAL (0L<<16)
  2961. #define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL (1L<<16)
  2962. #define BNX2_RPM_RC_CNTL_16_COMP_GREATER (2L<<16)
  2963. #define BNX2_RPM_RC_CNTL_16_COMP_LESS (3L<<16)
  2964. #define BNX2_RPM_RC_CNTL_16_MAP (1L<<18)
  2965. #define BNX2_RPM_RC_CNTL_16_SBIT (1L<<19)
  2966. #define BNX2_RPM_RC_CNTL_16_CMDSEL (0x1fL<<20)
  2967. #define BNX2_RPM_RC_CNTL_16_DISCARD (1L<<25)
  2968. #define BNX2_RPM_RC_CNTL_16_MASK (1L<<26)
  2969. #define BNX2_RPM_RC_CNTL_16_P1 (1L<<27)
  2970. #define BNX2_RPM_RC_CNTL_16_P2 (1L<<28)
  2971. #define BNX2_RPM_RC_CNTL_16_P3 (1L<<29)
  2972. #define BNX2_RPM_RC_CNTL_16_NBIT (1L<<30)
  2973. #define BNX2_RPM_RC_VALUE_MASK_16 0x000018e4
  2974. #define BNX2_RPM_RC_VALUE_MASK_16_VALUE (0xffffL<<0)
  2975. #define BNX2_RPM_RC_VALUE_MASK_16_MASK (0xffffL<<16)
  2976. #define BNX2_RPM_RC_CNTL_17 0x000018e8
  2977. #define BNX2_RPM_RC_CNTL_17_OFFSET (0xffL<<0)
  2978. #define BNX2_RPM_RC_CNTL_17_CLASS (0x7L<<8)
  2979. #define BNX2_RPM_RC_CNTL_17_PRIORITY (1L<<11)
  2980. #define BNX2_RPM_RC_CNTL_17_P4 (1L<<12)
  2981. #define BNX2_RPM_RC_CNTL_17_HDR_TYPE (0x7L<<13)
  2982. #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START (0L<<13)
  2983. #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP (1L<<13)
  2984. #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP (2L<<13)
  2985. #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP (3L<<13)
  2986. #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA (4L<<13)
  2987. #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP (5L<<13)
  2988. #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6 (6L<<13)
  2989. #define BNX2_RPM_RC_CNTL_17_COMP (0x3L<<16)
  2990. #define BNX2_RPM_RC_CNTL_17_COMP_EQUAL (0L<<16)
  2991. #define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL (1L<<16)
  2992. #define BNX2_RPM_RC_CNTL_17_COMP_GREATER (2L<<16)
  2993. #define BNX2_RPM_RC_CNTL_17_COMP_LESS (3L<<16)
  2994. #define BNX2_RPM_RC_CNTL_17_MAP (1L<<18)
  2995. #define BNX2_RPM_RC_CNTL_17_SBIT (1L<<19)
  2996. #define BNX2_RPM_RC_CNTL_17_CMDSEL (0x1fL<<20)
  2997. #define BNX2_RPM_RC_CNTL_17_DISCARD (1L<<25)
  2998. #define BNX2_RPM_RC_CNTL_17_MASK (1L<<26)
  2999. #define BNX2_RPM_RC_CNTL_17_P1 (1L<<27)
  3000. #define BNX2_RPM_RC_CNTL_17_P2 (1L<<28)
  3001. #define BNX2_RPM_RC_CNTL_17_P3 (1L<<29)
  3002. #define BNX2_RPM_RC_CNTL_17_NBIT (1L<<30)
  3003. #define BNX2_RPM_RC_VALUE_MASK_17 0x000018ec
  3004. #define BNX2_RPM_RC_VALUE_MASK_17_VALUE (0xffffL<<0)
  3005. #define BNX2_RPM_RC_VALUE_MASK_17_MASK (0xffffL<<16)
  3006. #define BNX2_RPM_RC_CNTL_18 0x000018f0
  3007. #define BNX2_RPM_RC_CNTL_18_OFFSET (0xffL<<0)
  3008. #define BNX2_RPM_RC_CNTL_18_CLASS (0x7L<<8)
  3009. #define BNX2_RPM_RC_CNTL_18_PRIORITY (1L<<11)
  3010. #define BNX2_RPM_RC_CNTL_18_P4 (1L<<12)
  3011. #define BNX2_RPM_RC_CNTL_18_HDR_TYPE (0x7L<<13)
  3012. #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START (0L<<13)
  3013. #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP (1L<<13)
  3014. #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP (2L<<13)
  3015. #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP (3L<<13)
  3016. #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA (4L<<13)
  3017. #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP (5L<<13)
  3018. #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6 (6L<<13)
  3019. #define BNX2_RPM_RC_CNTL_18_COMP (0x3L<<16)
  3020. #define BNX2_RPM_RC_CNTL_18_COMP_EQUAL (0L<<16)
  3021. #define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL (1L<<16)
  3022. #define BNX2_RPM_RC_CNTL_18_COMP_GREATER (2L<<16)
  3023. #define BNX2_RPM_RC_CNTL_18_COMP_LESS (3L<<16)
  3024. #define BNX2_RPM_RC_CNTL_18_MAP (1L<<18)
  3025. #define BNX2_RPM_RC_CNTL_18_SBIT (1L<<19)
  3026. #define BNX2_RPM_RC_CNTL_18_CMDSEL (0x1fL<<20)
  3027. #define BNX2_RPM_RC_CNTL_18_DISCARD (1L<<25)
  3028. #define BNX2_RPM_RC_CNTL_18_MASK (1L<<26)
  3029. #define BNX2_RPM_RC_CNTL_18_P1 (1L<<27)
  3030. #define BNX2_RPM_RC_CNTL_18_P2 (1L<<28)
  3031. #define BNX2_RPM_RC_CNTL_18_P3 (1L<<29)
  3032. #define BNX2_RPM_RC_CNTL_18_NBIT (1L<<30)
  3033. #define BNX2_RPM_RC_VALUE_MASK_18 0x000018f4
  3034. #define BNX2_RPM_RC_VALUE_MASK_18_VALUE (0xffffL<<0)
  3035. #define BNX2_RPM_RC_VALUE_MASK_18_MASK (0xffffL<<16)
  3036. #define BNX2_RPM_RC_CNTL_19 0x000018f8
  3037. #define BNX2_RPM_RC_CNTL_19_OFFSET (0xffL<<0)
  3038. #define BNX2_RPM_RC_CNTL_19_CLASS (0x7L<<8)
  3039. #define BNX2_RPM_RC_CNTL_19_PRIORITY (1L<<11)
  3040. #define BNX2_RPM_RC_CNTL_19_P4 (1L<<12)
  3041. #define BNX2_RPM_RC_CNTL_19_HDR_TYPE (0x7L<<13)
  3042. #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START (0L<<13)
  3043. #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP (1L<<13)
  3044. #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP (2L<<13)
  3045. #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP (3L<<13)
  3046. #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA (4L<<13)
  3047. #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP (5L<<13)
  3048. #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6 (6L<<13)
  3049. #define BNX2_RPM_RC_CNTL_19_COMP (0x3L<<16)
  3050. #define BNX2_RPM_RC_CNTL_19_COMP_EQUAL (0L<<16)
  3051. #define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL (1L<<16)
  3052. #define BNX2_RPM_RC_CNTL_19_COMP_GREATER (2L<<16)
  3053. #define BNX2_RPM_RC_CNTL_19_COMP_LESS (3L<<16)
  3054. #define BNX2_RPM_RC_CNTL_19_MAP (1L<<18)
  3055. #define BNX2_RPM_RC_CNTL_19_SBIT (1L<<19)
  3056. #define BNX2_RPM_RC_CNTL_19_CMDSEL (0x1fL<<20)
  3057. #define BNX2_RPM_RC_CNTL_19_DISCARD (1L<<25)
  3058. #define BNX2_RPM_RC_CNTL_19_MASK (1L<<26)
  3059. #define BNX2_RPM_RC_CNTL_19_P1 (1L<<27)
  3060. #define BNX2_RPM_RC_CNTL_19_P2 (1L<<28)
  3061. #define BNX2_RPM_RC_CNTL_19_P3 (1L<<29)
  3062. #define BNX2_RPM_RC_CNTL_19_NBIT (1L<<30)
  3063. #define BNX2_RPM_RC_VALUE_MASK_19 0x000018fc
  3064. #define BNX2_RPM_RC_VALUE_MASK_19_VALUE (0xffffL<<0)
  3065. #define BNX2_RPM_RC_VALUE_MASK_19_MASK (0xffffL<<16)
  3066. #define BNX2_RPM_RC_CNTL_0 0x00001900
  3067. #define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
  3068. #define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8)
  3069. #define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11)
  3070. #define BNX2_RPM_RC_CNTL_0_P4 (1L<<12)
  3071. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
  3072. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
  3073. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
  3074. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
  3075. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
  3076. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
  3077. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP (5L<<13)
  3078. #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6 (6L<<13)
  3079. #define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16)
  3080. #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
  3081. #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
  3082. #define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
  3083. #define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
  3084. #define BNX2_RPM_RC_CNTL_0_MAP_XI (1L<<18)
  3085. #define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19)
  3086. #define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
  3087. #define BNX2_RPM_RC_CNTL_0_MAP (1L<<24)
  3088. #define BNX2_RPM_RC_CNTL_0_CMDSEL_XI (0x1fL<<20)
  3089. #define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25)
  3090. #define BNX2_RPM_RC_CNTL_0_MASK (1L<<26)
  3091. #define BNX2_RPM_RC_CNTL_0_P1 (1L<<27)
  3092. #define BNX2_RPM_RC_CNTL_0_P2 (1L<<28)
  3093. #define BNX2_RPM_RC_CNTL_0_P3 (1L<<29)
  3094. #define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30)
  3095. #define BNX2_RPM_RC_VALUE_MASK_0 0x00001904
  3096. #define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
  3097. #define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
  3098. #define BNX2_RPM_RC_CNTL_1 0x00001908
  3099. #define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0)
  3100. #define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19)
  3101. #define BNX2_RPM_RC_CNTL_1_OFFSET_XI (0xffL<<0)
  3102. #define BNX2_RPM_RC_CNTL_1_CLASS_XI (0x7L<<8)
  3103. #define BNX2_RPM_RC_CNTL_1_PRIORITY_XI (1L<<11)
  3104. #define BNX2_RPM_RC_CNTL_1_P4_XI (1L<<12)
  3105. #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI (0x7L<<13)
  3106. #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI (0L<<13)
  3107. #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI (1L<<13)
  3108. #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI (2L<<13)
  3109. #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI (3L<<13)
  3110. #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI (4L<<13)
  3111. #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3112. #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI (6L<<13)
  3113. #define BNX2_RPM_RC_CNTL_1_COMP_XI (0x3L<<16)
  3114. #define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI (0L<<16)
  3115. #define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI (1L<<16)
  3116. #define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI (2L<<16)
  3117. #define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI (3L<<16)
  3118. #define BNX2_RPM_RC_CNTL_1_MAP_XI (1L<<18)
  3119. #define BNX2_RPM_RC_CNTL_1_SBIT_XI (1L<<19)
  3120. #define BNX2_RPM_RC_CNTL_1_CMDSEL_XI (0x1fL<<20)
  3121. #define BNX2_RPM_RC_CNTL_1_DISCARD_XI (1L<<25)
  3122. #define BNX2_RPM_RC_CNTL_1_MASK_XI (1L<<26)
  3123. #define BNX2_RPM_RC_CNTL_1_P1_XI (1L<<27)
  3124. #define BNX2_RPM_RC_CNTL_1_P2_XI (1L<<28)
  3125. #define BNX2_RPM_RC_CNTL_1_P3_XI (1L<<29)
  3126. #define BNX2_RPM_RC_CNTL_1_NBIT_XI (1L<<30)
  3127. #define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c
  3128. #define BNX2_RPM_RC_VALUE_MASK_1_VALUE (0xffffL<<0)
  3129. #define BNX2_RPM_RC_VALUE_MASK_1_MASK (0xffffL<<16)
  3130. #define BNX2_RPM_RC_CNTL_2 0x00001910
  3131. #define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0)
  3132. #define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19)
  3133. #define BNX2_RPM_RC_CNTL_2_OFFSET_XI (0xffL<<0)
  3134. #define BNX2_RPM_RC_CNTL_2_CLASS_XI (0x7L<<8)
  3135. #define BNX2_RPM_RC_CNTL_2_PRIORITY_XI (1L<<11)
  3136. #define BNX2_RPM_RC_CNTL_2_P4_XI (1L<<12)
  3137. #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI (0x7L<<13)
  3138. #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI (0L<<13)
  3139. #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI (1L<<13)
  3140. #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI (2L<<13)
  3141. #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI (3L<<13)
  3142. #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI (4L<<13)
  3143. #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3144. #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI (6L<<13)
  3145. #define BNX2_RPM_RC_CNTL_2_COMP_XI (0x3L<<16)
  3146. #define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI (0L<<16)
  3147. #define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI (1L<<16)
  3148. #define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI (2L<<16)
  3149. #define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI (3L<<16)
  3150. #define BNX2_RPM_RC_CNTL_2_MAP_XI (1L<<18)
  3151. #define BNX2_RPM_RC_CNTL_2_SBIT_XI (1L<<19)
  3152. #define BNX2_RPM_RC_CNTL_2_CMDSEL_XI (0x1fL<<20)
  3153. #define BNX2_RPM_RC_CNTL_2_DISCARD_XI (1L<<25)
  3154. #define BNX2_RPM_RC_CNTL_2_MASK_XI (1L<<26)
  3155. #define BNX2_RPM_RC_CNTL_2_P1_XI (1L<<27)
  3156. #define BNX2_RPM_RC_CNTL_2_P2_XI (1L<<28)
  3157. #define BNX2_RPM_RC_CNTL_2_P3_XI (1L<<29)
  3158. #define BNX2_RPM_RC_CNTL_2_NBIT_XI (1L<<30)
  3159. #define BNX2_RPM_RC_VALUE_MASK_2 0x00001914
  3160. #define BNX2_RPM_RC_VALUE_MASK_2_VALUE (0xffffL<<0)
  3161. #define BNX2_RPM_RC_VALUE_MASK_2_MASK (0xffffL<<16)
  3162. #define BNX2_RPM_RC_CNTL_3 0x00001918
  3163. #define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0)
  3164. #define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19)
  3165. #define BNX2_RPM_RC_CNTL_3_OFFSET_XI (0xffL<<0)
  3166. #define BNX2_RPM_RC_CNTL_3_CLASS_XI (0x7L<<8)
  3167. #define BNX2_RPM_RC_CNTL_3_PRIORITY_XI (1L<<11)
  3168. #define BNX2_RPM_RC_CNTL_3_P4_XI (1L<<12)
  3169. #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI (0x7L<<13)
  3170. #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI (0L<<13)
  3171. #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI (1L<<13)
  3172. #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI (2L<<13)
  3173. #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI (3L<<13)
  3174. #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI (4L<<13)
  3175. #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3176. #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI (6L<<13)
  3177. #define BNX2_RPM_RC_CNTL_3_COMP_XI (0x3L<<16)
  3178. #define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI (0L<<16)
  3179. #define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI (1L<<16)
  3180. #define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI (2L<<16)
  3181. #define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI (3L<<16)
  3182. #define BNX2_RPM_RC_CNTL_3_MAP_XI (1L<<18)
  3183. #define BNX2_RPM_RC_CNTL_3_SBIT_XI (1L<<19)
  3184. #define BNX2_RPM_RC_CNTL_3_CMDSEL_XI (0x1fL<<20)
  3185. #define BNX2_RPM_RC_CNTL_3_DISCARD_XI (1L<<25)
  3186. #define BNX2_RPM_RC_CNTL_3_MASK_XI (1L<<26)
  3187. #define BNX2_RPM_RC_CNTL_3_P1_XI (1L<<27)
  3188. #define BNX2_RPM_RC_CNTL_3_P2_XI (1L<<28)
  3189. #define BNX2_RPM_RC_CNTL_3_P3_XI (1L<<29)
  3190. #define BNX2_RPM_RC_CNTL_3_NBIT_XI (1L<<30)
  3191. #define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c
  3192. #define BNX2_RPM_RC_VALUE_MASK_3_VALUE (0xffffL<<0)
  3193. #define BNX2_RPM_RC_VALUE_MASK_3_MASK (0xffffL<<16)
  3194. #define BNX2_RPM_RC_CNTL_4 0x00001920
  3195. #define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0)
  3196. #define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19)
  3197. #define BNX2_RPM_RC_CNTL_4_OFFSET_XI (0xffL<<0)
  3198. #define BNX2_RPM_RC_CNTL_4_CLASS_XI (0x7L<<8)
  3199. #define BNX2_RPM_RC_CNTL_4_PRIORITY_XI (1L<<11)
  3200. #define BNX2_RPM_RC_CNTL_4_P4_XI (1L<<12)
  3201. #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI (0x7L<<13)
  3202. #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI (0L<<13)
  3203. #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI (1L<<13)
  3204. #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI (2L<<13)
  3205. #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI (3L<<13)
  3206. #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI (4L<<13)
  3207. #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3208. #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI (6L<<13)
  3209. #define BNX2_RPM_RC_CNTL_4_COMP_XI (0x3L<<16)
  3210. #define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI (0L<<16)
  3211. #define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI (1L<<16)
  3212. #define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI (2L<<16)
  3213. #define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI (3L<<16)
  3214. #define BNX2_RPM_RC_CNTL_4_MAP_XI (1L<<18)
  3215. #define BNX2_RPM_RC_CNTL_4_SBIT_XI (1L<<19)
  3216. #define BNX2_RPM_RC_CNTL_4_CMDSEL_XI (0x1fL<<20)
  3217. #define BNX2_RPM_RC_CNTL_4_DISCARD_XI (1L<<25)
  3218. #define BNX2_RPM_RC_CNTL_4_MASK_XI (1L<<26)
  3219. #define BNX2_RPM_RC_CNTL_4_P1_XI (1L<<27)
  3220. #define BNX2_RPM_RC_CNTL_4_P2_XI (1L<<28)
  3221. #define BNX2_RPM_RC_CNTL_4_P3_XI (1L<<29)
  3222. #define BNX2_RPM_RC_CNTL_4_NBIT_XI (1L<<30)
  3223. #define BNX2_RPM_RC_VALUE_MASK_4 0x00001924
  3224. #define BNX2_RPM_RC_VALUE_MASK_4_VALUE (0xffffL<<0)
  3225. #define BNX2_RPM_RC_VALUE_MASK_4_MASK (0xffffL<<16)
  3226. #define BNX2_RPM_RC_CNTL_5 0x00001928
  3227. #define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0)
  3228. #define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19)
  3229. #define BNX2_RPM_RC_CNTL_5_OFFSET_XI (0xffL<<0)
  3230. #define BNX2_RPM_RC_CNTL_5_CLASS_XI (0x7L<<8)
  3231. #define BNX2_RPM_RC_CNTL_5_PRIORITY_XI (1L<<11)
  3232. #define BNX2_RPM_RC_CNTL_5_P4_XI (1L<<12)
  3233. #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI (0x7L<<13)
  3234. #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI (0L<<13)
  3235. #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI (1L<<13)
  3236. #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI (2L<<13)
  3237. #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI (3L<<13)
  3238. #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI (4L<<13)
  3239. #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3240. #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI (6L<<13)
  3241. #define BNX2_RPM_RC_CNTL_5_COMP_XI (0x3L<<16)
  3242. #define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI (0L<<16)
  3243. #define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI (1L<<16)
  3244. #define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI (2L<<16)
  3245. #define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI (3L<<16)
  3246. #define BNX2_RPM_RC_CNTL_5_MAP_XI (1L<<18)
  3247. #define BNX2_RPM_RC_CNTL_5_SBIT_XI (1L<<19)
  3248. #define BNX2_RPM_RC_CNTL_5_CMDSEL_XI (0x1fL<<20)
  3249. #define BNX2_RPM_RC_CNTL_5_DISCARD_XI (1L<<25)
  3250. #define BNX2_RPM_RC_CNTL_5_MASK_XI (1L<<26)
  3251. #define BNX2_RPM_RC_CNTL_5_P1_XI (1L<<27)
  3252. #define BNX2_RPM_RC_CNTL_5_P2_XI (1L<<28)
  3253. #define BNX2_RPM_RC_CNTL_5_P3_XI (1L<<29)
  3254. #define BNX2_RPM_RC_CNTL_5_NBIT_XI (1L<<30)
  3255. #define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c
  3256. #define BNX2_RPM_RC_VALUE_MASK_5_VALUE (0xffffL<<0)
  3257. #define BNX2_RPM_RC_VALUE_MASK_5_MASK (0xffffL<<16)
  3258. #define BNX2_RPM_RC_CNTL_6 0x00001930
  3259. #define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0)
  3260. #define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19)
  3261. #define BNX2_RPM_RC_CNTL_6_OFFSET_XI (0xffL<<0)
  3262. #define BNX2_RPM_RC_CNTL_6_CLASS_XI (0x7L<<8)
  3263. #define BNX2_RPM_RC_CNTL_6_PRIORITY_XI (1L<<11)
  3264. #define BNX2_RPM_RC_CNTL_6_P4_XI (1L<<12)
  3265. #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI (0x7L<<13)
  3266. #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI (0L<<13)
  3267. #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI (1L<<13)
  3268. #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI (2L<<13)
  3269. #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI (3L<<13)
  3270. #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI (4L<<13)
  3271. #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3272. #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI (6L<<13)
  3273. #define BNX2_RPM_RC_CNTL_6_COMP_XI (0x3L<<16)
  3274. #define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI (0L<<16)
  3275. #define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI (1L<<16)
  3276. #define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI (2L<<16)
  3277. #define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI (3L<<16)
  3278. #define BNX2_RPM_RC_CNTL_6_MAP_XI (1L<<18)
  3279. #define BNX2_RPM_RC_CNTL_6_SBIT_XI (1L<<19)
  3280. #define BNX2_RPM_RC_CNTL_6_CMDSEL_XI (0x1fL<<20)
  3281. #define BNX2_RPM_RC_CNTL_6_DISCARD_XI (1L<<25)
  3282. #define BNX2_RPM_RC_CNTL_6_MASK_XI (1L<<26)
  3283. #define BNX2_RPM_RC_CNTL_6_P1_XI (1L<<27)
  3284. #define BNX2_RPM_RC_CNTL_6_P2_XI (1L<<28)
  3285. #define BNX2_RPM_RC_CNTL_6_P3_XI (1L<<29)
  3286. #define BNX2_RPM_RC_CNTL_6_NBIT_XI (1L<<30)
  3287. #define BNX2_RPM_RC_VALUE_MASK_6 0x00001934
  3288. #define BNX2_RPM_RC_VALUE_MASK_6_VALUE (0xffffL<<0)
  3289. #define BNX2_RPM_RC_VALUE_MASK_6_MASK (0xffffL<<16)
  3290. #define BNX2_RPM_RC_CNTL_7 0x00001938
  3291. #define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0)
  3292. #define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19)
  3293. #define BNX2_RPM_RC_CNTL_7_OFFSET_XI (0xffL<<0)
  3294. #define BNX2_RPM_RC_CNTL_7_CLASS_XI (0x7L<<8)
  3295. #define BNX2_RPM_RC_CNTL_7_PRIORITY_XI (1L<<11)
  3296. #define BNX2_RPM_RC_CNTL_7_P4_XI (1L<<12)
  3297. #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI (0x7L<<13)
  3298. #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI (0L<<13)
  3299. #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI (1L<<13)
  3300. #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI (2L<<13)
  3301. #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI (3L<<13)
  3302. #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI (4L<<13)
  3303. #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3304. #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI (6L<<13)
  3305. #define BNX2_RPM_RC_CNTL_7_COMP_XI (0x3L<<16)
  3306. #define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI (0L<<16)
  3307. #define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI (1L<<16)
  3308. #define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI (2L<<16)
  3309. #define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI (3L<<16)
  3310. #define BNX2_RPM_RC_CNTL_7_MAP_XI (1L<<18)
  3311. #define BNX2_RPM_RC_CNTL_7_SBIT_XI (1L<<19)
  3312. #define BNX2_RPM_RC_CNTL_7_CMDSEL_XI (0x1fL<<20)
  3313. #define BNX2_RPM_RC_CNTL_7_DISCARD_XI (1L<<25)
  3314. #define BNX2_RPM_RC_CNTL_7_MASK_XI (1L<<26)
  3315. #define BNX2_RPM_RC_CNTL_7_P1_XI (1L<<27)
  3316. #define BNX2_RPM_RC_CNTL_7_P2_XI (1L<<28)
  3317. #define BNX2_RPM_RC_CNTL_7_P3_XI (1L<<29)
  3318. #define BNX2_RPM_RC_CNTL_7_NBIT_XI (1L<<30)
  3319. #define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c
  3320. #define BNX2_RPM_RC_VALUE_MASK_7_VALUE (0xffffL<<0)
  3321. #define BNX2_RPM_RC_VALUE_MASK_7_MASK (0xffffL<<16)
  3322. #define BNX2_RPM_RC_CNTL_8 0x00001940
  3323. #define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0)
  3324. #define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19)
  3325. #define BNX2_RPM_RC_CNTL_8_OFFSET_XI (0xffL<<0)
  3326. #define BNX2_RPM_RC_CNTL_8_CLASS_XI (0x7L<<8)
  3327. #define BNX2_RPM_RC_CNTL_8_PRIORITY_XI (1L<<11)
  3328. #define BNX2_RPM_RC_CNTL_8_P4_XI (1L<<12)
  3329. #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI (0x7L<<13)
  3330. #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI (0L<<13)
  3331. #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI (1L<<13)
  3332. #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI (2L<<13)
  3333. #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI (3L<<13)
  3334. #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI (4L<<13)
  3335. #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3336. #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI (6L<<13)
  3337. #define BNX2_RPM_RC_CNTL_8_COMP_XI (0x3L<<16)
  3338. #define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI (0L<<16)
  3339. #define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI (1L<<16)
  3340. #define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI (2L<<16)
  3341. #define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI (3L<<16)
  3342. #define BNX2_RPM_RC_CNTL_8_MAP_XI (1L<<18)
  3343. #define BNX2_RPM_RC_CNTL_8_SBIT_XI (1L<<19)
  3344. #define BNX2_RPM_RC_CNTL_8_CMDSEL_XI (0x1fL<<20)
  3345. #define BNX2_RPM_RC_CNTL_8_DISCARD_XI (1L<<25)
  3346. #define BNX2_RPM_RC_CNTL_8_MASK_XI (1L<<26)
  3347. #define BNX2_RPM_RC_CNTL_8_P1_XI (1L<<27)
  3348. #define BNX2_RPM_RC_CNTL_8_P2_XI (1L<<28)
  3349. #define BNX2_RPM_RC_CNTL_8_P3_XI (1L<<29)
  3350. #define BNX2_RPM_RC_CNTL_8_NBIT_XI (1L<<30)
  3351. #define BNX2_RPM_RC_VALUE_MASK_8 0x00001944
  3352. #define BNX2_RPM_RC_VALUE_MASK_8_VALUE (0xffffL<<0)
  3353. #define BNX2_RPM_RC_VALUE_MASK_8_MASK (0xffffL<<16)
  3354. #define BNX2_RPM_RC_CNTL_9 0x00001948
  3355. #define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0)
  3356. #define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19)
  3357. #define BNX2_RPM_RC_CNTL_9_OFFSET_XI (0xffL<<0)
  3358. #define BNX2_RPM_RC_CNTL_9_CLASS_XI (0x7L<<8)
  3359. #define BNX2_RPM_RC_CNTL_9_PRIORITY_XI (1L<<11)
  3360. #define BNX2_RPM_RC_CNTL_9_P4_XI (1L<<12)
  3361. #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI (0x7L<<13)
  3362. #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI (0L<<13)
  3363. #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI (1L<<13)
  3364. #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI (2L<<13)
  3365. #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI (3L<<13)
  3366. #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI (4L<<13)
  3367. #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3368. #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI (6L<<13)
  3369. #define BNX2_RPM_RC_CNTL_9_COMP_XI (0x3L<<16)
  3370. #define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI (0L<<16)
  3371. #define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI (1L<<16)
  3372. #define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI (2L<<16)
  3373. #define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI (3L<<16)
  3374. #define BNX2_RPM_RC_CNTL_9_MAP_XI (1L<<18)
  3375. #define BNX2_RPM_RC_CNTL_9_SBIT_XI (1L<<19)
  3376. #define BNX2_RPM_RC_CNTL_9_CMDSEL_XI (0x1fL<<20)
  3377. #define BNX2_RPM_RC_CNTL_9_DISCARD_XI (1L<<25)
  3378. #define BNX2_RPM_RC_CNTL_9_MASK_XI (1L<<26)
  3379. #define BNX2_RPM_RC_CNTL_9_P1_XI (1L<<27)
  3380. #define BNX2_RPM_RC_CNTL_9_P2_XI (1L<<28)
  3381. #define BNX2_RPM_RC_CNTL_9_P3_XI (1L<<29)
  3382. #define BNX2_RPM_RC_CNTL_9_NBIT_XI (1L<<30)
  3383. #define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c
  3384. #define BNX2_RPM_RC_VALUE_MASK_9_VALUE (0xffffL<<0)
  3385. #define BNX2_RPM_RC_VALUE_MASK_9_MASK (0xffffL<<16)
  3386. #define BNX2_RPM_RC_CNTL_10 0x00001950
  3387. #define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0)
  3388. #define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19)
  3389. #define BNX2_RPM_RC_CNTL_10_OFFSET_XI (0xffL<<0)
  3390. #define BNX2_RPM_RC_CNTL_10_CLASS_XI (0x7L<<8)
  3391. #define BNX2_RPM_RC_CNTL_10_PRIORITY_XI (1L<<11)
  3392. #define BNX2_RPM_RC_CNTL_10_P4_XI (1L<<12)
  3393. #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI (0x7L<<13)
  3394. #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI (0L<<13)
  3395. #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI (1L<<13)
  3396. #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI (2L<<13)
  3397. #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI (3L<<13)
  3398. #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI (4L<<13)
  3399. #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3400. #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI (6L<<13)
  3401. #define BNX2_RPM_RC_CNTL_10_COMP_XI (0x3L<<16)
  3402. #define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI (0L<<16)
  3403. #define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI (1L<<16)
  3404. #define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI (2L<<16)
  3405. #define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI (3L<<16)
  3406. #define BNX2_RPM_RC_CNTL_10_MAP_XI (1L<<18)
  3407. #define BNX2_RPM_RC_CNTL_10_SBIT_XI (1L<<19)
  3408. #define BNX2_RPM_RC_CNTL_10_CMDSEL_XI (0x1fL<<20)
  3409. #define BNX2_RPM_RC_CNTL_10_DISCARD_XI (1L<<25)
  3410. #define BNX2_RPM_RC_CNTL_10_MASK_XI (1L<<26)
  3411. #define BNX2_RPM_RC_CNTL_10_P1_XI (1L<<27)
  3412. #define BNX2_RPM_RC_CNTL_10_P2_XI (1L<<28)
  3413. #define BNX2_RPM_RC_CNTL_10_P3_XI (1L<<29)
  3414. #define BNX2_RPM_RC_CNTL_10_NBIT_XI (1L<<30)
  3415. #define BNX2_RPM_RC_VALUE_MASK_10 0x00001954
  3416. #define BNX2_RPM_RC_VALUE_MASK_10_VALUE (0xffffL<<0)
  3417. #define BNX2_RPM_RC_VALUE_MASK_10_MASK (0xffffL<<16)
  3418. #define BNX2_RPM_RC_CNTL_11 0x00001958
  3419. #define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0)
  3420. #define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19)
  3421. #define BNX2_RPM_RC_CNTL_11_OFFSET_XI (0xffL<<0)
  3422. #define BNX2_RPM_RC_CNTL_11_CLASS_XI (0x7L<<8)
  3423. #define BNX2_RPM_RC_CNTL_11_PRIORITY_XI (1L<<11)
  3424. #define BNX2_RPM_RC_CNTL_11_P4_XI (1L<<12)
  3425. #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI (0x7L<<13)
  3426. #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI (0L<<13)
  3427. #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI (1L<<13)
  3428. #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI (2L<<13)
  3429. #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI (3L<<13)
  3430. #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI (4L<<13)
  3431. #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3432. #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI (6L<<13)
  3433. #define BNX2_RPM_RC_CNTL_11_COMP_XI (0x3L<<16)
  3434. #define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI (0L<<16)
  3435. #define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI (1L<<16)
  3436. #define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI (2L<<16)
  3437. #define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI (3L<<16)
  3438. #define BNX2_RPM_RC_CNTL_11_MAP_XI (1L<<18)
  3439. #define BNX2_RPM_RC_CNTL_11_SBIT_XI (1L<<19)
  3440. #define BNX2_RPM_RC_CNTL_11_CMDSEL_XI (0x1fL<<20)
  3441. #define BNX2_RPM_RC_CNTL_11_DISCARD_XI (1L<<25)
  3442. #define BNX2_RPM_RC_CNTL_11_MASK_XI (1L<<26)
  3443. #define BNX2_RPM_RC_CNTL_11_P1_XI (1L<<27)
  3444. #define BNX2_RPM_RC_CNTL_11_P2_XI (1L<<28)
  3445. #define BNX2_RPM_RC_CNTL_11_P3_XI (1L<<29)
  3446. #define BNX2_RPM_RC_CNTL_11_NBIT_XI (1L<<30)
  3447. #define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c
  3448. #define BNX2_RPM_RC_VALUE_MASK_11_VALUE (0xffffL<<0)
  3449. #define BNX2_RPM_RC_VALUE_MASK_11_MASK (0xffffL<<16)
  3450. #define BNX2_RPM_RC_CNTL_12 0x00001960
  3451. #define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0)
  3452. #define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19)
  3453. #define BNX2_RPM_RC_CNTL_12_OFFSET_XI (0xffL<<0)
  3454. #define BNX2_RPM_RC_CNTL_12_CLASS_XI (0x7L<<8)
  3455. #define BNX2_RPM_RC_CNTL_12_PRIORITY_XI (1L<<11)
  3456. #define BNX2_RPM_RC_CNTL_12_P4_XI (1L<<12)
  3457. #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI (0x7L<<13)
  3458. #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI (0L<<13)
  3459. #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI (1L<<13)
  3460. #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI (2L<<13)
  3461. #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI (3L<<13)
  3462. #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI (4L<<13)
  3463. #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3464. #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI (6L<<13)
  3465. #define BNX2_RPM_RC_CNTL_12_COMP_XI (0x3L<<16)
  3466. #define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI (0L<<16)
  3467. #define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI (1L<<16)
  3468. #define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI (2L<<16)
  3469. #define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI (3L<<16)
  3470. #define BNX2_RPM_RC_CNTL_12_MAP_XI (1L<<18)
  3471. #define BNX2_RPM_RC_CNTL_12_SBIT_XI (1L<<19)
  3472. #define BNX2_RPM_RC_CNTL_12_CMDSEL_XI (0x1fL<<20)
  3473. #define BNX2_RPM_RC_CNTL_12_DISCARD_XI (1L<<25)
  3474. #define BNX2_RPM_RC_CNTL_12_MASK_XI (1L<<26)
  3475. #define BNX2_RPM_RC_CNTL_12_P1_XI (1L<<27)
  3476. #define BNX2_RPM_RC_CNTL_12_P2_XI (1L<<28)
  3477. #define BNX2_RPM_RC_CNTL_12_P3_XI (1L<<29)
  3478. #define BNX2_RPM_RC_CNTL_12_NBIT_XI (1L<<30)
  3479. #define BNX2_RPM_RC_VALUE_MASK_12 0x00001964
  3480. #define BNX2_RPM_RC_VALUE_MASK_12_VALUE (0xffffL<<0)
  3481. #define BNX2_RPM_RC_VALUE_MASK_12_MASK (0xffffL<<16)
  3482. #define BNX2_RPM_RC_CNTL_13 0x00001968
  3483. #define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0)
  3484. #define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19)
  3485. #define BNX2_RPM_RC_CNTL_13_OFFSET_XI (0xffL<<0)
  3486. #define BNX2_RPM_RC_CNTL_13_CLASS_XI (0x7L<<8)
  3487. #define BNX2_RPM_RC_CNTL_13_PRIORITY_XI (1L<<11)
  3488. #define BNX2_RPM_RC_CNTL_13_P4_XI (1L<<12)
  3489. #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI (0x7L<<13)
  3490. #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI (0L<<13)
  3491. #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI (1L<<13)
  3492. #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI (2L<<13)
  3493. #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI (3L<<13)
  3494. #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI (4L<<13)
  3495. #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3496. #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI (6L<<13)
  3497. #define BNX2_RPM_RC_CNTL_13_COMP_XI (0x3L<<16)
  3498. #define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI (0L<<16)
  3499. #define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI (1L<<16)
  3500. #define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI (2L<<16)
  3501. #define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI (3L<<16)
  3502. #define BNX2_RPM_RC_CNTL_13_MAP_XI (1L<<18)
  3503. #define BNX2_RPM_RC_CNTL_13_SBIT_XI (1L<<19)
  3504. #define BNX2_RPM_RC_CNTL_13_CMDSEL_XI (0x1fL<<20)
  3505. #define BNX2_RPM_RC_CNTL_13_DISCARD_XI (1L<<25)
  3506. #define BNX2_RPM_RC_CNTL_13_MASK_XI (1L<<26)
  3507. #define BNX2_RPM_RC_CNTL_13_P1_XI (1L<<27)
  3508. #define BNX2_RPM_RC_CNTL_13_P2_XI (1L<<28)
  3509. #define BNX2_RPM_RC_CNTL_13_P3_XI (1L<<29)
  3510. #define BNX2_RPM_RC_CNTL_13_NBIT_XI (1L<<30)
  3511. #define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c
  3512. #define BNX2_RPM_RC_VALUE_MASK_13_VALUE (0xffffL<<0)
  3513. #define BNX2_RPM_RC_VALUE_MASK_13_MASK (0xffffL<<16)
  3514. #define BNX2_RPM_RC_CNTL_14 0x00001970
  3515. #define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0)
  3516. #define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19)
  3517. #define BNX2_RPM_RC_CNTL_14_OFFSET_XI (0xffL<<0)
  3518. #define BNX2_RPM_RC_CNTL_14_CLASS_XI (0x7L<<8)
  3519. #define BNX2_RPM_RC_CNTL_14_PRIORITY_XI (1L<<11)
  3520. #define BNX2_RPM_RC_CNTL_14_P4_XI (1L<<12)
  3521. #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI (0x7L<<13)
  3522. #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI (0L<<13)
  3523. #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI (1L<<13)
  3524. #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI (2L<<13)
  3525. #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI (3L<<13)
  3526. #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI (4L<<13)
  3527. #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3528. #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI (6L<<13)
  3529. #define BNX2_RPM_RC_CNTL_14_COMP_XI (0x3L<<16)
  3530. #define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI (0L<<16)
  3531. #define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI (1L<<16)
  3532. #define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI (2L<<16)
  3533. #define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI (3L<<16)
  3534. #define BNX2_RPM_RC_CNTL_14_MAP_XI (1L<<18)
  3535. #define BNX2_RPM_RC_CNTL_14_SBIT_XI (1L<<19)
  3536. #define BNX2_RPM_RC_CNTL_14_CMDSEL_XI (0x1fL<<20)
  3537. #define BNX2_RPM_RC_CNTL_14_DISCARD_XI (1L<<25)
  3538. #define BNX2_RPM_RC_CNTL_14_MASK_XI (1L<<26)
  3539. #define BNX2_RPM_RC_CNTL_14_P1_XI (1L<<27)
  3540. #define BNX2_RPM_RC_CNTL_14_P2_XI (1L<<28)
  3541. #define BNX2_RPM_RC_CNTL_14_P3_XI (1L<<29)
  3542. #define BNX2_RPM_RC_CNTL_14_NBIT_XI (1L<<30)
  3543. #define BNX2_RPM_RC_VALUE_MASK_14 0x00001974
  3544. #define BNX2_RPM_RC_VALUE_MASK_14_VALUE (0xffffL<<0)
  3545. #define BNX2_RPM_RC_VALUE_MASK_14_MASK (0xffffL<<16)
  3546. #define BNX2_RPM_RC_CNTL_15 0x00001978
  3547. #define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0)
  3548. #define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19)
  3549. #define BNX2_RPM_RC_CNTL_15_OFFSET_XI (0xffL<<0)
  3550. #define BNX2_RPM_RC_CNTL_15_CLASS_XI (0x7L<<8)
  3551. #define BNX2_RPM_RC_CNTL_15_PRIORITY_XI (1L<<11)
  3552. #define BNX2_RPM_RC_CNTL_15_P4_XI (1L<<12)
  3553. #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI (0x7L<<13)
  3554. #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI (0L<<13)
  3555. #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI (1L<<13)
  3556. #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI (2L<<13)
  3557. #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI (3L<<13)
  3558. #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI (4L<<13)
  3559. #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI (5L<<13)
  3560. #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI (6L<<13)
  3561. #define BNX2_RPM_RC_CNTL_15_COMP_XI (0x3L<<16)
  3562. #define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI (0L<<16)
  3563. #define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI (1L<<16)
  3564. #define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI (2L<<16)
  3565. #define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI (3L<<16)
  3566. #define BNX2_RPM_RC_CNTL_15_MAP_XI (1L<<18)
  3567. #define BNX2_RPM_RC_CNTL_15_SBIT_XI (1L<<19)
  3568. #define BNX2_RPM_RC_CNTL_15_CMDSEL_XI (0x1fL<<20)
  3569. #define BNX2_RPM_RC_CNTL_15_DISCARD_XI (1L<<25)
  3570. #define BNX2_RPM_RC_CNTL_15_MASK_XI (1L<<26)
  3571. #define BNX2_RPM_RC_CNTL_15_P1_XI (1L<<27)
  3572. #define BNX2_RPM_RC_CNTL_15_P2_XI (1L<<28)
  3573. #define BNX2_RPM_RC_CNTL_15_P3_XI (1L<<29)
  3574. #define BNX2_RPM_RC_CNTL_15_NBIT_XI (1L<<30)
  3575. #define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c
  3576. #define BNX2_RPM_RC_VALUE_MASK_15_VALUE (0xffffL<<0)
  3577. #define BNX2_RPM_RC_VALUE_MASK_15_MASK (0xffffL<<16)
  3578. #define BNX2_RPM_RC_CONFIG 0x00001980
  3579. #define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
  3580. #define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI (0xfffffL<<0)
  3581. #define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
  3582. #define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE (1L<<31)
  3583. #define BNX2_RPM_DEBUG0 0x00001984
  3584. #define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
  3585. #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
  3586. #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
  3587. #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
  3588. #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
  3589. #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
  3590. #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
  3591. #define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22)
  3592. #define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23)
  3593. #define BNX2_RPM_DEBUG0_DONE (1L<<24)
  3594. #define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
  3595. #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
  3596. #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
  3597. #define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
  3598. #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
  3599. #define BNX2_RPM_DEBUG1 0x00001988
  3600. #define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
  3601. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
  3602. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
  3603. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
  3604. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
  3605. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
  3606. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
  3607. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
  3608. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
  3609. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
  3610. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
  3611. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
  3612. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
  3613. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
  3614. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
  3615. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
  3616. #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
  3617. #define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
  3618. #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
  3619. #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
  3620. #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
  3621. #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
  3622. #define BNX2_RPM_DEBUG2 0x0000198c
  3623. #define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
  3624. #define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16)
  3625. #define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
  3626. #define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
  3627. #define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
  3628. #define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
  3629. #define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
  3630. #define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29)
  3631. #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
  3632. #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
  3633. #define BNX2_RPM_DEBUG3 0x00001990
  3634. #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
  3635. #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
  3636. #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
  3637. #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
  3638. #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
  3639. #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
  3640. #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
  3641. #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
  3642. #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
  3643. #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
  3644. #define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
  3645. #define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23)
  3646. #define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
  3647. #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
  3648. #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
  3649. #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
  3650. #define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
  3651. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
  3652. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
  3653. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
  3654. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
  3655. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
  3656. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
  3657. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
  3658. #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
  3659. #define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29)
  3660. #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
  3661. #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
  3662. #define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
  3663. #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
  3664. #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
  3665. #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
  3666. #define BNX2_RPM_DEBUG4 0x00001994
  3667. #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
  3668. #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
  3669. #define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
  3670. #define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
  3671. #define BNX2_RPM_DEBUG5 0x00001998
  3672. #define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
  3673. #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
  3674. #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
  3675. #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
  3676. #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
  3677. #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
  3678. #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
  3679. #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
  3680. #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
  3681. #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
  3682. #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
  3683. #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
  3684. #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
  3685. #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
  3686. #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
  3687. #define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31)
  3688. #define BNX2_RPM_DEBUG6 0x0000199c
  3689. #define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
  3690. #define BNX2_RPM_DEBUG6_VEC (0xffffL<<16)
  3691. #define BNX2_RPM_DEBUG7 0x000019a0
  3692. #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
  3693. #define BNX2_RPM_DEBUG8 0x000019a4
  3694. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
  3695. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
  3696. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
  3697. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
  3698. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
  3699. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
  3700. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
  3701. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
  3702. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
  3703. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
  3704. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
  3705. #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
  3706. #define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
  3707. #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
  3708. #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
  3709. #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
  3710. #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
  3711. #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
  3712. #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
  3713. #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
  3714. #define BNX2_RPM_DEBUG8_EOF_DET (1L<<12)
  3715. #define BNX2_RPM_DEBUG8_SOF_DET (1L<<13)
  3716. #define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
  3717. #define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15)
  3718. #define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
  3719. #define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
  3720. #define BNX2_RPM_DEBUG9 0x000019a8
  3721. #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
  3722. #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
  3723. #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
  3724. #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
  3725. #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
  3726. #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
  3727. #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
  3728. #define BNX2_RPM_DEBUG9_BEMEM_R_XI (0x1fL<<0)
  3729. #define BNX2_RPM_DEBUG9_EO_XI (1L<<5)
  3730. #define BNX2_RPM_DEBUG9_AEOF_DE_XI (1L<<6)
  3731. #define BNX2_RPM_DEBUG9_SO_XI (1L<<7)
  3732. #define BNX2_RPM_DEBUG9_WD64_CT_XI (0x1fL<<8)
  3733. #define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI (0x7L<<13)
  3734. #define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI (0xfL<<16)
  3735. #define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI (0x3ffL<<20)
  3736. #define BNX2_RPM_DEBUG9_DATA_IN_VL_XI (1L<<30)
  3737. #define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI (1L<<31)
  3738. #define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0
  3739. #define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4
  3740. #define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8
  3741. #define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc
  3742. #define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0
  3743. #define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4
  3744. #define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8
  3745. #define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc
  3746. #define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0
  3747. #define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4
  3748. #define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8
  3749. #define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec
  3750. #define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0
  3751. #define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4
  3752. #define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8
  3753. #define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc
  3754. #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL 0x00001a00
  3755. #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS (0xffffL<<0)
  3756. #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD (1L<<28)
  3757. #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE (1L<<29)
  3758. #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT (1L<<30)
  3759. #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR (1L<<31)
  3760. #define BNX2_RPM_ACPI_PATTERN_CTRL 0x00001a04
  3761. #define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID (0xfL<<0)
  3762. #define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR (1L<<30)
  3763. #define BNX2_RPM_ACPI_PATTERN_CTRL_WR (1L<<31)
  3764. #define BNX2_RPM_ACPI_DATA 0x00001a08
  3765. #define BNX2_RPM_ACPI_DATA_PATTERN_BE (0xffffffffL<<0)
  3766. #define BNX2_RPM_ACPI_PATTERN_LEN0 0x00001a0c
  3767. #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3 (0xffL<<0)
  3768. #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2 (0xffL<<8)
  3769. #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1 (0xffL<<16)
  3770. #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0 (0xffL<<24)
  3771. #define BNX2_RPM_ACPI_PATTERN_LEN1 0x00001a10
  3772. #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7 (0xffL<<0)
  3773. #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6 (0xffL<<8)
  3774. #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5 (0xffL<<16)
  3775. #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4 (0xffL<<24)
  3776. #define BNX2_RPM_ACPI_PATTERN_CRC0 0x00001a18
  3777. #define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0 (0xffffffffL<<0)
  3778. #define BNX2_RPM_ACPI_PATTERN_CRC1 0x00001a1c
  3779. #define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1 (0xffffffffL<<0)
  3780. #define BNX2_RPM_ACPI_PATTERN_CRC2 0x00001a20
  3781. #define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2 (0xffffffffL<<0)
  3782. #define BNX2_RPM_ACPI_PATTERN_CRC3 0x00001a24
  3783. #define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3 (0xffffffffL<<0)
  3784. #define BNX2_RPM_ACPI_PATTERN_CRC4 0x00001a28
  3785. #define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4 (0xffffffffL<<0)
  3786. #define BNX2_RPM_ACPI_PATTERN_CRC5 0x00001a2c
  3787. #define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5 (0xffffffffL<<0)
  3788. #define BNX2_RPM_ACPI_PATTERN_CRC6 0x00001a30
  3789. #define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6 (0xffffffffL<<0)
  3790. #define BNX2_RPM_ACPI_PATTERN_CRC7 0x00001a34
  3791. #define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7 (0xffffffffL<<0)
  3792. /*
  3793. * rbuf_reg definition
  3794. * offset: 0x200000
  3795. */
  3796. #define BNX2_RBUF_COMMAND 0x00200000
  3797. #define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
  3798. #define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1)
  3799. #define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2)
  3800. #define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL (1L<<3)
  3801. #define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4)
  3802. #define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5)
  3803. #define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE (1L<<6)
  3804. #define BNX2_RBUF_COMMAND_CU_ISOLATE_XI (1L<<5)
  3805. #define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI (1L<<6)
  3806. #define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI (1L<<7)
  3807. #define BNX2_RBUF_STATUS1 0x00200004
  3808. #define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
  3809. #define BNX2_RBUF_STATUS2 0x00200008
  3810. #define BNX2_RBUF_STATUS2_FREE_TAIL (0x1ffL<<0)
  3811. #define BNX2_RBUF_STATUS2_FREE_HEAD (0x1ffL<<16)
  3812. #define BNX2_RBUF_CONFIG 0x0020000c
  3813. #define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
  3814. #define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
  3815. #define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
  3816. #define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
  3817. #define BNX2_RBUF_FW_BUF_ALLOC_TYPE (1L<<16)
  3818. #define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ (1L<<31)
  3819. #define BNX2_RBUF_FW_BUF_FREE 0x00200014
  3820. #define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
  3821. #define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
  3822. #define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
  3823. #define BNX2_RBUF_FW_BUF_FREE_TYPE (1L<<25)
  3824. #define BNX2_RBUF_FW_BUF_FREE_FREE_REQ (1L<<31)
  3825. #define BNX2_RBUF_FW_BUF_SEL 0x00200018
  3826. #define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
  3827. #define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
  3828. #define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
  3829. #define BNX2_RBUF_FW_BUF_SEL_SEL_REQ (1L<<31)
  3830. #define BNX2_RBUF_CONFIG2 0x0020001c
  3831. #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
  3832. #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
  3833. #define BNX2_RBUF_CONFIG3 0x00200020
  3834. #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
  3835. #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
  3836. #define BNX2_RBUF_PKT_DATA 0x00208000
  3837. #define BNX2_RBUF_CLIST_DATA 0x00210000
  3838. #define BNX2_RBUF_BUF_DATA 0x00220000
  3839. /*
  3840. * rv2p_reg definition
  3841. * offset: 0x2800
  3842. */
  3843. #define BNX2_RV2P_COMMAND 0x00002800
  3844. #define BNX2_RV2P_COMMAND_ENABLED (1L<<0)
  3845. #define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
  3846. #define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
  3847. #define BNX2_RV2P_COMMAND_ABORT0 (1L<<4)
  3848. #define BNX2_RV2P_COMMAND_ABORT1 (1L<<5)
  3849. #define BNX2_RV2P_COMMAND_ABORT2 (1L<<6)
  3850. #define BNX2_RV2P_COMMAND_ABORT3 (1L<<7)
  3851. #define BNX2_RV2P_COMMAND_ABORT4 (1L<<8)
  3852. #define BNX2_RV2P_COMMAND_ABORT5 (1L<<9)
  3853. #define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16)
  3854. #define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17)
  3855. #define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18)
  3856. #define BNX2_RV2P_STATUS 0x00002804
  3857. #define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0)
  3858. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
  3859. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
  3860. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
  3861. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
  3862. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
  3863. #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
  3864. #define BNX2_RV2P_CONFIG 0x00002808
  3865. #define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0)
  3866. #define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1)
  3867. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
  3868. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
  3869. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
  3870. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
  3871. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
  3872. #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
  3873. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
  3874. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
  3875. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
  3876. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
  3877. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
  3878. #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
  3879. #define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
  3880. #define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
  3881. #define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
  3882. #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
  3883. #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
  3884. #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
  3885. #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
  3886. #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
  3887. #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
  3888. #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
  3889. #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
  3890. #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
  3891. #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
  3892. #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
  3893. #define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810
  3894. #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
  3895. #define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814
  3896. #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
  3897. #define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818
  3898. #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
  3899. #define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c
  3900. #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
  3901. #define BNX2_RV2P_INSTR_HIGH 0x00002830
  3902. #define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
  3903. #define BNX2_RV2P_INSTR_LOW 0x00002834
  3904. #define BNX2_RV2P_INSTR_LOW_LOW (0xffffffffL<<0)
  3905. #define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838
  3906. #define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
  3907. #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
  3908. #define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c
  3909. #define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
  3910. #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
  3911. #define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840
  3912. #define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844
  3913. #define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848
  3914. #define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c
  3915. #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  3916. #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  3917. #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  3918. #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  3919. #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  3920. #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  3921. #define BNX2_RV2P_MPFE_PFE_CTL 0x00002afc
  3922. #define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
  3923. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE (0xfL<<4)
  3924. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
  3925. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
  3926. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
  3927. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
  3928. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
  3929. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
  3930. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
  3931. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
  3932. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
  3933. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
  3934. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
  3935. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
  3936. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
  3937. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
  3938. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
  3939. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
  3940. #define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT (0xfL<<12)
  3941. #define BNX2_RV2P_MPFE_PFE_CTL_OFFSET (0x1ffL<<16)
  3942. #define BNX2_RV2P_RV2PPQ 0x00002b40
  3943. #define BNX2_RV2P_PFTQ_CMD 0x00002b78
  3944. #define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
  3945. #define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
  3946. #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
  3947. #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
  3948. #define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
  3949. #define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
  3950. #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
  3951. #define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
  3952. #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
  3953. #define BNX2_RV2P_PFTQ_CMD_POP (1L<<30)
  3954. #define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31)
  3955. #define BNX2_RV2P_PFTQ_CTL 0x00002b7c
  3956. #define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
  3957. #define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
  3958. #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
  3959. #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3960. #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3961. #define BNX2_RV2P_RV2PTQ 0x00002b80
  3962. #define BNX2_RV2P_TFTQ_CMD 0x00002bb8
  3963. #define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
  3964. #define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
  3965. #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
  3966. #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
  3967. #define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
  3968. #define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
  3969. #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
  3970. #define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
  3971. #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
  3972. #define BNX2_RV2P_TFTQ_CMD_POP (1L<<30)
  3973. #define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31)
  3974. #define BNX2_RV2P_TFTQ_CTL 0x00002bbc
  3975. #define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
  3976. #define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
  3977. #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
  3978. #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3979. #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3980. #define BNX2_RV2P_RV2PMQ 0x00002bc0
  3981. #define BNX2_RV2P_MFTQ_CMD 0x00002bf8
  3982. #define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
  3983. #define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
  3984. #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
  3985. #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
  3986. #define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
  3987. #define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
  3988. #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
  3989. #define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
  3990. #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
  3991. #define BNX2_RV2P_MFTQ_CMD_POP (1L<<30)
  3992. #define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31)
  3993. #define BNX2_RV2P_MFTQ_CTL 0x00002bfc
  3994. #define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
  3995. #define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
  3996. #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
  3997. #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  3998. #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  3999. /*
  4000. * mq_reg definition
  4001. * offset: 0x3c00
  4002. */
  4003. #define BNX2_MQ_COMMAND 0x00003c00
  4004. #define BNX2_MQ_COMMAND_ENABLED (1L<<0)
  4005. #define BNX2_MQ_COMMAND_INIT (1L<<1)
  4006. #define BNX2_MQ_COMMAND_OVERFLOW (1L<<4)
  4007. #define BNX2_MQ_COMMAND_WR_ERROR (1L<<5)
  4008. #define BNX2_MQ_COMMAND_RD_ERROR (1L<<6)
  4009. #define BNX2_MQ_COMMAND_IDB_CFG_ERROR (1L<<7)
  4010. #define BNX2_MQ_COMMAND_IDB_OVERFLOW (1L<<10)
  4011. #define BNX2_MQ_COMMAND_NO_BIN_ERROR (1L<<11)
  4012. #define BNX2_MQ_COMMAND_NO_MAP_ERROR (1L<<12)
  4013. #define BNX2_MQ_STATUS 0x00003c04
  4014. #define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
  4015. #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
  4016. #define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18)
  4017. #define BNX2_MQ_STATUS_IDB_OFLOW_STAT (1L<<19)
  4018. #define BNX2_MQ_CONFIG 0x00003c08
  4019. #define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
  4020. #define BNX2_MQ_CONFIG_HALT_DIS (1L<<1)
  4021. #define BNX2_MQ_CONFIG_BIN_MQ_MODE (1L<<2)
  4022. #define BNX2_MQ_CONFIG_DIS_IDB_DROP (1L<<3)
  4023. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
  4024. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
  4025. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
  4026. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
  4027. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
  4028. #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
  4029. #define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
  4030. #define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
  4031. #define BNX2_MQ_ENQUEUE1 0x00003c0c
  4032. #define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
  4033. #define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8)
  4034. #define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
  4035. #define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28)
  4036. #define BNX2_MQ_ENQUEUE2 0x00003c10
  4037. #define BNX2_MQ_BAD_WR_ADDR 0x00003c14
  4038. #define BNX2_MQ_BAD_RD_ADDR 0x00003c18
  4039. #define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c
  4040. #define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
  4041. #define BNX2_MQ_KNL_WIND_END 0x00003c20
  4042. #define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
  4043. #define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24
  4044. #define BNX2_MQ_KNL_TX_MASK1 0x00003c28
  4045. #define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c
  4046. #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
  4047. #define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34
  4048. #define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38
  4049. #define BNX2_MQ_KNL_TX_MASK2 0x00003c3c
  4050. #define BNX2_MQ_KNL_CMD_MASK2 0x00003c40
  4051. #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
  4052. #define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48
  4053. #define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
  4054. #define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50
  4055. #define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54
  4056. #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
  4057. #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
  4058. #define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
  4059. #define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64
  4060. #define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68
  4061. #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
  4062. #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
  4063. #define BNX2_MQ_MEM_WR_ADDR 0x00003c74
  4064. #define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
  4065. #define BNX2_MQ_MEM_WR_DATA0 0x00003c78
  4066. #define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
  4067. #define BNX2_MQ_MEM_WR_DATA1 0x00003c7c
  4068. #define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
  4069. #define BNX2_MQ_MEM_WR_DATA2 0x00003c80
  4070. #define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
  4071. #define BNX2_MQ_MEM_WR_DATA2_VALUE_XI (0x7fffffffL<<0)
  4072. #define BNX2_MQ_MEM_RD_ADDR 0x00003c84
  4073. #define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
  4074. #define BNX2_MQ_MEM_RD_DATA0 0x00003c88
  4075. #define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
  4076. #define BNX2_MQ_MEM_RD_DATA1 0x00003c8c
  4077. #define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
  4078. #define BNX2_MQ_MEM_RD_DATA2 0x00003c90
  4079. #define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
  4080. #define BNX2_MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffL<<0)
  4081. /*
  4082. * tsch_reg definition
  4083. * offset: 0x4c00
  4084. */
  4085. #define BNX2_TSCH_TSS_CFG 0x00004c1c
  4086. #define BNX2_TSCH_TSS_CFG_TSS_START_CID (0x7ffL<<8)
  4087. #define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON (0xfL<<24)
  4088. /*
  4089. * tbdr_reg definition
  4090. * offset: 0x5000
  4091. */
  4092. #define BNX2_TBDR_COMMAND 0x00005000
  4093. #define BNX2_TBDR_COMMAND_ENABLE (1L<<0)
  4094. #define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1)
  4095. #define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4)
  4096. #define BNX2_TBDR_STATUS 0x00005004
  4097. #define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0)
  4098. #define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1)
  4099. #define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
  4100. #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
  4101. #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
  4102. #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
  4103. #define BNX2_TBDR_STATUS_BURST_CNT (1L<<6)
  4104. #define BNX2_TBDR_CONFIG 0x00005008
  4105. #define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0)
  4106. #define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8)
  4107. #define BNX2_TBDR_CONFIG_PRIORITY (1L<<9)
  4108. #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
  4109. #define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
  4110. #define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
  4111. #define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
  4112. #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
  4113. #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
  4114. #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
  4115. #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
  4116. #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
  4117. #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
  4118. #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
  4119. #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
  4120. #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
  4121. #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
  4122. #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
  4123. #define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c
  4124. #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  4125. #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  4126. #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  4127. #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  4128. #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  4129. #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  4130. #define BNX2_TBDR_CKSUM_ERROR_STATUS 0x00005010
  4131. #define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
  4132. #define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
  4133. #define BNX2_TBDR_TBDRQ 0x000053c0
  4134. #define BNX2_TBDR_FTQ_CMD 0x000053f8
  4135. #define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
  4136. #define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10)
  4137. #define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
  4138. #define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
  4139. #define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
  4140. #define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26)
  4141. #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
  4142. #define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
  4143. #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
  4144. #define BNX2_TBDR_FTQ_CMD_POP (1L<<30)
  4145. #define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31)
  4146. #define BNX2_TBDR_FTQ_CTL 0x000053fc
  4147. #define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0)
  4148. #define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
  4149. #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  4150. #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  4151. #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  4152. /*
  4153. * tdma_reg definition
  4154. * offset: 0x5c00
  4155. */
  4156. #define BNX2_TDMA_COMMAND 0x00005c00
  4157. #define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
  4158. #define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4)
  4159. #define BNX2_TDMA_COMMAND_CS16_ERR (1L<<5)
  4160. #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
  4161. #define BNX2_TDMA_COMMAND_MASK_CS1 (1L<<20)
  4162. #define BNX2_TDMA_COMMAND_MASK_CS2 (1L<<21)
  4163. #define BNX2_TDMA_COMMAND_MASK_CS3 (1L<<22)
  4164. #define BNX2_TDMA_COMMAND_MASK_CS4 (1L<<23)
  4165. #define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR (1L<<24)
  4166. #define BNX2_TDMA_COMMAND_OFIFO_CLR (1L<<30)
  4167. #define BNX2_TDMA_COMMAND_IFIFO_CLR (1L<<31)
  4168. #define BNX2_TDMA_STATUS 0x00005c04
  4169. #define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
  4170. #define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
  4171. #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
  4172. #define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3)
  4173. #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
  4174. #define BNX2_TDMA_STATUS_BURST_CNT (1L<<17)
  4175. #define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH (0x3fL<<20)
  4176. #define BNX2_TDMA_STATUS_OFIFO_OVERFLOW (1L<<30)
  4177. #define BNX2_TDMA_STATUS_IFIFO_OVERFLOW (1L<<31)
  4178. #define BNX2_TDMA_CONFIG 0x00005c08
  4179. #define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
  4180. #define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1)
  4181. #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN (0x3L<<2)
  4182. #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0 (0L<<2)
  4183. #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1 (1L<<2)
  4184. #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2 (2L<<2)
  4185. #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3 (3L<<2)
  4186. #define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
  4187. #define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
  4188. #define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
  4189. #define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
  4190. #define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
  4191. #define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8)
  4192. #define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
  4193. #define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
  4194. #define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
  4195. #define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
  4196. #define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15)
  4197. #define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16)
  4198. #define BNX2_TDMA_CONFIG_CMPL_ENTRY (1L<<17)
  4199. #define BNX2_TDMA_CONFIG_OFIFO_CMP (1L<<19)
  4200. #define BNX2_TDMA_CONFIG_OFIFO_CMP_3 (0L<<19)
  4201. #define BNX2_TDMA_CONFIG_OFIFO_CMP_2 (1L<<19)
  4202. #define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
  4203. #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI (0x7L<<20)
  4204. #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI (0L<<20)
  4205. #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI (1L<<20)
  4206. #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI (2L<<20)
  4207. #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI (3L<<20)
  4208. #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI (4L<<20)
  4209. #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI (5L<<20)
  4210. #define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI (1L<<23)
  4211. #define BNX2_TDMA_CONFIG_BYTES_OST_XI (0x7L<<24)
  4212. #define BNX2_TDMA_CONFIG_BYTES_OST_512_XI (0L<<24)
  4213. #define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI (1L<<24)
  4214. #define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI (2L<<24)
  4215. #define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI (3L<<24)
  4216. #define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI (4L<<24)
  4217. #define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI (5L<<24)
  4218. #define BNX2_TDMA_CONFIG_HC_BYPASS_XI (1L<<27)
  4219. #define BNX2_TDMA_CONFIG_LCL_MRRS_XI (0x7L<<28)
  4220. #define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI (0L<<28)
  4221. #define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI (1L<<28)
  4222. #define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI (2L<<28)
  4223. #define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI (3L<<28)
  4224. #define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI (4L<<28)
  4225. #define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI (5L<<28)
  4226. #define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI (1L<<31)
  4227. #define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c
  4228. #define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
  4229. #define BNX2_TDMA_DBG_WATCHDOG 0x00005c10
  4230. #define BNX2_TDMA_DBG_TRIGGER 0x00005c14
  4231. #define BNX2_TDMA_DMAD_FSM 0x00005c80
  4232. #define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
  4233. #define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4)
  4234. #define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
  4235. #define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
  4236. #define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16)
  4237. #define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20)
  4238. #define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24)
  4239. #define BNX2_TDMA_DMAD_STATUS 0x00005c84
  4240. #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
  4241. #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
  4242. #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
  4243. #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
  4244. #define BNX2_TDMA_DR_INTF_FSM 0x00005c88
  4245. #define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
  4246. #define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
  4247. #define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
  4248. #define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
  4249. #define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
  4250. #define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c
  4251. #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
  4252. #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
  4253. #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
  4254. #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
  4255. #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
  4256. #define BNX2_TDMA_PUSH_FSM 0x00005c90
  4257. #define BNX2_TDMA_BD_IF_DEBUG 0x00005c94
  4258. #define BNX2_TDMA_DMAD_IF_DEBUG 0x00005c98
  4259. #define BNX2_TDMA_CTX_IF_DEBUG 0x00005c9c
  4260. #define BNX2_TDMA_TPBUF_IF_DEBUG 0x00005ca0
  4261. #define BNX2_TDMA_DR_IF_DEBUG 0x00005ca4
  4262. #define BNX2_TDMA_TPATQ_IF_DEBUG 0x00005ca8
  4263. #define BNX2_TDMA_TDMA_ILOCK_CKSUM 0x00005cac
  4264. #define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED (0xffffL<<0)
  4265. #define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED (0xffffL<<16)
  4266. #define BNX2_TDMA_TDMA_PCIE_CKSUM 0x00005cb0
  4267. #define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED (0xffffL<<0)
  4268. #define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED (0xffffL<<16)
  4269. #define BNX2_TDMA_TDMAQ 0x00005fc0
  4270. #define BNX2_TDMA_FTQ_CMD 0x00005ff8
  4271. #define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
  4272. #define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10)
  4273. #define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
  4274. #define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
  4275. #define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
  4276. #define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26)
  4277. #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
  4278. #define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
  4279. #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
  4280. #define BNX2_TDMA_FTQ_CMD_POP (1L<<30)
  4281. #define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31)
  4282. #define BNX2_TDMA_FTQ_CTL 0x00005ffc
  4283. #define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0)
  4284. #define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
  4285. #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  4286. #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  4287. #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  4288. /*
  4289. * hc_reg definition
  4290. * offset: 0x6800
  4291. */
  4292. #define BNX2_HC_COMMAND 0x00006800
  4293. #define BNX2_HC_COMMAND_ENABLE (1L<<0)
  4294. #define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4)
  4295. #define BNX2_HC_COMMAND_COAL_NOW (1L<<16)
  4296. #define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
  4297. #define BNX2_HC_COMMAND_STATS_NOW (1L<<18)
  4298. #define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19)
  4299. #define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
  4300. #define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
  4301. #define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19)
  4302. #define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19)
  4303. #define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21)
  4304. #define BNX2_HC_COMMAND_MAIN_PWR_INT (1L<<22)
  4305. #define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT (1L<<27)
  4306. #define BNX2_HC_STATUS 0x00006804
  4307. #define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
  4308. #define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
  4309. #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
  4310. #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
  4311. #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
  4312. #define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
  4313. #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
  4314. #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
  4315. #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
  4316. #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
  4317. #define BNX2_HC_CONFIG 0x00006808
  4318. #define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0)
  4319. #define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1)
  4320. #define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2)
  4321. #define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3)
  4322. #define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4)
  4323. #define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
  4324. #define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6)
  4325. #define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
  4326. #define BNX2_HC_CONFIG_PER_MODE (1L<<16)
  4327. #define BNX2_HC_CONFIG_ONE_SHOT (1L<<17)
  4328. #define BNX2_HC_CONFIG_USE_INT_PARAM (1L<<18)
  4329. #define BNX2_HC_CONFIG_SET_MASK_AT_RD (1L<<19)
  4330. #define BNX2_HC_CONFIG_PER_COLLECT_LIMIT (0xfL<<20)
  4331. #define BNX2_HC_CONFIG_SB_ADDR_INC (0x7L<<24)
  4332. #define BNX2_HC_CONFIG_SB_ADDR_INC_64B (0L<<24)
  4333. #define BNX2_HC_CONFIG_SB_ADDR_INC_128B (1L<<24)
  4334. #define BNX2_HC_CONFIG_SB_ADDR_INC_256B (2L<<24)
  4335. #define BNX2_HC_CONFIG_SB_ADDR_INC_512B (3L<<24)
  4336. #define BNX2_HC_CONFIG_SB_ADDR_INC_1024B (4L<<24)
  4337. #define BNX2_HC_CONFIG_SB_ADDR_INC_2048B (5L<<24)
  4338. #define BNX2_HC_CONFIG_SB_ADDR_INC_4096B (6L<<24)
  4339. #define BNX2_HC_CONFIG_SB_ADDR_INC_8192B (7L<<24)
  4340. #define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR (1L<<29)
  4341. #define BNX2_HC_CONFIG_UNMASK_ALL (1L<<30)
  4342. #define BNX2_HC_CONFIG_TX_SEL (1L<<31)
  4343. #define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c
  4344. #define BNX2_HC_STATUS_ADDR_L 0x00006810
  4345. #define BNX2_HC_STATUS_ADDR_H 0x00006814
  4346. #define BNX2_HC_STATISTICS_ADDR_L 0x00006818
  4347. #define BNX2_HC_STATISTICS_ADDR_H 0x0000681c
  4348. #define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820
  4349. #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
  4350. #define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
  4351. #define BNX2_HC_COMP_PROD_TRIP 0x00006824
  4352. #define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
  4353. #define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16)
  4354. #define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828
  4355. #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
  4356. #define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
  4357. #define BNX2_HC_RX_TICKS 0x0000682c
  4358. #define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0)
  4359. #define BNX2_HC_RX_TICKS_INT (0x3ffL<<16)
  4360. #define BNX2_HC_TX_TICKS 0x00006830
  4361. #define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0)
  4362. #define BNX2_HC_TX_TICKS_INT (0x3ffL<<16)
  4363. #define BNX2_HC_COM_TICKS 0x00006834
  4364. #define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0)
  4365. #define BNX2_HC_COM_TICKS_INT (0x3ffL<<16)
  4366. #define BNX2_HC_CMD_TICKS 0x00006838
  4367. #define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0)
  4368. #define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16)
  4369. #define BNX2_HC_PERIODIC_TICKS 0x0000683c
  4370. #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
  4371. #define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffL<<16)
  4372. #define BNX2_HC_STAT_COLLECT_TICKS 0x00006840
  4373. #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
  4374. #define BNX2_HC_STATS_TICKS 0x00006844
  4375. #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
  4376. #define BNX2_HC_STATS_INTERRUPT_STATUS 0x00006848
  4377. #define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffL<<0)
  4378. #define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffL<<16)
  4379. #define BNX2_HC_STAT_MEM_DATA 0x0000684c
  4380. #define BNX2_HC_STAT_GEN_SEL_0 0x00006850
  4381. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
  4382. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
  4383. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
  4384. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
  4385. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
  4386. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
  4387. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
  4388. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
  4389. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
  4390. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
  4391. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
  4392. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
  4393. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
  4394. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
  4395. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
  4396. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
  4397. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
  4398. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
  4399. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
  4400. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
  4401. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
  4402. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
  4403. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
  4404. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
  4405. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
  4406. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
  4407. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
  4408. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
  4409. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
  4410. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
  4411. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
  4412. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
  4413. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
  4414. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
  4415. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
  4416. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
  4417. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
  4418. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
  4419. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
  4420. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
  4421. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
  4422. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
  4423. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
  4424. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
  4425. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
  4426. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
  4427. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
  4428. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
  4429. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
  4430. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
  4431. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
  4432. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
  4433. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
  4434. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
  4435. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
  4436. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
  4437. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
  4438. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
  4439. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
  4440. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
  4441. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
  4442. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
  4443. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
  4444. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
  4445. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
  4446. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
  4447. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
  4448. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
  4449. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
  4450. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
  4451. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
  4452. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
  4453. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
  4454. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
  4455. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
  4456. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
  4457. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
  4458. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
  4459. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
  4460. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
  4461. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
  4462. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
  4463. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
  4464. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
  4465. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
  4466. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
  4467. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
  4468. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
  4469. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
  4470. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
  4471. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
  4472. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
  4473. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
  4474. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
  4475. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
  4476. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
  4477. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
  4478. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
  4479. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
  4480. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
  4481. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
  4482. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
  4483. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
  4484. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
  4485. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
  4486. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
  4487. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
  4488. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
  4489. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
  4490. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
  4491. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
  4492. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
  4493. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
  4494. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
  4495. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
  4496. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
  4497. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
  4498. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
  4499. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
  4500. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
  4501. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
  4502. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
  4503. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
  4504. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
  4505. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
  4506. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
  4507. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI (0xffL<<0)
  4508. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52L<<0)
  4509. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57L<<0)
  4510. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58L<<0)
  4511. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85L<<0)
  4512. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86L<<0)
  4513. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87L<<0)
  4514. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88L<<0)
  4515. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89L<<0)
  4516. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90L<<0)
  4517. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91L<<0)
  4518. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92L<<0)
  4519. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93L<<0)
  4520. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94L<<0)
  4521. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123L<<0)
  4522. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124L<<0)
  4523. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125L<<0)
  4524. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126L<<0)
  4525. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128L<<0)
  4526. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129L<<0)
  4527. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130L<<0)
  4528. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131L<<0)
  4529. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132L<<0)
  4530. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133L<<0)
  4531. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134L<<0)
  4532. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135L<<0)
  4533. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136L<<0)
  4534. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137L<<0)
  4535. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138L<<0)
  4536. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139L<<0)
  4537. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140L<<0)
  4538. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141L<<0)
  4539. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142L<<0)
  4540. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143L<<0)
  4541. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144L<<0)
  4542. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145L<<0)
  4543. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146L<<0)
  4544. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147L<<0)
  4545. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148L<<0)
  4546. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149L<<0)
  4547. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150L<<0)
  4548. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151L<<0)
  4549. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152L<<0)
  4550. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153L<<0)
  4551. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154L<<0)
  4552. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155L<<0)
  4553. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156L<<0)
  4554. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157L<<0)
  4555. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158L<<0)
  4556. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159L<<0)
  4557. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160L<<0)
  4558. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161L<<0)
  4559. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162L<<0)
  4560. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163L<<0)
  4561. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164L<<0)
  4562. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165L<<0)
  4563. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166L<<0)
  4564. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167L<<0)
  4565. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168L<<0)
  4566. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169L<<0)
  4567. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170L<<0)
  4568. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171L<<0)
  4569. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172L<<0)
  4570. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173L<<0)
  4571. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174L<<0)
  4572. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175L<<0)
  4573. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176L<<0)
  4574. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177L<<0)
  4575. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178L<<0)
  4576. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI (0xffL<<8)
  4577. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI (0xffL<<16)
  4578. #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI (0xffL<<24)
  4579. #define BNX2_HC_STAT_GEN_SEL_1 0x00006854
  4580. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
  4581. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
  4582. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
  4583. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
  4584. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI (0xffL<<0)
  4585. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI (0xffL<<8)
  4586. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI (0xffL<<16)
  4587. #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI (0xffL<<24)
  4588. #define BNX2_HC_STAT_GEN_SEL_2 0x00006858
  4589. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
  4590. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
  4591. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
  4592. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
  4593. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI (0xffL<<0)
  4594. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI (0xffL<<8)
  4595. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI (0xffL<<16)
  4596. #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI (0xffL<<24)
  4597. #define BNX2_HC_STAT_GEN_SEL_3 0x0000685c
  4598. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
  4599. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
  4600. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
  4601. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
  4602. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI (0xffL<<0)
  4603. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI (0xffL<<8)
  4604. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI (0xffL<<16)
  4605. #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI (0xffL<<24)
  4606. #define BNX2_HC_STAT_GEN_STAT0 0x00006888
  4607. #define BNX2_HC_STAT_GEN_STAT1 0x0000688c
  4608. #define BNX2_HC_STAT_GEN_STAT2 0x00006890
  4609. #define BNX2_HC_STAT_GEN_STAT3 0x00006894
  4610. #define BNX2_HC_STAT_GEN_STAT4 0x00006898
  4611. #define BNX2_HC_STAT_GEN_STAT5 0x0000689c
  4612. #define BNX2_HC_STAT_GEN_STAT6 0x000068a0
  4613. #define BNX2_HC_STAT_GEN_STAT7 0x000068a4
  4614. #define BNX2_HC_STAT_GEN_STAT8 0x000068a8
  4615. #define BNX2_HC_STAT_GEN_STAT9 0x000068ac
  4616. #define BNX2_HC_STAT_GEN_STAT10 0x000068b0
  4617. #define BNX2_HC_STAT_GEN_STAT11 0x000068b4
  4618. #define BNX2_HC_STAT_GEN_STAT12 0x000068b8
  4619. #define BNX2_HC_STAT_GEN_STAT13 0x000068bc
  4620. #define BNX2_HC_STAT_GEN_STAT14 0x000068c0
  4621. #define BNX2_HC_STAT_GEN_STAT15 0x000068c4
  4622. #define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8
  4623. #define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc
  4624. #define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0
  4625. #define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4
  4626. #define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8
  4627. #define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc
  4628. #define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0
  4629. #define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4
  4630. #define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8
  4631. #define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec
  4632. #define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0
  4633. #define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4
  4634. #define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8
  4635. #define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc
  4636. #define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900
  4637. #define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904
  4638. #define BNX2_HC_STAT_GEN_STAT_AC 0x000068c8
  4639. #define BNX2_HC_VIS 0x00006908
  4640. #define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
  4641. #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
  4642. #define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
  4643. #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
  4644. #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
  4645. #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
  4646. #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
  4647. #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
  4648. #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
  4649. #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
  4650. #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
  4651. #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
  4652. #define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8)
  4653. #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
  4654. #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
  4655. #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
  4656. #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
  4657. #define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
  4658. #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
  4659. #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
  4660. #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
  4661. #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
  4662. #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
  4663. #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
  4664. #define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12)
  4665. #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
  4666. #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
  4667. #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
  4668. #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
  4669. #define BNX2_HC_VIS_1 0x0000690c
  4670. #define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4)
  4671. #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
  4672. #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
  4673. #define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5)
  4674. #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
  4675. #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
  4676. #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
  4677. #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
  4678. #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
  4679. #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
  4680. #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
  4681. #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
  4682. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
  4683. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
  4684. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
  4685. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
  4686. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
  4687. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
  4688. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
  4689. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
  4690. #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
  4691. #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
  4692. #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
  4693. #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
  4694. #define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23)
  4695. #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
  4696. #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
  4697. #define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
  4698. #define BNX2_HC_VIS_1_INT_B (1L<<27)
  4699. #define BNX2_HC_DEBUG_VECT_PEEK 0x00006910
  4700. #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  4701. #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  4702. #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  4703. #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  4704. #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  4705. #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  4706. #define BNX2_HC_COALESCE_NOW 0x00006914
  4707. #define BNX2_HC_COALESCE_NOW_COAL_NOW (0x1ffL<<1)
  4708. #define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffL<<11)
  4709. #define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffL<<21)
  4710. #define BNX2_HC_MSIX_BIT_VECTOR 0x00006918
  4711. #define BNX2_HC_MSIX_BIT_VECTOR_VAL (0x1ffL<<0)
  4712. #define BNX2_HC_SB_CONFIG_1 0x00006a00
  4713. #define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE (1L<<1)
  4714. #define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE (1L<<2)
  4715. #define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE (1L<<3)
  4716. #define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE (1L<<4)
  4717. #define BNX2_HC_SB_CONFIG_1_PER_MODE (1L<<16)
  4718. #define BNX2_HC_SB_CONFIG_1_ONE_SHOT (1L<<17)
  4719. #define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM (1L<<18)
  4720. #define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfL<<20)
  4721. #define BNX2_HC_TX_QUICK_CONS_TRIP_1 0x00006a04
  4722. #define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0)
  4723. #define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT (0xffL<<16)
  4724. #define BNX2_HC_COMP_PROD_TRIP_1 0x00006a08
  4725. #define BNX2_HC_COMP_PROD_TRIP_1_VALUE (0xffL<<0)
  4726. #define BNX2_HC_COMP_PROD_TRIP_1_INT (0xffL<<16)
  4727. #define BNX2_HC_RX_QUICK_CONS_TRIP_1 0x00006a0c
  4728. #define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0)
  4729. #define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT (0xffL<<16)
  4730. #define BNX2_HC_RX_TICKS_1 0x00006a10
  4731. #define BNX2_HC_RX_TICKS_1_VALUE (0x3ffL<<0)
  4732. #define BNX2_HC_RX_TICKS_1_INT (0x3ffL<<16)
  4733. #define BNX2_HC_TX_TICKS_1 0x00006a14
  4734. #define BNX2_HC_TX_TICKS_1_VALUE (0x3ffL<<0)
  4735. #define BNX2_HC_TX_TICKS_1_INT (0x3ffL<<16)
  4736. #define BNX2_HC_COM_TICKS_1 0x00006a18
  4737. #define BNX2_HC_COM_TICKS_1_VALUE (0x3ffL<<0)
  4738. #define BNX2_HC_COM_TICKS_1_INT (0x3ffL<<16)
  4739. #define BNX2_HC_CMD_TICKS_1 0x00006a1c
  4740. #define BNX2_HC_CMD_TICKS_1_VALUE (0x3ffL<<0)
  4741. #define BNX2_HC_CMD_TICKS_1_INT (0x3ffL<<16)
  4742. #define BNX2_HC_PERIODIC_TICKS_1 0x00006a20
  4743. #define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffL<<0)
  4744. #define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffL<<16)
  4745. #define BNX2_HC_SB_CONFIG_2 0x00006a24
  4746. #define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE (1L<<1)
  4747. #define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE (1L<<2)
  4748. #define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE (1L<<3)
  4749. #define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE (1L<<4)
  4750. #define BNX2_HC_SB_CONFIG_2_PER_MODE (1L<<16)
  4751. #define BNX2_HC_SB_CONFIG_2_ONE_SHOT (1L<<17)
  4752. #define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM (1L<<18)
  4753. #define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfL<<20)
  4754. #define BNX2_HC_TX_QUICK_CONS_TRIP_2 0x00006a28
  4755. #define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0)
  4756. #define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT (0xffL<<16)
  4757. #define BNX2_HC_COMP_PROD_TRIP_2 0x00006a2c
  4758. #define BNX2_HC_COMP_PROD_TRIP_2_VALUE (0xffL<<0)
  4759. #define BNX2_HC_COMP_PROD_TRIP_2_INT (0xffL<<16)
  4760. #define BNX2_HC_RX_QUICK_CONS_TRIP_2 0x00006a30
  4761. #define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0)
  4762. #define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT (0xffL<<16)
  4763. #define BNX2_HC_RX_TICKS_2 0x00006a34
  4764. #define BNX2_HC_RX_TICKS_2_VALUE (0x3ffL<<0)
  4765. #define BNX2_HC_RX_TICKS_2_INT (0x3ffL<<16)
  4766. #define BNX2_HC_TX_TICKS_2 0x00006a38
  4767. #define BNX2_HC_TX_TICKS_2_VALUE (0x3ffL<<0)
  4768. #define BNX2_HC_TX_TICKS_2_INT (0x3ffL<<16)
  4769. #define BNX2_HC_COM_TICKS_2 0x00006a3c
  4770. #define BNX2_HC_COM_TICKS_2_VALUE (0x3ffL<<0)
  4771. #define BNX2_HC_COM_TICKS_2_INT (0x3ffL<<16)
  4772. #define BNX2_HC_CMD_TICKS_2 0x00006a40
  4773. #define BNX2_HC_CMD_TICKS_2_VALUE (0x3ffL<<0)
  4774. #define BNX2_HC_CMD_TICKS_2_INT (0x3ffL<<16)
  4775. #define BNX2_HC_PERIODIC_TICKS_2 0x00006a44
  4776. #define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffL<<0)
  4777. #define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffL<<16)
  4778. #define BNX2_HC_SB_CONFIG_3 0x00006a48
  4779. #define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE (1L<<1)
  4780. #define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE (1L<<2)
  4781. #define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE (1L<<3)
  4782. #define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE (1L<<4)
  4783. #define BNX2_HC_SB_CONFIG_3_PER_MODE (1L<<16)
  4784. #define BNX2_HC_SB_CONFIG_3_ONE_SHOT (1L<<17)
  4785. #define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM (1L<<18)
  4786. #define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfL<<20)
  4787. #define BNX2_HC_TX_QUICK_CONS_TRIP_3 0x00006a4c
  4788. #define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0)
  4789. #define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT (0xffL<<16)
  4790. #define BNX2_HC_COMP_PROD_TRIP_3 0x00006a50
  4791. #define BNX2_HC_COMP_PROD_TRIP_3_VALUE (0xffL<<0)
  4792. #define BNX2_HC_COMP_PROD_TRIP_3_INT (0xffL<<16)
  4793. #define BNX2_HC_RX_QUICK_CONS_TRIP_3 0x00006a54
  4794. #define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0)
  4795. #define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT (0xffL<<16)
  4796. #define BNX2_HC_RX_TICKS_3 0x00006a58
  4797. #define BNX2_HC_RX_TICKS_3_VALUE (0x3ffL<<0)
  4798. #define BNX2_HC_RX_TICKS_3_INT (0x3ffL<<16)
  4799. #define BNX2_HC_TX_TICKS_3 0x00006a5c
  4800. #define BNX2_HC_TX_TICKS_3_VALUE (0x3ffL<<0)
  4801. #define BNX2_HC_TX_TICKS_3_INT (0x3ffL<<16)
  4802. #define BNX2_HC_COM_TICKS_3 0x00006a60
  4803. #define BNX2_HC_COM_TICKS_3_VALUE (0x3ffL<<0)
  4804. #define BNX2_HC_COM_TICKS_3_INT (0x3ffL<<16)
  4805. #define BNX2_HC_CMD_TICKS_3 0x00006a64
  4806. #define BNX2_HC_CMD_TICKS_3_VALUE (0x3ffL<<0)
  4807. #define BNX2_HC_CMD_TICKS_3_INT (0x3ffL<<16)
  4808. #define BNX2_HC_PERIODIC_TICKS_3 0x00006a68
  4809. #define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffL<<0)
  4810. #define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffL<<16)
  4811. #define BNX2_HC_SB_CONFIG_4 0x00006a6c
  4812. #define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE (1L<<1)
  4813. #define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE (1L<<2)
  4814. #define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE (1L<<3)
  4815. #define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE (1L<<4)
  4816. #define BNX2_HC_SB_CONFIG_4_PER_MODE (1L<<16)
  4817. #define BNX2_HC_SB_CONFIG_4_ONE_SHOT (1L<<17)
  4818. #define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM (1L<<18)
  4819. #define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfL<<20)
  4820. #define BNX2_HC_TX_QUICK_CONS_TRIP_4 0x00006a70
  4821. #define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0)
  4822. #define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT (0xffL<<16)
  4823. #define BNX2_HC_COMP_PROD_TRIP_4 0x00006a74
  4824. #define BNX2_HC_COMP_PROD_TRIP_4_VALUE (0xffL<<0)
  4825. #define BNX2_HC_COMP_PROD_TRIP_4_INT (0xffL<<16)
  4826. #define BNX2_HC_RX_QUICK_CONS_TRIP_4 0x00006a78
  4827. #define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0)
  4828. #define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT (0xffL<<16)
  4829. #define BNX2_HC_RX_TICKS_4 0x00006a7c
  4830. #define BNX2_HC_RX_TICKS_4_VALUE (0x3ffL<<0)
  4831. #define BNX2_HC_RX_TICKS_4_INT (0x3ffL<<16)
  4832. #define BNX2_HC_TX_TICKS_4 0x00006a80
  4833. #define BNX2_HC_TX_TICKS_4_VALUE (0x3ffL<<0)
  4834. #define BNX2_HC_TX_TICKS_4_INT (0x3ffL<<16)
  4835. #define BNX2_HC_COM_TICKS_4 0x00006a84
  4836. #define BNX2_HC_COM_TICKS_4_VALUE (0x3ffL<<0)
  4837. #define BNX2_HC_COM_TICKS_4_INT (0x3ffL<<16)
  4838. #define BNX2_HC_CMD_TICKS_4 0x00006a88
  4839. #define BNX2_HC_CMD_TICKS_4_VALUE (0x3ffL<<0)
  4840. #define BNX2_HC_CMD_TICKS_4_INT (0x3ffL<<16)
  4841. #define BNX2_HC_PERIODIC_TICKS_4 0x00006a8c
  4842. #define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffL<<0)
  4843. #define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffL<<16)
  4844. #define BNX2_HC_SB_CONFIG_5 0x00006a90
  4845. #define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE (1L<<1)
  4846. #define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE (1L<<2)
  4847. #define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE (1L<<3)
  4848. #define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE (1L<<4)
  4849. #define BNX2_HC_SB_CONFIG_5_PER_MODE (1L<<16)
  4850. #define BNX2_HC_SB_CONFIG_5_ONE_SHOT (1L<<17)
  4851. #define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM (1L<<18)
  4852. #define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfL<<20)
  4853. #define BNX2_HC_TX_QUICK_CONS_TRIP_5 0x00006a94
  4854. #define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0)
  4855. #define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT (0xffL<<16)
  4856. #define BNX2_HC_COMP_PROD_TRIP_5 0x00006a98
  4857. #define BNX2_HC_COMP_PROD_TRIP_5_VALUE (0xffL<<0)
  4858. #define BNX2_HC_COMP_PROD_TRIP_5_INT (0xffL<<16)
  4859. #define BNX2_HC_RX_QUICK_CONS_TRIP_5 0x00006a9c
  4860. #define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0)
  4861. #define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT (0xffL<<16)
  4862. #define BNX2_HC_RX_TICKS_5 0x00006aa0
  4863. #define BNX2_HC_RX_TICKS_5_VALUE (0x3ffL<<0)
  4864. #define BNX2_HC_RX_TICKS_5_INT (0x3ffL<<16)
  4865. #define BNX2_HC_TX_TICKS_5 0x00006aa4
  4866. #define BNX2_HC_TX_TICKS_5_VALUE (0x3ffL<<0)
  4867. #define BNX2_HC_TX_TICKS_5_INT (0x3ffL<<16)
  4868. #define BNX2_HC_COM_TICKS_5 0x00006aa8
  4869. #define BNX2_HC_COM_TICKS_5_VALUE (0x3ffL<<0)
  4870. #define BNX2_HC_COM_TICKS_5_INT (0x3ffL<<16)
  4871. #define BNX2_HC_CMD_TICKS_5 0x00006aac
  4872. #define BNX2_HC_CMD_TICKS_5_VALUE (0x3ffL<<0)
  4873. #define BNX2_HC_CMD_TICKS_5_INT (0x3ffL<<16)
  4874. #define BNX2_HC_PERIODIC_TICKS_5 0x00006ab0
  4875. #define BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffL<<0)
  4876. #define BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffL<<16)
  4877. #define BNX2_HC_SB_CONFIG_6 0x00006ab4
  4878. #define BNX2_HC_SB_CONFIG_6_RX_TMR_MODE (1L<<1)
  4879. #define BNX2_HC_SB_CONFIG_6_TX_TMR_MODE (1L<<2)
  4880. #define BNX2_HC_SB_CONFIG_6_COM_TMR_MODE (1L<<3)
  4881. #define BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE (1L<<4)
  4882. #define BNX2_HC_SB_CONFIG_6_PER_MODE (1L<<16)
  4883. #define BNX2_HC_SB_CONFIG_6_ONE_SHOT (1L<<17)
  4884. #define BNX2_HC_SB_CONFIG_6_USE_INT_PARAM (1L<<18)
  4885. #define BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfL<<20)
  4886. #define BNX2_HC_TX_QUICK_CONS_TRIP_6 0x00006ab8
  4887. #define BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0)
  4888. #define BNX2_HC_TX_QUICK_CONS_TRIP_6_INT (0xffL<<16)
  4889. #define BNX2_HC_COMP_PROD_TRIP_6 0x00006abc
  4890. #define BNX2_HC_COMP_PROD_TRIP_6_VALUE (0xffL<<0)
  4891. #define BNX2_HC_COMP_PROD_TRIP_6_INT (0xffL<<16)
  4892. #define BNX2_HC_RX_QUICK_CONS_TRIP_6 0x00006ac0
  4893. #define BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0)
  4894. #define BNX2_HC_RX_QUICK_CONS_TRIP_6_INT (0xffL<<16)
  4895. #define BNX2_HC_RX_TICKS_6 0x00006ac4
  4896. #define BNX2_HC_RX_TICKS_6_VALUE (0x3ffL<<0)
  4897. #define BNX2_HC_RX_TICKS_6_INT (0x3ffL<<16)
  4898. #define BNX2_HC_TX_TICKS_6 0x00006ac8
  4899. #define BNX2_HC_TX_TICKS_6_VALUE (0x3ffL<<0)
  4900. #define BNX2_HC_TX_TICKS_6_INT (0x3ffL<<16)
  4901. #define BNX2_HC_COM_TICKS_6 0x00006acc
  4902. #define BNX2_HC_COM_TICKS_6_VALUE (0x3ffL<<0)
  4903. #define BNX2_HC_COM_TICKS_6_INT (0x3ffL<<16)
  4904. #define BNX2_HC_CMD_TICKS_6 0x00006ad0
  4905. #define BNX2_HC_CMD_TICKS_6_VALUE (0x3ffL<<0)
  4906. #define BNX2_HC_CMD_TICKS_6_INT (0x3ffL<<16)
  4907. #define BNX2_HC_PERIODIC_TICKS_6 0x00006ad4
  4908. #define BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffL<<0)
  4909. #define BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffL<<16)
  4910. #define BNX2_HC_SB_CONFIG_7 0x00006ad8
  4911. #define BNX2_HC_SB_CONFIG_7_RX_TMR_MODE (1L<<1)
  4912. #define BNX2_HC_SB_CONFIG_7_TX_TMR_MODE (1L<<2)
  4913. #define BNX2_HC_SB_CONFIG_7_COM_TMR_MODE (1L<<3)
  4914. #define BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE (1L<<4)
  4915. #define BNX2_HC_SB_CONFIG_7_PER_MODE (1L<<16)
  4916. #define BNX2_HC_SB_CONFIG_7_ONE_SHOT (1L<<17)
  4917. #define BNX2_HC_SB_CONFIG_7_USE_INT_PARAM (1L<<18)
  4918. #define BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfL<<20)
  4919. #define BNX2_HC_TX_QUICK_CONS_TRIP_7 0x00006adc
  4920. #define BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0)
  4921. #define BNX2_HC_TX_QUICK_CONS_TRIP_7_INT (0xffL<<16)
  4922. #define BNX2_HC_COMP_PROD_TRIP_7 0x00006ae0
  4923. #define BNX2_HC_COMP_PROD_TRIP_7_VALUE (0xffL<<0)
  4924. #define BNX2_HC_COMP_PROD_TRIP_7_INT (0xffL<<16)
  4925. #define BNX2_HC_RX_QUICK_CONS_TRIP_7 0x00006ae4
  4926. #define BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0)
  4927. #define BNX2_HC_RX_QUICK_CONS_TRIP_7_INT (0xffL<<16)
  4928. #define BNX2_HC_RX_TICKS_7 0x00006ae8
  4929. #define BNX2_HC_RX_TICKS_7_VALUE (0x3ffL<<0)
  4930. #define BNX2_HC_RX_TICKS_7_INT (0x3ffL<<16)
  4931. #define BNX2_HC_TX_TICKS_7 0x00006aec
  4932. #define BNX2_HC_TX_TICKS_7_VALUE (0x3ffL<<0)
  4933. #define BNX2_HC_TX_TICKS_7_INT (0x3ffL<<16)
  4934. #define BNX2_HC_COM_TICKS_7 0x00006af0
  4935. #define BNX2_HC_COM_TICKS_7_VALUE (0x3ffL<<0)
  4936. #define BNX2_HC_COM_TICKS_7_INT (0x3ffL<<16)
  4937. #define BNX2_HC_CMD_TICKS_7 0x00006af4
  4938. #define BNX2_HC_CMD_TICKS_7_VALUE (0x3ffL<<0)
  4939. #define BNX2_HC_CMD_TICKS_7_INT (0x3ffL<<16)
  4940. #define BNX2_HC_PERIODIC_TICKS_7 0x00006af8
  4941. #define BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffL<<0)
  4942. #define BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffL<<16)
  4943. #define BNX2_HC_SB_CONFIG_8 0x00006afc
  4944. #define BNX2_HC_SB_CONFIG_8_RX_TMR_MODE (1L<<1)
  4945. #define BNX2_HC_SB_CONFIG_8_TX_TMR_MODE (1L<<2)
  4946. #define BNX2_HC_SB_CONFIG_8_COM_TMR_MODE (1L<<3)
  4947. #define BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE (1L<<4)
  4948. #define BNX2_HC_SB_CONFIG_8_PER_MODE (1L<<16)
  4949. #define BNX2_HC_SB_CONFIG_8_ONE_SHOT (1L<<17)
  4950. #define BNX2_HC_SB_CONFIG_8_USE_INT_PARAM (1L<<18)
  4951. #define BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfL<<20)
  4952. #define BNX2_HC_TX_QUICK_CONS_TRIP_8 0x00006b00
  4953. #define BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0)
  4954. #define BNX2_HC_TX_QUICK_CONS_TRIP_8_INT (0xffL<<16)
  4955. #define BNX2_HC_COMP_PROD_TRIP_8 0x00006b04
  4956. #define BNX2_HC_COMP_PROD_TRIP_8_VALUE (0xffL<<0)
  4957. #define BNX2_HC_COMP_PROD_TRIP_8_INT (0xffL<<16)
  4958. #define BNX2_HC_RX_QUICK_CONS_TRIP_8 0x00006b08
  4959. #define BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0)
  4960. #define BNX2_HC_RX_QUICK_CONS_TRIP_8_INT (0xffL<<16)
  4961. #define BNX2_HC_RX_TICKS_8 0x00006b0c
  4962. #define BNX2_HC_RX_TICKS_8_VALUE (0x3ffL<<0)
  4963. #define BNX2_HC_RX_TICKS_8_INT (0x3ffL<<16)
  4964. #define BNX2_HC_TX_TICKS_8 0x00006b10
  4965. #define BNX2_HC_TX_TICKS_8_VALUE (0x3ffL<<0)
  4966. #define BNX2_HC_TX_TICKS_8_INT (0x3ffL<<16)
  4967. #define BNX2_HC_COM_TICKS_8 0x00006b14
  4968. #define BNX2_HC_COM_TICKS_8_VALUE (0x3ffL<<0)
  4969. #define BNX2_HC_COM_TICKS_8_INT (0x3ffL<<16)
  4970. #define BNX2_HC_CMD_TICKS_8 0x00006b18
  4971. #define BNX2_HC_CMD_TICKS_8_VALUE (0x3ffL<<0)
  4972. #define BNX2_HC_CMD_TICKS_8_INT (0x3ffL<<16)
  4973. #define BNX2_HC_PERIODIC_TICKS_8 0x00006b1c
  4974. #define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0)
  4975. #define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16)
  4976. /*
  4977. * txp_reg definition
  4978. * offset: 0x40000
  4979. */
  4980. #define BNX2_TXP_CPU_MODE 0x00045000
  4981. #define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0)
  4982. #define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1)
  4983. #define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  4984. #define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  4985. #define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
  4986. #define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
  4987. #define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10)
  4988. #define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  4989. #define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  4990. #define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  4991. #define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  4992. #define BNX2_TXP_CPU_STATE 0x00045004
  4993. #define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0)
  4994. #define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
  4995. #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  4996. #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  4997. #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  4998. #define BNX2_TXP_CPU_STATE_BAD_PC_HALTED (1L<<6)
  4999. #define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
  5000. #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  5001. #define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
  5002. #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  5003. #define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12)
  5004. #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  5005. #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
  5006. #define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
  5007. #define BNX2_TXP_CPU_EVENT_MASK 0x00045008
  5008. #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  5009. #define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  5010. #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  5011. #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  5012. #define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  5013. #define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  5014. #define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  5015. #define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  5016. #define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  5017. #define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  5018. #define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  5019. #define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c
  5020. #define BNX2_TXP_CPU_INSTRUCTION 0x00045020
  5021. #define BNX2_TXP_CPU_DATA_ACCESS 0x00045024
  5022. #define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028
  5023. #define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
  5024. #define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
  5025. #define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034
  5026. #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  5027. #define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  5028. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
  5029. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  5030. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  5031. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  5032. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  5033. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  5034. #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  5035. #define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
  5036. #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  5037. #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  5038. #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  5039. #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  5040. #define BNX2_TXP_CPU_REG_FILE 0x00045200
  5041. #define BNX2_TXP_TXPQ 0x000453c0
  5042. #define BNX2_TXP_FTQ_CMD 0x000453f8
  5043. #define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
  5044. #define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10)
  5045. #define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
  5046. #define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
  5047. #define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25)
  5048. #define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26)
  5049. #define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
  5050. #define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28)
  5051. #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
  5052. #define BNX2_TXP_FTQ_CMD_POP (1L<<30)
  5053. #define BNX2_TXP_FTQ_CMD_BUSY (1L<<31)
  5054. #define BNX2_TXP_FTQ_CTL 0x000453fc
  5055. #define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0)
  5056. #define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1)
  5057. #define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  5058. #define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  5059. #define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  5060. #define BNX2_TXP_SCRATCH 0x00060000
  5061. /*
  5062. * tpat_reg definition
  5063. * offset: 0x80000
  5064. */
  5065. #define BNX2_TPAT_CPU_MODE 0x00085000
  5066. #define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
  5067. #define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1)
  5068. #define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  5069. #define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  5070. #define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
  5071. #define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
  5072. #define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
  5073. #define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  5074. #define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  5075. #define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  5076. #define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  5077. #define BNX2_TPAT_CPU_STATE 0x00085004
  5078. #define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
  5079. #define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
  5080. #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  5081. #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  5082. #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  5083. #define BNX2_TPAT_CPU_STATE_BAD_PC_HALTED (1L<<6)
  5084. #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
  5085. #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  5086. #define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
  5087. #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  5088. #define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
  5089. #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  5090. #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
  5091. #define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
  5092. #define BNX2_TPAT_CPU_EVENT_MASK 0x00085008
  5093. #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  5094. #define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  5095. #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  5096. #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  5097. #define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  5098. #define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  5099. #define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  5100. #define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  5101. #define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  5102. #define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  5103. #define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  5104. #define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
  5105. #define BNX2_TPAT_CPU_INSTRUCTION 0x00085020
  5106. #define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024
  5107. #define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
  5108. #define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
  5109. #define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
  5110. #define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034
  5111. #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  5112. #define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  5113. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
  5114. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  5115. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  5116. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  5117. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  5118. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  5119. #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  5120. #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
  5121. #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  5122. #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  5123. #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  5124. #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  5125. #define BNX2_TPAT_CPU_REG_FILE 0x00085200
  5126. #define BNX2_TPAT_TPATQ 0x000853c0
  5127. #define BNX2_TPAT_FTQ_CMD 0x000853f8
  5128. #define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
  5129. #define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10)
  5130. #define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
  5131. #define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
  5132. #define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
  5133. #define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26)
  5134. #define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
  5135. #define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
  5136. #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
  5137. #define BNX2_TPAT_FTQ_CMD_POP (1L<<30)
  5138. #define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31)
  5139. #define BNX2_TPAT_FTQ_CTL 0x000853fc
  5140. #define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0)
  5141. #define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
  5142. #define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  5143. #define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  5144. #define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  5145. #define BNX2_TPAT_SCRATCH 0x000a0000
  5146. /*
  5147. * rxp_reg definition
  5148. * offset: 0xc0000
  5149. */
  5150. #define BNX2_RXP_CPU_MODE 0x000c5000
  5151. #define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0)
  5152. #define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1)
  5153. #define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  5154. #define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  5155. #define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
  5156. #define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
  5157. #define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10)
  5158. #define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  5159. #define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  5160. #define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  5161. #define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  5162. #define BNX2_RXP_CPU_STATE 0x000c5004
  5163. #define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0)
  5164. #define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
  5165. #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  5166. #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  5167. #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  5168. #define BNX2_RXP_CPU_STATE_BAD_PC_HALTED (1L<<6)
  5169. #define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
  5170. #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  5171. #define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
  5172. #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  5173. #define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12)
  5174. #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  5175. #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
  5176. #define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
  5177. #define BNX2_RXP_CPU_EVENT_MASK 0x000c5008
  5178. #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  5179. #define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  5180. #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  5181. #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  5182. #define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  5183. #define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  5184. #define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  5185. #define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  5186. #define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  5187. #define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  5188. #define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  5189. #define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c
  5190. #define BNX2_RXP_CPU_INSTRUCTION 0x000c5020
  5191. #define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024
  5192. #define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
  5193. #define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
  5194. #define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
  5195. #define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034
  5196. #define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  5197. #define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  5198. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
  5199. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  5200. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  5201. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  5202. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  5203. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  5204. #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  5205. #define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
  5206. #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  5207. #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  5208. #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  5209. #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  5210. #define BNX2_RXP_CPU_REG_FILE 0x000c5200
  5211. #define BNX2_RXP_PFE_PFE_CTL 0x000c537c
  5212. #define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
  5213. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
  5214. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
  5215. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
  5216. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
  5217. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
  5218. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
  5219. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
  5220. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
  5221. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
  5222. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
  5223. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
  5224. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
  5225. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
  5226. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
  5227. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
  5228. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
  5229. #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
  5230. #define BNX2_RXP_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
  5231. #define BNX2_RXP_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
  5232. #define BNX2_RXP_RXPCQ 0x000c5380
  5233. #define BNX2_RXP_CFTQ_CMD 0x000c53b8
  5234. #define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
  5235. #define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10)
  5236. #define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
  5237. #define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
  5238. #define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
  5239. #define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26)
  5240. #define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
  5241. #define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
  5242. #define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
  5243. #define BNX2_RXP_CFTQ_CMD_POP (1L<<30)
  5244. #define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31)
  5245. #define BNX2_RXP_CFTQ_CTL 0x000c53bc
  5246. #define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0)
  5247. #define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
  5248. #define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
  5249. #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  5250. #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  5251. #define BNX2_RXP_RXPQ 0x000c53c0
  5252. #define BNX2_RXP_FTQ_CMD 0x000c53f8
  5253. #define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
  5254. #define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10)
  5255. #define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
  5256. #define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
  5257. #define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25)
  5258. #define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26)
  5259. #define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
  5260. #define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28)
  5261. #define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
  5262. #define BNX2_RXP_FTQ_CMD_POP (1L<<30)
  5263. #define BNX2_RXP_FTQ_CMD_BUSY (1L<<31)
  5264. #define BNX2_RXP_FTQ_CTL 0x000c53fc
  5265. #define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0)
  5266. #define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1)
  5267. #define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  5268. #define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  5269. #define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  5270. #define BNX2_RXP_SCRATCH 0x000e0000
  5271. /*
  5272. * com_reg definition
  5273. * offset: 0x100000
  5274. */
  5275. #define BNX2_COM_CKSUM_ERROR_STATUS 0x00100000
  5276. #define BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
  5277. #define BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
  5278. #define BNX2_COM_CPU_MODE 0x00105000
  5279. #define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
  5280. #define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1)
  5281. #define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  5282. #define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  5283. #define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6)
  5284. #define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
  5285. #define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10)
  5286. #define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  5287. #define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  5288. #define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  5289. #define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  5290. #define BNX2_COM_CPU_STATE 0x00105004
  5291. #define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0)
  5292. #define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
  5293. #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  5294. #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  5295. #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  5296. #define BNX2_COM_CPU_STATE_BAD_PC_HALTED (1L<<6)
  5297. #define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
  5298. #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  5299. #define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10)
  5300. #define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  5301. #define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12)
  5302. #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  5303. #define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
  5304. #define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31)
  5305. #define BNX2_COM_CPU_EVENT_MASK 0x00105008
  5306. #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  5307. #define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  5308. #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  5309. #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  5310. #define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  5311. #define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  5312. #define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  5313. #define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  5314. #define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  5315. #define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  5316. #define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  5317. #define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c
  5318. #define BNX2_COM_CPU_INSTRUCTION 0x00105020
  5319. #define BNX2_COM_CPU_DATA_ACCESS 0x00105024
  5320. #define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028
  5321. #define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c
  5322. #define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
  5323. #define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034
  5324. #define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  5325. #define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  5326. #define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038
  5327. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  5328. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  5329. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  5330. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  5331. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  5332. #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  5333. #define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048
  5334. #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  5335. #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  5336. #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  5337. #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  5338. #define BNX2_COM_CPU_REG_FILE 0x00105200
  5339. #define BNX2_COM_COMTQ_PFE_PFE_CTL 0x001052bc
  5340. #define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
  5341. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
  5342. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
  5343. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
  5344. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
  5345. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
  5346. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
  5347. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
  5348. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
  5349. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
  5350. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
  5351. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
  5352. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
  5353. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
  5354. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
  5355. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
  5356. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
  5357. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
  5358. #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
  5359. #define BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
  5360. #define BNX2_COM_COMXQ 0x00105340
  5361. #define BNX2_COM_COMXQ_FTQ_CMD 0x00105378
  5362. #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
  5363. #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
  5364. #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
  5365. #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
  5366. #define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
  5367. #define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
  5368. #define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
  5369. #define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
  5370. #define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
  5371. #define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30)
  5372. #define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
  5373. #define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c
  5374. #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
  5375. #define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
  5376. #define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  5377. #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  5378. #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  5379. #define BNX2_COM_COMTQ 0x00105380
  5380. #define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8
  5381. #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
  5382. #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
  5383. #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
  5384. #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
  5385. #define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
  5386. #define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
  5387. #define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
  5388. #define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
  5389. #define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
  5390. #define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30)
  5391. #define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
  5392. #define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc
  5393. #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
  5394. #define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
  5395. #define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  5396. #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  5397. #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  5398. #define BNX2_COM_COMQ 0x001053c0
  5399. #define BNX2_COM_COMQ_FTQ_CMD 0x001053f8
  5400. #define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
  5401. #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
  5402. #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
  5403. #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
  5404. #define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
  5405. #define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
  5406. #define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
  5407. #define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
  5408. #define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
  5409. #define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30)
  5410. #define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
  5411. #define BNX2_COM_COMQ_FTQ_CTL 0x001053fc
  5412. #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
  5413. #define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
  5414. #define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  5415. #define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  5416. #define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  5417. #define BNX2_COM_SCRATCH 0x00120000
  5418. #define BNX2_FW_RX_DROP_COUNT 0x00120084
  5419. /*
  5420. * cp_reg definition
  5421. * offset: 0x180000
  5422. */
  5423. #define BNX2_CP_CKSUM_ERROR_STATUS 0x00180000
  5424. #define BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
  5425. #define BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
  5426. #define BNX2_CP_CPU_MODE 0x00185000
  5427. #define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
  5428. #define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1)
  5429. #define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  5430. #define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  5431. #define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6)
  5432. #define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
  5433. #define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10)
  5434. #define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  5435. #define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  5436. #define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  5437. #define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  5438. #define BNX2_CP_CPU_STATE 0x00185004
  5439. #define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0)
  5440. #define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
  5441. #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  5442. #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  5443. #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  5444. #define BNX2_CP_CPU_STATE_BAD_PC_HALTED (1L<<6)
  5445. #define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
  5446. #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  5447. #define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10)
  5448. #define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  5449. #define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12)
  5450. #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  5451. #define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
  5452. #define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31)
  5453. #define BNX2_CP_CPU_EVENT_MASK 0x00185008
  5454. #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  5455. #define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  5456. #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  5457. #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  5458. #define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  5459. #define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  5460. #define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  5461. #define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  5462. #define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  5463. #define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  5464. #define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  5465. #define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c
  5466. #define BNX2_CP_CPU_INSTRUCTION 0x00185020
  5467. #define BNX2_CP_CPU_DATA_ACCESS 0x00185024
  5468. #define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028
  5469. #define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c
  5470. #define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
  5471. #define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034
  5472. #define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  5473. #define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  5474. #define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038
  5475. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  5476. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  5477. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  5478. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  5479. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  5480. #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  5481. #define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048
  5482. #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  5483. #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  5484. #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  5485. #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  5486. #define BNX2_CP_CPU_REG_FILE 0x00185200
  5487. #define BNX2_CP_CPQ_PFE_PFE_CTL 0x001853bc
  5488. #define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
  5489. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
  5490. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
  5491. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
  5492. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
  5493. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
  5494. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
  5495. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
  5496. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
  5497. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
  5498. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
  5499. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
  5500. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
  5501. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
  5502. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
  5503. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
  5504. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
  5505. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
  5506. #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
  5507. #define BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
  5508. #define BNX2_CP_CPQ 0x001853c0
  5509. #define BNX2_CP_CPQ_FTQ_CMD 0x001853f8
  5510. #define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
  5511. #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
  5512. #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
  5513. #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
  5514. #define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
  5515. #define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
  5516. #define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
  5517. #define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
  5518. #define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
  5519. #define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30)
  5520. #define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
  5521. #define BNX2_CP_CPQ_FTQ_CTL 0x001853fc
  5522. #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
  5523. #define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
  5524. #define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  5525. #define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  5526. #define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  5527. #define BNX2_CP_SCRATCH 0x001a0000
  5528. /*
  5529. * mcp_reg definition
  5530. * offset: 0x140000
  5531. */
  5532. #define BNX2_MCP_MCP_CONTROL 0x00140080
  5533. #define BNX2_MCP_MCP_CONTROL_SMBUS_SEL (1L<<30)
  5534. #define BNX2_MCP_MCP_CONTROL_MCP_ISOLATE (1L<<31)
  5535. #define BNX2_MCP_MCP_ATTENTION_STATUS 0x00140084
  5536. #define BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL (1L<<29)
  5537. #define BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT (1L<<30)
  5538. #define BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT (1L<<31)
  5539. #define BNX2_MCP_MCP_HEARTBEAT_CONTROL 0x00140088
  5540. #define BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE (1L<<31)
  5541. #define BNX2_MCP_MCP_HEARTBEAT_STATUS 0x0014008c
  5542. #define BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD (0x7ffL<<0)
  5543. #define BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID (1L<<31)
  5544. #define BNX2_MCP_MCP_HEARTBEAT 0x00140090
  5545. #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT (0x3fffffffL<<0)
  5546. #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC (1L<<30)
  5547. #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET (1L<<31)
  5548. #define BNX2_MCP_WATCHDOG_RESET 0x00140094
  5549. #define BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET (1L<<31)
  5550. #define BNX2_MCP_WATCHDOG_CONTROL 0x00140098
  5551. #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT (0xfffffffL<<0)
  5552. #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN (1L<<29)
  5553. #define BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE (1L<<30)
  5554. #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE (1L<<31)
  5555. #define BNX2_MCP_ACCESS_LOCK 0x0014009c
  5556. #define BNX2_MCP_ACCESS_LOCK_LOCK (1L<<31)
  5557. #define BNX2_MCP_TOE_ID 0x001400a0
  5558. #define BNX2_MCP_TOE_ID_FUNCTION_ID (1L<<31)
  5559. #define BNX2_MCP_MAILBOX_CFG 0x001400a4
  5560. #define BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET (0x3fffL<<0)
  5561. #define BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE (0xfffL<<20)
  5562. #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC 0x001400a8
  5563. #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET (0x3fffL<<0)
  5564. #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE (0xfffL<<20)
  5565. #define BNX2_MCP_MCP_DOORBELL 0x001400ac
  5566. #define BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL (1L<<31)
  5567. #define BNX2_MCP_DRIVER_DOORBELL 0x001400b0
  5568. #define BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL (1L<<31)
  5569. #define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC 0x001400b4
  5570. #define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL (1L<<31)
  5571. #define BNX2_MCP_CPU_MODE 0x00145000
  5572. #define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
  5573. #define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1)
  5574. #define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
  5575. #define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
  5576. #define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
  5577. #define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
  5578. #define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10)
  5579. #define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
  5580. #define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
  5581. #define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
  5582. #define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
  5583. #define BNX2_MCP_CPU_STATE 0x00145004
  5584. #define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0)
  5585. #define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
  5586. #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
  5587. #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
  5588. #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
  5589. #define BNX2_MCP_CPU_STATE_BAD_PC_HALTED (1L<<6)
  5590. #define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
  5591. #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
  5592. #define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
  5593. #define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
  5594. #define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12)
  5595. #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
  5596. #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
  5597. #define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
  5598. #define BNX2_MCP_CPU_EVENT_MASK 0x00145008
  5599. #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
  5600. #define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
  5601. #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
  5602. #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
  5603. #define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
  5604. #define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
  5605. #define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
  5606. #define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
  5607. #define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
  5608. #define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
  5609. #define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
  5610. #define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c
  5611. #define BNX2_MCP_CPU_INSTRUCTION 0x00145020
  5612. #define BNX2_MCP_CPU_DATA_ACCESS 0x00145024
  5613. #define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028
  5614. #define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
  5615. #define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
  5616. #define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034
  5617. #define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
  5618. #define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
  5619. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
  5620. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
  5621. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
  5622. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
  5623. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
  5624. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
  5625. #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
  5626. #define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
  5627. #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
  5628. #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
  5629. #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
  5630. #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
  5631. #define BNX2_MCP_CPU_REG_FILE 0x00145200
  5632. #define BNX2_MCP_MCPQ 0x001453c0
  5633. #define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8
  5634. #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
  5635. #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
  5636. #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
  5637. #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
  5638. #define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
  5639. #define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
  5640. #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
  5641. #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
  5642. #define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
  5643. #define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
  5644. #define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
  5645. #define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc
  5646. #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
  5647. #define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
  5648. #define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
  5649. #define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
  5650. #define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
  5651. #define BNX2_MCP_ROM 0x00150000
  5652. #define BNX2_MCP_SCRATCH 0x00160000
  5653. #define BNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH
  5654. #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
  5655. #define BNX2_SHM_HDR_SIGNATURE_SIG 0x53530000
  5656. #define BNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
  5657. #define BNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
  5658. #define BNX2_SHM_HDR_ADDR_0 BNX2_MCP_SCRATCH + 4
  5659. #define BNX2_SHM_HDR_ADDR_1 BNX2_MCP_SCRATCH + 8
  5660. #define NUM_MC_HASH_REGISTERS 8
  5661. /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
  5662. #define PHY_BCM5706_PHY_ID 0x00206160
  5663. #define PHY_ID(id) ((id) & 0xfffffff0)
  5664. #define PHY_REV_ID(id) ((id) & 0xf)
  5665. /* 5708 Serdes PHY registers */
  5666. #define BCM5708S_BMCR_FORCE_2500 0x20
  5667. #define BCM5708S_UP1 0xb
  5668. #define BCM5708S_UP1_2G5 0x1
  5669. #define BCM5708S_BLK_ADDR 0x1f
  5670. #define BCM5708S_BLK_ADDR_DIG 0x0000
  5671. #define BCM5708S_BLK_ADDR_DIG3 0x0002
  5672. #define BCM5708S_BLK_ADDR_TX_MISC 0x0005
  5673. /* Digital Block */
  5674. #define BCM5708S_1000X_CTL1 0x10
  5675. #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
  5676. #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
  5677. #define BCM5708S_1000X_CTL2 0x11
  5678. #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
  5679. #define BCM5708S_1000X_STAT1 0x14
  5680. #define BCM5708S_1000X_STAT1_SGMII 0x0001
  5681. #define BCM5708S_1000X_STAT1_LINK 0x0002
  5682. #define BCM5708S_1000X_STAT1_FD 0x0004
  5683. #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
  5684. #define BCM5708S_1000X_STAT1_SPEED_10 0x0000
  5685. #define BCM5708S_1000X_STAT1_SPEED_100 0x0008
  5686. #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
  5687. #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
  5688. #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
  5689. #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
  5690. /* Digital3 Block */
  5691. #define BCM5708S_DIG_3_0 0x10
  5692. #define BCM5708S_DIG_3_0_USE_IEEE 0x0001
  5693. /* Tx/Misc Block */
  5694. #define BCM5708S_TX_ACTL1 0x15
  5695. #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
  5696. #define BCM5708S_TX_ACTL3 0x17
  5697. #define MII_BNX2_DSP_RW_PORT 0x15
  5698. #define MII_BNX2_DSP_ADDRESS 0x17
  5699. #define MII_BNX2_DSP_EXPAND_REG 0x0f00
  5700. #define MIN_ETHERNET_PACKET_SIZE 60
  5701. #define MAX_ETHERNET_PACKET_SIZE 1514
  5702. #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
  5703. #define RX_COPY_THRESH 92
  5704. #define DMA_READ_CHANS 5
  5705. #define DMA_WRITE_CHANS 3
  5706. /* Use CPU native page size up to 16K for the ring sizes. */
  5707. #if (PAGE_SHIFT > 14)
  5708. #define BCM_PAGE_BITS 14
  5709. #else
  5710. #define BCM_PAGE_BITS PAGE_SHIFT
  5711. #endif
  5712. #define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
  5713. #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
  5714. #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
  5715. #define MAX_RX_RINGS 4
  5716. #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
  5717. #define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
  5718. #define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
  5719. #define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
  5720. (MAX_TX_DESC_CNT - 1)) ? \
  5721. (x) + 2 : (x) + 1
  5722. #define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT)
  5723. #define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) == \
  5724. (MAX_RX_DESC_CNT - 1)) ? \
  5725. (x) + 2 : (x) + 1
  5726. #define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
  5727. #define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> (BCM_PAGE_BITS - 4))
  5728. #define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
  5729. /* Context size. */
  5730. #define CTX_SHIFT 7
  5731. #define CTX_SIZE (1 << CTX_SHIFT)
  5732. #define CTX_MASK (CTX_SIZE - 1)
  5733. #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
  5734. #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
  5735. #define PHY_CTX_SHIFT 6
  5736. #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT)
  5737. #define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
  5738. #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT)
  5739. #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT)
  5740. #define MB_KERNEL_CTX_SHIFT 8
  5741. #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT)
  5742. #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
  5743. #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
  5744. #define MAX_CID_CNT 0x4000
  5745. #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
  5746. #define INVALID_CID_ADDR 0xffffffff
  5747. #define TX_CID 16
  5748. #define TX_TSS_CID 32
  5749. #define RX_CID 0
  5750. #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
  5751. #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
  5752. struct sw_bd {
  5753. struct sk_buff *skb;
  5754. DECLARE_PCI_UNMAP_ADDR(mapping)
  5755. };
  5756. /* Buffered flash (Atmel: AT45DB011B) specific information */
  5757. #define SEEPROM_PAGE_BITS 2
  5758. #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
  5759. #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
  5760. #define SEEPROM_PAGE_SIZE 4
  5761. #define SEEPROM_TOTAL_SIZE 65536
  5762. #define BUFFERED_FLASH_PAGE_BITS 9
  5763. #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
  5764. #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
  5765. #define BUFFERED_FLASH_PAGE_SIZE 264
  5766. #define BUFFERED_FLASH_TOTAL_SIZE 0x21000
  5767. #define SAIFUN_FLASH_PAGE_BITS 8
  5768. #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
  5769. #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
  5770. #define SAIFUN_FLASH_PAGE_SIZE 256
  5771. #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
  5772. #define ST_MICRO_FLASH_PAGE_BITS 8
  5773. #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
  5774. #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
  5775. #define ST_MICRO_FLASH_PAGE_SIZE 256
  5776. #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
  5777. #define NVRAM_TIMEOUT_COUNT 30000
  5778. #define FLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \
  5779. BNX2_NVM_CFG1_BUFFER_MODE | \
  5780. BNX2_NVM_CFG1_PROTECT_MODE | \
  5781. BNX2_NVM_CFG1_FLASH_SIZE)
  5782. #define FLASH_BACKUP_STRAP_MASK (0xf << 26)
  5783. struct flash_spec {
  5784. u32 strapping;
  5785. u32 config1;
  5786. u32 config2;
  5787. u32 config3;
  5788. u32 write1;
  5789. u32 buffered;
  5790. u32 page_bits;
  5791. u32 page_size;
  5792. u32 addr_mask;
  5793. u32 total_size;
  5794. u8 *name;
  5795. };
  5796. struct bnx2 {
  5797. /* Fields used in the tx and intr/napi performance paths are grouped */
  5798. /* together in the beginning of the structure. */
  5799. void __iomem *regview;
  5800. struct net_device *dev;
  5801. struct pci_dev *pdev;
  5802. atomic_t intr_sem;
  5803. struct status_block *status_blk;
  5804. u32 last_status_idx;
  5805. u32 flags;
  5806. #define PCIX_FLAG 1
  5807. #define PCI_32BIT_FLAG 2
  5808. #define ONE_TDMA_FLAG 4 /* no longer used */
  5809. #define NO_WOL_FLAG 8
  5810. #define USING_DAC_FLAG 0x10
  5811. #define USING_MSI_FLAG 0x20
  5812. #define ASF_ENABLE_FLAG 0x40
  5813. /* Put tx producer and consumer fields in separate cache lines. */
  5814. u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
  5815. u16 tx_prod;
  5816. u32 tx_bidx_addr;
  5817. u32 tx_bseq_addr;
  5818. u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
  5819. u16 hw_tx_cons;
  5820. #ifdef BCM_VLAN
  5821. struct vlan_group *vlgrp;
  5822. #endif
  5823. u32 rx_offset;
  5824. u32 rx_buf_use_size; /* useable size */
  5825. u32 rx_buf_size; /* with alignment */
  5826. u32 rx_max_ring_idx;
  5827. u32 rx_prod_bseq;
  5828. u16 rx_prod;
  5829. u16 rx_cons;
  5830. u16 hw_rx_cons;
  5831. u32 rx_csum;
  5832. struct sw_bd *rx_buf_ring;
  5833. struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
  5834. /* TX constants */
  5835. struct tx_bd *tx_desc_ring;
  5836. struct sw_bd *tx_buf_ring;
  5837. int tx_ring_size;
  5838. u32 tx_wake_thresh;
  5839. /* End of fields used in the performance code paths. */
  5840. char *name;
  5841. int timer_interval;
  5842. int current_interval;
  5843. struct timer_list timer;
  5844. struct work_struct reset_task;
  5845. int in_reset_task;
  5846. /* Used to synchronize phy accesses. */
  5847. spinlock_t phy_lock;
  5848. u32 phy_flags;
  5849. #define PHY_SERDES_FLAG 1
  5850. #define PHY_CRC_FIX_FLAG 2
  5851. #define PHY_PARALLEL_DETECT_FLAG 4
  5852. #define PHY_2_5G_CAPABLE_FLAG 8
  5853. #define PHY_INT_MODE_MASK_FLAG 0x300
  5854. #define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
  5855. #define PHY_INT_MODE_LINK_READY_FLAG 0x200
  5856. #define PHY_DIS_EARLY_DAC_FLAG 0x400
  5857. u32 chip_id;
  5858. /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
  5859. #define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
  5860. #define CHIP_NUM_5706 0x57060000
  5861. #define CHIP_NUM_5708 0x57080000
  5862. #define CHIP_NUM_5709 0x57090000
  5863. #define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
  5864. #define CHIP_REV_Ax 0x00000000
  5865. #define CHIP_REV_Bx 0x00001000
  5866. #define CHIP_REV_Cx 0x00002000
  5867. #define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
  5868. #define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f)
  5869. #define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
  5870. #define CHIP_ID_5706_A0 0x57060000
  5871. #define CHIP_ID_5706_A1 0x57060010
  5872. #define CHIP_ID_5706_A2 0x57060020
  5873. #define CHIP_ID_5708_A0 0x57080000
  5874. #define CHIP_ID_5708_B0 0x57081000
  5875. #define CHIP_ID_5708_B1 0x57081010
  5876. #define CHIP_ID_5709_A0 0x57090000
  5877. #define CHIP_ID_5709_A1 0x57090010
  5878. #define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf)
  5879. /* A serdes chip will have the first bit of the bond id set. */
  5880. #define CHIP_BOND_ID_SERDES_BIT 0x01
  5881. u32 phy_addr;
  5882. u32 phy_id;
  5883. u16 bus_speed_mhz;
  5884. u8 wol;
  5885. u8 pad;
  5886. u16 fw_wr_seq;
  5887. u16 fw_drv_pulse_wr_seq;
  5888. dma_addr_t tx_desc_mapping;
  5889. int rx_max_ring;
  5890. int rx_ring_size;
  5891. dma_addr_t rx_desc_mapping[MAX_RX_RINGS];
  5892. u16 tx_quick_cons_trip;
  5893. u16 tx_quick_cons_trip_int;
  5894. u16 rx_quick_cons_trip;
  5895. u16 rx_quick_cons_trip_int;
  5896. u16 comp_prod_trip;
  5897. u16 comp_prod_trip_int;
  5898. u16 tx_ticks;
  5899. u16 tx_ticks_int;
  5900. u16 com_ticks;
  5901. u16 com_ticks_int;
  5902. u16 cmd_ticks;
  5903. u16 cmd_ticks_int;
  5904. u16 rx_ticks;
  5905. u16 rx_ticks_int;
  5906. u32 stats_ticks;
  5907. dma_addr_t status_blk_mapping;
  5908. struct statistics_block *stats_blk;
  5909. dma_addr_t stats_blk_mapping;
  5910. int ctx_pages;
  5911. void *ctx_blk[4];
  5912. dma_addr_t ctx_blk_mapping[4];
  5913. u32 hc_cmd;
  5914. u32 rx_mode;
  5915. u16 req_line_speed;
  5916. u8 req_duplex;
  5917. u8 link_up;
  5918. u16 line_speed;
  5919. u8 duplex;
  5920. u8 flow_ctrl; /* actual flow ctrl settings */
  5921. /* may be different from */
  5922. /* req_flow_ctrl if autoneg */
  5923. #define FLOW_CTRL_TX 1
  5924. #define FLOW_CTRL_RX 2
  5925. u32 advertising;
  5926. u8 req_flow_ctrl; /* flow ctrl advertisement */
  5927. /* settings or forced */
  5928. /* settings */
  5929. u8 autoneg;
  5930. #define AUTONEG_SPEED 1
  5931. #define AUTONEG_FLOW_CTRL 2
  5932. u8 loopback;
  5933. #define MAC_LOOPBACK 1
  5934. #define PHY_LOOPBACK 2
  5935. u8 serdes_an_pending;
  5936. #define SERDES_AN_TIMEOUT (HZ / 3)
  5937. #define SERDES_FORCED_TIMEOUT (HZ / 10)
  5938. u8 mac_addr[8];
  5939. u32 shmem_base;
  5940. u32 fw_ver;
  5941. int pm_cap;
  5942. int pcix_cap;
  5943. struct net_device_stats net_stats;
  5944. struct flash_spec *flash_info;
  5945. u32 flash_size;
  5946. int status_stats_size;
  5947. struct z_stream_s *strm;
  5948. void *gunzip_buf;
  5949. };
  5950. static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
  5951. static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
  5952. #define REG_RD(bp, offset) \
  5953. readl(bp->regview + offset)
  5954. #define REG_WR(bp, offset, val) \
  5955. writel(val, bp->regview + offset)
  5956. #define REG_WR16(bp, offset, val) \
  5957. writew(val, bp->regview + offset)
  5958. #define REG_RD_IND(bp, offset) \
  5959. bnx2_reg_rd_ind(bp, offset)
  5960. #define REG_WR_IND(bp, offset, val) \
  5961. bnx2_reg_wr_ind(bp, offset, val)
  5962. /* Indirect context access. Unlike the MBQ_WR, these macros will not
  5963. * trigger a chip event. */
  5964. static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
  5965. #define CTX_WR(bp, cid_addr, offset, val) \
  5966. bnx2_ctx_wr(bp, cid_addr, offset, val)
  5967. struct cpu_reg {
  5968. u32 mode;
  5969. u32 mode_value_halt;
  5970. u32 mode_value_sstep;
  5971. u32 state;
  5972. u32 state_value_clear;
  5973. u32 gpr0;
  5974. u32 evmask;
  5975. u32 pc;
  5976. u32 inst;
  5977. u32 bp;
  5978. u32 spad_base;
  5979. u32 mips_view_base;
  5980. };
  5981. struct fw_info {
  5982. const u32 ver_major;
  5983. const u32 ver_minor;
  5984. const u32 ver_fix;
  5985. const u32 start_addr;
  5986. /* Text section. */
  5987. const u32 text_addr;
  5988. const u32 text_len;
  5989. const u32 text_index;
  5990. u32 *text;
  5991. u8 *gz_text;
  5992. const u32 gz_text_len;
  5993. /* Data section. */
  5994. const u32 data_addr;
  5995. const u32 data_len;
  5996. const u32 data_index;
  5997. const u32 *data;
  5998. /* SBSS section. */
  5999. const u32 sbss_addr;
  6000. const u32 sbss_len;
  6001. const u32 sbss_index;
  6002. const u32 *sbss;
  6003. /* BSS section. */
  6004. const u32 bss_addr;
  6005. const u32 bss_len;
  6006. const u32 bss_index;
  6007. const u32 *bss;
  6008. /* Read-only section. */
  6009. const u32 rodata_addr;
  6010. const u32 rodata_len;
  6011. const u32 rodata_index;
  6012. const u32 *rodata;
  6013. };
  6014. #define RV2P_PROC1 0
  6015. #define RV2P_PROC2 1
  6016. /* This value (in milliseconds) determines the frequency of the driver
  6017. * issuing the PULSE message code. The firmware monitors this periodic
  6018. * pulse to determine when to switch to an OS-absent mode. */
  6019. #define DRV_PULSE_PERIOD_MS 250
  6020. /* This value (in milliseconds) determines how long the driver should
  6021. * wait for an acknowledgement from the firmware before timing out. Once
  6022. * the firmware has timed out, the driver will assume there is no firmware
  6023. * running and there won't be any firmware-driver synchronization during a
  6024. * driver reset. */
  6025. #define FW_ACK_TIME_OUT_MS 100
  6026. #define BNX2_DRV_RESET_SIGNATURE 0x00000000
  6027. #define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
  6028. //#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */
  6029. #define BNX2_DRV_MB 0x00000004
  6030. #define BNX2_DRV_MSG_CODE 0xff000000
  6031. #define BNX2_DRV_MSG_CODE_RESET 0x01000000
  6032. #define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000
  6033. #define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000
  6034. #define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
  6035. #define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
  6036. #define BNX2_DRV_MSG_CODE_PULSE 0x06000000
  6037. #define BNX2_DRV_MSG_CODE_DIAG 0x07000000
  6038. #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
  6039. #define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000
  6040. #define BNX2_DRV_MSG_DATA 0x00ff0000
  6041. #define BNX2_DRV_MSG_DATA_WAIT0 0x00010000
  6042. #define BNX2_DRV_MSG_DATA_WAIT1 0x00020000
  6043. #define BNX2_DRV_MSG_DATA_WAIT2 0x00030000
  6044. #define BNX2_DRV_MSG_DATA_WAIT3 0x00040000
  6045. #define BNX2_DRV_MSG_SEQ 0x0000ffff
  6046. #define BNX2_FW_MB 0x00000008
  6047. #define BNX2_FW_MSG_ACK 0x0000ffff
  6048. #define BNX2_FW_MSG_STATUS_MASK 0x00ff0000
  6049. #define BNX2_FW_MSG_STATUS_OK 0x00000000
  6050. #define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
  6051. #define BNX2_LINK_STATUS 0x0000000c
  6052. #define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff
  6053. #define BNX2_LINK_STATUS_LINK_UP 0x1
  6054. #define BNX2_LINK_STATUS_LINK_DOWN 0x0
  6055. #define BNX2_LINK_STATUS_SPEED_MASK 0x1e
  6056. #define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1)
  6057. #define BNX2_LINK_STATUS_10HALF (1<<1)
  6058. #define BNX2_LINK_STATUS_10FULL (2<<1)
  6059. #define BNX2_LINK_STATUS_100HALF (3<<1)
  6060. #define BNX2_LINK_STATUS_100BASE_T4 (4<<1)
  6061. #define BNX2_LINK_STATUS_100FULL (5<<1)
  6062. #define BNX2_LINK_STATUS_1000HALF (6<<1)
  6063. #define BNX2_LINK_STATUS_1000FULL (7<<1)
  6064. #define BNX2_LINK_STATUS_2500HALF (8<<1)
  6065. #define BNX2_LINK_STATUS_2500FULL (9<<1)
  6066. #define BNX2_LINK_STATUS_AN_ENABLED (1<<5)
  6067. #define BNX2_LINK_STATUS_AN_COMPLETE (1<<6)
  6068. #define BNX2_LINK_STATUS_PARALLEL_DET (1<<7)
  6069. #define BNX2_LINK_STATUS_RESERVED (1<<8)
  6070. #define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
  6071. #define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
  6072. #define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
  6073. #define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
  6074. #define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
  6075. #define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
  6076. #define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
  6077. #define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16)
  6078. #define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17)
  6079. #define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
  6080. #define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
  6081. #define BNX2_LINK_STATUS_SERDES_LINK (1<<20)
  6082. #define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
  6083. #define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
  6084. #define BNX2_DRV_PULSE_MB 0x00000010
  6085. #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
  6086. /* Indicate to the firmware not to go into the
  6087. * OS absent when it is not getting driver pulse.
  6088. * This is used for debugging. */
  6089. #define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
  6090. #define BNX2_DEV_INFO_SIGNATURE 0x00000020
  6091. #define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900
  6092. #define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
  6093. #define BNX2_DEV_INFO_FEATURE_CFG_VALID 0x01
  6094. #define BNX2_DEV_INFO_SECONDARY_PORT 0x80
  6095. #define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
  6096. #define BNX2_SHARED_HW_CFG_PART_NUM 0x00000024
  6097. #define BNX2_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
  6098. #define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
  6099. #define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
  6100. #define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
  6101. #define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
  6102. #define BNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038
  6103. #define BNX2_SHARED_HW_CFG_CONFIG 0x0000003c
  6104. #define BNX2_SHARED_HW_CFG_DESIGN_NIC 0
  6105. #define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1
  6106. #define BNX2_SHARED_HW_CFG_PHY_COPPER 0
  6107. #define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2
  6108. #define BNX2_SHARED_HW_CFG_PHY_2_5G 0x20
  6109. #define BNX2_SHARED_HW_CFG_PHY_BACKPLANE 0x40
  6110. #define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
  6111. #define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300
  6112. #define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
  6113. #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
  6114. #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
  6115. #define BNX2_SHARED_HW_CFG_CONFIG2 0x00000040
  6116. #define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000
  6117. #define BNX2_DEV_INFO_BC_REV 0x0000004c
  6118. #define BNX2_PORT_HW_CFG_MAC_UPPER 0x00000050
  6119. #define BNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff
  6120. #define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054
  6121. #define BNX2_PORT_HW_CFG_CONFIG 0x00000058
  6122. #define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
  6123. #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
  6124. #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
  6125. #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
  6126. #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
  6127. #define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
  6128. #define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
  6129. #define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
  6130. #define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
  6131. #define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
  6132. #define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
  6133. #define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
  6134. #define BNX2_DEV_INFO_FORMAT_REV 0x000000c4
  6135. #define BNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000
  6136. #define BNX2_DEV_INFO_FORMAT_REV_ID ('A' << 24)
  6137. #define BNX2_SHARED_FEATURE 0x000000c8
  6138. #define BNX2_SHARED_FEATURE_MASK 0xffffffff
  6139. #define BNX2_PORT_FEATURE 0x000000d8
  6140. #define BNX2_PORT2_FEATURE 0x00000014c
  6141. #define BNX2_PORT_FEATURE_WOL_ENABLED 0x01000000
  6142. #define BNX2_PORT_FEATURE_MBA_ENABLED 0x02000000
  6143. #define BNX2_PORT_FEATURE_ASF_ENABLED 0x04000000
  6144. #define BNX2_PORT_FEATURE_IMD_ENABLED 0x08000000
  6145. #define BNX2_PORT_FEATURE_BAR1_SIZE_MASK 0xf
  6146. #define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
  6147. #define BNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1
  6148. #define BNX2_PORT_FEATURE_BAR1_SIZE_128K 0x2
  6149. #define BNX2_PORT_FEATURE_BAR1_SIZE_256K 0x3
  6150. #define BNX2_PORT_FEATURE_BAR1_SIZE_512K 0x4
  6151. #define BNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5
  6152. #define BNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6
  6153. #define BNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7
  6154. #define BNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8
  6155. #define BNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9
  6156. #define BNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa
  6157. #define BNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb
  6158. #define BNX2_PORT_FEATURE_BAR1_SIZE_128M 0xc
  6159. #define BNX2_PORT_FEATURE_BAR1_SIZE_256M 0xd
  6160. #define BNX2_PORT_FEATURE_BAR1_SIZE_512M 0xe
  6161. #define BNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf
  6162. #define BNX2_PORT_FEATURE_WOL 0xdc
  6163. #define BNX2_PORT2_FEATURE_WOL 0x150
  6164. #define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
  6165. #define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
  6166. #define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
  6167. #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
  6168. #define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
  6169. #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
  6170. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
  6171. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
  6172. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
  6173. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
  6174. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
  6175. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
  6176. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
  6177. #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
  6178. #define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
  6179. #define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
  6180. #define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
  6181. #define BNX2_PORT_FEATURE_MBA 0xe0
  6182. #define BNX2_PORT2_FEATURE_MBA 0x154
  6183. #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
  6184. #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
  6185. #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
  6186. #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
  6187. #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
  6188. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
  6189. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
  6190. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
  6191. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
  6192. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
  6193. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
  6194. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
  6195. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
  6196. #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
  6197. #define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
  6198. #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
  6199. #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
  6200. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
  6201. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
  6202. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
  6203. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
  6204. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
  6205. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
  6206. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
  6207. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
  6208. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
  6209. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
  6210. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
  6211. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
  6212. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
  6213. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
  6214. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
  6215. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
  6216. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
  6217. #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
  6218. #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
  6219. #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
  6220. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
  6221. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
  6222. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
  6223. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
  6224. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
  6225. #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
  6226. #define BNX2_PORT_FEATURE_IMD 0xe4
  6227. #define BNX2_PORT2_FEATURE_IMD 0x158
  6228. #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
  6229. #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
  6230. #define BNX2_PORT_FEATURE_VLAN 0xe8
  6231. #define BNX2_PORT2_FEATURE_VLAN 0x15c
  6232. #define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
  6233. #define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
  6234. #define BNX2_BC_STATE_RESET_TYPE 0x000001c0
  6235. #define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254
  6236. #define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
  6237. #define BNX2_BC_STATE_RESET_TYPE_NONE (BNX2_BC_STATE_RESET_TYPE_SIG | \
  6238. 0x00010000)
  6239. #define BNX2_BC_STATE_RESET_TYPE_PCI (BNX2_BC_STATE_RESET_TYPE_SIG | \
  6240. 0x00020000)
  6241. #define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \
  6242. 0x00030000)
  6243. #define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
  6244. #define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
  6245. DRV_MSG_CODE_RESET)
  6246. #define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
  6247. DRV_MSG_CODE_UNLOAD)
  6248. #define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \
  6249. DRV_MSG_CODE_SHUTDOWN)
  6250. #define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \
  6251. DRV_MSG_CODE_WOL)
  6252. #define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \
  6253. DRV_MSG_CODE_DIAG)
  6254. #define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \
  6255. (msg))
  6256. #define BNX2_BC_STATE 0x000001c4
  6257. #define BNX2_BC_STATE_ERR_MASK 0x0000ff00
  6258. #define BNX2_BC_STATE_SIGN 0x42530000
  6259. #define BNX2_BC_STATE_SIGN_MASK 0xffff0000
  6260. #define BNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1)
  6261. #define BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2)
  6262. #define BNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3)
  6263. #define BNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4)
  6264. #define BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5)
  6265. #define BNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6)
  6266. #define BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7)
  6267. #define BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8)
  6268. #define BNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9)
  6269. #define BNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81)
  6270. #define BNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82)
  6271. #define BNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83)
  6272. #define BNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84)
  6273. #define BNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85)
  6274. #define BNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86)
  6275. #define BNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87)
  6276. #define BNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88)
  6277. #define BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89)
  6278. #define BNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100)
  6279. #define BNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200)
  6280. #define BNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300)
  6281. #define BNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400)
  6282. #define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500)
  6283. #define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600)
  6284. #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700)
  6285. #define BNX2_BC_STATE_DEBUG_CMD 0x1dc
  6286. #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
  6287. #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
  6288. #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
  6289. #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
  6290. #define HOST_VIEW_SHMEM_BASE 0x167c00
  6291. #endif