bnx2.c 146 KB

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  1. /* bnx2.c: Broadcom NX2 network driver.
  2. *
  3. * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Written by: Michael Chan (mchan@broadcom.com)
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/kernel.h>
  14. #include <linux/timer.h>
  15. #include <linux/errno.h>
  16. #include <linux/ioport.h>
  17. #include <linux/slab.h>
  18. #include <linux/vmalloc.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/pci.h>
  21. #include <linux/init.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/skbuff.h>
  25. #include <linux/dma-mapping.h>
  26. #include <asm/bitops.h>
  27. #include <asm/io.h>
  28. #include <asm/irq.h>
  29. #include <linux/delay.h>
  30. #include <asm/byteorder.h>
  31. #include <asm/page.h>
  32. #include <linux/time.h>
  33. #include <linux/ethtool.h>
  34. #include <linux/mii.h>
  35. #ifdef NETIF_F_HW_VLAN_TX
  36. #include <linux/if_vlan.h>
  37. #define BCM_VLAN 1
  38. #endif
  39. #include <net/ip.h>
  40. #include <net/tcp.h>
  41. #include <net/checksum.h>
  42. #include <linux/workqueue.h>
  43. #include <linux/crc32.h>
  44. #include <linux/prefetch.h>
  45. #include <linux/cache.h>
  46. #include <linux/zlib.h>
  47. #include "bnx2.h"
  48. #include "bnx2_fw.h"
  49. #include "bnx2_fw2.h"
  50. #define DRV_MODULE_NAME "bnx2"
  51. #define PFX DRV_MODULE_NAME ": "
  52. #define DRV_MODULE_VERSION "1.5.8.1"
  53. #define DRV_MODULE_RELDATE "May 7, 2007"
  54. #define RUN_AT(x) (jiffies + (x))
  55. /* Time in jiffies before concluding the transmitter is hung. */
  56. #define TX_TIMEOUT (5*HZ)
  57. static const char version[] __devinitdata =
  58. "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  59. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  60. MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
  61. MODULE_LICENSE("GPL");
  62. MODULE_VERSION(DRV_MODULE_VERSION);
  63. static int disable_msi = 0;
  64. module_param(disable_msi, int, 0);
  65. MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  66. typedef enum {
  67. BCM5706 = 0,
  68. NC370T,
  69. NC370I,
  70. BCM5706S,
  71. NC370F,
  72. BCM5708,
  73. BCM5708S,
  74. BCM5709,
  75. } board_t;
  76. /* indexed by board_t, above */
  77. static const struct {
  78. char *name;
  79. } board_info[] __devinitdata = {
  80. { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  81. { "HP NC370T Multifunction Gigabit Server Adapter" },
  82. { "HP NC370i Multifunction Gigabit Server Adapter" },
  83. { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
  84. { "HP NC370F Multifunction Gigabit Server Adapter" },
  85. { "Broadcom NetXtreme II BCM5708 1000Base-T" },
  86. { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
  87. { "Broadcom NetXtreme II BCM5709 1000Base-T" },
  88. };
  89. static struct pci_device_id bnx2_pci_tbl[] = {
  90. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  91. PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
  92. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  93. PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
  94. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
  95. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
  96. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
  97. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
  98. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  99. PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
  100. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
  101. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
  102. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
  103. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
  104. { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
  105. PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
  106. { 0, }
  107. };
  108. static struct flash_spec flash_table[] =
  109. {
  110. /* Slow EEPROM */
  111. {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
  112. 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  113. SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  114. "EEPROM - slow"},
  115. /* Expansion entry 0001 */
  116. {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
  117. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  118. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  119. "Entry 0001"},
  120. /* Saifun SA25F010 (non-buffered flash) */
  121. /* strap, cfg1, & write1 need updates */
  122. {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
  123. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  124. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
  125. "Non-buffered flash (128kB)"},
  126. /* Saifun SA25F020 (non-buffered flash) */
  127. /* strap, cfg1, & write1 need updates */
  128. {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
  129. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  130. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
  131. "Non-buffered flash (256kB)"},
  132. /* Expansion entry 0100 */
  133. {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
  134. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  135. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  136. "Entry 0100"},
  137. /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
  138. {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
  139. 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
  140. ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
  141. "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
  142. /* Entry 0110: ST M45PE20 (non-buffered flash)*/
  143. {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
  144. 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
  145. ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
  146. "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
  147. /* Saifun SA25F005 (non-buffered flash) */
  148. /* strap, cfg1, & write1 need updates */
  149. {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
  150. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  151. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
  152. "Non-buffered flash (64kB)"},
  153. /* Fast EEPROM */
  154. {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
  155. 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  156. SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  157. "EEPROM - fast"},
  158. /* Expansion entry 1001 */
  159. {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
  160. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  161. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  162. "Entry 1001"},
  163. /* Expansion entry 1010 */
  164. {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
  165. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  166. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  167. "Entry 1010"},
  168. /* ATMEL AT45DB011B (buffered flash) */
  169. {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
  170. 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  171. BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
  172. "Buffered flash (128kB)"},
  173. /* Expansion entry 1100 */
  174. {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
  175. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  176. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  177. "Entry 1100"},
  178. /* Expansion entry 1101 */
  179. {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
  180. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  181. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  182. "Entry 1101"},
  183. /* Ateml Expansion entry 1110 */
  184. {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
  185. 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  186. BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
  187. "Entry 1110 (Atmel)"},
  188. /* ATMEL AT45DB021B (buffered flash) */
  189. {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
  190. 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  191. BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
  192. "Buffered flash (256kB)"},
  193. };
  194. MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
  195. static inline u32 bnx2_tx_avail(struct bnx2 *bp)
  196. {
  197. u32 diff;
  198. smp_mb();
  199. /* The ring uses 256 indices for 255 entries, one of them
  200. * needs to be skipped.
  201. */
  202. diff = bp->tx_prod - bp->tx_cons;
  203. if (unlikely(diff >= TX_DESC_CNT)) {
  204. diff &= 0xffff;
  205. if (diff == TX_DESC_CNT)
  206. diff = MAX_TX_DESC_CNT;
  207. }
  208. return (bp->tx_ring_size - diff);
  209. }
  210. static u32
  211. bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
  212. {
  213. REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
  214. return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
  215. }
  216. static void
  217. bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
  218. {
  219. REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
  220. REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
  221. }
  222. static void
  223. bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
  224. {
  225. offset += cid_addr;
  226. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  227. int i;
  228. REG_WR(bp, BNX2_CTX_CTX_DATA, val);
  229. REG_WR(bp, BNX2_CTX_CTX_CTRL,
  230. offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
  231. for (i = 0; i < 5; i++) {
  232. u32 val;
  233. val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
  234. if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
  235. break;
  236. udelay(5);
  237. }
  238. } else {
  239. REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
  240. REG_WR(bp, BNX2_CTX_DATA, val);
  241. }
  242. }
  243. static int
  244. bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
  245. {
  246. u32 val1;
  247. int i, ret;
  248. if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
  249. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  250. val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  251. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  252. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  253. udelay(40);
  254. }
  255. val1 = (bp->phy_addr << 21) | (reg << 16) |
  256. BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
  257. BNX2_EMAC_MDIO_COMM_START_BUSY;
  258. REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
  259. for (i = 0; i < 50; i++) {
  260. udelay(10);
  261. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  262. if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
  263. udelay(5);
  264. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  265. val1 &= BNX2_EMAC_MDIO_COMM_DATA;
  266. break;
  267. }
  268. }
  269. if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
  270. *val = 0x0;
  271. ret = -EBUSY;
  272. }
  273. else {
  274. *val = val1;
  275. ret = 0;
  276. }
  277. if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
  278. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  279. val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  280. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  281. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  282. udelay(40);
  283. }
  284. return ret;
  285. }
  286. static int
  287. bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
  288. {
  289. u32 val1;
  290. int i, ret;
  291. if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
  292. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  293. val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  294. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  295. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  296. udelay(40);
  297. }
  298. val1 = (bp->phy_addr << 21) | (reg << 16) | val |
  299. BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
  300. BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
  301. REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
  302. for (i = 0; i < 50; i++) {
  303. udelay(10);
  304. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  305. if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
  306. udelay(5);
  307. break;
  308. }
  309. }
  310. if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
  311. ret = -EBUSY;
  312. else
  313. ret = 0;
  314. if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
  315. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  316. val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  317. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  318. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  319. udelay(40);
  320. }
  321. return ret;
  322. }
  323. static void
  324. bnx2_disable_int(struct bnx2 *bp)
  325. {
  326. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  327. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  328. REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
  329. }
  330. static void
  331. bnx2_enable_int(struct bnx2 *bp)
  332. {
  333. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  334. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  335. BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
  336. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  337. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
  338. REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
  339. }
  340. static void
  341. bnx2_disable_int_sync(struct bnx2 *bp)
  342. {
  343. atomic_inc(&bp->intr_sem);
  344. bnx2_disable_int(bp);
  345. synchronize_irq(bp->pdev->irq);
  346. }
  347. static void
  348. bnx2_netif_stop(struct bnx2 *bp)
  349. {
  350. bnx2_disable_int_sync(bp);
  351. if (netif_running(bp->dev)) {
  352. netif_poll_disable(bp->dev);
  353. netif_tx_disable(bp->dev);
  354. bp->dev->trans_start = jiffies; /* prevent tx timeout */
  355. }
  356. }
  357. static void
  358. bnx2_netif_start(struct bnx2 *bp)
  359. {
  360. if (atomic_dec_and_test(&bp->intr_sem)) {
  361. if (netif_running(bp->dev)) {
  362. netif_wake_queue(bp->dev);
  363. netif_poll_enable(bp->dev);
  364. bnx2_enable_int(bp);
  365. }
  366. }
  367. }
  368. static void
  369. bnx2_free_mem(struct bnx2 *bp)
  370. {
  371. int i;
  372. for (i = 0; i < bp->ctx_pages; i++) {
  373. if (bp->ctx_blk[i]) {
  374. pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
  375. bp->ctx_blk[i],
  376. bp->ctx_blk_mapping[i]);
  377. bp->ctx_blk[i] = NULL;
  378. }
  379. }
  380. if (bp->status_blk) {
  381. pci_free_consistent(bp->pdev, bp->status_stats_size,
  382. bp->status_blk, bp->status_blk_mapping);
  383. bp->status_blk = NULL;
  384. bp->stats_blk = NULL;
  385. }
  386. if (bp->tx_desc_ring) {
  387. pci_free_consistent(bp->pdev,
  388. sizeof(struct tx_bd) * TX_DESC_CNT,
  389. bp->tx_desc_ring, bp->tx_desc_mapping);
  390. bp->tx_desc_ring = NULL;
  391. }
  392. kfree(bp->tx_buf_ring);
  393. bp->tx_buf_ring = NULL;
  394. for (i = 0; i < bp->rx_max_ring; i++) {
  395. if (bp->rx_desc_ring[i])
  396. pci_free_consistent(bp->pdev,
  397. sizeof(struct rx_bd) * RX_DESC_CNT,
  398. bp->rx_desc_ring[i],
  399. bp->rx_desc_mapping[i]);
  400. bp->rx_desc_ring[i] = NULL;
  401. }
  402. vfree(bp->rx_buf_ring);
  403. bp->rx_buf_ring = NULL;
  404. }
  405. static int
  406. bnx2_alloc_mem(struct bnx2 *bp)
  407. {
  408. int i, status_blk_size;
  409. bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
  410. GFP_KERNEL);
  411. if (bp->tx_buf_ring == NULL)
  412. return -ENOMEM;
  413. bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
  414. sizeof(struct tx_bd) *
  415. TX_DESC_CNT,
  416. &bp->tx_desc_mapping);
  417. if (bp->tx_desc_ring == NULL)
  418. goto alloc_mem_err;
  419. bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
  420. bp->rx_max_ring);
  421. if (bp->rx_buf_ring == NULL)
  422. goto alloc_mem_err;
  423. memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
  424. bp->rx_max_ring);
  425. for (i = 0; i < bp->rx_max_ring; i++) {
  426. bp->rx_desc_ring[i] =
  427. pci_alloc_consistent(bp->pdev,
  428. sizeof(struct rx_bd) * RX_DESC_CNT,
  429. &bp->rx_desc_mapping[i]);
  430. if (bp->rx_desc_ring[i] == NULL)
  431. goto alloc_mem_err;
  432. }
  433. /* Combine status and statistics blocks into one allocation. */
  434. status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
  435. bp->status_stats_size = status_blk_size +
  436. sizeof(struct statistics_block);
  437. bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
  438. &bp->status_blk_mapping);
  439. if (bp->status_blk == NULL)
  440. goto alloc_mem_err;
  441. memset(bp->status_blk, 0, bp->status_stats_size);
  442. bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
  443. status_blk_size);
  444. bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
  445. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  446. bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
  447. if (bp->ctx_pages == 0)
  448. bp->ctx_pages = 1;
  449. for (i = 0; i < bp->ctx_pages; i++) {
  450. bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
  451. BCM_PAGE_SIZE,
  452. &bp->ctx_blk_mapping[i]);
  453. if (bp->ctx_blk[i] == NULL)
  454. goto alloc_mem_err;
  455. }
  456. }
  457. return 0;
  458. alloc_mem_err:
  459. bnx2_free_mem(bp);
  460. return -ENOMEM;
  461. }
  462. static void
  463. bnx2_report_fw_link(struct bnx2 *bp)
  464. {
  465. u32 fw_link_status = 0;
  466. if (bp->link_up) {
  467. u32 bmsr;
  468. switch (bp->line_speed) {
  469. case SPEED_10:
  470. if (bp->duplex == DUPLEX_HALF)
  471. fw_link_status = BNX2_LINK_STATUS_10HALF;
  472. else
  473. fw_link_status = BNX2_LINK_STATUS_10FULL;
  474. break;
  475. case SPEED_100:
  476. if (bp->duplex == DUPLEX_HALF)
  477. fw_link_status = BNX2_LINK_STATUS_100HALF;
  478. else
  479. fw_link_status = BNX2_LINK_STATUS_100FULL;
  480. break;
  481. case SPEED_1000:
  482. if (bp->duplex == DUPLEX_HALF)
  483. fw_link_status = BNX2_LINK_STATUS_1000HALF;
  484. else
  485. fw_link_status = BNX2_LINK_STATUS_1000FULL;
  486. break;
  487. case SPEED_2500:
  488. if (bp->duplex == DUPLEX_HALF)
  489. fw_link_status = BNX2_LINK_STATUS_2500HALF;
  490. else
  491. fw_link_status = BNX2_LINK_STATUS_2500FULL;
  492. break;
  493. }
  494. fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
  495. if (bp->autoneg) {
  496. fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
  497. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  498. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  499. if (!(bmsr & BMSR_ANEGCOMPLETE) ||
  500. bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
  501. fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
  502. else
  503. fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
  504. }
  505. }
  506. else
  507. fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
  508. REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
  509. }
  510. static void
  511. bnx2_report_link(struct bnx2 *bp)
  512. {
  513. if (bp->link_up) {
  514. netif_carrier_on(bp->dev);
  515. printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
  516. printk("%d Mbps ", bp->line_speed);
  517. if (bp->duplex == DUPLEX_FULL)
  518. printk("full duplex");
  519. else
  520. printk("half duplex");
  521. if (bp->flow_ctrl) {
  522. if (bp->flow_ctrl & FLOW_CTRL_RX) {
  523. printk(", receive ");
  524. if (bp->flow_ctrl & FLOW_CTRL_TX)
  525. printk("& transmit ");
  526. }
  527. else {
  528. printk(", transmit ");
  529. }
  530. printk("flow control ON");
  531. }
  532. printk("\n");
  533. }
  534. else {
  535. netif_carrier_off(bp->dev);
  536. printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
  537. }
  538. bnx2_report_fw_link(bp);
  539. }
  540. static void
  541. bnx2_resolve_flow_ctrl(struct bnx2 *bp)
  542. {
  543. u32 local_adv, remote_adv;
  544. bp->flow_ctrl = 0;
  545. if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
  546. (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
  547. if (bp->duplex == DUPLEX_FULL) {
  548. bp->flow_ctrl = bp->req_flow_ctrl;
  549. }
  550. return;
  551. }
  552. if (bp->duplex != DUPLEX_FULL) {
  553. return;
  554. }
  555. if ((bp->phy_flags & PHY_SERDES_FLAG) &&
  556. (CHIP_NUM(bp) == CHIP_NUM_5708)) {
  557. u32 val;
  558. bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
  559. if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
  560. bp->flow_ctrl |= FLOW_CTRL_TX;
  561. if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
  562. bp->flow_ctrl |= FLOW_CTRL_RX;
  563. return;
  564. }
  565. bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
  566. bnx2_read_phy(bp, MII_LPA, &remote_adv);
  567. if (bp->phy_flags & PHY_SERDES_FLAG) {
  568. u32 new_local_adv = 0;
  569. u32 new_remote_adv = 0;
  570. if (local_adv & ADVERTISE_1000XPAUSE)
  571. new_local_adv |= ADVERTISE_PAUSE_CAP;
  572. if (local_adv & ADVERTISE_1000XPSE_ASYM)
  573. new_local_adv |= ADVERTISE_PAUSE_ASYM;
  574. if (remote_adv & ADVERTISE_1000XPAUSE)
  575. new_remote_adv |= ADVERTISE_PAUSE_CAP;
  576. if (remote_adv & ADVERTISE_1000XPSE_ASYM)
  577. new_remote_adv |= ADVERTISE_PAUSE_ASYM;
  578. local_adv = new_local_adv;
  579. remote_adv = new_remote_adv;
  580. }
  581. /* See Table 28B-3 of 802.3ab-1999 spec. */
  582. if (local_adv & ADVERTISE_PAUSE_CAP) {
  583. if(local_adv & ADVERTISE_PAUSE_ASYM) {
  584. if (remote_adv & ADVERTISE_PAUSE_CAP) {
  585. bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  586. }
  587. else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
  588. bp->flow_ctrl = FLOW_CTRL_RX;
  589. }
  590. }
  591. else {
  592. if (remote_adv & ADVERTISE_PAUSE_CAP) {
  593. bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  594. }
  595. }
  596. }
  597. else if (local_adv & ADVERTISE_PAUSE_ASYM) {
  598. if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
  599. (remote_adv & ADVERTISE_PAUSE_ASYM)) {
  600. bp->flow_ctrl = FLOW_CTRL_TX;
  601. }
  602. }
  603. }
  604. static int
  605. bnx2_5708s_linkup(struct bnx2 *bp)
  606. {
  607. u32 val;
  608. bp->link_up = 1;
  609. bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
  610. switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
  611. case BCM5708S_1000X_STAT1_SPEED_10:
  612. bp->line_speed = SPEED_10;
  613. break;
  614. case BCM5708S_1000X_STAT1_SPEED_100:
  615. bp->line_speed = SPEED_100;
  616. break;
  617. case BCM5708S_1000X_STAT1_SPEED_1G:
  618. bp->line_speed = SPEED_1000;
  619. break;
  620. case BCM5708S_1000X_STAT1_SPEED_2G5:
  621. bp->line_speed = SPEED_2500;
  622. break;
  623. }
  624. if (val & BCM5708S_1000X_STAT1_FD)
  625. bp->duplex = DUPLEX_FULL;
  626. else
  627. bp->duplex = DUPLEX_HALF;
  628. return 0;
  629. }
  630. static int
  631. bnx2_5706s_linkup(struct bnx2 *bp)
  632. {
  633. u32 bmcr, local_adv, remote_adv, common;
  634. bp->link_up = 1;
  635. bp->line_speed = SPEED_1000;
  636. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  637. if (bmcr & BMCR_FULLDPLX) {
  638. bp->duplex = DUPLEX_FULL;
  639. }
  640. else {
  641. bp->duplex = DUPLEX_HALF;
  642. }
  643. if (!(bmcr & BMCR_ANENABLE)) {
  644. return 0;
  645. }
  646. bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
  647. bnx2_read_phy(bp, MII_LPA, &remote_adv);
  648. common = local_adv & remote_adv;
  649. if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
  650. if (common & ADVERTISE_1000XFULL) {
  651. bp->duplex = DUPLEX_FULL;
  652. }
  653. else {
  654. bp->duplex = DUPLEX_HALF;
  655. }
  656. }
  657. return 0;
  658. }
  659. static int
  660. bnx2_copper_linkup(struct bnx2 *bp)
  661. {
  662. u32 bmcr;
  663. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  664. if (bmcr & BMCR_ANENABLE) {
  665. u32 local_adv, remote_adv, common;
  666. bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
  667. bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
  668. common = local_adv & (remote_adv >> 2);
  669. if (common & ADVERTISE_1000FULL) {
  670. bp->line_speed = SPEED_1000;
  671. bp->duplex = DUPLEX_FULL;
  672. }
  673. else if (common & ADVERTISE_1000HALF) {
  674. bp->line_speed = SPEED_1000;
  675. bp->duplex = DUPLEX_HALF;
  676. }
  677. else {
  678. bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
  679. bnx2_read_phy(bp, MII_LPA, &remote_adv);
  680. common = local_adv & remote_adv;
  681. if (common & ADVERTISE_100FULL) {
  682. bp->line_speed = SPEED_100;
  683. bp->duplex = DUPLEX_FULL;
  684. }
  685. else if (common & ADVERTISE_100HALF) {
  686. bp->line_speed = SPEED_100;
  687. bp->duplex = DUPLEX_HALF;
  688. }
  689. else if (common & ADVERTISE_10FULL) {
  690. bp->line_speed = SPEED_10;
  691. bp->duplex = DUPLEX_FULL;
  692. }
  693. else if (common & ADVERTISE_10HALF) {
  694. bp->line_speed = SPEED_10;
  695. bp->duplex = DUPLEX_HALF;
  696. }
  697. else {
  698. bp->line_speed = 0;
  699. bp->link_up = 0;
  700. }
  701. }
  702. }
  703. else {
  704. if (bmcr & BMCR_SPEED100) {
  705. bp->line_speed = SPEED_100;
  706. }
  707. else {
  708. bp->line_speed = SPEED_10;
  709. }
  710. if (bmcr & BMCR_FULLDPLX) {
  711. bp->duplex = DUPLEX_FULL;
  712. }
  713. else {
  714. bp->duplex = DUPLEX_HALF;
  715. }
  716. }
  717. return 0;
  718. }
  719. static int
  720. bnx2_set_mac_link(struct bnx2 *bp)
  721. {
  722. u32 val;
  723. REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
  724. if (bp->link_up && (bp->line_speed == SPEED_1000) &&
  725. (bp->duplex == DUPLEX_HALF)) {
  726. REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
  727. }
  728. /* Configure the EMAC mode register. */
  729. val = REG_RD(bp, BNX2_EMAC_MODE);
  730. val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
  731. BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
  732. BNX2_EMAC_MODE_25G_MODE);
  733. if (bp->link_up) {
  734. switch (bp->line_speed) {
  735. case SPEED_10:
  736. if (CHIP_NUM(bp) != CHIP_NUM_5706) {
  737. val |= BNX2_EMAC_MODE_PORT_MII_10M;
  738. break;
  739. }
  740. /* fall through */
  741. case SPEED_100:
  742. val |= BNX2_EMAC_MODE_PORT_MII;
  743. break;
  744. case SPEED_2500:
  745. val |= BNX2_EMAC_MODE_25G_MODE;
  746. /* fall through */
  747. case SPEED_1000:
  748. val |= BNX2_EMAC_MODE_PORT_GMII;
  749. break;
  750. }
  751. }
  752. else {
  753. val |= BNX2_EMAC_MODE_PORT_GMII;
  754. }
  755. /* Set the MAC to operate in the appropriate duplex mode. */
  756. if (bp->duplex == DUPLEX_HALF)
  757. val |= BNX2_EMAC_MODE_HALF_DUPLEX;
  758. REG_WR(bp, BNX2_EMAC_MODE, val);
  759. /* Enable/disable rx PAUSE. */
  760. bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
  761. if (bp->flow_ctrl & FLOW_CTRL_RX)
  762. bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
  763. REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
  764. /* Enable/disable tx PAUSE. */
  765. val = REG_RD(bp, BNX2_EMAC_TX_MODE);
  766. val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
  767. if (bp->flow_ctrl & FLOW_CTRL_TX)
  768. val |= BNX2_EMAC_TX_MODE_FLOW_EN;
  769. REG_WR(bp, BNX2_EMAC_TX_MODE, val);
  770. /* Acknowledge the interrupt. */
  771. REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
  772. return 0;
  773. }
  774. static int
  775. bnx2_set_link(struct bnx2 *bp)
  776. {
  777. u32 bmsr;
  778. u8 link_up;
  779. if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
  780. bp->link_up = 1;
  781. return 0;
  782. }
  783. link_up = bp->link_up;
  784. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  785. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  786. if ((bp->phy_flags & PHY_SERDES_FLAG) &&
  787. (CHIP_NUM(bp) == CHIP_NUM_5706)) {
  788. u32 val;
  789. val = REG_RD(bp, BNX2_EMAC_STATUS);
  790. if (val & BNX2_EMAC_STATUS_LINK)
  791. bmsr |= BMSR_LSTATUS;
  792. else
  793. bmsr &= ~BMSR_LSTATUS;
  794. }
  795. if (bmsr & BMSR_LSTATUS) {
  796. bp->link_up = 1;
  797. if (bp->phy_flags & PHY_SERDES_FLAG) {
  798. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  799. bnx2_5706s_linkup(bp);
  800. else if (CHIP_NUM(bp) == CHIP_NUM_5708)
  801. bnx2_5708s_linkup(bp);
  802. }
  803. else {
  804. bnx2_copper_linkup(bp);
  805. }
  806. bnx2_resolve_flow_ctrl(bp);
  807. }
  808. else {
  809. if ((bp->phy_flags & PHY_SERDES_FLAG) &&
  810. (bp->autoneg & AUTONEG_SPEED)) {
  811. u32 bmcr;
  812. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  813. bmcr &= ~BCM5708S_BMCR_FORCE_2500;
  814. if (!(bmcr & BMCR_ANENABLE)) {
  815. bnx2_write_phy(bp, MII_BMCR, bmcr |
  816. BMCR_ANENABLE);
  817. }
  818. }
  819. bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
  820. bp->link_up = 0;
  821. }
  822. if (bp->link_up != link_up) {
  823. bnx2_report_link(bp);
  824. }
  825. bnx2_set_mac_link(bp);
  826. return 0;
  827. }
  828. static int
  829. bnx2_reset_phy(struct bnx2 *bp)
  830. {
  831. int i;
  832. u32 reg;
  833. bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
  834. #define PHY_RESET_MAX_WAIT 100
  835. for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
  836. udelay(10);
  837. bnx2_read_phy(bp, MII_BMCR, &reg);
  838. if (!(reg & BMCR_RESET)) {
  839. udelay(20);
  840. break;
  841. }
  842. }
  843. if (i == PHY_RESET_MAX_WAIT) {
  844. return -EBUSY;
  845. }
  846. return 0;
  847. }
  848. static u32
  849. bnx2_phy_get_pause_adv(struct bnx2 *bp)
  850. {
  851. u32 adv = 0;
  852. if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
  853. (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
  854. if (bp->phy_flags & PHY_SERDES_FLAG) {
  855. adv = ADVERTISE_1000XPAUSE;
  856. }
  857. else {
  858. adv = ADVERTISE_PAUSE_CAP;
  859. }
  860. }
  861. else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
  862. if (bp->phy_flags & PHY_SERDES_FLAG) {
  863. adv = ADVERTISE_1000XPSE_ASYM;
  864. }
  865. else {
  866. adv = ADVERTISE_PAUSE_ASYM;
  867. }
  868. }
  869. else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
  870. if (bp->phy_flags & PHY_SERDES_FLAG) {
  871. adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  872. }
  873. else {
  874. adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  875. }
  876. }
  877. return adv;
  878. }
  879. static int
  880. bnx2_setup_serdes_phy(struct bnx2 *bp)
  881. {
  882. u32 adv, bmcr, up1;
  883. u32 new_adv = 0;
  884. if (!(bp->autoneg & AUTONEG_SPEED)) {
  885. u32 new_bmcr;
  886. int force_link_down = 0;
  887. bnx2_read_phy(bp, MII_ADVERTISE, &adv);
  888. adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
  889. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  890. new_bmcr = bmcr & ~(BMCR_ANENABLE | BCM5708S_BMCR_FORCE_2500);
  891. new_bmcr |= BMCR_SPEED1000;
  892. if (bp->req_line_speed == SPEED_2500) {
  893. new_bmcr |= BCM5708S_BMCR_FORCE_2500;
  894. bnx2_read_phy(bp, BCM5708S_UP1, &up1);
  895. if (!(up1 & BCM5708S_UP1_2G5)) {
  896. up1 |= BCM5708S_UP1_2G5;
  897. bnx2_write_phy(bp, BCM5708S_UP1, up1);
  898. force_link_down = 1;
  899. }
  900. } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  901. bnx2_read_phy(bp, BCM5708S_UP1, &up1);
  902. if (up1 & BCM5708S_UP1_2G5) {
  903. up1 &= ~BCM5708S_UP1_2G5;
  904. bnx2_write_phy(bp, BCM5708S_UP1, up1);
  905. force_link_down = 1;
  906. }
  907. }
  908. if (bp->req_duplex == DUPLEX_FULL) {
  909. adv |= ADVERTISE_1000XFULL;
  910. new_bmcr |= BMCR_FULLDPLX;
  911. }
  912. else {
  913. adv |= ADVERTISE_1000XHALF;
  914. new_bmcr &= ~BMCR_FULLDPLX;
  915. }
  916. if ((new_bmcr != bmcr) || (force_link_down)) {
  917. /* Force a link down visible on the other side */
  918. if (bp->link_up) {
  919. bnx2_write_phy(bp, MII_ADVERTISE, adv &
  920. ~(ADVERTISE_1000XFULL |
  921. ADVERTISE_1000XHALF));
  922. bnx2_write_phy(bp, MII_BMCR, bmcr |
  923. BMCR_ANRESTART | BMCR_ANENABLE);
  924. bp->link_up = 0;
  925. netif_carrier_off(bp->dev);
  926. bnx2_write_phy(bp, MII_BMCR, new_bmcr);
  927. bnx2_report_link(bp);
  928. }
  929. bnx2_write_phy(bp, MII_ADVERTISE, adv);
  930. bnx2_write_phy(bp, MII_BMCR, new_bmcr);
  931. }
  932. return 0;
  933. }
  934. if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
  935. bnx2_read_phy(bp, BCM5708S_UP1, &up1);
  936. up1 |= BCM5708S_UP1_2G5;
  937. bnx2_write_phy(bp, BCM5708S_UP1, up1);
  938. }
  939. if (bp->advertising & ADVERTISED_1000baseT_Full)
  940. new_adv |= ADVERTISE_1000XFULL;
  941. new_adv |= bnx2_phy_get_pause_adv(bp);
  942. bnx2_read_phy(bp, MII_ADVERTISE, &adv);
  943. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  944. bp->serdes_an_pending = 0;
  945. if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
  946. /* Force a link down visible on the other side */
  947. if (bp->link_up) {
  948. bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
  949. spin_unlock_bh(&bp->phy_lock);
  950. msleep(20);
  951. spin_lock_bh(&bp->phy_lock);
  952. }
  953. bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
  954. bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
  955. BMCR_ANENABLE);
  956. /* Speed up link-up time when the link partner
  957. * does not autonegotiate which is very common
  958. * in blade servers. Some blade servers use
  959. * IPMI for kerboard input and it's important
  960. * to minimize link disruptions. Autoneg. involves
  961. * exchanging base pages plus 3 next pages and
  962. * normally completes in about 120 msec.
  963. */
  964. bp->current_interval = SERDES_AN_TIMEOUT;
  965. bp->serdes_an_pending = 1;
  966. mod_timer(&bp->timer, jiffies + bp->current_interval);
  967. }
  968. return 0;
  969. }
  970. #define ETHTOOL_ALL_FIBRE_SPEED \
  971. (ADVERTISED_1000baseT_Full)
  972. #define ETHTOOL_ALL_COPPER_SPEED \
  973. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
  974. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
  975. ADVERTISED_1000baseT_Full)
  976. #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
  977. ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
  978. #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
  979. static int
  980. bnx2_setup_copper_phy(struct bnx2 *bp)
  981. {
  982. u32 bmcr;
  983. u32 new_bmcr;
  984. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  985. if (bp->autoneg & AUTONEG_SPEED) {
  986. u32 adv_reg, adv1000_reg;
  987. u32 new_adv_reg = 0;
  988. u32 new_adv1000_reg = 0;
  989. bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
  990. adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
  991. ADVERTISE_PAUSE_ASYM);
  992. bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
  993. adv1000_reg &= PHY_ALL_1000_SPEED;
  994. if (bp->advertising & ADVERTISED_10baseT_Half)
  995. new_adv_reg |= ADVERTISE_10HALF;
  996. if (bp->advertising & ADVERTISED_10baseT_Full)
  997. new_adv_reg |= ADVERTISE_10FULL;
  998. if (bp->advertising & ADVERTISED_100baseT_Half)
  999. new_adv_reg |= ADVERTISE_100HALF;
  1000. if (bp->advertising & ADVERTISED_100baseT_Full)
  1001. new_adv_reg |= ADVERTISE_100FULL;
  1002. if (bp->advertising & ADVERTISED_1000baseT_Full)
  1003. new_adv1000_reg |= ADVERTISE_1000FULL;
  1004. new_adv_reg |= ADVERTISE_CSMA;
  1005. new_adv_reg |= bnx2_phy_get_pause_adv(bp);
  1006. if ((adv1000_reg != new_adv1000_reg) ||
  1007. (adv_reg != new_adv_reg) ||
  1008. ((bmcr & BMCR_ANENABLE) == 0)) {
  1009. bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
  1010. bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
  1011. bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
  1012. BMCR_ANENABLE);
  1013. }
  1014. else if (bp->link_up) {
  1015. /* Flow ctrl may have changed from auto to forced */
  1016. /* or vice-versa. */
  1017. bnx2_resolve_flow_ctrl(bp);
  1018. bnx2_set_mac_link(bp);
  1019. }
  1020. return 0;
  1021. }
  1022. new_bmcr = 0;
  1023. if (bp->req_line_speed == SPEED_100) {
  1024. new_bmcr |= BMCR_SPEED100;
  1025. }
  1026. if (bp->req_duplex == DUPLEX_FULL) {
  1027. new_bmcr |= BMCR_FULLDPLX;
  1028. }
  1029. if (new_bmcr != bmcr) {
  1030. u32 bmsr;
  1031. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  1032. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  1033. if (bmsr & BMSR_LSTATUS) {
  1034. /* Force link down */
  1035. bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
  1036. spin_unlock_bh(&bp->phy_lock);
  1037. msleep(50);
  1038. spin_lock_bh(&bp->phy_lock);
  1039. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  1040. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  1041. }
  1042. bnx2_write_phy(bp, MII_BMCR, new_bmcr);
  1043. /* Normally, the new speed is setup after the link has
  1044. * gone down and up again. In some cases, link will not go
  1045. * down so we need to set up the new speed here.
  1046. */
  1047. if (bmsr & BMSR_LSTATUS) {
  1048. bp->line_speed = bp->req_line_speed;
  1049. bp->duplex = bp->req_duplex;
  1050. bnx2_resolve_flow_ctrl(bp);
  1051. bnx2_set_mac_link(bp);
  1052. }
  1053. }
  1054. return 0;
  1055. }
  1056. static int
  1057. bnx2_setup_phy(struct bnx2 *bp)
  1058. {
  1059. if (bp->loopback == MAC_LOOPBACK)
  1060. return 0;
  1061. if (bp->phy_flags & PHY_SERDES_FLAG) {
  1062. return (bnx2_setup_serdes_phy(bp));
  1063. }
  1064. else {
  1065. return (bnx2_setup_copper_phy(bp));
  1066. }
  1067. }
  1068. static int
  1069. bnx2_init_5708s_phy(struct bnx2 *bp)
  1070. {
  1071. u32 val;
  1072. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
  1073. bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
  1074. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
  1075. bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
  1076. val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
  1077. bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
  1078. bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
  1079. val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
  1080. bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
  1081. if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
  1082. bnx2_read_phy(bp, BCM5708S_UP1, &val);
  1083. val |= BCM5708S_UP1_2G5;
  1084. bnx2_write_phy(bp, BCM5708S_UP1, val);
  1085. }
  1086. if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
  1087. (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
  1088. (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
  1089. /* increase tx signal amplitude */
  1090. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1091. BCM5708S_BLK_ADDR_TX_MISC);
  1092. bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
  1093. val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
  1094. bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
  1095. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
  1096. }
  1097. val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
  1098. BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
  1099. if (val) {
  1100. u32 is_backplane;
  1101. is_backplane = REG_RD_IND(bp, bp->shmem_base +
  1102. BNX2_SHARED_HW_CFG_CONFIG);
  1103. if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
  1104. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1105. BCM5708S_BLK_ADDR_TX_MISC);
  1106. bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
  1107. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  1108. BCM5708S_BLK_ADDR_DIG);
  1109. }
  1110. }
  1111. return 0;
  1112. }
  1113. static int
  1114. bnx2_init_5706s_phy(struct bnx2 *bp)
  1115. {
  1116. bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
  1117. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  1118. REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
  1119. if (bp->dev->mtu > 1500) {
  1120. u32 val;
  1121. /* Set extended packet length bit */
  1122. bnx2_write_phy(bp, 0x18, 0x7);
  1123. bnx2_read_phy(bp, 0x18, &val);
  1124. bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
  1125. bnx2_write_phy(bp, 0x1c, 0x6c00);
  1126. bnx2_read_phy(bp, 0x1c, &val);
  1127. bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
  1128. }
  1129. else {
  1130. u32 val;
  1131. bnx2_write_phy(bp, 0x18, 0x7);
  1132. bnx2_read_phy(bp, 0x18, &val);
  1133. bnx2_write_phy(bp, 0x18, val & ~0x4007);
  1134. bnx2_write_phy(bp, 0x1c, 0x6c00);
  1135. bnx2_read_phy(bp, 0x1c, &val);
  1136. bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
  1137. }
  1138. return 0;
  1139. }
  1140. static int
  1141. bnx2_init_copper_phy(struct bnx2 *bp)
  1142. {
  1143. u32 val;
  1144. if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
  1145. bnx2_write_phy(bp, 0x18, 0x0c00);
  1146. bnx2_write_phy(bp, 0x17, 0x000a);
  1147. bnx2_write_phy(bp, 0x15, 0x310b);
  1148. bnx2_write_phy(bp, 0x17, 0x201f);
  1149. bnx2_write_phy(bp, 0x15, 0x9506);
  1150. bnx2_write_phy(bp, 0x17, 0x401f);
  1151. bnx2_write_phy(bp, 0x15, 0x14e2);
  1152. bnx2_write_phy(bp, 0x18, 0x0400);
  1153. }
  1154. if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
  1155. bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
  1156. MII_BNX2_DSP_EXPAND_REG | 0x8);
  1157. bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
  1158. val &= ~(1 << 8);
  1159. bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
  1160. }
  1161. if (bp->dev->mtu > 1500) {
  1162. /* Set extended packet length bit */
  1163. bnx2_write_phy(bp, 0x18, 0x7);
  1164. bnx2_read_phy(bp, 0x18, &val);
  1165. bnx2_write_phy(bp, 0x18, val | 0x4000);
  1166. bnx2_read_phy(bp, 0x10, &val);
  1167. bnx2_write_phy(bp, 0x10, val | 0x1);
  1168. }
  1169. else {
  1170. bnx2_write_phy(bp, 0x18, 0x7);
  1171. bnx2_read_phy(bp, 0x18, &val);
  1172. bnx2_write_phy(bp, 0x18, val & ~0x4007);
  1173. bnx2_read_phy(bp, 0x10, &val);
  1174. bnx2_write_phy(bp, 0x10, val & ~0x1);
  1175. }
  1176. /* ethernet@wirespeed */
  1177. bnx2_write_phy(bp, 0x18, 0x7007);
  1178. bnx2_read_phy(bp, 0x18, &val);
  1179. bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
  1180. return 0;
  1181. }
  1182. static int
  1183. bnx2_init_phy(struct bnx2 *bp)
  1184. {
  1185. u32 val;
  1186. int rc = 0;
  1187. bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
  1188. bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
  1189. REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
  1190. bnx2_reset_phy(bp);
  1191. bnx2_read_phy(bp, MII_PHYSID1, &val);
  1192. bp->phy_id = val << 16;
  1193. bnx2_read_phy(bp, MII_PHYSID2, &val);
  1194. bp->phy_id |= val & 0xffff;
  1195. if (bp->phy_flags & PHY_SERDES_FLAG) {
  1196. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  1197. rc = bnx2_init_5706s_phy(bp);
  1198. else if (CHIP_NUM(bp) == CHIP_NUM_5708)
  1199. rc = bnx2_init_5708s_phy(bp);
  1200. }
  1201. else {
  1202. rc = bnx2_init_copper_phy(bp);
  1203. }
  1204. bnx2_setup_phy(bp);
  1205. return rc;
  1206. }
  1207. static int
  1208. bnx2_set_mac_loopback(struct bnx2 *bp)
  1209. {
  1210. u32 mac_mode;
  1211. mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
  1212. mac_mode &= ~BNX2_EMAC_MODE_PORT;
  1213. mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
  1214. REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
  1215. bp->link_up = 1;
  1216. return 0;
  1217. }
  1218. static int bnx2_test_link(struct bnx2 *);
  1219. static int
  1220. bnx2_set_phy_loopback(struct bnx2 *bp)
  1221. {
  1222. u32 mac_mode;
  1223. int rc, i;
  1224. spin_lock_bh(&bp->phy_lock);
  1225. rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
  1226. BMCR_SPEED1000);
  1227. spin_unlock_bh(&bp->phy_lock);
  1228. if (rc)
  1229. return rc;
  1230. for (i = 0; i < 10; i++) {
  1231. if (bnx2_test_link(bp) == 0)
  1232. break;
  1233. msleep(100);
  1234. }
  1235. mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
  1236. mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
  1237. BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
  1238. BNX2_EMAC_MODE_25G_MODE);
  1239. mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
  1240. REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
  1241. bp->link_up = 1;
  1242. return 0;
  1243. }
  1244. static int
  1245. bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
  1246. {
  1247. int i;
  1248. u32 val;
  1249. bp->fw_wr_seq++;
  1250. msg_data |= bp->fw_wr_seq;
  1251. REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
  1252. /* wait for an acknowledgement. */
  1253. for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
  1254. msleep(10);
  1255. val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
  1256. if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
  1257. break;
  1258. }
  1259. if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
  1260. return 0;
  1261. /* If we timed out, inform the firmware that this is the case. */
  1262. if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
  1263. if (!silent)
  1264. printk(KERN_ERR PFX "fw sync timeout, reset code = "
  1265. "%x\n", msg_data);
  1266. msg_data &= ~BNX2_DRV_MSG_CODE;
  1267. msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
  1268. REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
  1269. return -EBUSY;
  1270. }
  1271. if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
  1272. return -EIO;
  1273. return 0;
  1274. }
  1275. static int
  1276. bnx2_init_5709_context(struct bnx2 *bp)
  1277. {
  1278. int i, ret = 0;
  1279. u32 val;
  1280. val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
  1281. val |= (BCM_PAGE_BITS - 8) << 16;
  1282. REG_WR(bp, BNX2_CTX_COMMAND, val);
  1283. for (i = 0; i < bp->ctx_pages; i++) {
  1284. int j;
  1285. REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  1286. (bp->ctx_blk_mapping[i] & 0xffffffff) |
  1287. BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
  1288. REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  1289. (u64) bp->ctx_blk_mapping[i] >> 32);
  1290. REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
  1291. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  1292. for (j = 0; j < 10; j++) {
  1293. val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  1294. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  1295. break;
  1296. udelay(5);
  1297. }
  1298. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  1299. ret = -EBUSY;
  1300. break;
  1301. }
  1302. }
  1303. return ret;
  1304. }
  1305. static void
  1306. bnx2_init_context(struct bnx2 *bp)
  1307. {
  1308. u32 vcid;
  1309. vcid = 96;
  1310. while (vcid) {
  1311. u32 vcid_addr, pcid_addr, offset;
  1312. vcid--;
  1313. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  1314. u32 new_vcid;
  1315. vcid_addr = GET_PCID_ADDR(vcid);
  1316. if (vcid & 0x8) {
  1317. new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
  1318. }
  1319. else {
  1320. new_vcid = vcid;
  1321. }
  1322. pcid_addr = GET_PCID_ADDR(new_vcid);
  1323. }
  1324. else {
  1325. vcid_addr = GET_CID_ADDR(vcid);
  1326. pcid_addr = vcid_addr;
  1327. }
  1328. REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
  1329. REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
  1330. /* Zero out the context. */
  1331. for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
  1332. CTX_WR(bp, 0x00, offset, 0);
  1333. }
  1334. REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
  1335. REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
  1336. }
  1337. }
  1338. static int
  1339. bnx2_alloc_bad_rbuf(struct bnx2 *bp)
  1340. {
  1341. u16 *good_mbuf;
  1342. u32 good_mbuf_cnt;
  1343. u32 val;
  1344. good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
  1345. if (good_mbuf == NULL) {
  1346. printk(KERN_ERR PFX "Failed to allocate memory in "
  1347. "bnx2_alloc_bad_rbuf\n");
  1348. return -ENOMEM;
  1349. }
  1350. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  1351. BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
  1352. good_mbuf_cnt = 0;
  1353. /* Allocate a bunch of mbufs and save the good ones in an array. */
  1354. val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
  1355. while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
  1356. REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
  1357. val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
  1358. val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
  1359. /* The addresses with Bit 9 set are bad memory blocks. */
  1360. if (!(val & (1 << 9))) {
  1361. good_mbuf[good_mbuf_cnt] = (u16) val;
  1362. good_mbuf_cnt++;
  1363. }
  1364. val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
  1365. }
  1366. /* Free the good ones back to the mbuf pool thus discarding
  1367. * all the bad ones. */
  1368. while (good_mbuf_cnt) {
  1369. good_mbuf_cnt--;
  1370. val = good_mbuf[good_mbuf_cnt];
  1371. val = (val << 9) | val | 1;
  1372. REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
  1373. }
  1374. kfree(good_mbuf);
  1375. return 0;
  1376. }
  1377. static void
  1378. bnx2_set_mac_addr(struct bnx2 *bp)
  1379. {
  1380. u32 val;
  1381. u8 *mac_addr = bp->dev->dev_addr;
  1382. val = (mac_addr[0] << 8) | mac_addr[1];
  1383. REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
  1384. val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
  1385. (mac_addr[4] << 8) | mac_addr[5];
  1386. REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
  1387. }
  1388. static inline int
  1389. bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
  1390. {
  1391. struct sk_buff *skb;
  1392. struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
  1393. dma_addr_t mapping;
  1394. struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
  1395. unsigned long align;
  1396. skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
  1397. if (skb == NULL) {
  1398. return -ENOMEM;
  1399. }
  1400. if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
  1401. skb_reserve(skb, BNX2_RX_ALIGN - align);
  1402. mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
  1403. PCI_DMA_FROMDEVICE);
  1404. rx_buf->skb = skb;
  1405. pci_unmap_addr_set(rx_buf, mapping, mapping);
  1406. rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
  1407. rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  1408. bp->rx_prod_bseq += bp->rx_buf_use_size;
  1409. return 0;
  1410. }
  1411. static void
  1412. bnx2_phy_int(struct bnx2 *bp)
  1413. {
  1414. u32 new_link_state, old_link_state;
  1415. new_link_state = bp->status_blk->status_attn_bits &
  1416. STATUS_ATTN_BITS_LINK_STATE;
  1417. old_link_state = bp->status_blk->status_attn_bits_ack &
  1418. STATUS_ATTN_BITS_LINK_STATE;
  1419. if (new_link_state != old_link_state) {
  1420. if (new_link_state) {
  1421. REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
  1422. STATUS_ATTN_BITS_LINK_STATE);
  1423. }
  1424. else {
  1425. REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
  1426. STATUS_ATTN_BITS_LINK_STATE);
  1427. }
  1428. bnx2_set_link(bp);
  1429. }
  1430. }
  1431. static void
  1432. bnx2_tx_int(struct bnx2 *bp)
  1433. {
  1434. struct status_block *sblk = bp->status_blk;
  1435. u16 hw_cons, sw_cons, sw_ring_cons;
  1436. int tx_free_bd = 0;
  1437. hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
  1438. if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
  1439. hw_cons++;
  1440. }
  1441. sw_cons = bp->tx_cons;
  1442. while (sw_cons != hw_cons) {
  1443. struct sw_bd *tx_buf;
  1444. struct sk_buff *skb;
  1445. int i, last;
  1446. sw_ring_cons = TX_RING_IDX(sw_cons);
  1447. tx_buf = &bp->tx_buf_ring[sw_ring_cons];
  1448. skb = tx_buf->skb;
  1449. /* partial BD completions possible with TSO packets */
  1450. if (skb_is_gso(skb)) {
  1451. u16 last_idx, last_ring_idx;
  1452. last_idx = sw_cons +
  1453. skb_shinfo(skb)->nr_frags + 1;
  1454. last_ring_idx = sw_ring_cons +
  1455. skb_shinfo(skb)->nr_frags + 1;
  1456. if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
  1457. last_idx++;
  1458. }
  1459. if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
  1460. break;
  1461. }
  1462. }
  1463. pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
  1464. skb_headlen(skb), PCI_DMA_TODEVICE);
  1465. tx_buf->skb = NULL;
  1466. last = skb_shinfo(skb)->nr_frags;
  1467. for (i = 0; i < last; i++) {
  1468. sw_cons = NEXT_TX_BD(sw_cons);
  1469. pci_unmap_page(bp->pdev,
  1470. pci_unmap_addr(
  1471. &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
  1472. mapping),
  1473. skb_shinfo(skb)->frags[i].size,
  1474. PCI_DMA_TODEVICE);
  1475. }
  1476. sw_cons = NEXT_TX_BD(sw_cons);
  1477. tx_free_bd += last + 1;
  1478. dev_kfree_skb(skb);
  1479. hw_cons = bp->hw_tx_cons =
  1480. sblk->status_tx_quick_consumer_index0;
  1481. if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
  1482. hw_cons++;
  1483. }
  1484. }
  1485. bp->tx_cons = sw_cons;
  1486. /* Need to make the tx_cons update visible to bnx2_start_xmit()
  1487. * before checking for netif_queue_stopped(). Without the
  1488. * memory barrier, there is a small possibility that bnx2_start_xmit()
  1489. * will miss it and cause the queue to be stopped forever.
  1490. */
  1491. smp_mb();
  1492. if (unlikely(netif_queue_stopped(bp->dev)) &&
  1493. (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
  1494. netif_tx_lock(bp->dev);
  1495. if ((netif_queue_stopped(bp->dev)) &&
  1496. (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
  1497. netif_wake_queue(bp->dev);
  1498. netif_tx_unlock(bp->dev);
  1499. }
  1500. }
  1501. static inline void
  1502. bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
  1503. u16 cons, u16 prod)
  1504. {
  1505. struct sw_bd *cons_rx_buf, *prod_rx_buf;
  1506. struct rx_bd *cons_bd, *prod_bd;
  1507. cons_rx_buf = &bp->rx_buf_ring[cons];
  1508. prod_rx_buf = &bp->rx_buf_ring[prod];
  1509. pci_dma_sync_single_for_device(bp->pdev,
  1510. pci_unmap_addr(cons_rx_buf, mapping),
  1511. bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
  1512. bp->rx_prod_bseq += bp->rx_buf_use_size;
  1513. prod_rx_buf->skb = skb;
  1514. if (cons == prod)
  1515. return;
  1516. pci_unmap_addr_set(prod_rx_buf, mapping,
  1517. pci_unmap_addr(cons_rx_buf, mapping));
  1518. cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
  1519. prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
  1520. prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
  1521. prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
  1522. }
  1523. static int
  1524. bnx2_rx_int(struct bnx2 *bp, int budget)
  1525. {
  1526. struct status_block *sblk = bp->status_blk;
  1527. u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
  1528. struct l2_fhdr *rx_hdr;
  1529. int rx_pkt = 0;
  1530. hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
  1531. if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
  1532. hw_cons++;
  1533. }
  1534. sw_cons = bp->rx_cons;
  1535. sw_prod = bp->rx_prod;
  1536. /* Memory barrier necessary as speculative reads of the rx
  1537. * buffer can be ahead of the index in the status block
  1538. */
  1539. rmb();
  1540. while (sw_cons != hw_cons) {
  1541. unsigned int len;
  1542. u32 status;
  1543. struct sw_bd *rx_buf;
  1544. struct sk_buff *skb;
  1545. dma_addr_t dma_addr;
  1546. sw_ring_cons = RX_RING_IDX(sw_cons);
  1547. sw_ring_prod = RX_RING_IDX(sw_prod);
  1548. rx_buf = &bp->rx_buf_ring[sw_ring_cons];
  1549. skb = rx_buf->skb;
  1550. rx_buf->skb = NULL;
  1551. dma_addr = pci_unmap_addr(rx_buf, mapping);
  1552. pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
  1553. bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
  1554. rx_hdr = (struct l2_fhdr *) skb->data;
  1555. len = rx_hdr->l2_fhdr_pkt_len - 4;
  1556. if ((status = rx_hdr->l2_fhdr_status) &
  1557. (L2_FHDR_ERRORS_BAD_CRC |
  1558. L2_FHDR_ERRORS_PHY_DECODE |
  1559. L2_FHDR_ERRORS_ALIGNMENT |
  1560. L2_FHDR_ERRORS_TOO_SHORT |
  1561. L2_FHDR_ERRORS_GIANT_FRAME)) {
  1562. goto reuse_rx;
  1563. }
  1564. /* Since we don't have a jumbo ring, copy small packets
  1565. * if mtu > 1500
  1566. */
  1567. if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
  1568. struct sk_buff *new_skb;
  1569. new_skb = netdev_alloc_skb(bp->dev, len + 2);
  1570. if (new_skb == NULL)
  1571. goto reuse_rx;
  1572. /* aligned copy */
  1573. memcpy(new_skb->data,
  1574. skb->data + bp->rx_offset - 2,
  1575. len + 2);
  1576. skb_reserve(new_skb, 2);
  1577. skb_put(new_skb, len);
  1578. bnx2_reuse_rx_skb(bp, skb,
  1579. sw_ring_cons, sw_ring_prod);
  1580. skb = new_skb;
  1581. }
  1582. else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
  1583. pci_unmap_single(bp->pdev, dma_addr,
  1584. bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
  1585. skb_reserve(skb, bp->rx_offset);
  1586. skb_put(skb, len);
  1587. }
  1588. else {
  1589. reuse_rx:
  1590. bnx2_reuse_rx_skb(bp, skb,
  1591. sw_ring_cons, sw_ring_prod);
  1592. goto next_rx;
  1593. }
  1594. skb->protocol = eth_type_trans(skb, bp->dev);
  1595. if ((len > (bp->dev->mtu + ETH_HLEN)) &&
  1596. (ntohs(skb->protocol) != 0x8100)) {
  1597. dev_kfree_skb(skb);
  1598. goto next_rx;
  1599. }
  1600. skb->ip_summed = CHECKSUM_NONE;
  1601. if (bp->rx_csum &&
  1602. (status & (L2_FHDR_STATUS_TCP_SEGMENT |
  1603. L2_FHDR_STATUS_UDP_DATAGRAM))) {
  1604. if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
  1605. L2_FHDR_ERRORS_UDP_XSUM)) == 0))
  1606. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1607. }
  1608. #ifdef BCM_VLAN
  1609. if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
  1610. vlan_hwaccel_receive_skb(skb, bp->vlgrp,
  1611. rx_hdr->l2_fhdr_vlan_tag);
  1612. }
  1613. else
  1614. #endif
  1615. netif_receive_skb(skb);
  1616. bp->dev->last_rx = jiffies;
  1617. rx_pkt++;
  1618. next_rx:
  1619. sw_cons = NEXT_RX_BD(sw_cons);
  1620. sw_prod = NEXT_RX_BD(sw_prod);
  1621. if ((rx_pkt == budget))
  1622. break;
  1623. /* Refresh hw_cons to see if there is new work */
  1624. if (sw_cons == hw_cons) {
  1625. hw_cons = bp->hw_rx_cons =
  1626. sblk->status_rx_quick_consumer_index0;
  1627. if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
  1628. hw_cons++;
  1629. rmb();
  1630. }
  1631. }
  1632. bp->rx_cons = sw_cons;
  1633. bp->rx_prod = sw_prod;
  1634. REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
  1635. REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
  1636. mmiowb();
  1637. return rx_pkt;
  1638. }
  1639. /* MSI ISR - The only difference between this and the INTx ISR
  1640. * is that the MSI interrupt is always serviced.
  1641. */
  1642. static irqreturn_t
  1643. bnx2_msi(int irq, void *dev_instance)
  1644. {
  1645. struct net_device *dev = dev_instance;
  1646. struct bnx2 *bp = netdev_priv(dev);
  1647. prefetch(bp->status_blk);
  1648. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  1649. BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
  1650. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  1651. /* Return here if interrupt is disabled. */
  1652. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  1653. return IRQ_HANDLED;
  1654. netif_rx_schedule(dev);
  1655. return IRQ_HANDLED;
  1656. }
  1657. static irqreturn_t
  1658. bnx2_interrupt(int irq, void *dev_instance)
  1659. {
  1660. struct net_device *dev = dev_instance;
  1661. struct bnx2 *bp = netdev_priv(dev);
  1662. /* When using INTx, it is possible for the interrupt to arrive
  1663. * at the CPU before the status block posted prior to the
  1664. * interrupt. Reading a register will flush the status block.
  1665. * When using MSI, the MSI message will always complete after
  1666. * the status block write.
  1667. */
  1668. if ((bp->status_blk->status_idx == bp->last_status_idx) &&
  1669. (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
  1670. BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
  1671. return IRQ_NONE;
  1672. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  1673. BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
  1674. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  1675. /* Return here if interrupt is shared and is disabled. */
  1676. if (unlikely(atomic_read(&bp->intr_sem) != 0))
  1677. return IRQ_HANDLED;
  1678. netif_rx_schedule(dev);
  1679. return IRQ_HANDLED;
  1680. }
  1681. static inline int
  1682. bnx2_has_work(struct bnx2 *bp)
  1683. {
  1684. struct status_block *sblk = bp->status_blk;
  1685. if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
  1686. (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
  1687. return 1;
  1688. if ((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
  1689. (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
  1690. return 1;
  1691. return 0;
  1692. }
  1693. static int
  1694. bnx2_poll(struct net_device *dev, int *budget)
  1695. {
  1696. struct bnx2 *bp = netdev_priv(dev);
  1697. if ((bp->status_blk->status_attn_bits &
  1698. STATUS_ATTN_BITS_LINK_STATE) !=
  1699. (bp->status_blk->status_attn_bits_ack &
  1700. STATUS_ATTN_BITS_LINK_STATE)) {
  1701. spin_lock(&bp->phy_lock);
  1702. bnx2_phy_int(bp);
  1703. spin_unlock(&bp->phy_lock);
  1704. /* This is needed to take care of transient status
  1705. * during link changes.
  1706. */
  1707. REG_WR(bp, BNX2_HC_COMMAND,
  1708. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  1709. REG_RD(bp, BNX2_HC_COMMAND);
  1710. }
  1711. if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
  1712. bnx2_tx_int(bp);
  1713. if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
  1714. int orig_budget = *budget;
  1715. int work_done;
  1716. if (orig_budget > dev->quota)
  1717. orig_budget = dev->quota;
  1718. work_done = bnx2_rx_int(bp, orig_budget);
  1719. *budget -= work_done;
  1720. dev->quota -= work_done;
  1721. }
  1722. bp->last_status_idx = bp->status_blk->status_idx;
  1723. rmb();
  1724. if (!bnx2_has_work(bp)) {
  1725. netif_rx_complete(dev);
  1726. if (likely(bp->flags & USING_MSI_FLAG)) {
  1727. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  1728. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  1729. bp->last_status_idx);
  1730. return 0;
  1731. }
  1732. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  1733. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  1734. BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
  1735. bp->last_status_idx);
  1736. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  1737. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  1738. bp->last_status_idx);
  1739. return 0;
  1740. }
  1741. return 1;
  1742. }
  1743. /* Called with rtnl_lock from vlan functions and also netif_tx_lock
  1744. * from set_multicast.
  1745. */
  1746. static void
  1747. bnx2_set_rx_mode(struct net_device *dev)
  1748. {
  1749. struct bnx2 *bp = netdev_priv(dev);
  1750. u32 rx_mode, sort_mode;
  1751. int i;
  1752. spin_lock_bh(&bp->phy_lock);
  1753. rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
  1754. BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
  1755. sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
  1756. #ifdef BCM_VLAN
  1757. if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
  1758. rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
  1759. #else
  1760. if (!(bp->flags & ASF_ENABLE_FLAG))
  1761. rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
  1762. #endif
  1763. if (dev->flags & IFF_PROMISC) {
  1764. /* Promiscuous mode. */
  1765. rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
  1766. sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
  1767. BNX2_RPM_SORT_USER0_PROM_VLAN;
  1768. }
  1769. else if (dev->flags & IFF_ALLMULTI) {
  1770. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  1771. REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  1772. 0xffffffff);
  1773. }
  1774. sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
  1775. }
  1776. else {
  1777. /* Accept one or more multicast(s). */
  1778. struct dev_mc_list *mclist;
  1779. u32 mc_filter[NUM_MC_HASH_REGISTERS];
  1780. u32 regidx;
  1781. u32 bit;
  1782. u32 crc;
  1783. memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
  1784. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  1785. i++, mclist = mclist->next) {
  1786. crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
  1787. bit = crc & 0xff;
  1788. regidx = (bit & 0xe0) >> 5;
  1789. bit &= 0x1f;
  1790. mc_filter[regidx] |= (1 << bit);
  1791. }
  1792. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  1793. REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  1794. mc_filter[i]);
  1795. }
  1796. sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
  1797. }
  1798. if (rx_mode != bp->rx_mode) {
  1799. bp->rx_mode = rx_mode;
  1800. REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
  1801. }
  1802. REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
  1803. REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
  1804. REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
  1805. spin_unlock_bh(&bp->phy_lock);
  1806. }
  1807. #define FW_BUF_SIZE 0x8000
  1808. static int
  1809. bnx2_gunzip_init(struct bnx2 *bp)
  1810. {
  1811. if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL)
  1812. goto gunzip_nomem1;
  1813. if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL)
  1814. goto gunzip_nomem2;
  1815. bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
  1816. if (bp->strm->workspace == NULL)
  1817. goto gunzip_nomem3;
  1818. return 0;
  1819. gunzip_nomem3:
  1820. kfree(bp->strm);
  1821. bp->strm = NULL;
  1822. gunzip_nomem2:
  1823. vfree(bp->gunzip_buf);
  1824. bp->gunzip_buf = NULL;
  1825. gunzip_nomem1:
  1826. printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for "
  1827. "uncompression.\n", bp->dev->name);
  1828. return -ENOMEM;
  1829. }
  1830. static void
  1831. bnx2_gunzip_end(struct bnx2 *bp)
  1832. {
  1833. kfree(bp->strm->workspace);
  1834. kfree(bp->strm);
  1835. bp->strm = NULL;
  1836. if (bp->gunzip_buf) {
  1837. vfree(bp->gunzip_buf);
  1838. bp->gunzip_buf = NULL;
  1839. }
  1840. }
  1841. static int
  1842. bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen)
  1843. {
  1844. int n, rc;
  1845. /* check gzip header */
  1846. if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
  1847. return -EINVAL;
  1848. n = 10;
  1849. #define FNAME 0x8
  1850. if (zbuf[3] & FNAME)
  1851. while ((zbuf[n++] != 0) && (n < len));
  1852. bp->strm->next_in = zbuf + n;
  1853. bp->strm->avail_in = len - n;
  1854. bp->strm->next_out = bp->gunzip_buf;
  1855. bp->strm->avail_out = FW_BUF_SIZE;
  1856. rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
  1857. if (rc != Z_OK)
  1858. return rc;
  1859. rc = zlib_inflate(bp->strm, Z_FINISH);
  1860. *outlen = FW_BUF_SIZE - bp->strm->avail_out;
  1861. *outbuf = bp->gunzip_buf;
  1862. if ((rc != Z_OK) && (rc != Z_STREAM_END))
  1863. printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
  1864. bp->dev->name, bp->strm->msg);
  1865. zlib_inflateEnd(bp->strm);
  1866. if (rc == Z_STREAM_END)
  1867. return 0;
  1868. return rc;
  1869. }
  1870. static void
  1871. load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
  1872. u32 rv2p_proc)
  1873. {
  1874. int i;
  1875. u32 val;
  1876. for (i = 0; i < rv2p_code_len; i += 8) {
  1877. REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
  1878. rv2p_code++;
  1879. REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
  1880. rv2p_code++;
  1881. if (rv2p_proc == RV2P_PROC1) {
  1882. val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
  1883. REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
  1884. }
  1885. else {
  1886. val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
  1887. REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
  1888. }
  1889. }
  1890. /* Reset the processor, un-stall is done later. */
  1891. if (rv2p_proc == RV2P_PROC1) {
  1892. REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
  1893. }
  1894. else {
  1895. REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
  1896. }
  1897. }
  1898. static int
  1899. load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
  1900. {
  1901. u32 offset;
  1902. u32 val;
  1903. int rc;
  1904. /* Halt the CPU. */
  1905. val = REG_RD_IND(bp, cpu_reg->mode);
  1906. val |= cpu_reg->mode_value_halt;
  1907. REG_WR_IND(bp, cpu_reg->mode, val);
  1908. REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
  1909. /* Load the Text area. */
  1910. offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
  1911. if (fw->gz_text) {
  1912. u32 text_len;
  1913. void *text;
  1914. rc = bnx2_gunzip(bp, fw->gz_text, fw->gz_text_len, &text,
  1915. &text_len);
  1916. if (rc)
  1917. return rc;
  1918. fw->text = text;
  1919. }
  1920. if (fw->gz_text) {
  1921. int j;
  1922. for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
  1923. REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
  1924. }
  1925. }
  1926. /* Load the Data area. */
  1927. offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
  1928. if (fw->data) {
  1929. int j;
  1930. for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
  1931. REG_WR_IND(bp, offset, fw->data[j]);
  1932. }
  1933. }
  1934. /* Load the SBSS area. */
  1935. offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
  1936. if (fw->sbss) {
  1937. int j;
  1938. for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
  1939. REG_WR_IND(bp, offset, fw->sbss[j]);
  1940. }
  1941. }
  1942. /* Load the BSS area. */
  1943. offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
  1944. if (fw->bss) {
  1945. int j;
  1946. for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
  1947. REG_WR_IND(bp, offset, fw->bss[j]);
  1948. }
  1949. }
  1950. /* Load the Read-Only area. */
  1951. offset = cpu_reg->spad_base +
  1952. (fw->rodata_addr - cpu_reg->mips_view_base);
  1953. if (fw->rodata) {
  1954. int j;
  1955. for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
  1956. REG_WR_IND(bp, offset, fw->rodata[j]);
  1957. }
  1958. }
  1959. /* Clear the pre-fetch instruction. */
  1960. REG_WR_IND(bp, cpu_reg->inst, 0);
  1961. REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
  1962. /* Start the CPU. */
  1963. val = REG_RD_IND(bp, cpu_reg->mode);
  1964. val &= ~cpu_reg->mode_value_halt;
  1965. REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
  1966. REG_WR_IND(bp, cpu_reg->mode, val);
  1967. return 0;
  1968. }
  1969. static int
  1970. bnx2_init_cpus(struct bnx2 *bp)
  1971. {
  1972. struct cpu_reg cpu_reg;
  1973. struct fw_info *fw;
  1974. int rc = 0;
  1975. void *text;
  1976. u32 text_len;
  1977. if ((rc = bnx2_gunzip_init(bp)) != 0)
  1978. return rc;
  1979. /* Initialize the RV2P processor. */
  1980. rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text,
  1981. &text_len);
  1982. if (rc)
  1983. goto init_cpu_err;
  1984. load_rv2p_fw(bp, text, text_len, RV2P_PROC1);
  1985. rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text,
  1986. &text_len);
  1987. if (rc)
  1988. goto init_cpu_err;
  1989. load_rv2p_fw(bp, text, text_len, RV2P_PROC2);
  1990. /* Initialize the RX Processor. */
  1991. cpu_reg.mode = BNX2_RXP_CPU_MODE;
  1992. cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
  1993. cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
  1994. cpu_reg.state = BNX2_RXP_CPU_STATE;
  1995. cpu_reg.state_value_clear = 0xffffff;
  1996. cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
  1997. cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
  1998. cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
  1999. cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
  2000. cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
  2001. cpu_reg.spad_base = BNX2_RXP_SCRATCH;
  2002. cpu_reg.mips_view_base = 0x8000000;
  2003. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2004. fw = &bnx2_rxp_fw_09;
  2005. else
  2006. fw = &bnx2_rxp_fw_06;
  2007. rc = load_cpu_fw(bp, &cpu_reg, fw);
  2008. if (rc)
  2009. goto init_cpu_err;
  2010. /* Initialize the TX Processor. */
  2011. cpu_reg.mode = BNX2_TXP_CPU_MODE;
  2012. cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
  2013. cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
  2014. cpu_reg.state = BNX2_TXP_CPU_STATE;
  2015. cpu_reg.state_value_clear = 0xffffff;
  2016. cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
  2017. cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
  2018. cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
  2019. cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
  2020. cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
  2021. cpu_reg.spad_base = BNX2_TXP_SCRATCH;
  2022. cpu_reg.mips_view_base = 0x8000000;
  2023. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2024. fw = &bnx2_txp_fw_09;
  2025. else
  2026. fw = &bnx2_txp_fw_06;
  2027. rc = load_cpu_fw(bp, &cpu_reg, fw);
  2028. if (rc)
  2029. goto init_cpu_err;
  2030. /* Initialize the TX Patch-up Processor. */
  2031. cpu_reg.mode = BNX2_TPAT_CPU_MODE;
  2032. cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
  2033. cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
  2034. cpu_reg.state = BNX2_TPAT_CPU_STATE;
  2035. cpu_reg.state_value_clear = 0xffffff;
  2036. cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
  2037. cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
  2038. cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
  2039. cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
  2040. cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
  2041. cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
  2042. cpu_reg.mips_view_base = 0x8000000;
  2043. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2044. fw = &bnx2_tpat_fw_09;
  2045. else
  2046. fw = &bnx2_tpat_fw_06;
  2047. rc = load_cpu_fw(bp, &cpu_reg, fw);
  2048. if (rc)
  2049. goto init_cpu_err;
  2050. /* Initialize the Completion Processor. */
  2051. cpu_reg.mode = BNX2_COM_CPU_MODE;
  2052. cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
  2053. cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
  2054. cpu_reg.state = BNX2_COM_CPU_STATE;
  2055. cpu_reg.state_value_clear = 0xffffff;
  2056. cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
  2057. cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
  2058. cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
  2059. cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
  2060. cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
  2061. cpu_reg.spad_base = BNX2_COM_SCRATCH;
  2062. cpu_reg.mips_view_base = 0x8000000;
  2063. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2064. fw = &bnx2_com_fw_09;
  2065. else
  2066. fw = &bnx2_com_fw_06;
  2067. rc = load_cpu_fw(bp, &cpu_reg, fw);
  2068. if (rc)
  2069. goto init_cpu_err;
  2070. /* Initialize the Command Processor. */
  2071. cpu_reg.mode = BNX2_CP_CPU_MODE;
  2072. cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
  2073. cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
  2074. cpu_reg.state = BNX2_CP_CPU_STATE;
  2075. cpu_reg.state_value_clear = 0xffffff;
  2076. cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
  2077. cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
  2078. cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
  2079. cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
  2080. cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
  2081. cpu_reg.spad_base = BNX2_CP_SCRATCH;
  2082. cpu_reg.mips_view_base = 0x8000000;
  2083. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  2084. fw = &bnx2_cp_fw_09;
  2085. rc = load_cpu_fw(bp, &cpu_reg, fw);
  2086. if (rc)
  2087. goto init_cpu_err;
  2088. }
  2089. init_cpu_err:
  2090. bnx2_gunzip_end(bp);
  2091. return rc;
  2092. }
  2093. static int
  2094. bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
  2095. {
  2096. u16 pmcsr;
  2097. pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
  2098. switch (state) {
  2099. case PCI_D0: {
  2100. u32 val;
  2101. pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
  2102. (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
  2103. PCI_PM_CTRL_PME_STATUS);
  2104. if (pmcsr & PCI_PM_CTRL_STATE_MASK)
  2105. /* delay required during transition out of D3hot */
  2106. msleep(20);
  2107. val = REG_RD(bp, BNX2_EMAC_MODE);
  2108. val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
  2109. val &= ~BNX2_EMAC_MODE_MPKT;
  2110. REG_WR(bp, BNX2_EMAC_MODE, val);
  2111. val = REG_RD(bp, BNX2_RPM_CONFIG);
  2112. val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
  2113. REG_WR(bp, BNX2_RPM_CONFIG, val);
  2114. break;
  2115. }
  2116. case PCI_D3hot: {
  2117. int i;
  2118. u32 val, wol_msg;
  2119. if (bp->wol) {
  2120. u32 advertising;
  2121. u8 autoneg;
  2122. autoneg = bp->autoneg;
  2123. advertising = bp->advertising;
  2124. bp->autoneg = AUTONEG_SPEED;
  2125. bp->advertising = ADVERTISED_10baseT_Half |
  2126. ADVERTISED_10baseT_Full |
  2127. ADVERTISED_100baseT_Half |
  2128. ADVERTISED_100baseT_Full |
  2129. ADVERTISED_Autoneg;
  2130. bnx2_setup_copper_phy(bp);
  2131. bp->autoneg = autoneg;
  2132. bp->advertising = advertising;
  2133. bnx2_set_mac_addr(bp);
  2134. val = REG_RD(bp, BNX2_EMAC_MODE);
  2135. /* Enable port mode. */
  2136. val &= ~BNX2_EMAC_MODE_PORT;
  2137. val |= BNX2_EMAC_MODE_PORT_MII |
  2138. BNX2_EMAC_MODE_MPKT_RCVD |
  2139. BNX2_EMAC_MODE_ACPI_RCVD |
  2140. BNX2_EMAC_MODE_MPKT;
  2141. REG_WR(bp, BNX2_EMAC_MODE, val);
  2142. /* receive all multicast */
  2143. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  2144. REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  2145. 0xffffffff);
  2146. }
  2147. REG_WR(bp, BNX2_EMAC_RX_MODE,
  2148. BNX2_EMAC_RX_MODE_SORT_MODE);
  2149. val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
  2150. BNX2_RPM_SORT_USER0_MC_EN;
  2151. REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
  2152. REG_WR(bp, BNX2_RPM_SORT_USER0, val);
  2153. REG_WR(bp, BNX2_RPM_SORT_USER0, val |
  2154. BNX2_RPM_SORT_USER0_ENA);
  2155. /* Need to enable EMAC and RPM for WOL. */
  2156. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  2157. BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
  2158. BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
  2159. BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
  2160. val = REG_RD(bp, BNX2_RPM_CONFIG);
  2161. val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
  2162. REG_WR(bp, BNX2_RPM_CONFIG, val);
  2163. wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
  2164. }
  2165. else {
  2166. wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
  2167. }
  2168. if (!(bp->flags & NO_WOL_FLAG))
  2169. bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
  2170. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  2171. if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
  2172. (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
  2173. if (bp->wol)
  2174. pmcsr |= 3;
  2175. }
  2176. else {
  2177. pmcsr |= 3;
  2178. }
  2179. if (bp->wol) {
  2180. pmcsr |= PCI_PM_CTRL_PME_ENABLE;
  2181. }
  2182. pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
  2183. pmcsr);
  2184. /* No more memory access after this point until
  2185. * device is brought back to D0.
  2186. */
  2187. udelay(50);
  2188. break;
  2189. }
  2190. default:
  2191. return -EINVAL;
  2192. }
  2193. return 0;
  2194. }
  2195. static int
  2196. bnx2_acquire_nvram_lock(struct bnx2 *bp)
  2197. {
  2198. u32 val;
  2199. int j;
  2200. /* Request access to the flash interface. */
  2201. REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
  2202. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  2203. val = REG_RD(bp, BNX2_NVM_SW_ARB);
  2204. if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
  2205. break;
  2206. udelay(5);
  2207. }
  2208. if (j >= NVRAM_TIMEOUT_COUNT)
  2209. return -EBUSY;
  2210. return 0;
  2211. }
  2212. static int
  2213. bnx2_release_nvram_lock(struct bnx2 *bp)
  2214. {
  2215. int j;
  2216. u32 val;
  2217. /* Relinquish nvram interface. */
  2218. REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
  2219. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  2220. val = REG_RD(bp, BNX2_NVM_SW_ARB);
  2221. if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
  2222. break;
  2223. udelay(5);
  2224. }
  2225. if (j >= NVRAM_TIMEOUT_COUNT)
  2226. return -EBUSY;
  2227. return 0;
  2228. }
  2229. static int
  2230. bnx2_enable_nvram_write(struct bnx2 *bp)
  2231. {
  2232. u32 val;
  2233. val = REG_RD(bp, BNX2_MISC_CFG);
  2234. REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
  2235. if (!bp->flash_info->buffered) {
  2236. int j;
  2237. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  2238. REG_WR(bp, BNX2_NVM_COMMAND,
  2239. BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
  2240. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  2241. udelay(5);
  2242. val = REG_RD(bp, BNX2_NVM_COMMAND);
  2243. if (val & BNX2_NVM_COMMAND_DONE)
  2244. break;
  2245. }
  2246. if (j >= NVRAM_TIMEOUT_COUNT)
  2247. return -EBUSY;
  2248. }
  2249. return 0;
  2250. }
  2251. static void
  2252. bnx2_disable_nvram_write(struct bnx2 *bp)
  2253. {
  2254. u32 val;
  2255. val = REG_RD(bp, BNX2_MISC_CFG);
  2256. REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
  2257. }
  2258. static void
  2259. bnx2_enable_nvram_access(struct bnx2 *bp)
  2260. {
  2261. u32 val;
  2262. val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
  2263. /* Enable both bits, even on read. */
  2264. REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
  2265. val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
  2266. }
  2267. static void
  2268. bnx2_disable_nvram_access(struct bnx2 *bp)
  2269. {
  2270. u32 val;
  2271. val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
  2272. /* Disable both bits, even after read. */
  2273. REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
  2274. val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
  2275. BNX2_NVM_ACCESS_ENABLE_WR_EN));
  2276. }
  2277. static int
  2278. bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
  2279. {
  2280. u32 cmd;
  2281. int j;
  2282. if (bp->flash_info->buffered)
  2283. /* Buffered flash, no erase needed */
  2284. return 0;
  2285. /* Build an erase command */
  2286. cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
  2287. BNX2_NVM_COMMAND_DOIT;
  2288. /* Need to clear DONE bit separately. */
  2289. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  2290. /* Address of the NVRAM to read from. */
  2291. REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  2292. /* Issue an erase command. */
  2293. REG_WR(bp, BNX2_NVM_COMMAND, cmd);
  2294. /* Wait for completion. */
  2295. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  2296. u32 val;
  2297. udelay(5);
  2298. val = REG_RD(bp, BNX2_NVM_COMMAND);
  2299. if (val & BNX2_NVM_COMMAND_DONE)
  2300. break;
  2301. }
  2302. if (j >= NVRAM_TIMEOUT_COUNT)
  2303. return -EBUSY;
  2304. return 0;
  2305. }
  2306. static int
  2307. bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
  2308. {
  2309. u32 cmd;
  2310. int j;
  2311. /* Build the command word. */
  2312. cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
  2313. /* Calculate an offset of a buffered flash. */
  2314. if (bp->flash_info->buffered) {
  2315. offset = ((offset / bp->flash_info->page_size) <<
  2316. bp->flash_info->page_bits) +
  2317. (offset % bp->flash_info->page_size);
  2318. }
  2319. /* Need to clear DONE bit separately. */
  2320. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  2321. /* Address of the NVRAM to read from. */
  2322. REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  2323. /* Issue a read command. */
  2324. REG_WR(bp, BNX2_NVM_COMMAND, cmd);
  2325. /* Wait for completion. */
  2326. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  2327. u32 val;
  2328. udelay(5);
  2329. val = REG_RD(bp, BNX2_NVM_COMMAND);
  2330. if (val & BNX2_NVM_COMMAND_DONE) {
  2331. val = REG_RD(bp, BNX2_NVM_READ);
  2332. val = be32_to_cpu(val);
  2333. memcpy(ret_val, &val, 4);
  2334. break;
  2335. }
  2336. }
  2337. if (j >= NVRAM_TIMEOUT_COUNT)
  2338. return -EBUSY;
  2339. return 0;
  2340. }
  2341. static int
  2342. bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
  2343. {
  2344. u32 cmd, val32;
  2345. int j;
  2346. /* Build the command word. */
  2347. cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
  2348. /* Calculate an offset of a buffered flash. */
  2349. if (bp->flash_info->buffered) {
  2350. offset = ((offset / bp->flash_info->page_size) <<
  2351. bp->flash_info->page_bits) +
  2352. (offset % bp->flash_info->page_size);
  2353. }
  2354. /* Need to clear DONE bit separately. */
  2355. REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
  2356. memcpy(&val32, val, 4);
  2357. val32 = cpu_to_be32(val32);
  2358. /* Write the data. */
  2359. REG_WR(bp, BNX2_NVM_WRITE, val32);
  2360. /* Address of the NVRAM to write to. */
  2361. REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
  2362. /* Issue the write command. */
  2363. REG_WR(bp, BNX2_NVM_COMMAND, cmd);
  2364. /* Wait for completion. */
  2365. for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
  2366. udelay(5);
  2367. if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
  2368. break;
  2369. }
  2370. if (j >= NVRAM_TIMEOUT_COUNT)
  2371. return -EBUSY;
  2372. return 0;
  2373. }
  2374. static int
  2375. bnx2_init_nvram(struct bnx2 *bp)
  2376. {
  2377. u32 val;
  2378. int j, entry_count, rc;
  2379. struct flash_spec *flash;
  2380. /* Determine the selected interface. */
  2381. val = REG_RD(bp, BNX2_NVM_CFG1);
  2382. entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
  2383. rc = 0;
  2384. if (val & 0x40000000) {
  2385. /* Flash interface has been reconfigured */
  2386. for (j = 0, flash = &flash_table[0]; j < entry_count;
  2387. j++, flash++) {
  2388. if ((val & FLASH_BACKUP_STRAP_MASK) ==
  2389. (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
  2390. bp->flash_info = flash;
  2391. break;
  2392. }
  2393. }
  2394. }
  2395. else {
  2396. u32 mask;
  2397. /* Not yet been reconfigured */
  2398. if (val & (1 << 23))
  2399. mask = FLASH_BACKUP_STRAP_MASK;
  2400. else
  2401. mask = FLASH_STRAP_MASK;
  2402. for (j = 0, flash = &flash_table[0]; j < entry_count;
  2403. j++, flash++) {
  2404. if ((val & mask) == (flash->strapping & mask)) {
  2405. bp->flash_info = flash;
  2406. /* Request access to the flash interface. */
  2407. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  2408. return rc;
  2409. /* Enable access to flash interface */
  2410. bnx2_enable_nvram_access(bp);
  2411. /* Reconfigure the flash interface */
  2412. REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
  2413. REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
  2414. REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
  2415. REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
  2416. /* Disable access to flash interface */
  2417. bnx2_disable_nvram_access(bp);
  2418. bnx2_release_nvram_lock(bp);
  2419. break;
  2420. }
  2421. }
  2422. } /* if (val & 0x40000000) */
  2423. if (j == entry_count) {
  2424. bp->flash_info = NULL;
  2425. printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
  2426. return -ENODEV;
  2427. }
  2428. val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
  2429. val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
  2430. if (val)
  2431. bp->flash_size = val;
  2432. else
  2433. bp->flash_size = bp->flash_info->total_size;
  2434. return rc;
  2435. }
  2436. static int
  2437. bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
  2438. int buf_size)
  2439. {
  2440. int rc = 0;
  2441. u32 cmd_flags, offset32, len32, extra;
  2442. if (buf_size == 0)
  2443. return 0;
  2444. /* Request access to the flash interface. */
  2445. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  2446. return rc;
  2447. /* Enable access to flash interface */
  2448. bnx2_enable_nvram_access(bp);
  2449. len32 = buf_size;
  2450. offset32 = offset;
  2451. extra = 0;
  2452. cmd_flags = 0;
  2453. if (offset32 & 3) {
  2454. u8 buf[4];
  2455. u32 pre_len;
  2456. offset32 &= ~3;
  2457. pre_len = 4 - (offset & 3);
  2458. if (pre_len >= len32) {
  2459. pre_len = len32;
  2460. cmd_flags = BNX2_NVM_COMMAND_FIRST |
  2461. BNX2_NVM_COMMAND_LAST;
  2462. }
  2463. else {
  2464. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  2465. }
  2466. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  2467. if (rc)
  2468. return rc;
  2469. memcpy(ret_buf, buf + (offset & 3), pre_len);
  2470. offset32 += 4;
  2471. ret_buf += pre_len;
  2472. len32 -= pre_len;
  2473. }
  2474. if (len32 & 3) {
  2475. extra = 4 - (len32 & 3);
  2476. len32 = (len32 + 4) & ~3;
  2477. }
  2478. if (len32 == 4) {
  2479. u8 buf[4];
  2480. if (cmd_flags)
  2481. cmd_flags = BNX2_NVM_COMMAND_LAST;
  2482. else
  2483. cmd_flags = BNX2_NVM_COMMAND_FIRST |
  2484. BNX2_NVM_COMMAND_LAST;
  2485. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  2486. memcpy(ret_buf, buf, 4 - extra);
  2487. }
  2488. else if (len32 > 0) {
  2489. u8 buf[4];
  2490. /* Read the first word. */
  2491. if (cmd_flags)
  2492. cmd_flags = 0;
  2493. else
  2494. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  2495. rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
  2496. /* Advance to the next dword. */
  2497. offset32 += 4;
  2498. ret_buf += 4;
  2499. len32 -= 4;
  2500. while (len32 > 4 && rc == 0) {
  2501. rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
  2502. /* Advance to the next dword. */
  2503. offset32 += 4;
  2504. ret_buf += 4;
  2505. len32 -= 4;
  2506. }
  2507. if (rc)
  2508. return rc;
  2509. cmd_flags = BNX2_NVM_COMMAND_LAST;
  2510. rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
  2511. memcpy(ret_buf, buf, 4 - extra);
  2512. }
  2513. /* Disable access to flash interface */
  2514. bnx2_disable_nvram_access(bp);
  2515. bnx2_release_nvram_lock(bp);
  2516. return rc;
  2517. }
  2518. static int
  2519. bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
  2520. int buf_size)
  2521. {
  2522. u32 written, offset32, len32;
  2523. u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
  2524. int rc = 0;
  2525. int align_start, align_end;
  2526. buf = data_buf;
  2527. offset32 = offset;
  2528. len32 = buf_size;
  2529. align_start = align_end = 0;
  2530. if ((align_start = (offset32 & 3))) {
  2531. offset32 &= ~3;
  2532. len32 += align_start;
  2533. if (len32 < 4)
  2534. len32 = 4;
  2535. if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
  2536. return rc;
  2537. }
  2538. if (len32 & 3) {
  2539. align_end = 4 - (len32 & 3);
  2540. len32 += align_end;
  2541. if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
  2542. return rc;
  2543. }
  2544. if (align_start || align_end) {
  2545. align_buf = kmalloc(len32, GFP_KERNEL);
  2546. if (align_buf == NULL)
  2547. return -ENOMEM;
  2548. if (align_start) {
  2549. memcpy(align_buf, start, 4);
  2550. }
  2551. if (align_end) {
  2552. memcpy(align_buf + len32 - 4, end, 4);
  2553. }
  2554. memcpy(align_buf + align_start, data_buf, buf_size);
  2555. buf = align_buf;
  2556. }
  2557. if (bp->flash_info->buffered == 0) {
  2558. flash_buffer = kmalloc(264, GFP_KERNEL);
  2559. if (flash_buffer == NULL) {
  2560. rc = -ENOMEM;
  2561. goto nvram_write_end;
  2562. }
  2563. }
  2564. written = 0;
  2565. while ((written < len32) && (rc == 0)) {
  2566. u32 page_start, page_end, data_start, data_end;
  2567. u32 addr, cmd_flags;
  2568. int i;
  2569. /* Find the page_start addr */
  2570. page_start = offset32 + written;
  2571. page_start -= (page_start % bp->flash_info->page_size);
  2572. /* Find the page_end addr */
  2573. page_end = page_start + bp->flash_info->page_size;
  2574. /* Find the data_start addr */
  2575. data_start = (written == 0) ? offset32 : page_start;
  2576. /* Find the data_end addr */
  2577. data_end = (page_end > offset32 + len32) ?
  2578. (offset32 + len32) : page_end;
  2579. /* Request access to the flash interface. */
  2580. if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
  2581. goto nvram_write_end;
  2582. /* Enable access to flash interface */
  2583. bnx2_enable_nvram_access(bp);
  2584. cmd_flags = BNX2_NVM_COMMAND_FIRST;
  2585. if (bp->flash_info->buffered == 0) {
  2586. int j;
  2587. /* Read the whole page into the buffer
  2588. * (non-buffer flash only) */
  2589. for (j = 0; j < bp->flash_info->page_size; j += 4) {
  2590. if (j == (bp->flash_info->page_size - 4)) {
  2591. cmd_flags |= BNX2_NVM_COMMAND_LAST;
  2592. }
  2593. rc = bnx2_nvram_read_dword(bp,
  2594. page_start + j,
  2595. &flash_buffer[j],
  2596. cmd_flags);
  2597. if (rc)
  2598. goto nvram_write_end;
  2599. cmd_flags = 0;
  2600. }
  2601. }
  2602. /* Enable writes to flash interface (unlock write-protect) */
  2603. if ((rc = bnx2_enable_nvram_write(bp)) != 0)
  2604. goto nvram_write_end;
  2605. /* Loop to write back the buffer data from page_start to
  2606. * data_start */
  2607. i = 0;
  2608. if (bp->flash_info->buffered == 0) {
  2609. /* Erase the page */
  2610. if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
  2611. goto nvram_write_end;
  2612. /* Re-enable the write again for the actual write */
  2613. bnx2_enable_nvram_write(bp);
  2614. for (addr = page_start; addr < data_start;
  2615. addr += 4, i += 4) {
  2616. rc = bnx2_nvram_write_dword(bp, addr,
  2617. &flash_buffer[i], cmd_flags);
  2618. if (rc != 0)
  2619. goto nvram_write_end;
  2620. cmd_flags = 0;
  2621. }
  2622. }
  2623. /* Loop to write the new data from data_start to data_end */
  2624. for (addr = data_start; addr < data_end; addr += 4, i += 4) {
  2625. if ((addr == page_end - 4) ||
  2626. ((bp->flash_info->buffered) &&
  2627. (addr == data_end - 4))) {
  2628. cmd_flags |= BNX2_NVM_COMMAND_LAST;
  2629. }
  2630. rc = bnx2_nvram_write_dword(bp, addr, buf,
  2631. cmd_flags);
  2632. if (rc != 0)
  2633. goto nvram_write_end;
  2634. cmd_flags = 0;
  2635. buf += 4;
  2636. }
  2637. /* Loop to write back the buffer data from data_end
  2638. * to page_end */
  2639. if (bp->flash_info->buffered == 0) {
  2640. for (addr = data_end; addr < page_end;
  2641. addr += 4, i += 4) {
  2642. if (addr == page_end-4) {
  2643. cmd_flags = BNX2_NVM_COMMAND_LAST;
  2644. }
  2645. rc = bnx2_nvram_write_dword(bp, addr,
  2646. &flash_buffer[i], cmd_flags);
  2647. if (rc != 0)
  2648. goto nvram_write_end;
  2649. cmd_flags = 0;
  2650. }
  2651. }
  2652. /* Disable writes to flash interface (lock write-protect) */
  2653. bnx2_disable_nvram_write(bp);
  2654. /* Disable access to flash interface */
  2655. bnx2_disable_nvram_access(bp);
  2656. bnx2_release_nvram_lock(bp);
  2657. /* Increment written */
  2658. written += data_end - data_start;
  2659. }
  2660. nvram_write_end:
  2661. kfree(flash_buffer);
  2662. kfree(align_buf);
  2663. return rc;
  2664. }
  2665. static int
  2666. bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
  2667. {
  2668. u32 val;
  2669. int i, rc = 0;
  2670. /* Wait for the current PCI transaction to complete before
  2671. * issuing a reset. */
  2672. REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
  2673. BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
  2674. BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
  2675. BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
  2676. BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
  2677. val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
  2678. udelay(5);
  2679. /* Wait for the firmware to tell us it is ok to issue a reset. */
  2680. bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
  2681. /* Deposit a driver reset signature so the firmware knows that
  2682. * this is a soft reset. */
  2683. REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
  2684. BNX2_DRV_RESET_SIGNATURE_MAGIC);
  2685. /* Do a dummy read to force the chip to complete all current transaction
  2686. * before we issue a reset. */
  2687. val = REG_RD(bp, BNX2_MISC_ID);
  2688. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  2689. REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
  2690. REG_RD(bp, BNX2_MISC_COMMAND);
  2691. udelay(5);
  2692. val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  2693. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
  2694. pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
  2695. } else {
  2696. val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  2697. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  2698. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
  2699. /* Chip reset. */
  2700. REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
  2701. if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
  2702. (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
  2703. current->state = TASK_UNINTERRUPTIBLE;
  2704. schedule_timeout(HZ / 50);
  2705. }
  2706. /* Reset takes approximate 30 usec */
  2707. for (i = 0; i < 10; i++) {
  2708. val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
  2709. if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  2710. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
  2711. break;
  2712. udelay(10);
  2713. }
  2714. if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  2715. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
  2716. printk(KERN_ERR PFX "Chip reset did not complete\n");
  2717. return -EBUSY;
  2718. }
  2719. }
  2720. /* Make sure byte swapping is properly configured. */
  2721. val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
  2722. if (val != 0x01020304) {
  2723. printk(KERN_ERR PFX "Chip not in correct endian mode\n");
  2724. return -ENODEV;
  2725. }
  2726. /* Wait for the firmware to finish its initialization. */
  2727. rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
  2728. if (rc)
  2729. return rc;
  2730. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  2731. /* Adjust the voltage regular to two steps lower. The default
  2732. * of this register is 0x0000000e. */
  2733. REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
  2734. /* Remove bad rbuf memory from the free pool. */
  2735. rc = bnx2_alloc_bad_rbuf(bp);
  2736. }
  2737. return rc;
  2738. }
  2739. static int
  2740. bnx2_init_chip(struct bnx2 *bp)
  2741. {
  2742. u32 val;
  2743. int rc;
  2744. /* Make sure the interrupt is not active. */
  2745. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2746. val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
  2747. BNX2_DMA_CONFIG_DATA_WORD_SWAP |
  2748. #ifdef __BIG_ENDIAN
  2749. BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
  2750. #endif
  2751. BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
  2752. DMA_READ_CHANS << 12 |
  2753. DMA_WRITE_CHANS << 16;
  2754. val |= (0x2 << 20) | (1 << 11);
  2755. if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
  2756. val |= (1 << 23);
  2757. if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
  2758. (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
  2759. val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
  2760. REG_WR(bp, BNX2_DMA_CONFIG, val);
  2761. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  2762. val = REG_RD(bp, BNX2_TDMA_CONFIG);
  2763. val |= BNX2_TDMA_CONFIG_ONE_DMA;
  2764. REG_WR(bp, BNX2_TDMA_CONFIG, val);
  2765. }
  2766. if (bp->flags & PCIX_FLAG) {
  2767. u16 val16;
  2768. pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
  2769. &val16);
  2770. pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
  2771. val16 & ~PCI_X_CMD_ERO);
  2772. }
  2773. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  2774. BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
  2775. BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
  2776. BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
  2777. /* Initialize context mapping and zero out the quick contexts. The
  2778. * context block must have already been enabled. */
  2779. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  2780. bnx2_init_5709_context(bp);
  2781. else
  2782. bnx2_init_context(bp);
  2783. if ((rc = bnx2_init_cpus(bp)) != 0)
  2784. return rc;
  2785. bnx2_init_nvram(bp);
  2786. bnx2_set_mac_addr(bp);
  2787. val = REG_RD(bp, BNX2_MQ_CONFIG);
  2788. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  2789. val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
  2790. if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
  2791. val |= BNX2_MQ_CONFIG_HALT_DIS;
  2792. REG_WR(bp, BNX2_MQ_CONFIG, val);
  2793. val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
  2794. REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
  2795. REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
  2796. val = (BCM_PAGE_BITS - 8) << 24;
  2797. REG_WR(bp, BNX2_RV2P_CONFIG, val);
  2798. /* Configure page size. */
  2799. val = REG_RD(bp, BNX2_TBDR_CONFIG);
  2800. val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
  2801. val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
  2802. REG_WR(bp, BNX2_TBDR_CONFIG, val);
  2803. val = bp->mac_addr[0] +
  2804. (bp->mac_addr[1] << 8) +
  2805. (bp->mac_addr[2] << 16) +
  2806. bp->mac_addr[3] +
  2807. (bp->mac_addr[4] << 8) +
  2808. (bp->mac_addr[5] << 16);
  2809. REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
  2810. /* Program the MTU. Also include 4 bytes for CRC32. */
  2811. val = bp->dev->mtu + ETH_HLEN + 4;
  2812. if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
  2813. val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
  2814. REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
  2815. bp->last_status_idx = 0;
  2816. bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
  2817. /* Set up how to generate a link change interrupt. */
  2818. REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
  2819. REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
  2820. (u64) bp->status_blk_mapping & 0xffffffff);
  2821. REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
  2822. REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
  2823. (u64) bp->stats_blk_mapping & 0xffffffff);
  2824. REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
  2825. (u64) bp->stats_blk_mapping >> 32);
  2826. REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
  2827. (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
  2828. REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
  2829. (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
  2830. REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
  2831. (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
  2832. REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
  2833. REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
  2834. REG_WR(bp, BNX2_HC_COM_TICKS,
  2835. (bp->com_ticks_int << 16) | bp->com_ticks);
  2836. REG_WR(bp, BNX2_HC_CMD_TICKS,
  2837. (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
  2838. REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
  2839. REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
  2840. if (CHIP_ID(bp) == CHIP_ID_5706_A1)
  2841. REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
  2842. else {
  2843. REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
  2844. BNX2_HC_CONFIG_TX_TMR_MODE |
  2845. BNX2_HC_CONFIG_COLLECT_STATS);
  2846. }
  2847. /* Clear internal stats counters. */
  2848. REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
  2849. REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
  2850. if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
  2851. BNX2_PORT_FEATURE_ASF_ENABLED)
  2852. bp->flags |= ASF_ENABLE_FLAG;
  2853. /* Initialize the receive filter. */
  2854. bnx2_set_rx_mode(bp->dev);
  2855. rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
  2856. 0);
  2857. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
  2858. REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
  2859. udelay(20);
  2860. bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
  2861. return rc;
  2862. }
  2863. static void
  2864. bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
  2865. {
  2866. u32 val, offset0, offset1, offset2, offset3;
  2867. if (CHIP_NUM(bp) == CHIP_NUM_5709) {
  2868. offset0 = BNX2_L2CTX_TYPE_XI;
  2869. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  2870. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  2871. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  2872. } else {
  2873. offset0 = BNX2_L2CTX_TYPE;
  2874. offset1 = BNX2_L2CTX_CMD_TYPE;
  2875. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  2876. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  2877. }
  2878. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  2879. CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
  2880. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  2881. CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
  2882. val = (u64) bp->tx_desc_mapping >> 32;
  2883. CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
  2884. val = (u64) bp->tx_desc_mapping & 0xffffffff;
  2885. CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
  2886. }
  2887. static void
  2888. bnx2_init_tx_ring(struct bnx2 *bp)
  2889. {
  2890. struct tx_bd *txbd;
  2891. u32 cid;
  2892. bp->tx_wake_thresh = bp->tx_ring_size / 2;
  2893. txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
  2894. txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
  2895. txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
  2896. bp->tx_prod = 0;
  2897. bp->tx_cons = 0;
  2898. bp->hw_tx_cons = 0;
  2899. bp->tx_prod_bseq = 0;
  2900. cid = TX_CID;
  2901. bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
  2902. bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
  2903. bnx2_init_tx_context(bp, cid);
  2904. }
  2905. static void
  2906. bnx2_init_rx_ring(struct bnx2 *bp)
  2907. {
  2908. struct rx_bd *rxbd;
  2909. int i;
  2910. u16 prod, ring_prod;
  2911. u32 val;
  2912. /* 8 for CRC and VLAN */
  2913. bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
  2914. /* hw alignment */
  2915. bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
  2916. ring_prod = prod = bp->rx_prod = 0;
  2917. bp->rx_cons = 0;
  2918. bp->hw_rx_cons = 0;
  2919. bp->rx_prod_bseq = 0;
  2920. for (i = 0; i < bp->rx_max_ring; i++) {
  2921. int j;
  2922. rxbd = &bp->rx_desc_ring[i][0];
  2923. for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
  2924. rxbd->rx_bd_len = bp->rx_buf_use_size;
  2925. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  2926. }
  2927. if (i == (bp->rx_max_ring - 1))
  2928. j = 0;
  2929. else
  2930. j = i + 1;
  2931. rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
  2932. rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
  2933. 0xffffffff;
  2934. }
  2935. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
  2936. val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
  2937. val |= 0x02 << 8;
  2938. CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
  2939. val = (u64) bp->rx_desc_mapping[0] >> 32;
  2940. CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
  2941. val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
  2942. CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
  2943. for (i = 0; i < bp->rx_ring_size; i++) {
  2944. if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
  2945. break;
  2946. }
  2947. prod = NEXT_RX_BD(prod);
  2948. ring_prod = RX_RING_IDX(prod);
  2949. }
  2950. bp->rx_prod = prod;
  2951. REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
  2952. REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
  2953. }
  2954. static void
  2955. bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
  2956. {
  2957. u32 num_rings, max;
  2958. bp->rx_ring_size = size;
  2959. num_rings = 1;
  2960. while (size > MAX_RX_DESC_CNT) {
  2961. size -= MAX_RX_DESC_CNT;
  2962. num_rings++;
  2963. }
  2964. /* round to next power of 2 */
  2965. max = MAX_RX_RINGS;
  2966. while ((max & num_rings) == 0)
  2967. max >>= 1;
  2968. if (num_rings != max)
  2969. max <<= 1;
  2970. bp->rx_max_ring = max;
  2971. bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
  2972. }
  2973. static void
  2974. bnx2_free_tx_skbs(struct bnx2 *bp)
  2975. {
  2976. int i;
  2977. if (bp->tx_buf_ring == NULL)
  2978. return;
  2979. for (i = 0; i < TX_DESC_CNT; ) {
  2980. struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
  2981. struct sk_buff *skb = tx_buf->skb;
  2982. int j, last;
  2983. if (skb == NULL) {
  2984. i++;
  2985. continue;
  2986. }
  2987. pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
  2988. skb_headlen(skb), PCI_DMA_TODEVICE);
  2989. tx_buf->skb = NULL;
  2990. last = skb_shinfo(skb)->nr_frags;
  2991. for (j = 0; j < last; j++) {
  2992. tx_buf = &bp->tx_buf_ring[i + j + 1];
  2993. pci_unmap_page(bp->pdev,
  2994. pci_unmap_addr(tx_buf, mapping),
  2995. skb_shinfo(skb)->frags[j].size,
  2996. PCI_DMA_TODEVICE);
  2997. }
  2998. dev_kfree_skb(skb);
  2999. i += j + 1;
  3000. }
  3001. }
  3002. static void
  3003. bnx2_free_rx_skbs(struct bnx2 *bp)
  3004. {
  3005. int i;
  3006. if (bp->rx_buf_ring == NULL)
  3007. return;
  3008. for (i = 0; i < bp->rx_max_ring_idx; i++) {
  3009. struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
  3010. struct sk_buff *skb = rx_buf->skb;
  3011. if (skb == NULL)
  3012. continue;
  3013. pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
  3014. bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
  3015. rx_buf->skb = NULL;
  3016. dev_kfree_skb(skb);
  3017. }
  3018. }
  3019. static void
  3020. bnx2_free_skbs(struct bnx2 *bp)
  3021. {
  3022. bnx2_free_tx_skbs(bp);
  3023. bnx2_free_rx_skbs(bp);
  3024. }
  3025. static int
  3026. bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
  3027. {
  3028. int rc;
  3029. rc = bnx2_reset_chip(bp, reset_code);
  3030. bnx2_free_skbs(bp);
  3031. if (rc)
  3032. return rc;
  3033. if ((rc = bnx2_init_chip(bp)) != 0)
  3034. return rc;
  3035. bnx2_init_tx_ring(bp);
  3036. bnx2_init_rx_ring(bp);
  3037. return 0;
  3038. }
  3039. static int
  3040. bnx2_init_nic(struct bnx2 *bp)
  3041. {
  3042. int rc;
  3043. if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
  3044. return rc;
  3045. spin_lock_bh(&bp->phy_lock);
  3046. bnx2_init_phy(bp);
  3047. spin_unlock_bh(&bp->phy_lock);
  3048. bnx2_set_link(bp);
  3049. return 0;
  3050. }
  3051. static int
  3052. bnx2_test_registers(struct bnx2 *bp)
  3053. {
  3054. int ret;
  3055. int i;
  3056. static const struct {
  3057. u16 offset;
  3058. u16 flags;
  3059. u32 rw_mask;
  3060. u32 ro_mask;
  3061. } reg_tbl[] = {
  3062. { 0x006c, 0, 0x00000000, 0x0000003f },
  3063. { 0x0090, 0, 0xffffffff, 0x00000000 },
  3064. { 0x0094, 0, 0x00000000, 0x00000000 },
  3065. { 0x0404, 0, 0x00003f00, 0x00000000 },
  3066. { 0x0418, 0, 0x00000000, 0xffffffff },
  3067. { 0x041c, 0, 0x00000000, 0xffffffff },
  3068. { 0x0420, 0, 0x00000000, 0x80ffffff },
  3069. { 0x0424, 0, 0x00000000, 0x00000000 },
  3070. { 0x0428, 0, 0x00000000, 0x00000001 },
  3071. { 0x0450, 0, 0x00000000, 0x0000ffff },
  3072. { 0x0454, 0, 0x00000000, 0xffffffff },
  3073. { 0x0458, 0, 0x00000000, 0xffffffff },
  3074. { 0x0808, 0, 0x00000000, 0xffffffff },
  3075. { 0x0854, 0, 0x00000000, 0xffffffff },
  3076. { 0x0868, 0, 0x00000000, 0x77777777 },
  3077. { 0x086c, 0, 0x00000000, 0x77777777 },
  3078. { 0x0870, 0, 0x00000000, 0x77777777 },
  3079. { 0x0874, 0, 0x00000000, 0x77777777 },
  3080. { 0x0c00, 0, 0x00000000, 0x00000001 },
  3081. { 0x0c04, 0, 0x00000000, 0x03ff0001 },
  3082. { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
  3083. { 0x1000, 0, 0x00000000, 0x00000001 },
  3084. { 0x1004, 0, 0x00000000, 0x000f0001 },
  3085. { 0x1408, 0, 0x01c00800, 0x00000000 },
  3086. { 0x149c, 0, 0x8000ffff, 0x00000000 },
  3087. { 0x14a8, 0, 0x00000000, 0x000001ff },
  3088. { 0x14ac, 0, 0x0fffffff, 0x10000000 },
  3089. { 0x14b0, 0, 0x00000002, 0x00000001 },
  3090. { 0x14b8, 0, 0x00000000, 0x00000000 },
  3091. { 0x14c0, 0, 0x00000000, 0x00000009 },
  3092. { 0x14c4, 0, 0x00003fff, 0x00000000 },
  3093. { 0x14cc, 0, 0x00000000, 0x00000001 },
  3094. { 0x14d0, 0, 0xffffffff, 0x00000000 },
  3095. { 0x1800, 0, 0x00000000, 0x00000001 },
  3096. { 0x1804, 0, 0x00000000, 0x00000003 },
  3097. { 0x2800, 0, 0x00000000, 0x00000001 },
  3098. { 0x2804, 0, 0x00000000, 0x00003f01 },
  3099. { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
  3100. { 0x2810, 0, 0xffff0000, 0x00000000 },
  3101. { 0x2814, 0, 0xffff0000, 0x00000000 },
  3102. { 0x2818, 0, 0xffff0000, 0x00000000 },
  3103. { 0x281c, 0, 0xffff0000, 0x00000000 },
  3104. { 0x2834, 0, 0xffffffff, 0x00000000 },
  3105. { 0x2840, 0, 0x00000000, 0xffffffff },
  3106. { 0x2844, 0, 0x00000000, 0xffffffff },
  3107. { 0x2848, 0, 0xffffffff, 0x00000000 },
  3108. { 0x284c, 0, 0xf800f800, 0x07ff07ff },
  3109. { 0x2c00, 0, 0x00000000, 0x00000011 },
  3110. { 0x2c04, 0, 0x00000000, 0x00030007 },
  3111. { 0x3c00, 0, 0x00000000, 0x00000001 },
  3112. { 0x3c04, 0, 0x00000000, 0x00070000 },
  3113. { 0x3c08, 0, 0x00007f71, 0x07f00000 },
  3114. { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
  3115. { 0x3c10, 0, 0xffffffff, 0x00000000 },
  3116. { 0x3c14, 0, 0x00000000, 0xffffffff },
  3117. { 0x3c18, 0, 0x00000000, 0xffffffff },
  3118. { 0x3c1c, 0, 0xfffff000, 0x00000000 },
  3119. { 0x3c20, 0, 0xffffff00, 0x00000000 },
  3120. { 0x5004, 0, 0x00000000, 0x0000007f },
  3121. { 0x5008, 0, 0x0f0007ff, 0x00000000 },
  3122. { 0x500c, 0, 0xf800f800, 0x07ff07ff },
  3123. { 0x5c00, 0, 0x00000000, 0x00000001 },
  3124. { 0x5c04, 0, 0x00000000, 0x0003000f },
  3125. { 0x5c08, 0, 0x00000003, 0x00000000 },
  3126. { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
  3127. { 0x5c10, 0, 0x00000000, 0xffffffff },
  3128. { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
  3129. { 0x5c84, 0, 0x00000000, 0x0000f333 },
  3130. { 0x5c88, 0, 0x00000000, 0x00077373 },
  3131. { 0x5c8c, 0, 0x00000000, 0x0007f737 },
  3132. { 0x6808, 0, 0x0000ff7f, 0x00000000 },
  3133. { 0x680c, 0, 0xffffffff, 0x00000000 },
  3134. { 0x6810, 0, 0xffffffff, 0x00000000 },
  3135. { 0x6814, 0, 0xffffffff, 0x00000000 },
  3136. { 0x6818, 0, 0xffffffff, 0x00000000 },
  3137. { 0x681c, 0, 0xffffffff, 0x00000000 },
  3138. { 0x6820, 0, 0x00ff00ff, 0x00000000 },
  3139. { 0x6824, 0, 0x00ff00ff, 0x00000000 },
  3140. { 0x6828, 0, 0x00ff00ff, 0x00000000 },
  3141. { 0x682c, 0, 0x03ff03ff, 0x00000000 },
  3142. { 0x6830, 0, 0x03ff03ff, 0x00000000 },
  3143. { 0x6834, 0, 0x03ff03ff, 0x00000000 },
  3144. { 0x6838, 0, 0x03ff03ff, 0x00000000 },
  3145. { 0x683c, 0, 0x0000ffff, 0x00000000 },
  3146. { 0x6840, 0, 0x00000ff0, 0x00000000 },
  3147. { 0x6844, 0, 0x00ffff00, 0x00000000 },
  3148. { 0x684c, 0, 0xffffffff, 0x00000000 },
  3149. { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
  3150. { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
  3151. { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
  3152. { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
  3153. { 0x6908, 0, 0x00000000, 0x0001ff0f },
  3154. { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
  3155. { 0xffff, 0, 0x00000000, 0x00000000 },
  3156. };
  3157. ret = 0;
  3158. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  3159. u32 offset, rw_mask, ro_mask, save_val, val;
  3160. offset = (u32) reg_tbl[i].offset;
  3161. rw_mask = reg_tbl[i].rw_mask;
  3162. ro_mask = reg_tbl[i].ro_mask;
  3163. save_val = readl(bp->regview + offset);
  3164. writel(0, bp->regview + offset);
  3165. val = readl(bp->regview + offset);
  3166. if ((val & rw_mask) != 0) {
  3167. goto reg_test_err;
  3168. }
  3169. if ((val & ro_mask) != (save_val & ro_mask)) {
  3170. goto reg_test_err;
  3171. }
  3172. writel(0xffffffff, bp->regview + offset);
  3173. val = readl(bp->regview + offset);
  3174. if ((val & rw_mask) != rw_mask) {
  3175. goto reg_test_err;
  3176. }
  3177. if ((val & ro_mask) != (save_val & ro_mask)) {
  3178. goto reg_test_err;
  3179. }
  3180. writel(save_val, bp->regview + offset);
  3181. continue;
  3182. reg_test_err:
  3183. writel(save_val, bp->regview + offset);
  3184. ret = -ENODEV;
  3185. break;
  3186. }
  3187. return ret;
  3188. }
  3189. static int
  3190. bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
  3191. {
  3192. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
  3193. 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
  3194. int i;
  3195. for (i = 0; i < sizeof(test_pattern) / 4; i++) {
  3196. u32 offset;
  3197. for (offset = 0; offset < size; offset += 4) {
  3198. REG_WR_IND(bp, start + offset, test_pattern[i]);
  3199. if (REG_RD_IND(bp, start + offset) !=
  3200. test_pattern[i]) {
  3201. return -ENODEV;
  3202. }
  3203. }
  3204. }
  3205. return 0;
  3206. }
  3207. static int
  3208. bnx2_test_memory(struct bnx2 *bp)
  3209. {
  3210. int ret = 0;
  3211. int i;
  3212. static const struct {
  3213. u32 offset;
  3214. u32 len;
  3215. } mem_tbl[] = {
  3216. { 0x60000, 0x4000 },
  3217. { 0xa0000, 0x3000 },
  3218. { 0xe0000, 0x4000 },
  3219. { 0x120000, 0x4000 },
  3220. { 0x1a0000, 0x4000 },
  3221. { 0x160000, 0x4000 },
  3222. { 0xffffffff, 0 },
  3223. };
  3224. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  3225. if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
  3226. mem_tbl[i].len)) != 0) {
  3227. return ret;
  3228. }
  3229. }
  3230. return ret;
  3231. }
  3232. #define BNX2_MAC_LOOPBACK 0
  3233. #define BNX2_PHY_LOOPBACK 1
  3234. static int
  3235. bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
  3236. {
  3237. unsigned int pkt_size, num_pkts, i;
  3238. struct sk_buff *skb, *rx_skb;
  3239. unsigned char *packet;
  3240. u16 rx_start_idx, rx_idx;
  3241. dma_addr_t map;
  3242. struct tx_bd *txbd;
  3243. struct sw_bd *rx_buf;
  3244. struct l2_fhdr *rx_hdr;
  3245. int ret = -ENODEV;
  3246. if (loopback_mode == BNX2_MAC_LOOPBACK) {
  3247. bp->loopback = MAC_LOOPBACK;
  3248. bnx2_set_mac_loopback(bp);
  3249. }
  3250. else if (loopback_mode == BNX2_PHY_LOOPBACK) {
  3251. bp->loopback = PHY_LOOPBACK;
  3252. bnx2_set_phy_loopback(bp);
  3253. }
  3254. else
  3255. return -EINVAL;
  3256. pkt_size = 1514;
  3257. skb = netdev_alloc_skb(bp->dev, pkt_size);
  3258. if (!skb)
  3259. return -ENOMEM;
  3260. packet = skb_put(skb, pkt_size);
  3261. memcpy(packet, bp->dev->dev_addr, 6);
  3262. memset(packet + 6, 0x0, 8);
  3263. for (i = 14; i < pkt_size; i++)
  3264. packet[i] = (unsigned char) (i & 0xff);
  3265. map = pci_map_single(bp->pdev, skb->data, pkt_size,
  3266. PCI_DMA_TODEVICE);
  3267. REG_WR(bp, BNX2_HC_COMMAND,
  3268. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3269. REG_RD(bp, BNX2_HC_COMMAND);
  3270. udelay(5);
  3271. rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
  3272. num_pkts = 0;
  3273. txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
  3274. txbd->tx_bd_haddr_hi = (u64) map >> 32;
  3275. txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
  3276. txbd->tx_bd_mss_nbytes = pkt_size;
  3277. txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
  3278. num_pkts++;
  3279. bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
  3280. bp->tx_prod_bseq += pkt_size;
  3281. REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
  3282. REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
  3283. udelay(100);
  3284. REG_WR(bp, BNX2_HC_COMMAND,
  3285. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3286. REG_RD(bp, BNX2_HC_COMMAND);
  3287. udelay(5);
  3288. pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
  3289. dev_kfree_skb(skb);
  3290. if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
  3291. goto loopback_test_done;
  3292. }
  3293. rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
  3294. if (rx_idx != rx_start_idx + num_pkts) {
  3295. goto loopback_test_done;
  3296. }
  3297. rx_buf = &bp->rx_buf_ring[rx_start_idx];
  3298. rx_skb = rx_buf->skb;
  3299. rx_hdr = (struct l2_fhdr *) rx_skb->data;
  3300. skb_reserve(rx_skb, bp->rx_offset);
  3301. pci_dma_sync_single_for_cpu(bp->pdev,
  3302. pci_unmap_addr(rx_buf, mapping),
  3303. bp->rx_buf_size, PCI_DMA_FROMDEVICE);
  3304. if (rx_hdr->l2_fhdr_status &
  3305. (L2_FHDR_ERRORS_BAD_CRC |
  3306. L2_FHDR_ERRORS_PHY_DECODE |
  3307. L2_FHDR_ERRORS_ALIGNMENT |
  3308. L2_FHDR_ERRORS_TOO_SHORT |
  3309. L2_FHDR_ERRORS_GIANT_FRAME)) {
  3310. goto loopback_test_done;
  3311. }
  3312. if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
  3313. goto loopback_test_done;
  3314. }
  3315. for (i = 14; i < pkt_size; i++) {
  3316. if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
  3317. goto loopback_test_done;
  3318. }
  3319. }
  3320. ret = 0;
  3321. loopback_test_done:
  3322. bp->loopback = 0;
  3323. return ret;
  3324. }
  3325. #define BNX2_MAC_LOOPBACK_FAILED 1
  3326. #define BNX2_PHY_LOOPBACK_FAILED 2
  3327. #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
  3328. BNX2_PHY_LOOPBACK_FAILED)
  3329. static int
  3330. bnx2_test_loopback(struct bnx2 *bp)
  3331. {
  3332. int rc = 0;
  3333. if (!netif_running(bp->dev))
  3334. return BNX2_LOOPBACK_FAILED;
  3335. bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
  3336. spin_lock_bh(&bp->phy_lock);
  3337. bnx2_init_phy(bp);
  3338. spin_unlock_bh(&bp->phy_lock);
  3339. if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
  3340. rc |= BNX2_MAC_LOOPBACK_FAILED;
  3341. if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
  3342. rc |= BNX2_PHY_LOOPBACK_FAILED;
  3343. return rc;
  3344. }
  3345. #define NVRAM_SIZE 0x200
  3346. #define CRC32_RESIDUAL 0xdebb20e3
  3347. static int
  3348. bnx2_test_nvram(struct bnx2 *bp)
  3349. {
  3350. u32 buf[NVRAM_SIZE / 4];
  3351. u8 *data = (u8 *) buf;
  3352. int rc = 0;
  3353. u32 magic, csum;
  3354. if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
  3355. goto test_nvram_done;
  3356. magic = be32_to_cpu(buf[0]);
  3357. if (magic != 0x669955aa) {
  3358. rc = -ENODEV;
  3359. goto test_nvram_done;
  3360. }
  3361. if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
  3362. goto test_nvram_done;
  3363. csum = ether_crc_le(0x100, data);
  3364. if (csum != CRC32_RESIDUAL) {
  3365. rc = -ENODEV;
  3366. goto test_nvram_done;
  3367. }
  3368. csum = ether_crc_le(0x100, data + 0x100);
  3369. if (csum != CRC32_RESIDUAL) {
  3370. rc = -ENODEV;
  3371. }
  3372. test_nvram_done:
  3373. return rc;
  3374. }
  3375. static int
  3376. bnx2_test_link(struct bnx2 *bp)
  3377. {
  3378. u32 bmsr;
  3379. spin_lock_bh(&bp->phy_lock);
  3380. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  3381. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  3382. spin_unlock_bh(&bp->phy_lock);
  3383. if (bmsr & BMSR_LSTATUS) {
  3384. return 0;
  3385. }
  3386. return -ENODEV;
  3387. }
  3388. static int
  3389. bnx2_test_intr(struct bnx2 *bp)
  3390. {
  3391. int i;
  3392. u16 status_idx;
  3393. if (!netif_running(bp->dev))
  3394. return -ENODEV;
  3395. status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
  3396. /* This register is not touched during run-time. */
  3397. REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
  3398. REG_RD(bp, BNX2_HC_COMMAND);
  3399. for (i = 0; i < 10; i++) {
  3400. if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
  3401. status_idx) {
  3402. break;
  3403. }
  3404. msleep_interruptible(10);
  3405. }
  3406. if (i < 10)
  3407. return 0;
  3408. return -ENODEV;
  3409. }
  3410. static void
  3411. bnx2_5706_serdes_timer(struct bnx2 *bp)
  3412. {
  3413. spin_lock(&bp->phy_lock);
  3414. if (bp->serdes_an_pending)
  3415. bp->serdes_an_pending--;
  3416. else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
  3417. u32 bmcr;
  3418. bp->current_interval = bp->timer_interval;
  3419. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  3420. if (bmcr & BMCR_ANENABLE) {
  3421. u32 phy1, phy2;
  3422. bnx2_write_phy(bp, 0x1c, 0x7c00);
  3423. bnx2_read_phy(bp, 0x1c, &phy1);
  3424. bnx2_write_phy(bp, 0x17, 0x0f01);
  3425. bnx2_read_phy(bp, 0x15, &phy2);
  3426. bnx2_write_phy(bp, 0x17, 0x0f01);
  3427. bnx2_read_phy(bp, 0x15, &phy2);
  3428. if ((phy1 & 0x10) && /* SIGNAL DETECT */
  3429. !(phy2 & 0x20)) { /* no CONFIG */
  3430. bmcr &= ~BMCR_ANENABLE;
  3431. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  3432. bnx2_write_phy(bp, MII_BMCR, bmcr);
  3433. bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
  3434. }
  3435. }
  3436. }
  3437. else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
  3438. (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
  3439. u32 phy2;
  3440. bnx2_write_phy(bp, 0x17, 0x0f01);
  3441. bnx2_read_phy(bp, 0x15, &phy2);
  3442. if (phy2 & 0x20) {
  3443. u32 bmcr;
  3444. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  3445. bmcr |= BMCR_ANENABLE;
  3446. bnx2_write_phy(bp, MII_BMCR, bmcr);
  3447. bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
  3448. }
  3449. } else
  3450. bp->current_interval = bp->timer_interval;
  3451. spin_unlock(&bp->phy_lock);
  3452. }
  3453. static void
  3454. bnx2_5708_serdes_timer(struct bnx2 *bp)
  3455. {
  3456. if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
  3457. bp->serdes_an_pending = 0;
  3458. return;
  3459. }
  3460. spin_lock(&bp->phy_lock);
  3461. if (bp->serdes_an_pending)
  3462. bp->serdes_an_pending--;
  3463. else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
  3464. u32 bmcr;
  3465. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  3466. if (bmcr & BMCR_ANENABLE) {
  3467. bmcr &= ~BMCR_ANENABLE;
  3468. bmcr |= BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500;
  3469. bnx2_write_phy(bp, MII_BMCR, bmcr);
  3470. bp->current_interval = SERDES_FORCED_TIMEOUT;
  3471. } else {
  3472. bmcr &= ~(BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500);
  3473. bmcr |= BMCR_ANENABLE;
  3474. bnx2_write_phy(bp, MII_BMCR, bmcr);
  3475. bp->serdes_an_pending = 2;
  3476. bp->current_interval = bp->timer_interval;
  3477. }
  3478. } else
  3479. bp->current_interval = bp->timer_interval;
  3480. spin_unlock(&bp->phy_lock);
  3481. }
  3482. static void
  3483. bnx2_timer(unsigned long data)
  3484. {
  3485. struct bnx2 *bp = (struct bnx2 *) data;
  3486. u32 msg;
  3487. if (!netif_running(bp->dev))
  3488. return;
  3489. if (atomic_read(&bp->intr_sem) != 0)
  3490. goto bnx2_restart_timer;
  3491. msg = (u32) ++bp->fw_drv_pulse_wr_seq;
  3492. REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
  3493. bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
  3494. if (bp->phy_flags & PHY_SERDES_FLAG) {
  3495. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  3496. bnx2_5706_serdes_timer(bp);
  3497. else if (CHIP_NUM(bp) == CHIP_NUM_5708)
  3498. bnx2_5708_serdes_timer(bp);
  3499. }
  3500. bnx2_restart_timer:
  3501. mod_timer(&bp->timer, jiffies + bp->current_interval);
  3502. }
  3503. /* Called with rtnl_lock */
  3504. static int
  3505. bnx2_open(struct net_device *dev)
  3506. {
  3507. struct bnx2 *bp = netdev_priv(dev);
  3508. int rc;
  3509. bnx2_set_power_state(bp, PCI_D0);
  3510. bnx2_disable_int(bp);
  3511. rc = bnx2_alloc_mem(bp);
  3512. if (rc)
  3513. return rc;
  3514. if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
  3515. (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
  3516. !disable_msi) {
  3517. if (pci_enable_msi(bp->pdev) == 0) {
  3518. bp->flags |= USING_MSI_FLAG;
  3519. rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
  3520. dev);
  3521. }
  3522. else {
  3523. rc = request_irq(bp->pdev->irq, bnx2_interrupt,
  3524. IRQF_SHARED, dev->name, dev);
  3525. }
  3526. }
  3527. else {
  3528. rc = request_irq(bp->pdev->irq, bnx2_interrupt, IRQF_SHARED,
  3529. dev->name, dev);
  3530. }
  3531. if (rc) {
  3532. bnx2_free_mem(bp);
  3533. return rc;
  3534. }
  3535. rc = bnx2_init_nic(bp);
  3536. if (rc) {
  3537. free_irq(bp->pdev->irq, dev);
  3538. if (bp->flags & USING_MSI_FLAG) {
  3539. pci_disable_msi(bp->pdev);
  3540. bp->flags &= ~USING_MSI_FLAG;
  3541. }
  3542. bnx2_free_skbs(bp);
  3543. bnx2_free_mem(bp);
  3544. return rc;
  3545. }
  3546. mod_timer(&bp->timer, jiffies + bp->current_interval);
  3547. atomic_set(&bp->intr_sem, 0);
  3548. bnx2_enable_int(bp);
  3549. if (bp->flags & USING_MSI_FLAG) {
  3550. /* Test MSI to make sure it is working
  3551. * If MSI test fails, go back to INTx mode
  3552. */
  3553. if (bnx2_test_intr(bp) != 0) {
  3554. printk(KERN_WARNING PFX "%s: No interrupt was generated"
  3555. " using MSI, switching to INTx mode. Please"
  3556. " report this failure to the PCI maintainer"
  3557. " and include system chipset information.\n",
  3558. bp->dev->name);
  3559. bnx2_disable_int(bp);
  3560. free_irq(bp->pdev->irq, dev);
  3561. pci_disable_msi(bp->pdev);
  3562. bp->flags &= ~USING_MSI_FLAG;
  3563. rc = bnx2_init_nic(bp);
  3564. if (!rc) {
  3565. rc = request_irq(bp->pdev->irq, bnx2_interrupt,
  3566. IRQF_SHARED, dev->name, dev);
  3567. }
  3568. if (rc) {
  3569. bnx2_free_skbs(bp);
  3570. bnx2_free_mem(bp);
  3571. del_timer_sync(&bp->timer);
  3572. return rc;
  3573. }
  3574. bnx2_enable_int(bp);
  3575. }
  3576. }
  3577. if (bp->flags & USING_MSI_FLAG) {
  3578. printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
  3579. }
  3580. netif_start_queue(dev);
  3581. return 0;
  3582. }
  3583. static void
  3584. bnx2_reset_task(struct work_struct *work)
  3585. {
  3586. struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
  3587. if (!netif_running(bp->dev))
  3588. return;
  3589. bp->in_reset_task = 1;
  3590. bnx2_netif_stop(bp);
  3591. bnx2_init_nic(bp);
  3592. atomic_set(&bp->intr_sem, 1);
  3593. bnx2_netif_start(bp);
  3594. bp->in_reset_task = 0;
  3595. }
  3596. static void
  3597. bnx2_tx_timeout(struct net_device *dev)
  3598. {
  3599. struct bnx2 *bp = netdev_priv(dev);
  3600. /* This allows the netif to be shutdown gracefully before resetting */
  3601. schedule_work(&bp->reset_task);
  3602. }
  3603. #ifdef BCM_VLAN
  3604. /* Called with rtnl_lock */
  3605. static void
  3606. bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
  3607. {
  3608. struct bnx2 *bp = netdev_priv(dev);
  3609. bnx2_netif_stop(bp);
  3610. bp->vlgrp = vlgrp;
  3611. bnx2_set_rx_mode(dev);
  3612. bnx2_netif_start(bp);
  3613. }
  3614. /* Called with rtnl_lock */
  3615. static void
  3616. bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
  3617. {
  3618. struct bnx2 *bp = netdev_priv(dev);
  3619. bnx2_netif_stop(bp);
  3620. vlan_group_set_device(bp->vlgrp, vid, NULL);
  3621. bnx2_set_rx_mode(dev);
  3622. bnx2_netif_start(bp);
  3623. }
  3624. #endif
  3625. /* Called with netif_tx_lock.
  3626. * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
  3627. * netif_wake_queue().
  3628. */
  3629. static int
  3630. bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
  3631. {
  3632. struct bnx2 *bp = netdev_priv(dev);
  3633. dma_addr_t mapping;
  3634. struct tx_bd *txbd;
  3635. struct sw_bd *tx_buf;
  3636. u32 len, vlan_tag_flags, last_frag, mss;
  3637. u16 prod, ring_prod;
  3638. int i;
  3639. if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
  3640. netif_stop_queue(dev);
  3641. printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
  3642. dev->name);
  3643. return NETDEV_TX_BUSY;
  3644. }
  3645. len = skb_headlen(skb);
  3646. prod = bp->tx_prod;
  3647. ring_prod = TX_RING_IDX(prod);
  3648. vlan_tag_flags = 0;
  3649. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  3650. vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
  3651. }
  3652. if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
  3653. vlan_tag_flags |=
  3654. (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
  3655. }
  3656. if ((mss = skb_shinfo(skb)->gso_size)) {
  3657. u32 tcp_opt_len, ip_tcp_len;
  3658. if (skb_header_cloned(skb) &&
  3659. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  3660. dev_kfree_skb(skb);
  3661. return NETDEV_TX_OK;
  3662. }
  3663. tcp_opt_len = ((skb->h.th->doff - 5) * 4);
  3664. vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
  3665. tcp_opt_len = 0;
  3666. if (skb->h.th->doff > 5) {
  3667. tcp_opt_len = (skb->h.th->doff - 5) << 2;
  3668. }
  3669. ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
  3670. skb->nh.iph->check = 0;
  3671. skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
  3672. skb->h.th->check =
  3673. ~csum_tcpudp_magic(skb->nh.iph->saddr,
  3674. skb->nh.iph->daddr,
  3675. 0, IPPROTO_TCP, 0);
  3676. if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
  3677. vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
  3678. (tcp_opt_len >> 2)) << 8;
  3679. }
  3680. }
  3681. else
  3682. {
  3683. mss = 0;
  3684. }
  3685. mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  3686. tx_buf = &bp->tx_buf_ring[ring_prod];
  3687. tx_buf->skb = skb;
  3688. pci_unmap_addr_set(tx_buf, mapping, mapping);
  3689. txbd = &bp->tx_desc_ring[ring_prod];
  3690. txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
  3691. txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  3692. txbd->tx_bd_mss_nbytes = len | (mss << 16);
  3693. txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
  3694. last_frag = skb_shinfo(skb)->nr_frags;
  3695. for (i = 0; i < last_frag; i++) {
  3696. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3697. prod = NEXT_TX_BD(prod);
  3698. ring_prod = TX_RING_IDX(prod);
  3699. txbd = &bp->tx_desc_ring[ring_prod];
  3700. len = frag->size;
  3701. mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
  3702. len, PCI_DMA_TODEVICE);
  3703. pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
  3704. mapping, mapping);
  3705. txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
  3706. txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
  3707. txbd->tx_bd_mss_nbytes = len | (mss << 16);
  3708. txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
  3709. }
  3710. txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
  3711. prod = NEXT_TX_BD(prod);
  3712. bp->tx_prod_bseq += skb->len;
  3713. REG_WR16(bp, bp->tx_bidx_addr, prod);
  3714. REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
  3715. mmiowb();
  3716. bp->tx_prod = prod;
  3717. dev->trans_start = jiffies;
  3718. if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
  3719. netif_stop_queue(dev);
  3720. if (bnx2_tx_avail(bp) > bp->tx_wake_thresh)
  3721. netif_wake_queue(dev);
  3722. }
  3723. return NETDEV_TX_OK;
  3724. }
  3725. /* Called with rtnl_lock */
  3726. static int
  3727. bnx2_close(struct net_device *dev)
  3728. {
  3729. struct bnx2 *bp = netdev_priv(dev);
  3730. u32 reset_code;
  3731. /* Calling flush_scheduled_work() may deadlock because
  3732. * linkwatch_event() may be on the workqueue and it will try to get
  3733. * the rtnl_lock which we are holding.
  3734. */
  3735. while (bp->in_reset_task)
  3736. msleep(1);
  3737. bnx2_netif_stop(bp);
  3738. del_timer_sync(&bp->timer);
  3739. if (bp->flags & NO_WOL_FLAG)
  3740. reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
  3741. else if (bp->wol)
  3742. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
  3743. else
  3744. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
  3745. bnx2_reset_chip(bp, reset_code);
  3746. free_irq(bp->pdev->irq, dev);
  3747. if (bp->flags & USING_MSI_FLAG) {
  3748. pci_disable_msi(bp->pdev);
  3749. bp->flags &= ~USING_MSI_FLAG;
  3750. }
  3751. bnx2_free_skbs(bp);
  3752. bnx2_free_mem(bp);
  3753. bp->link_up = 0;
  3754. netif_carrier_off(bp->dev);
  3755. bnx2_set_power_state(bp, PCI_D3hot);
  3756. return 0;
  3757. }
  3758. #define GET_NET_STATS64(ctr) \
  3759. (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
  3760. (unsigned long) (ctr##_lo)
  3761. #define GET_NET_STATS32(ctr) \
  3762. (ctr##_lo)
  3763. #if (BITS_PER_LONG == 64)
  3764. #define GET_NET_STATS GET_NET_STATS64
  3765. #else
  3766. #define GET_NET_STATS GET_NET_STATS32
  3767. #endif
  3768. static struct net_device_stats *
  3769. bnx2_get_stats(struct net_device *dev)
  3770. {
  3771. struct bnx2 *bp = netdev_priv(dev);
  3772. struct statistics_block *stats_blk = bp->stats_blk;
  3773. struct net_device_stats *net_stats = &bp->net_stats;
  3774. if (bp->stats_blk == NULL) {
  3775. return net_stats;
  3776. }
  3777. net_stats->rx_packets =
  3778. GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
  3779. GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
  3780. GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
  3781. net_stats->tx_packets =
  3782. GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
  3783. GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
  3784. GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
  3785. net_stats->rx_bytes =
  3786. GET_NET_STATS(stats_blk->stat_IfHCInOctets);
  3787. net_stats->tx_bytes =
  3788. GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
  3789. net_stats->multicast =
  3790. GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
  3791. net_stats->collisions =
  3792. (unsigned long) stats_blk->stat_EtherStatsCollisions;
  3793. net_stats->rx_length_errors =
  3794. (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
  3795. stats_blk->stat_EtherStatsOverrsizePkts);
  3796. net_stats->rx_over_errors =
  3797. (unsigned long) stats_blk->stat_IfInMBUFDiscards;
  3798. net_stats->rx_frame_errors =
  3799. (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
  3800. net_stats->rx_crc_errors =
  3801. (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
  3802. net_stats->rx_errors = net_stats->rx_length_errors +
  3803. net_stats->rx_over_errors + net_stats->rx_frame_errors +
  3804. net_stats->rx_crc_errors;
  3805. net_stats->tx_aborted_errors =
  3806. (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
  3807. stats_blk->stat_Dot3StatsLateCollisions);
  3808. if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
  3809. (CHIP_ID(bp) == CHIP_ID_5708_A0))
  3810. net_stats->tx_carrier_errors = 0;
  3811. else {
  3812. net_stats->tx_carrier_errors =
  3813. (unsigned long)
  3814. stats_blk->stat_Dot3StatsCarrierSenseErrors;
  3815. }
  3816. net_stats->tx_errors =
  3817. (unsigned long)
  3818. stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
  3819. +
  3820. net_stats->tx_aborted_errors +
  3821. net_stats->tx_carrier_errors;
  3822. net_stats->rx_missed_errors =
  3823. (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
  3824. stats_blk->stat_FwRxDrop);
  3825. return net_stats;
  3826. }
  3827. /* All ethtool functions called with rtnl_lock */
  3828. static int
  3829. bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  3830. {
  3831. struct bnx2 *bp = netdev_priv(dev);
  3832. cmd->supported = SUPPORTED_Autoneg;
  3833. if (bp->phy_flags & PHY_SERDES_FLAG) {
  3834. cmd->supported |= SUPPORTED_1000baseT_Full |
  3835. SUPPORTED_FIBRE;
  3836. cmd->port = PORT_FIBRE;
  3837. }
  3838. else {
  3839. cmd->supported |= SUPPORTED_10baseT_Half |
  3840. SUPPORTED_10baseT_Full |
  3841. SUPPORTED_100baseT_Half |
  3842. SUPPORTED_100baseT_Full |
  3843. SUPPORTED_1000baseT_Full |
  3844. SUPPORTED_TP;
  3845. cmd->port = PORT_TP;
  3846. }
  3847. cmd->advertising = bp->advertising;
  3848. if (bp->autoneg & AUTONEG_SPEED) {
  3849. cmd->autoneg = AUTONEG_ENABLE;
  3850. }
  3851. else {
  3852. cmd->autoneg = AUTONEG_DISABLE;
  3853. }
  3854. if (netif_carrier_ok(dev)) {
  3855. cmd->speed = bp->line_speed;
  3856. cmd->duplex = bp->duplex;
  3857. }
  3858. else {
  3859. cmd->speed = -1;
  3860. cmd->duplex = -1;
  3861. }
  3862. cmd->transceiver = XCVR_INTERNAL;
  3863. cmd->phy_address = bp->phy_addr;
  3864. return 0;
  3865. }
  3866. static int
  3867. bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  3868. {
  3869. struct bnx2 *bp = netdev_priv(dev);
  3870. u8 autoneg = bp->autoneg;
  3871. u8 req_duplex = bp->req_duplex;
  3872. u16 req_line_speed = bp->req_line_speed;
  3873. u32 advertising = bp->advertising;
  3874. if (cmd->autoneg == AUTONEG_ENABLE) {
  3875. autoneg |= AUTONEG_SPEED;
  3876. cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
  3877. /* allow advertising 1 speed */
  3878. if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
  3879. (cmd->advertising == ADVERTISED_10baseT_Full) ||
  3880. (cmd->advertising == ADVERTISED_100baseT_Half) ||
  3881. (cmd->advertising == ADVERTISED_100baseT_Full)) {
  3882. if (bp->phy_flags & PHY_SERDES_FLAG)
  3883. return -EINVAL;
  3884. advertising = cmd->advertising;
  3885. }
  3886. else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
  3887. advertising = cmd->advertising;
  3888. }
  3889. else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
  3890. return -EINVAL;
  3891. }
  3892. else {
  3893. if (bp->phy_flags & PHY_SERDES_FLAG) {
  3894. advertising = ETHTOOL_ALL_FIBRE_SPEED;
  3895. }
  3896. else {
  3897. advertising = ETHTOOL_ALL_COPPER_SPEED;
  3898. }
  3899. }
  3900. advertising |= ADVERTISED_Autoneg;
  3901. }
  3902. else {
  3903. if (bp->phy_flags & PHY_SERDES_FLAG) {
  3904. if ((cmd->speed != SPEED_1000 &&
  3905. cmd->speed != SPEED_2500) ||
  3906. (cmd->duplex != DUPLEX_FULL))
  3907. return -EINVAL;
  3908. if (cmd->speed == SPEED_2500 &&
  3909. !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
  3910. return -EINVAL;
  3911. }
  3912. else if (cmd->speed == SPEED_1000) {
  3913. return -EINVAL;
  3914. }
  3915. autoneg &= ~AUTONEG_SPEED;
  3916. req_line_speed = cmd->speed;
  3917. req_duplex = cmd->duplex;
  3918. advertising = 0;
  3919. }
  3920. bp->autoneg = autoneg;
  3921. bp->advertising = advertising;
  3922. bp->req_line_speed = req_line_speed;
  3923. bp->req_duplex = req_duplex;
  3924. spin_lock_bh(&bp->phy_lock);
  3925. bnx2_setup_phy(bp);
  3926. spin_unlock_bh(&bp->phy_lock);
  3927. return 0;
  3928. }
  3929. static void
  3930. bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  3931. {
  3932. struct bnx2 *bp = netdev_priv(dev);
  3933. strcpy(info->driver, DRV_MODULE_NAME);
  3934. strcpy(info->version, DRV_MODULE_VERSION);
  3935. strcpy(info->bus_info, pci_name(bp->pdev));
  3936. info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
  3937. info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
  3938. info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
  3939. info->fw_version[1] = info->fw_version[3] = '.';
  3940. info->fw_version[5] = 0;
  3941. }
  3942. #define BNX2_REGDUMP_LEN (32 * 1024)
  3943. static int
  3944. bnx2_get_regs_len(struct net_device *dev)
  3945. {
  3946. return BNX2_REGDUMP_LEN;
  3947. }
  3948. static void
  3949. bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
  3950. {
  3951. u32 *p = _p, i, offset;
  3952. u8 *orig_p = _p;
  3953. struct bnx2 *bp = netdev_priv(dev);
  3954. u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
  3955. 0x0800, 0x0880, 0x0c00, 0x0c10,
  3956. 0x0c30, 0x0d08, 0x1000, 0x101c,
  3957. 0x1040, 0x1048, 0x1080, 0x10a4,
  3958. 0x1400, 0x1490, 0x1498, 0x14f0,
  3959. 0x1500, 0x155c, 0x1580, 0x15dc,
  3960. 0x1600, 0x1658, 0x1680, 0x16d8,
  3961. 0x1800, 0x1820, 0x1840, 0x1854,
  3962. 0x1880, 0x1894, 0x1900, 0x1984,
  3963. 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
  3964. 0x1c80, 0x1c94, 0x1d00, 0x1d84,
  3965. 0x2000, 0x2030, 0x23c0, 0x2400,
  3966. 0x2800, 0x2820, 0x2830, 0x2850,
  3967. 0x2b40, 0x2c10, 0x2fc0, 0x3058,
  3968. 0x3c00, 0x3c94, 0x4000, 0x4010,
  3969. 0x4080, 0x4090, 0x43c0, 0x4458,
  3970. 0x4c00, 0x4c18, 0x4c40, 0x4c54,
  3971. 0x4fc0, 0x5010, 0x53c0, 0x5444,
  3972. 0x5c00, 0x5c18, 0x5c80, 0x5c90,
  3973. 0x5fc0, 0x6000, 0x6400, 0x6428,
  3974. 0x6800, 0x6848, 0x684c, 0x6860,
  3975. 0x6888, 0x6910, 0x8000 };
  3976. regs->version = 0;
  3977. memset(p, 0, BNX2_REGDUMP_LEN);
  3978. if (!netif_running(bp->dev))
  3979. return;
  3980. i = 0;
  3981. offset = reg_boundaries[0];
  3982. p += offset;
  3983. while (offset < BNX2_REGDUMP_LEN) {
  3984. *p++ = REG_RD(bp, offset);
  3985. offset += 4;
  3986. if (offset == reg_boundaries[i + 1]) {
  3987. offset = reg_boundaries[i + 2];
  3988. p = (u32 *) (orig_p + offset);
  3989. i += 2;
  3990. }
  3991. }
  3992. }
  3993. static void
  3994. bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  3995. {
  3996. struct bnx2 *bp = netdev_priv(dev);
  3997. if (bp->flags & NO_WOL_FLAG) {
  3998. wol->supported = 0;
  3999. wol->wolopts = 0;
  4000. }
  4001. else {
  4002. wol->supported = WAKE_MAGIC;
  4003. if (bp->wol)
  4004. wol->wolopts = WAKE_MAGIC;
  4005. else
  4006. wol->wolopts = 0;
  4007. }
  4008. memset(&wol->sopass, 0, sizeof(wol->sopass));
  4009. }
  4010. static int
  4011. bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  4012. {
  4013. struct bnx2 *bp = netdev_priv(dev);
  4014. if (wol->wolopts & ~WAKE_MAGIC)
  4015. return -EINVAL;
  4016. if (wol->wolopts & WAKE_MAGIC) {
  4017. if (bp->flags & NO_WOL_FLAG)
  4018. return -EINVAL;
  4019. bp->wol = 1;
  4020. }
  4021. else {
  4022. bp->wol = 0;
  4023. }
  4024. return 0;
  4025. }
  4026. static int
  4027. bnx2_nway_reset(struct net_device *dev)
  4028. {
  4029. struct bnx2 *bp = netdev_priv(dev);
  4030. u32 bmcr;
  4031. if (!(bp->autoneg & AUTONEG_SPEED)) {
  4032. return -EINVAL;
  4033. }
  4034. spin_lock_bh(&bp->phy_lock);
  4035. /* Force a link down visible on the other side */
  4036. if (bp->phy_flags & PHY_SERDES_FLAG) {
  4037. bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
  4038. spin_unlock_bh(&bp->phy_lock);
  4039. msleep(20);
  4040. spin_lock_bh(&bp->phy_lock);
  4041. bp->current_interval = SERDES_AN_TIMEOUT;
  4042. bp->serdes_an_pending = 1;
  4043. mod_timer(&bp->timer, jiffies + bp->current_interval);
  4044. }
  4045. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  4046. bmcr &= ~BMCR_LOOPBACK;
  4047. bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
  4048. spin_unlock_bh(&bp->phy_lock);
  4049. return 0;
  4050. }
  4051. static int
  4052. bnx2_get_eeprom_len(struct net_device *dev)
  4053. {
  4054. struct bnx2 *bp = netdev_priv(dev);
  4055. if (bp->flash_info == NULL)
  4056. return 0;
  4057. return (int) bp->flash_size;
  4058. }
  4059. static int
  4060. bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  4061. u8 *eebuf)
  4062. {
  4063. struct bnx2 *bp = netdev_priv(dev);
  4064. int rc;
  4065. /* parameters already validated in ethtool_get_eeprom */
  4066. rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
  4067. return rc;
  4068. }
  4069. static int
  4070. bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
  4071. u8 *eebuf)
  4072. {
  4073. struct bnx2 *bp = netdev_priv(dev);
  4074. int rc;
  4075. /* parameters already validated in ethtool_set_eeprom */
  4076. rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
  4077. return rc;
  4078. }
  4079. static int
  4080. bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
  4081. {
  4082. struct bnx2 *bp = netdev_priv(dev);
  4083. memset(coal, 0, sizeof(struct ethtool_coalesce));
  4084. coal->rx_coalesce_usecs = bp->rx_ticks;
  4085. coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
  4086. coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
  4087. coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
  4088. coal->tx_coalesce_usecs = bp->tx_ticks;
  4089. coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
  4090. coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
  4091. coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
  4092. coal->stats_block_coalesce_usecs = bp->stats_ticks;
  4093. return 0;
  4094. }
  4095. static int
  4096. bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
  4097. {
  4098. struct bnx2 *bp = netdev_priv(dev);
  4099. bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
  4100. if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
  4101. bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
  4102. if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
  4103. bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
  4104. if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
  4105. bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
  4106. if (bp->rx_quick_cons_trip_int > 0xff)
  4107. bp->rx_quick_cons_trip_int = 0xff;
  4108. bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
  4109. if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
  4110. bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
  4111. if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
  4112. bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
  4113. if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
  4114. bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
  4115. if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
  4116. 0xff;
  4117. bp->stats_ticks = coal->stats_block_coalesce_usecs;
  4118. if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
  4119. bp->stats_ticks &= 0xffff00;
  4120. if (netif_running(bp->dev)) {
  4121. bnx2_netif_stop(bp);
  4122. bnx2_init_nic(bp);
  4123. bnx2_netif_start(bp);
  4124. }
  4125. return 0;
  4126. }
  4127. static void
  4128. bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  4129. {
  4130. struct bnx2 *bp = netdev_priv(dev);
  4131. ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
  4132. ering->rx_mini_max_pending = 0;
  4133. ering->rx_jumbo_max_pending = 0;
  4134. ering->rx_pending = bp->rx_ring_size;
  4135. ering->rx_mini_pending = 0;
  4136. ering->rx_jumbo_pending = 0;
  4137. ering->tx_max_pending = MAX_TX_DESC_CNT;
  4138. ering->tx_pending = bp->tx_ring_size;
  4139. }
  4140. static int
  4141. bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  4142. {
  4143. struct bnx2 *bp = netdev_priv(dev);
  4144. if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
  4145. (ering->tx_pending > MAX_TX_DESC_CNT) ||
  4146. (ering->tx_pending <= MAX_SKB_FRAGS)) {
  4147. return -EINVAL;
  4148. }
  4149. if (netif_running(bp->dev)) {
  4150. bnx2_netif_stop(bp);
  4151. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
  4152. bnx2_free_skbs(bp);
  4153. bnx2_free_mem(bp);
  4154. }
  4155. bnx2_set_rx_ring_size(bp, ering->rx_pending);
  4156. bp->tx_ring_size = ering->tx_pending;
  4157. if (netif_running(bp->dev)) {
  4158. int rc;
  4159. rc = bnx2_alloc_mem(bp);
  4160. if (rc)
  4161. return rc;
  4162. bnx2_init_nic(bp);
  4163. bnx2_netif_start(bp);
  4164. }
  4165. return 0;
  4166. }
  4167. static void
  4168. bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  4169. {
  4170. struct bnx2 *bp = netdev_priv(dev);
  4171. epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
  4172. epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
  4173. epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
  4174. }
  4175. static int
  4176. bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  4177. {
  4178. struct bnx2 *bp = netdev_priv(dev);
  4179. bp->req_flow_ctrl = 0;
  4180. if (epause->rx_pause)
  4181. bp->req_flow_ctrl |= FLOW_CTRL_RX;
  4182. if (epause->tx_pause)
  4183. bp->req_flow_ctrl |= FLOW_CTRL_TX;
  4184. if (epause->autoneg) {
  4185. bp->autoneg |= AUTONEG_FLOW_CTRL;
  4186. }
  4187. else {
  4188. bp->autoneg &= ~AUTONEG_FLOW_CTRL;
  4189. }
  4190. spin_lock_bh(&bp->phy_lock);
  4191. bnx2_setup_phy(bp);
  4192. spin_unlock_bh(&bp->phy_lock);
  4193. return 0;
  4194. }
  4195. static u32
  4196. bnx2_get_rx_csum(struct net_device *dev)
  4197. {
  4198. struct bnx2 *bp = netdev_priv(dev);
  4199. return bp->rx_csum;
  4200. }
  4201. static int
  4202. bnx2_set_rx_csum(struct net_device *dev, u32 data)
  4203. {
  4204. struct bnx2 *bp = netdev_priv(dev);
  4205. bp->rx_csum = data;
  4206. return 0;
  4207. }
  4208. static int
  4209. bnx2_set_tso(struct net_device *dev, u32 data)
  4210. {
  4211. if (data)
  4212. dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
  4213. else
  4214. dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
  4215. return 0;
  4216. }
  4217. #define BNX2_NUM_STATS 46
  4218. static struct {
  4219. char string[ETH_GSTRING_LEN];
  4220. } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
  4221. { "rx_bytes" },
  4222. { "rx_error_bytes" },
  4223. { "tx_bytes" },
  4224. { "tx_error_bytes" },
  4225. { "rx_ucast_packets" },
  4226. { "rx_mcast_packets" },
  4227. { "rx_bcast_packets" },
  4228. { "tx_ucast_packets" },
  4229. { "tx_mcast_packets" },
  4230. { "tx_bcast_packets" },
  4231. { "tx_mac_errors" },
  4232. { "tx_carrier_errors" },
  4233. { "rx_crc_errors" },
  4234. { "rx_align_errors" },
  4235. { "tx_single_collisions" },
  4236. { "tx_multi_collisions" },
  4237. { "tx_deferred" },
  4238. { "tx_excess_collisions" },
  4239. { "tx_late_collisions" },
  4240. { "tx_total_collisions" },
  4241. { "rx_fragments" },
  4242. { "rx_jabbers" },
  4243. { "rx_undersize_packets" },
  4244. { "rx_oversize_packets" },
  4245. { "rx_64_byte_packets" },
  4246. { "rx_65_to_127_byte_packets" },
  4247. { "rx_128_to_255_byte_packets" },
  4248. { "rx_256_to_511_byte_packets" },
  4249. { "rx_512_to_1023_byte_packets" },
  4250. { "rx_1024_to_1522_byte_packets" },
  4251. { "rx_1523_to_9022_byte_packets" },
  4252. { "tx_64_byte_packets" },
  4253. { "tx_65_to_127_byte_packets" },
  4254. { "tx_128_to_255_byte_packets" },
  4255. { "tx_256_to_511_byte_packets" },
  4256. { "tx_512_to_1023_byte_packets" },
  4257. { "tx_1024_to_1522_byte_packets" },
  4258. { "tx_1523_to_9022_byte_packets" },
  4259. { "rx_xon_frames" },
  4260. { "rx_xoff_frames" },
  4261. { "tx_xon_frames" },
  4262. { "tx_xoff_frames" },
  4263. { "rx_mac_ctrl_frames" },
  4264. { "rx_filtered_packets" },
  4265. { "rx_discards" },
  4266. { "rx_fw_discards" },
  4267. };
  4268. #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
  4269. static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
  4270. STATS_OFFSET32(stat_IfHCInOctets_hi),
  4271. STATS_OFFSET32(stat_IfHCInBadOctets_hi),
  4272. STATS_OFFSET32(stat_IfHCOutOctets_hi),
  4273. STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
  4274. STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
  4275. STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
  4276. STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
  4277. STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
  4278. STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
  4279. STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
  4280. STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
  4281. STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
  4282. STATS_OFFSET32(stat_Dot3StatsFCSErrors),
  4283. STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
  4284. STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
  4285. STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
  4286. STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
  4287. STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
  4288. STATS_OFFSET32(stat_Dot3StatsLateCollisions),
  4289. STATS_OFFSET32(stat_EtherStatsCollisions),
  4290. STATS_OFFSET32(stat_EtherStatsFragments),
  4291. STATS_OFFSET32(stat_EtherStatsJabbers),
  4292. STATS_OFFSET32(stat_EtherStatsUndersizePkts),
  4293. STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
  4294. STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
  4295. STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
  4296. STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
  4297. STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
  4298. STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
  4299. STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
  4300. STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
  4301. STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
  4302. STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
  4303. STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
  4304. STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
  4305. STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
  4306. STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
  4307. STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
  4308. STATS_OFFSET32(stat_XonPauseFramesReceived),
  4309. STATS_OFFSET32(stat_XoffPauseFramesReceived),
  4310. STATS_OFFSET32(stat_OutXonSent),
  4311. STATS_OFFSET32(stat_OutXoffSent),
  4312. STATS_OFFSET32(stat_MacControlFramesReceived),
  4313. STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
  4314. STATS_OFFSET32(stat_IfInMBUFDiscards),
  4315. STATS_OFFSET32(stat_FwRxDrop),
  4316. };
  4317. /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
  4318. * skipped because of errata.
  4319. */
  4320. static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
  4321. 8,0,8,8,8,8,8,8,8,8,
  4322. 4,0,4,4,4,4,4,4,4,4,
  4323. 4,4,4,4,4,4,4,4,4,4,
  4324. 4,4,4,4,4,4,4,4,4,4,
  4325. 4,4,4,4,4,4,
  4326. };
  4327. static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
  4328. 8,0,8,8,8,8,8,8,8,8,
  4329. 4,4,4,4,4,4,4,4,4,4,
  4330. 4,4,4,4,4,4,4,4,4,4,
  4331. 4,4,4,4,4,4,4,4,4,4,
  4332. 4,4,4,4,4,4,
  4333. };
  4334. #define BNX2_NUM_TESTS 6
  4335. static struct {
  4336. char string[ETH_GSTRING_LEN];
  4337. } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
  4338. { "register_test (offline)" },
  4339. { "memory_test (offline)" },
  4340. { "loopback_test (offline)" },
  4341. { "nvram_test (online)" },
  4342. { "interrupt_test (online)" },
  4343. { "link_test (online)" },
  4344. };
  4345. static int
  4346. bnx2_self_test_count(struct net_device *dev)
  4347. {
  4348. return BNX2_NUM_TESTS;
  4349. }
  4350. static void
  4351. bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
  4352. {
  4353. struct bnx2 *bp = netdev_priv(dev);
  4354. memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
  4355. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  4356. int i;
  4357. bnx2_netif_stop(bp);
  4358. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
  4359. bnx2_free_skbs(bp);
  4360. if (bnx2_test_registers(bp) != 0) {
  4361. buf[0] = 1;
  4362. etest->flags |= ETH_TEST_FL_FAILED;
  4363. }
  4364. if (bnx2_test_memory(bp) != 0) {
  4365. buf[1] = 1;
  4366. etest->flags |= ETH_TEST_FL_FAILED;
  4367. }
  4368. if ((buf[2] = bnx2_test_loopback(bp)) != 0)
  4369. etest->flags |= ETH_TEST_FL_FAILED;
  4370. if (!netif_running(bp->dev)) {
  4371. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
  4372. }
  4373. else {
  4374. bnx2_init_nic(bp);
  4375. bnx2_netif_start(bp);
  4376. }
  4377. /* wait for link up */
  4378. for (i = 0; i < 7; i++) {
  4379. if (bp->link_up)
  4380. break;
  4381. msleep_interruptible(1000);
  4382. }
  4383. }
  4384. if (bnx2_test_nvram(bp) != 0) {
  4385. buf[3] = 1;
  4386. etest->flags |= ETH_TEST_FL_FAILED;
  4387. }
  4388. if (bnx2_test_intr(bp) != 0) {
  4389. buf[4] = 1;
  4390. etest->flags |= ETH_TEST_FL_FAILED;
  4391. }
  4392. if (bnx2_test_link(bp) != 0) {
  4393. buf[5] = 1;
  4394. etest->flags |= ETH_TEST_FL_FAILED;
  4395. }
  4396. }
  4397. static void
  4398. bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  4399. {
  4400. switch (stringset) {
  4401. case ETH_SS_STATS:
  4402. memcpy(buf, bnx2_stats_str_arr,
  4403. sizeof(bnx2_stats_str_arr));
  4404. break;
  4405. case ETH_SS_TEST:
  4406. memcpy(buf, bnx2_tests_str_arr,
  4407. sizeof(bnx2_tests_str_arr));
  4408. break;
  4409. }
  4410. }
  4411. static int
  4412. bnx2_get_stats_count(struct net_device *dev)
  4413. {
  4414. return BNX2_NUM_STATS;
  4415. }
  4416. static void
  4417. bnx2_get_ethtool_stats(struct net_device *dev,
  4418. struct ethtool_stats *stats, u64 *buf)
  4419. {
  4420. struct bnx2 *bp = netdev_priv(dev);
  4421. int i;
  4422. u32 *hw_stats = (u32 *) bp->stats_blk;
  4423. u8 *stats_len_arr = NULL;
  4424. if (hw_stats == NULL) {
  4425. memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
  4426. return;
  4427. }
  4428. if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
  4429. (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
  4430. (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
  4431. (CHIP_ID(bp) == CHIP_ID_5708_A0))
  4432. stats_len_arr = bnx2_5706_stats_len_arr;
  4433. else
  4434. stats_len_arr = bnx2_5708_stats_len_arr;
  4435. for (i = 0; i < BNX2_NUM_STATS; i++) {
  4436. if (stats_len_arr[i] == 0) {
  4437. /* skip this counter */
  4438. buf[i] = 0;
  4439. continue;
  4440. }
  4441. if (stats_len_arr[i] == 4) {
  4442. /* 4-byte counter */
  4443. buf[i] = (u64)
  4444. *(hw_stats + bnx2_stats_offset_arr[i]);
  4445. continue;
  4446. }
  4447. /* 8-byte counter */
  4448. buf[i] = (((u64) *(hw_stats +
  4449. bnx2_stats_offset_arr[i])) << 32) +
  4450. *(hw_stats + bnx2_stats_offset_arr[i] + 1);
  4451. }
  4452. }
  4453. static int
  4454. bnx2_phys_id(struct net_device *dev, u32 data)
  4455. {
  4456. struct bnx2 *bp = netdev_priv(dev);
  4457. int i;
  4458. u32 save;
  4459. if (data == 0)
  4460. data = 2;
  4461. save = REG_RD(bp, BNX2_MISC_CFG);
  4462. REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
  4463. for (i = 0; i < (data * 2); i++) {
  4464. if ((i % 2) == 0) {
  4465. REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
  4466. }
  4467. else {
  4468. REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
  4469. BNX2_EMAC_LED_1000MB_OVERRIDE |
  4470. BNX2_EMAC_LED_100MB_OVERRIDE |
  4471. BNX2_EMAC_LED_10MB_OVERRIDE |
  4472. BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
  4473. BNX2_EMAC_LED_TRAFFIC);
  4474. }
  4475. msleep_interruptible(500);
  4476. if (signal_pending(current))
  4477. break;
  4478. }
  4479. REG_WR(bp, BNX2_EMAC_LED, 0);
  4480. REG_WR(bp, BNX2_MISC_CFG, save);
  4481. return 0;
  4482. }
  4483. static const struct ethtool_ops bnx2_ethtool_ops = {
  4484. .get_settings = bnx2_get_settings,
  4485. .set_settings = bnx2_set_settings,
  4486. .get_drvinfo = bnx2_get_drvinfo,
  4487. .get_regs_len = bnx2_get_regs_len,
  4488. .get_regs = bnx2_get_regs,
  4489. .get_wol = bnx2_get_wol,
  4490. .set_wol = bnx2_set_wol,
  4491. .nway_reset = bnx2_nway_reset,
  4492. .get_link = ethtool_op_get_link,
  4493. .get_eeprom_len = bnx2_get_eeprom_len,
  4494. .get_eeprom = bnx2_get_eeprom,
  4495. .set_eeprom = bnx2_set_eeprom,
  4496. .get_coalesce = bnx2_get_coalesce,
  4497. .set_coalesce = bnx2_set_coalesce,
  4498. .get_ringparam = bnx2_get_ringparam,
  4499. .set_ringparam = bnx2_set_ringparam,
  4500. .get_pauseparam = bnx2_get_pauseparam,
  4501. .set_pauseparam = bnx2_set_pauseparam,
  4502. .get_rx_csum = bnx2_get_rx_csum,
  4503. .set_rx_csum = bnx2_set_rx_csum,
  4504. .get_tx_csum = ethtool_op_get_tx_csum,
  4505. .set_tx_csum = ethtool_op_set_tx_csum,
  4506. .get_sg = ethtool_op_get_sg,
  4507. .set_sg = ethtool_op_set_sg,
  4508. .get_tso = ethtool_op_get_tso,
  4509. .set_tso = bnx2_set_tso,
  4510. .self_test_count = bnx2_self_test_count,
  4511. .self_test = bnx2_self_test,
  4512. .get_strings = bnx2_get_strings,
  4513. .phys_id = bnx2_phys_id,
  4514. .get_stats_count = bnx2_get_stats_count,
  4515. .get_ethtool_stats = bnx2_get_ethtool_stats,
  4516. .get_perm_addr = ethtool_op_get_perm_addr,
  4517. };
  4518. /* Called with rtnl_lock */
  4519. static int
  4520. bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  4521. {
  4522. struct mii_ioctl_data *data = if_mii(ifr);
  4523. struct bnx2 *bp = netdev_priv(dev);
  4524. int err;
  4525. switch(cmd) {
  4526. case SIOCGMIIPHY:
  4527. data->phy_id = bp->phy_addr;
  4528. /* fallthru */
  4529. case SIOCGMIIREG: {
  4530. u32 mii_regval;
  4531. if (!netif_running(dev))
  4532. return -EAGAIN;
  4533. spin_lock_bh(&bp->phy_lock);
  4534. err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
  4535. spin_unlock_bh(&bp->phy_lock);
  4536. data->val_out = mii_regval;
  4537. return err;
  4538. }
  4539. case SIOCSMIIREG:
  4540. if (!capable(CAP_NET_ADMIN))
  4541. return -EPERM;
  4542. if (!netif_running(dev))
  4543. return -EAGAIN;
  4544. spin_lock_bh(&bp->phy_lock);
  4545. err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
  4546. spin_unlock_bh(&bp->phy_lock);
  4547. return err;
  4548. default:
  4549. /* do nothing */
  4550. break;
  4551. }
  4552. return -EOPNOTSUPP;
  4553. }
  4554. /* Called with rtnl_lock */
  4555. static int
  4556. bnx2_change_mac_addr(struct net_device *dev, void *p)
  4557. {
  4558. struct sockaddr *addr = p;
  4559. struct bnx2 *bp = netdev_priv(dev);
  4560. if (!is_valid_ether_addr(addr->sa_data))
  4561. return -EINVAL;
  4562. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  4563. if (netif_running(dev))
  4564. bnx2_set_mac_addr(bp);
  4565. return 0;
  4566. }
  4567. /* Called with rtnl_lock */
  4568. static int
  4569. bnx2_change_mtu(struct net_device *dev, int new_mtu)
  4570. {
  4571. struct bnx2 *bp = netdev_priv(dev);
  4572. if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
  4573. ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
  4574. return -EINVAL;
  4575. dev->mtu = new_mtu;
  4576. if (netif_running(dev)) {
  4577. bnx2_netif_stop(bp);
  4578. bnx2_init_nic(bp);
  4579. bnx2_netif_start(bp);
  4580. }
  4581. return 0;
  4582. }
  4583. #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
  4584. static void
  4585. poll_bnx2(struct net_device *dev)
  4586. {
  4587. struct bnx2 *bp = netdev_priv(dev);
  4588. disable_irq(bp->pdev->irq);
  4589. bnx2_interrupt(bp->pdev->irq, dev);
  4590. enable_irq(bp->pdev->irq);
  4591. }
  4592. #endif
  4593. static void __devinit
  4594. bnx2_get_5709_media(struct bnx2 *bp)
  4595. {
  4596. u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
  4597. u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
  4598. u32 strap;
  4599. if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
  4600. return;
  4601. else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
  4602. bp->phy_flags |= PHY_SERDES_FLAG;
  4603. return;
  4604. }
  4605. if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
  4606. strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
  4607. else
  4608. strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
  4609. if (PCI_FUNC(bp->pdev->devfn) == 0) {
  4610. switch (strap) {
  4611. case 0x4:
  4612. case 0x5:
  4613. case 0x6:
  4614. bp->phy_flags |= PHY_SERDES_FLAG;
  4615. return;
  4616. }
  4617. } else {
  4618. switch (strap) {
  4619. case 0x1:
  4620. case 0x2:
  4621. case 0x4:
  4622. bp->phy_flags |= PHY_SERDES_FLAG;
  4623. return;
  4624. }
  4625. }
  4626. }
  4627. static int __devinit
  4628. bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
  4629. {
  4630. struct bnx2 *bp;
  4631. unsigned long mem_len;
  4632. int rc;
  4633. u32 reg;
  4634. SET_MODULE_OWNER(dev);
  4635. SET_NETDEV_DEV(dev, &pdev->dev);
  4636. bp = netdev_priv(dev);
  4637. bp->flags = 0;
  4638. bp->phy_flags = 0;
  4639. /* enable device (incl. PCI PM wakeup), and bus-mastering */
  4640. rc = pci_enable_device(pdev);
  4641. if (rc) {
  4642. dev_err(&pdev->dev, "Cannot enable PCI device, aborting.");
  4643. goto err_out;
  4644. }
  4645. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  4646. dev_err(&pdev->dev,
  4647. "Cannot find PCI device base address, aborting.\n");
  4648. rc = -ENODEV;
  4649. goto err_out_disable;
  4650. }
  4651. rc = pci_request_regions(pdev, DRV_MODULE_NAME);
  4652. if (rc) {
  4653. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
  4654. goto err_out_disable;
  4655. }
  4656. pci_set_master(pdev);
  4657. bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  4658. if (bp->pm_cap == 0) {
  4659. dev_err(&pdev->dev,
  4660. "Cannot find power management capability, aborting.\n");
  4661. rc = -EIO;
  4662. goto err_out_release;
  4663. }
  4664. if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
  4665. bp->flags |= USING_DAC_FLAG;
  4666. if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
  4667. dev_err(&pdev->dev,
  4668. "pci_set_consistent_dma_mask failed, aborting.\n");
  4669. rc = -EIO;
  4670. goto err_out_release;
  4671. }
  4672. }
  4673. else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
  4674. dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
  4675. rc = -EIO;
  4676. goto err_out_release;
  4677. }
  4678. bp->dev = dev;
  4679. bp->pdev = pdev;
  4680. spin_lock_init(&bp->phy_lock);
  4681. INIT_WORK(&bp->reset_task, bnx2_reset_task);
  4682. dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
  4683. mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
  4684. dev->mem_end = dev->mem_start + mem_len;
  4685. dev->irq = pdev->irq;
  4686. bp->regview = ioremap_nocache(dev->base_addr, mem_len);
  4687. if (!bp->regview) {
  4688. dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
  4689. rc = -ENOMEM;
  4690. goto err_out_release;
  4691. }
  4692. /* Configure byte swap and enable write to the reg_window registers.
  4693. * Rely on CPU to do target byte swapping on big endian systems
  4694. * The chip's target access swapping will not swap all accesses
  4695. */
  4696. pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
  4697. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  4698. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
  4699. bnx2_set_power_state(bp, PCI_D0);
  4700. bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
  4701. if (CHIP_NUM(bp) != CHIP_NUM_5709) {
  4702. bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
  4703. if (bp->pcix_cap == 0) {
  4704. dev_err(&pdev->dev,
  4705. "Cannot find PCIX capability, aborting.\n");
  4706. rc = -EIO;
  4707. goto err_out_unmap;
  4708. }
  4709. }
  4710. /* Get bus information. */
  4711. reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
  4712. if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
  4713. u32 clkreg;
  4714. bp->flags |= PCIX_FLAG;
  4715. clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
  4716. clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
  4717. switch (clkreg) {
  4718. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
  4719. bp->bus_speed_mhz = 133;
  4720. break;
  4721. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
  4722. bp->bus_speed_mhz = 100;
  4723. break;
  4724. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
  4725. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
  4726. bp->bus_speed_mhz = 66;
  4727. break;
  4728. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
  4729. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
  4730. bp->bus_speed_mhz = 50;
  4731. break;
  4732. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
  4733. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
  4734. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
  4735. bp->bus_speed_mhz = 33;
  4736. break;
  4737. }
  4738. }
  4739. else {
  4740. if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
  4741. bp->bus_speed_mhz = 66;
  4742. else
  4743. bp->bus_speed_mhz = 33;
  4744. }
  4745. if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
  4746. bp->flags |= PCI_32BIT_FLAG;
  4747. /* 5706A0 may falsely detect SERR and PERR. */
  4748. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  4749. reg = REG_RD(bp, PCI_COMMAND);
  4750. reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  4751. REG_WR(bp, PCI_COMMAND, reg);
  4752. }
  4753. else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
  4754. !(bp->flags & PCIX_FLAG)) {
  4755. dev_err(&pdev->dev,
  4756. "5706 A1 can only be used in a PCIX bus, aborting.\n");
  4757. goto err_out_unmap;
  4758. }
  4759. bnx2_init_nvram(bp);
  4760. reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
  4761. if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
  4762. BNX2_SHM_HDR_SIGNATURE_SIG) {
  4763. u32 off = PCI_FUNC(pdev->devfn) << 2;
  4764. bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off);
  4765. } else
  4766. bp->shmem_base = HOST_VIEW_SHMEM_BASE;
  4767. /* Get the permanent MAC address. First we need to make sure the
  4768. * firmware is actually running.
  4769. */
  4770. reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
  4771. if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
  4772. BNX2_DEV_INFO_SIGNATURE_MAGIC) {
  4773. dev_err(&pdev->dev, "Firmware not running, aborting.\n");
  4774. rc = -ENODEV;
  4775. goto err_out_unmap;
  4776. }
  4777. bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
  4778. reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
  4779. bp->mac_addr[0] = (u8) (reg >> 8);
  4780. bp->mac_addr[1] = (u8) reg;
  4781. reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
  4782. bp->mac_addr[2] = (u8) (reg >> 24);
  4783. bp->mac_addr[3] = (u8) (reg >> 16);
  4784. bp->mac_addr[4] = (u8) (reg >> 8);
  4785. bp->mac_addr[5] = (u8) reg;
  4786. bp->tx_ring_size = MAX_TX_DESC_CNT;
  4787. bnx2_set_rx_ring_size(bp, 255);
  4788. bp->rx_csum = 1;
  4789. bp->rx_offset = sizeof(struct l2_fhdr) + 2;
  4790. bp->tx_quick_cons_trip_int = 20;
  4791. bp->tx_quick_cons_trip = 20;
  4792. bp->tx_ticks_int = 80;
  4793. bp->tx_ticks = 80;
  4794. bp->rx_quick_cons_trip_int = 6;
  4795. bp->rx_quick_cons_trip = 6;
  4796. bp->rx_ticks_int = 18;
  4797. bp->rx_ticks = 18;
  4798. bp->stats_ticks = 1000000 & 0xffff00;
  4799. bp->timer_interval = HZ;
  4800. bp->current_interval = HZ;
  4801. bp->phy_addr = 1;
  4802. /* Disable WOL support if we are running on a SERDES chip. */
  4803. if (CHIP_NUM(bp) == CHIP_NUM_5709)
  4804. bnx2_get_5709_media(bp);
  4805. else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
  4806. bp->phy_flags |= PHY_SERDES_FLAG;
  4807. if (bp->phy_flags & PHY_SERDES_FLAG) {
  4808. bp->flags |= NO_WOL_FLAG;
  4809. if (CHIP_NUM(bp) != CHIP_NUM_5706) {
  4810. bp->phy_addr = 2;
  4811. reg = REG_RD_IND(bp, bp->shmem_base +
  4812. BNX2_SHARED_HW_CFG_CONFIG);
  4813. if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
  4814. bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
  4815. }
  4816. } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
  4817. CHIP_NUM(bp) == CHIP_NUM_5708)
  4818. bp->phy_flags |= PHY_CRC_FIX_FLAG;
  4819. else if (CHIP_ID(bp) == CHIP_ID_5709_A0)
  4820. bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG;
  4821. if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
  4822. (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
  4823. (CHIP_ID(bp) == CHIP_ID_5708_B1))
  4824. bp->flags |= NO_WOL_FLAG;
  4825. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  4826. bp->tx_quick_cons_trip_int =
  4827. bp->tx_quick_cons_trip;
  4828. bp->tx_ticks_int = bp->tx_ticks;
  4829. bp->rx_quick_cons_trip_int =
  4830. bp->rx_quick_cons_trip;
  4831. bp->rx_ticks_int = bp->rx_ticks;
  4832. bp->comp_prod_trip_int = bp->comp_prod_trip;
  4833. bp->com_ticks_int = bp->com_ticks;
  4834. bp->cmd_ticks_int = bp->cmd_ticks;
  4835. }
  4836. /* Disable MSI on 5706 if AMD 8132 bridge is found.
  4837. *
  4838. * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
  4839. * with byte enables disabled on the unused 32-bit word. This is legal
  4840. * but causes problems on the AMD 8132 which will eventually stop
  4841. * responding after a while.
  4842. *
  4843. * AMD believes this incompatibility is unique to the 5706, and
  4844. * prefers to locally disable MSI rather than globally disabling it.
  4845. */
  4846. if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
  4847. struct pci_dev *amd_8132 = NULL;
  4848. while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
  4849. PCI_DEVICE_ID_AMD_8132_BRIDGE,
  4850. amd_8132))) {
  4851. u8 rev;
  4852. pci_read_config_byte(amd_8132, PCI_REVISION_ID, &rev);
  4853. if (rev >= 0x10 && rev <= 0x13) {
  4854. disable_msi = 1;
  4855. pci_dev_put(amd_8132);
  4856. break;
  4857. }
  4858. }
  4859. }
  4860. bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
  4861. bp->req_line_speed = 0;
  4862. if (bp->phy_flags & PHY_SERDES_FLAG) {
  4863. bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
  4864. reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
  4865. reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
  4866. if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
  4867. bp->autoneg = 0;
  4868. bp->req_line_speed = bp->line_speed = SPEED_1000;
  4869. bp->req_duplex = DUPLEX_FULL;
  4870. }
  4871. }
  4872. else {
  4873. bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
  4874. }
  4875. bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
  4876. init_timer(&bp->timer);
  4877. bp->timer.expires = RUN_AT(bp->timer_interval);
  4878. bp->timer.data = (unsigned long) bp;
  4879. bp->timer.function = bnx2_timer;
  4880. return 0;
  4881. err_out_unmap:
  4882. if (bp->regview) {
  4883. iounmap(bp->regview);
  4884. bp->regview = NULL;
  4885. }
  4886. err_out_release:
  4887. pci_release_regions(pdev);
  4888. err_out_disable:
  4889. pci_disable_device(pdev);
  4890. pci_set_drvdata(pdev, NULL);
  4891. err_out:
  4892. return rc;
  4893. }
  4894. static int __devinit
  4895. bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  4896. {
  4897. static int version_printed = 0;
  4898. struct net_device *dev = NULL;
  4899. struct bnx2 *bp;
  4900. int rc, i;
  4901. if (version_printed++ == 0)
  4902. printk(KERN_INFO "%s", version);
  4903. /* dev zeroed in init_etherdev */
  4904. dev = alloc_etherdev(sizeof(*bp));
  4905. if (!dev)
  4906. return -ENOMEM;
  4907. rc = bnx2_init_board(pdev, dev);
  4908. if (rc < 0) {
  4909. free_netdev(dev);
  4910. return rc;
  4911. }
  4912. dev->open = bnx2_open;
  4913. dev->hard_start_xmit = bnx2_start_xmit;
  4914. dev->stop = bnx2_close;
  4915. dev->get_stats = bnx2_get_stats;
  4916. dev->set_multicast_list = bnx2_set_rx_mode;
  4917. dev->do_ioctl = bnx2_ioctl;
  4918. dev->set_mac_address = bnx2_change_mac_addr;
  4919. dev->change_mtu = bnx2_change_mtu;
  4920. dev->tx_timeout = bnx2_tx_timeout;
  4921. dev->watchdog_timeo = TX_TIMEOUT;
  4922. #ifdef BCM_VLAN
  4923. dev->vlan_rx_register = bnx2_vlan_rx_register;
  4924. dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
  4925. #endif
  4926. dev->poll = bnx2_poll;
  4927. dev->ethtool_ops = &bnx2_ethtool_ops;
  4928. dev->weight = 64;
  4929. bp = netdev_priv(dev);
  4930. #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
  4931. dev->poll_controller = poll_bnx2;
  4932. #endif
  4933. if ((rc = register_netdev(dev))) {
  4934. dev_err(&pdev->dev, "Cannot register net device\n");
  4935. if (bp->regview)
  4936. iounmap(bp->regview);
  4937. pci_release_regions(pdev);
  4938. pci_disable_device(pdev);
  4939. pci_set_drvdata(pdev, NULL);
  4940. free_netdev(dev);
  4941. return rc;
  4942. }
  4943. pci_set_drvdata(pdev, dev);
  4944. memcpy(dev->dev_addr, bp->mac_addr, 6);
  4945. memcpy(dev->perm_addr, bp->mac_addr, 6);
  4946. bp->name = board_info[ent->driver_data].name,
  4947. printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
  4948. "IRQ %d, ",
  4949. dev->name,
  4950. bp->name,
  4951. ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
  4952. ((CHIP_ID(bp) & 0x0ff0) >> 4),
  4953. ((bp->flags & PCIX_FLAG) ? "-X" : ""),
  4954. ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
  4955. bp->bus_speed_mhz,
  4956. dev->base_addr,
  4957. bp->pdev->irq);
  4958. printk("node addr ");
  4959. for (i = 0; i < 6; i++)
  4960. printk("%2.2x", dev->dev_addr[i]);
  4961. printk("\n");
  4962. dev->features |= NETIF_F_SG;
  4963. if (bp->flags & USING_DAC_FLAG)
  4964. dev->features |= NETIF_F_HIGHDMA;
  4965. dev->features |= NETIF_F_IP_CSUM;
  4966. #ifdef BCM_VLAN
  4967. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  4968. #endif
  4969. dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
  4970. netif_carrier_off(bp->dev);
  4971. return 0;
  4972. }
  4973. static void __devexit
  4974. bnx2_remove_one(struct pci_dev *pdev)
  4975. {
  4976. struct net_device *dev = pci_get_drvdata(pdev);
  4977. struct bnx2 *bp = netdev_priv(dev);
  4978. flush_scheduled_work();
  4979. unregister_netdev(dev);
  4980. if (bp->regview)
  4981. iounmap(bp->regview);
  4982. free_netdev(dev);
  4983. pci_release_regions(pdev);
  4984. pci_disable_device(pdev);
  4985. pci_set_drvdata(pdev, NULL);
  4986. }
  4987. static int
  4988. bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
  4989. {
  4990. struct net_device *dev = pci_get_drvdata(pdev);
  4991. struct bnx2 *bp = netdev_priv(dev);
  4992. u32 reset_code;
  4993. if (!netif_running(dev))
  4994. return 0;
  4995. flush_scheduled_work();
  4996. bnx2_netif_stop(bp);
  4997. netif_device_detach(dev);
  4998. del_timer_sync(&bp->timer);
  4999. if (bp->flags & NO_WOL_FLAG)
  5000. reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
  5001. else if (bp->wol)
  5002. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
  5003. else
  5004. reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
  5005. bnx2_reset_chip(bp, reset_code);
  5006. bnx2_free_skbs(bp);
  5007. pci_save_state(pdev);
  5008. bnx2_set_power_state(bp, pci_choose_state(pdev, state));
  5009. return 0;
  5010. }
  5011. static int
  5012. bnx2_resume(struct pci_dev *pdev)
  5013. {
  5014. struct net_device *dev = pci_get_drvdata(pdev);
  5015. struct bnx2 *bp = netdev_priv(dev);
  5016. if (!netif_running(dev))
  5017. return 0;
  5018. pci_restore_state(pdev);
  5019. bnx2_set_power_state(bp, PCI_D0);
  5020. netif_device_attach(dev);
  5021. bnx2_init_nic(bp);
  5022. bnx2_netif_start(bp);
  5023. return 0;
  5024. }
  5025. static struct pci_driver bnx2_pci_driver = {
  5026. .name = DRV_MODULE_NAME,
  5027. .id_table = bnx2_pci_tbl,
  5028. .probe = bnx2_init_one,
  5029. .remove = __devexit_p(bnx2_remove_one),
  5030. .suspend = bnx2_suspend,
  5031. .resume = bnx2_resume,
  5032. };
  5033. static int __init bnx2_init(void)
  5034. {
  5035. return pci_register_driver(&bnx2_pci_driver);
  5036. }
  5037. static void __exit bnx2_cleanup(void)
  5038. {
  5039. pci_unregister_driver(&bnx2_pci_driver);
  5040. }
  5041. module_init(bnx2_init);
  5042. module_exit(bnx2_cleanup);