bmac.c 41 KB

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  1. /*
  2. * Network device driver for the BMAC ethernet controller on
  3. * Apple Powermacs. Assumes it's under a DBDMA controller.
  4. *
  5. * Copyright (C) 1998 Randy Gobbel.
  6. *
  7. * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to
  8. * dynamic procfs inode.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/delay.h>
  15. #include <linux/string.h>
  16. #include <linux/timer.h>
  17. #include <linux/proc_fs.h>
  18. #include <linux/init.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/crc32.h>
  21. #include <linux/bitrev.h>
  22. #include <asm/prom.h>
  23. #include <asm/dbdma.h>
  24. #include <asm/io.h>
  25. #include <asm/page.h>
  26. #include <asm/pgtable.h>
  27. #include <asm/machdep.h>
  28. #include <asm/pmac_feature.h>
  29. #include <asm/macio.h>
  30. #include <asm/irq.h>
  31. #include "bmac.h"
  32. #define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1))))
  33. #define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1)))
  34. /*
  35. * CRC polynomial - used in working out multicast filter bits.
  36. */
  37. #define ENET_CRCPOLY 0x04c11db7
  38. /* switch to use multicast code lifted from sunhme driver */
  39. #define SUNHME_MULTICAST
  40. #define N_RX_RING 64
  41. #define N_TX_RING 32
  42. #define MAX_TX_ACTIVE 1
  43. #define ETHERCRC 4
  44. #define ETHERMINPACKET 64
  45. #define ETHERMTU 1500
  46. #define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2)
  47. #define TX_TIMEOUT HZ /* 1 second */
  48. /* Bits in transmit DMA status */
  49. #define TX_DMA_ERR 0x80
  50. #define XXDEBUG(args)
  51. struct bmac_data {
  52. /* volatile struct bmac *bmac; */
  53. struct sk_buff_head *queue;
  54. volatile struct dbdma_regs __iomem *tx_dma;
  55. int tx_dma_intr;
  56. volatile struct dbdma_regs __iomem *rx_dma;
  57. int rx_dma_intr;
  58. volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
  59. volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
  60. struct macio_dev *mdev;
  61. int is_bmac_plus;
  62. struct sk_buff *rx_bufs[N_RX_RING];
  63. int rx_fill;
  64. int rx_empty;
  65. struct sk_buff *tx_bufs[N_TX_RING];
  66. int tx_fill;
  67. int tx_empty;
  68. unsigned char tx_fullup;
  69. struct net_device_stats stats;
  70. struct timer_list tx_timeout;
  71. int timeout_active;
  72. int sleeping;
  73. int opened;
  74. unsigned short hash_use_count[64];
  75. unsigned short hash_table_mask[4];
  76. spinlock_t lock;
  77. };
  78. #if 0 /* Move that to ethtool */
  79. typedef struct bmac_reg_entry {
  80. char *name;
  81. unsigned short reg_offset;
  82. } bmac_reg_entry_t;
  83. #define N_REG_ENTRIES 31
  84. static bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = {
  85. {"MEMADD", MEMADD},
  86. {"MEMDATAHI", MEMDATAHI},
  87. {"MEMDATALO", MEMDATALO},
  88. {"TXPNTR", TXPNTR},
  89. {"RXPNTR", RXPNTR},
  90. {"IPG1", IPG1},
  91. {"IPG2", IPG2},
  92. {"ALIMIT", ALIMIT},
  93. {"SLOT", SLOT},
  94. {"PALEN", PALEN},
  95. {"PAPAT", PAPAT},
  96. {"TXSFD", TXSFD},
  97. {"JAM", JAM},
  98. {"TXCFG", TXCFG},
  99. {"TXMAX", TXMAX},
  100. {"TXMIN", TXMIN},
  101. {"PAREG", PAREG},
  102. {"DCNT", DCNT},
  103. {"NCCNT", NCCNT},
  104. {"NTCNT", NTCNT},
  105. {"EXCNT", EXCNT},
  106. {"LTCNT", LTCNT},
  107. {"TXSM", TXSM},
  108. {"RXCFG", RXCFG},
  109. {"RXMAX", RXMAX},
  110. {"RXMIN", RXMIN},
  111. {"FRCNT", FRCNT},
  112. {"AECNT", AECNT},
  113. {"FECNT", FECNT},
  114. {"RXSM", RXSM},
  115. {"RXCV", RXCV}
  116. };
  117. #endif
  118. static unsigned char *bmac_emergency_rxbuf;
  119. /*
  120. * Number of bytes of private data per BMAC: allow enough for
  121. * the rx and tx dma commands plus a branch dma command each,
  122. * and another 16 bytes to allow us to align the dma command
  123. * buffers on a 16 byte boundary.
  124. */
  125. #define PRIV_BYTES (sizeof(struct bmac_data) \
  126. + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \
  127. + sizeof(struct sk_buff_head))
  128. static int bmac_open(struct net_device *dev);
  129. static int bmac_close(struct net_device *dev);
  130. static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev);
  131. static struct net_device_stats *bmac_stats(struct net_device *dev);
  132. static void bmac_set_multicast(struct net_device *dev);
  133. static void bmac_reset_and_enable(struct net_device *dev);
  134. static void bmac_start_chip(struct net_device *dev);
  135. static void bmac_init_chip(struct net_device *dev);
  136. static void bmac_init_registers(struct net_device *dev);
  137. static void bmac_enable_and_reset_chip(struct net_device *dev);
  138. static int bmac_set_address(struct net_device *dev, void *addr);
  139. static irqreturn_t bmac_misc_intr(int irq, void *dev_id);
  140. static irqreturn_t bmac_txdma_intr(int irq, void *dev_id);
  141. static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id);
  142. static void bmac_set_timeout(struct net_device *dev);
  143. static void bmac_tx_timeout(unsigned long data);
  144. static int bmac_output(struct sk_buff *skb, struct net_device *dev);
  145. static void bmac_start(struct net_device *dev);
  146. #define DBDMA_SET(x) ( ((x) | (x) << 16) )
  147. #define DBDMA_CLEAR(x) ( (x) << 16)
  148. static inline void
  149. dbdma_st32(volatile __u32 __iomem *a, unsigned long x)
  150. {
  151. __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory");
  152. return;
  153. }
  154. static inline unsigned long
  155. dbdma_ld32(volatile __u32 __iomem *a)
  156. {
  157. __u32 swap;
  158. __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a));
  159. return swap;
  160. }
  161. static void
  162. dbdma_continue(volatile struct dbdma_regs __iomem *dmap)
  163. {
  164. dbdma_st32(&dmap->control,
  165. DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD));
  166. eieio();
  167. }
  168. static void
  169. dbdma_reset(volatile struct dbdma_regs __iomem *dmap)
  170. {
  171. dbdma_st32(&dmap->control,
  172. DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN));
  173. eieio();
  174. while (dbdma_ld32(&dmap->status) & RUN)
  175. eieio();
  176. }
  177. static void
  178. dbdma_setcmd(volatile struct dbdma_cmd *cp,
  179. unsigned short cmd, unsigned count, unsigned long addr,
  180. unsigned long cmd_dep)
  181. {
  182. out_le16(&cp->command, cmd);
  183. out_le16(&cp->req_count, count);
  184. out_le32(&cp->phy_addr, addr);
  185. out_le32(&cp->cmd_dep, cmd_dep);
  186. out_le16(&cp->xfer_status, 0);
  187. out_le16(&cp->res_count, 0);
  188. }
  189. static inline
  190. void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )
  191. {
  192. out_le16((void __iomem *)dev->base_addr + reg_offset, data);
  193. }
  194. static inline
  195. unsigned short bmread(struct net_device *dev, unsigned long reg_offset )
  196. {
  197. return in_le16((void __iomem *)dev->base_addr + reg_offset);
  198. }
  199. static void
  200. bmac_enable_and_reset_chip(struct net_device *dev)
  201. {
  202. struct bmac_data *bp = netdev_priv(dev);
  203. volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
  204. volatile struct dbdma_regs __iomem *td = bp->tx_dma;
  205. if (rd)
  206. dbdma_reset(rd);
  207. if (td)
  208. dbdma_reset(td);
  209. pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 1);
  210. }
  211. #define MIFDELAY udelay(10)
  212. static unsigned int
  213. bmac_mif_readbits(struct net_device *dev, int nb)
  214. {
  215. unsigned int val = 0;
  216. while (--nb >= 0) {
  217. bmwrite(dev, MIFCSR, 0);
  218. MIFDELAY;
  219. if (bmread(dev, MIFCSR) & 8)
  220. val |= 1 << nb;
  221. bmwrite(dev, MIFCSR, 1);
  222. MIFDELAY;
  223. }
  224. bmwrite(dev, MIFCSR, 0);
  225. MIFDELAY;
  226. bmwrite(dev, MIFCSR, 1);
  227. MIFDELAY;
  228. return val;
  229. }
  230. static void
  231. bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb)
  232. {
  233. int b;
  234. while (--nb >= 0) {
  235. b = (val & (1 << nb))? 6: 4;
  236. bmwrite(dev, MIFCSR, b);
  237. MIFDELAY;
  238. bmwrite(dev, MIFCSR, b|1);
  239. MIFDELAY;
  240. }
  241. }
  242. static unsigned int
  243. bmac_mif_read(struct net_device *dev, unsigned int addr)
  244. {
  245. unsigned int val;
  246. bmwrite(dev, MIFCSR, 4);
  247. MIFDELAY;
  248. bmac_mif_writebits(dev, ~0U, 32);
  249. bmac_mif_writebits(dev, 6, 4);
  250. bmac_mif_writebits(dev, addr, 10);
  251. bmwrite(dev, MIFCSR, 2);
  252. MIFDELAY;
  253. bmwrite(dev, MIFCSR, 1);
  254. MIFDELAY;
  255. val = bmac_mif_readbits(dev, 17);
  256. bmwrite(dev, MIFCSR, 4);
  257. MIFDELAY;
  258. return val;
  259. }
  260. static void
  261. bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val)
  262. {
  263. bmwrite(dev, MIFCSR, 4);
  264. MIFDELAY;
  265. bmac_mif_writebits(dev, ~0U, 32);
  266. bmac_mif_writebits(dev, 5, 4);
  267. bmac_mif_writebits(dev, addr, 10);
  268. bmac_mif_writebits(dev, 2, 2);
  269. bmac_mif_writebits(dev, val, 16);
  270. bmac_mif_writebits(dev, 3, 2);
  271. }
  272. static void
  273. bmac_init_registers(struct net_device *dev)
  274. {
  275. struct bmac_data *bp = netdev_priv(dev);
  276. volatile unsigned short regValue;
  277. unsigned short *pWord16;
  278. int i;
  279. /* XXDEBUG(("bmac: enter init_registers\n")); */
  280. bmwrite(dev, RXRST, RxResetValue);
  281. bmwrite(dev, TXRST, TxResetBit);
  282. i = 100;
  283. do {
  284. --i;
  285. udelay(10000);
  286. regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */
  287. } while ((regValue & TxResetBit) && i > 0);
  288. if (!bp->is_bmac_plus) {
  289. regValue = bmread(dev, XCVRIF);
  290. regValue |= ClkBit | SerialMode | COLActiveLow;
  291. bmwrite(dev, XCVRIF, regValue);
  292. udelay(10000);
  293. }
  294. bmwrite(dev, RSEED, (unsigned short)0x1968);
  295. regValue = bmread(dev, XIFC);
  296. regValue |= TxOutputEnable;
  297. bmwrite(dev, XIFC, regValue);
  298. bmread(dev, PAREG);
  299. /* set collision counters to 0 */
  300. bmwrite(dev, NCCNT, 0);
  301. bmwrite(dev, NTCNT, 0);
  302. bmwrite(dev, EXCNT, 0);
  303. bmwrite(dev, LTCNT, 0);
  304. /* set rx counters to 0 */
  305. bmwrite(dev, FRCNT, 0);
  306. bmwrite(dev, LECNT, 0);
  307. bmwrite(dev, AECNT, 0);
  308. bmwrite(dev, FECNT, 0);
  309. bmwrite(dev, RXCV, 0);
  310. /* set tx fifo information */
  311. bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */
  312. bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */
  313. bmwrite(dev, TXFIFOCSR, TxFIFOEnable );
  314. /* set rx fifo information */
  315. bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
  316. bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
  317. //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */
  318. bmread(dev, STATUS); /* read it just to clear it */
  319. /* zero out the chip Hash Filter registers */
  320. for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
  321. bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
  322. bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
  323. bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
  324. bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
  325. pWord16 = (unsigned short *)dev->dev_addr;
  326. bmwrite(dev, MADD0, *pWord16++);
  327. bmwrite(dev, MADD1, *pWord16++);
  328. bmwrite(dev, MADD2, *pWord16);
  329. bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);
  330. bmwrite(dev, INTDISABLE, EnableNormal);
  331. return;
  332. }
  333. #if 0
  334. static void
  335. bmac_disable_interrupts(struct net_device *dev)
  336. {
  337. bmwrite(dev, INTDISABLE, DisableAll);
  338. }
  339. static void
  340. bmac_enable_interrupts(struct net_device *dev)
  341. {
  342. bmwrite(dev, INTDISABLE, EnableNormal);
  343. }
  344. #endif
  345. static void
  346. bmac_start_chip(struct net_device *dev)
  347. {
  348. struct bmac_data *bp = netdev_priv(dev);
  349. volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
  350. unsigned short oldConfig;
  351. /* enable rx dma channel */
  352. dbdma_continue(rd);
  353. oldConfig = bmread(dev, TXCFG);
  354. bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
  355. /* turn on rx plus any other bits already on (promiscuous possibly) */
  356. oldConfig = bmread(dev, RXCFG);
  357. bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
  358. udelay(20000);
  359. }
  360. static void
  361. bmac_init_phy(struct net_device *dev)
  362. {
  363. unsigned int addr;
  364. struct bmac_data *bp = netdev_priv(dev);
  365. printk(KERN_DEBUG "phy registers:");
  366. for (addr = 0; addr < 32; ++addr) {
  367. if ((addr & 7) == 0)
  368. printk("\n" KERN_DEBUG);
  369. printk(" %.4x", bmac_mif_read(dev, addr));
  370. }
  371. printk("\n");
  372. if (bp->is_bmac_plus) {
  373. unsigned int capable, ctrl;
  374. ctrl = bmac_mif_read(dev, 0);
  375. capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1;
  376. if (bmac_mif_read(dev, 4) != capable
  377. || (ctrl & 0x1000) == 0) {
  378. bmac_mif_write(dev, 4, capable);
  379. bmac_mif_write(dev, 0, 0x1200);
  380. } else
  381. bmac_mif_write(dev, 0, 0x1000);
  382. }
  383. }
  384. static void bmac_init_chip(struct net_device *dev)
  385. {
  386. bmac_init_phy(dev);
  387. bmac_init_registers(dev);
  388. }
  389. #ifdef CONFIG_PM
  390. static int bmac_suspend(struct macio_dev *mdev, pm_message_t state)
  391. {
  392. struct net_device* dev = macio_get_drvdata(mdev);
  393. struct bmac_data *bp = netdev_priv(dev);
  394. unsigned long flags;
  395. unsigned short config;
  396. int i;
  397. netif_device_detach(dev);
  398. /* prolly should wait for dma to finish & turn off the chip */
  399. spin_lock_irqsave(&bp->lock, flags);
  400. if (bp->timeout_active) {
  401. del_timer(&bp->tx_timeout);
  402. bp->timeout_active = 0;
  403. }
  404. disable_irq(dev->irq);
  405. disable_irq(bp->tx_dma_intr);
  406. disable_irq(bp->rx_dma_intr);
  407. bp->sleeping = 1;
  408. spin_unlock_irqrestore(&bp->lock, flags);
  409. if (bp->opened) {
  410. volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
  411. volatile struct dbdma_regs __iomem *td = bp->tx_dma;
  412. config = bmread(dev, RXCFG);
  413. bmwrite(dev, RXCFG, (config & ~RxMACEnable));
  414. config = bmread(dev, TXCFG);
  415. bmwrite(dev, TXCFG, (config & ~TxMACEnable));
  416. bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
  417. /* disable rx and tx dma */
  418. st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
  419. st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
  420. /* free some skb's */
  421. for (i=0; i<N_RX_RING; i++) {
  422. if (bp->rx_bufs[i] != NULL) {
  423. dev_kfree_skb(bp->rx_bufs[i]);
  424. bp->rx_bufs[i] = NULL;
  425. }
  426. }
  427. for (i = 0; i<N_TX_RING; i++) {
  428. if (bp->tx_bufs[i] != NULL) {
  429. dev_kfree_skb(bp->tx_bufs[i]);
  430. bp->tx_bufs[i] = NULL;
  431. }
  432. }
  433. }
  434. pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
  435. return 0;
  436. }
  437. static int bmac_resume(struct macio_dev *mdev)
  438. {
  439. struct net_device* dev = macio_get_drvdata(mdev);
  440. struct bmac_data *bp = netdev_priv(dev);
  441. /* see if this is enough */
  442. if (bp->opened)
  443. bmac_reset_and_enable(dev);
  444. enable_irq(dev->irq);
  445. enable_irq(bp->tx_dma_intr);
  446. enable_irq(bp->rx_dma_intr);
  447. netif_device_attach(dev);
  448. return 0;
  449. }
  450. #endif /* CONFIG_PM */
  451. static int bmac_set_address(struct net_device *dev, void *addr)
  452. {
  453. struct bmac_data *bp = netdev_priv(dev);
  454. unsigned char *p = addr;
  455. unsigned short *pWord16;
  456. unsigned long flags;
  457. int i;
  458. XXDEBUG(("bmac: enter set_address\n"));
  459. spin_lock_irqsave(&bp->lock, flags);
  460. for (i = 0; i < 6; ++i) {
  461. dev->dev_addr[i] = p[i];
  462. }
  463. /* load up the hardware address */
  464. pWord16 = (unsigned short *)dev->dev_addr;
  465. bmwrite(dev, MADD0, *pWord16++);
  466. bmwrite(dev, MADD1, *pWord16++);
  467. bmwrite(dev, MADD2, *pWord16);
  468. spin_unlock_irqrestore(&bp->lock, flags);
  469. XXDEBUG(("bmac: exit set_address\n"));
  470. return 0;
  471. }
  472. static inline void bmac_set_timeout(struct net_device *dev)
  473. {
  474. struct bmac_data *bp = netdev_priv(dev);
  475. unsigned long flags;
  476. spin_lock_irqsave(&bp->lock, flags);
  477. if (bp->timeout_active)
  478. del_timer(&bp->tx_timeout);
  479. bp->tx_timeout.expires = jiffies + TX_TIMEOUT;
  480. bp->tx_timeout.function = bmac_tx_timeout;
  481. bp->tx_timeout.data = (unsigned long) dev;
  482. add_timer(&bp->tx_timeout);
  483. bp->timeout_active = 1;
  484. spin_unlock_irqrestore(&bp->lock, flags);
  485. }
  486. static void
  487. bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
  488. {
  489. void *vaddr;
  490. unsigned long baddr;
  491. unsigned long len;
  492. len = skb->len;
  493. vaddr = skb->data;
  494. baddr = virt_to_bus(vaddr);
  495. dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0);
  496. }
  497. static void
  498. bmac_construct_rxbuff(struct sk_buff *skb, volatile struct dbdma_cmd *cp)
  499. {
  500. unsigned char *addr = skb? skb->data: bmac_emergency_rxbuf;
  501. dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN,
  502. virt_to_bus(addr), 0);
  503. }
  504. static void
  505. bmac_init_tx_ring(struct bmac_data *bp)
  506. {
  507. volatile struct dbdma_regs __iomem *td = bp->tx_dma;
  508. memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd));
  509. bp->tx_empty = 0;
  510. bp->tx_fill = 0;
  511. bp->tx_fullup = 0;
  512. /* put a branch at the end of the tx command list */
  513. dbdma_setcmd(&bp->tx_cmds[N_TX_RING],
  514. (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds));
  515. /* reset tx dma */
  516. dbdma_reset(td);
  517. out_le32(&td->wait_sel, 0x00200020);
  518. out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds));
  519. }
  520. static int
  521. bmac_init_rx_ring(struct bmac_data *bp)
  522. {
  523. volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
  524. int i;
  525. struct sk_buff *skb;
  526. /* initialize list of sk_buffs for receiving and set up recv dma */
  527. memset((char *)bp->rx_cmds, 0,
  528. (N_RX_RING + 1) * sizeof(struct dbdma_cmd));
  529. for (i = 0; i < N_RX_RING; i++) {
  530. if ((skb = bp->rx_bufs[i]) == NULL) {
  531. bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
  532. if (skb != NULL)
  533. skb_reserve(skb, 2);
  534. }
  535. bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
  536. }
  537. bp->rx_empty = 0;
  538. bp->rx_fill = i;
  539. /* Put a branch back to the beginning of the receive command list */
  540. dbdma_setcmd(&bp->rx_cmds[N_RX_RING],
  541. (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds));
  542. /* start rx dma */
  543. dbdma_reset(rd);
  544. out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds));
  545. return 1;
  546. }
  547. static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev)
  548. {
  549. struct bmac_data *bp = netdev_priv(dev);
  550. volatile struct dbdma_regs __iomem *td = bp->tx_dma;
  551. int i;
  552. /* see if there's a free slot in the tx ring */
  553. /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */
  554. /* bp->tx_empty, bp->tx_fill)); */
  555. i = bp->tx_fill + 1;
  556. if (i >= N_TX_RING)
  557. i = 0;
  558. if (i == bp->tx_empty) {
  559. netif_stop_queue(dev);
  560. bp->tx_fullup = 1;
  561. XXDEBUG(("bmac_transmit_packet: tx ring full\n"));
  562. return -1; /* can't take it at the moment */
  563. }
  564. dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0);
  565. bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]);
  566. bp->tx_bufs[bp->tx_fill] = skb;
  567. bp->tx_fill = i;
  568. bp->stats.tx_bytes += skb->len;
  569. dbdma_continue(td);
  570. return 0;
  571. }
  572. static int rxintcount;
  573. static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id)
  574. {
  575. struct net_device *dev = (struct net_device *) dev_id;
  576. struct bmac_data *bp = netdev_priv(dev);
  577. volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
  578. volatile struct dbdma_cmd *cp;
  579. int i, nb, stat;
  580. struct sk_buff *skb;
  581. unsigned int residual;
  582. int last;
  583. unsigned long flags;
  584. spin_lock_irqsave(&bp->lock, flags);
  585. if (++rxintcount < 10) {
  586. XXDEBUG(("bmac_rxdma_intr\n"));
  587. }
  588. last = -1;
  589. i = bp->rx_empty;
  590. while (1) {
  591. cp = &bp->rx_cmds[i];
  592. stat = ld_le16(&cp->xfer_status);
  593. residual = ld_le16(&cp->res_count);
  594. if ((stat & ACTIVE) == 0)
  595. break;
  596. nb = RX_BUFLEN - residual - 2;
  597. if (nb < (ETHERMINPACKET - ETHERCRC)) {
  598. skb = NULL;
  599. bp->stats.rx_length_errors++;
  600. bp->stats.rx_errors++;
  601. } else {
  602. skb = bp->rx_bufs[i];
  603. bp->rx_bufs[i] = NULL;
  604. }
  605. if (skb != NULL) {
  606. nb -= ETHERCRC;
  607. skb_put(skb, nb);
  608. skb->dev = dev;
  609. skb->protocol = eth_type_trans(skb, dev);
  610. netif_rx(skb);
  611. dev->last_rx = jiffies;
  612. ++bp->stats.rx_packets;
  613. bp->stats.rx_bytes += nb;
  614. } else {
  615. ++bp->stats.rx_dropped;
  616. }
  617. dev->last_rx = jiffies;
  618. if ((skb = bp->rx_bufs[i]) == NULL) {
  619. bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2);
  620. if (skb != NULL)
  621. skb_reserve(bp->rx_bufs[i], 2);
  622. }
  623. bmac_construct_rxbuff(skb, &bp->rx_cmds[i]);
  624. st_le16(&cp->res_count, 0);
  625. st_le16(&cp->xfer_status, 0);
  626. last = i;
  627. if (++i >= N_RX_RING) i = 0;
  628. }
  629. if (last != -1) {
  630. bp->rx_fill = last;
  631. bp->rx_empty = i;
  632. }
  633. dbdma_continue(rd);
  634. spin_unlock_irqrestore(&bp->lock, flags);
  635. if (rxintcount < 10) {
  636. XXDEBUG(("bmac_rxdma_intr done\n"));
  637. }
  638. return IRQ_HANDLED;
  639. }
  640. static int txintcount;
  641. static irqreturn_t bmac_txdma_intr(int irq, void *dev_id)
  642. {
  643. struct net_device *dev = (struct net_device *) dev_id;
  644. struct bmac_data *bp = netdev_priv(dev);
  645. volatile struct dbdma_cmd *cp;
  646. int stat;
  647. unsigned long flags;
  648. spin_lock_irqsave(&bp->lock, flags);
  649. if (txintcount++ < 10) {
  650. XXDEBUG(("bmac_txdma_intr\n"));
  651. }
  652. /* del_timer(&bp->tx_timeout); */
  653. /* bp->timeout_active = 0; */
  654. while (1) {
  655. cp = &bp->tx_cmds[bp->tx_empty];
  656. stat = ld_le16(&cp->xfer_status);
  657. if (txintcount < 10) {
  658. XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat));
  659. }
  660. if (!(stat & ACTIVE)) {
  661. /*
  662. * status field might not have been filled by DBDMA
  663. */
  664. if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr)))
  665. break;
  666. }
  667. if (bp->tx_bufs[bp->tx_empty]) {
  668. ++bp->stats.tx_packets;
  669. dev_kfree_skb_irq(bp->tx_bufs[bp->tx_empty]);
  670. }
  671. bp->tx_bufs[bp->tx_empty] = NULL;
  672. bp->tx_fullup = 0;
  673. netif_wake_queue(dev);
  674. if (++bp->tx_empty >= N_TX_RING)
  675. bp->tx_empty = 0;
  676. if (bp->tx_empty == bp->tx_fill)
  677. break;
  678. }
  679. spin_unlock_irqrestore(&bp->lock, flags);
  680. if (txintcount < 10) {
  681. XXDEBUG(("bmac_txdma_intr done->bmac_start\n"));
  682. }
  683. bmac_start(dev);
  684. return IRQ_HANDLED;
  685. }
  686. static struct net_device_stats *bmac_stats(struct net_device *dev)
  687. {
  688. struct bmac_data *p = netdev_priv(dev);
  689. return &p->stats;
  690. }
  691. #ifndef SUNHME_MULTICAST
  692. /* Real fast bit-reversal algorithm, 6-bit values */
  693. static int reverse6[64] = {
  694. 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38,
  695. 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c,
  696. 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a,
  697. 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e,
  698. 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39,
  699. 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d,
  700. 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b,
  701. 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f
  702. };
  703. static unsigned int
  704. crc416(unsigned int curval, unsigned short nxtval)
  705. {
  706. register unsigned int counter, cur = curval, next = nxtval;
  707. register int high_crc_set, low_data_set;
  708. /* Swap bytes */
  709. next = ((next & 0x00FF) << 8) | (next >> 8);
  710. /* Compute bit-by-bit */
  711. for (counter = 0; counter < 16; ++counter) {
  712. /* is high CRC bit set? */
  713. if ((cur & 0x80000000) == 0) high_crc_set = 0;
  714. else high_crc_set = 1;
  715. cur = cur << 1;
  716. if ((next & 0x0001) == 0) low_data_set = 0;
  717. else low_data_set = 1;
  718. next = next >> 1;
  719. /* do the XOR */
  720. if (high_crc_set ^ low_data_set) cur = cur ^ ENET_CRCPOLY;
  721. }
  722. return cur;
  723. }
  724. static unsigned int
  725. bmac_crc(unsigned short *address)
  726. {
  727. unsigned int newcrc;
  728. XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address, address[1], address[2]));
  729. newcrc = crc416(0xffffffff, *address); /* address bits 47 - 32 */
  730. newcrc = crc416(newcrc, address[1]); /* address bits 31 - 16 */
  731. newcrc = crc416(newcrc, address[2]); /* address bits 15 - 0 */
  732. return(newcrc);
  733. }
  734. /*
  735. * Add requested mcast addr to BMac's hash table filter.
  736. *
  737. */
  738. static void
  739. bmac_addhash(struct bmac_data *bp, unsigned char *addr)
  740. {
  741. unsigned int crc;
  742. unsigned short mask;
  743. if (!(*addr)) return;
  744. crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
  745. crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
  746. if (bp->hash_use_count[crc]++) return; /* This bit is already set */
  747. mask = crc % 16;
  748. mask = (unsigned char)1 << mask;
  749. bp->hash_use_count[crc/16] |= mask;
  750. }
  751. static void
  752. bmac_removehash(struct bmac_data *bp, unsigned char *addr)
  753. {
  754. unsigned int crc;
  755. unsigned char mask;
  756. /* Now, delete the address from the filter copy, as indicated */
  757. crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */
  758. crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */
  759. if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */
  760. if (--bp->hash_use_count[crc]) return; /* That bit is still in use */
  761. mask = crc % 16;
  762. mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */
  763. bp->hash_table_mask[crc/16] &= mask;
  764. }
  765. /*
  766. * Sync the adapter with the software copy of the multicast mask
  767. * (logical address filter).
  768. */
  769. static void
  770. bmac_rx_off(struct net_device *dev)
  771. {
  772. unsigned short rx_cfg;
  773. rx_cfg = bmread(dev, RXCFG);
  774. rx_cfg &= ~RxMACEnable;
  775. bmwrite(dev, RXCFG, rx_cfg);
  776. do {
  777. rx_cfg = bmread(dev, RXCFG);
  778. } while (rx_cfg & RxMACEnable);
  779. }
  780. unsigned short
  781. bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable)
  782. {
  783. unsigned short rx_cfg;
  784. rx_cfg = bmread(dev, RXCFG);
  785. rx_cfg |= RxMACEnable;
  786. if (hash_enable) rx_cfg |= RxHashFilterEnable;
  787. else rx_cfg &= ~RxHashFilterEnable;
  788. if (promisc_enable) rx_cfg |= RxPromiscEnable;
  789. else rx_cfg &= ~RxPromiscEnable;
  790. bmwrite(dev, RXRST, RxResetValue);
  791. bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */
  792. bmwrite(dev, RXFIFOCSR, RxFIFOEnable );
  793. bmwrite(dev, RXCFG, rx_cfg );
  794. return rx_cfg;
  795. }
  796. static void
  797. bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp)
  798. {
  799. bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */
  800. bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */
  801. bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */
  802. bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */
  803. }
  804. #if 0
  805. static void
  806. bmac_add_multi(struct net_device *dev,
  807. struct bmac_data *bp, unsigned char *addr)
  808. {
  809. /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */
  810. bmac_addhash(bp, addr);
  811. bmac_rx_off(dev);
  812. bmac_update_hash_table_mask(dev, bp);
  813. bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
  814. /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */
  815. }
  816. static void
  817. bmac_remove_multi(struct net_device *dev,
  818. struct bmac_data *bp, unsigned char *addr)
  819. {
  820. bmac_removehash(bp, addr);
  821. bmac_rx_off(dev);
  822. bmac_update_hash_table_mask(dev, bp);
  823. bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0);
  824. }
  825. #endif
  826. /* Set or clear the multicast filter for this adaptor.
  827. num_addrs == -1 Promiscuous mode, receive all packets
  828. num_addrs == 0 Normal mode, clear multicast list
  829. num_addrs > 0 Multicast mode, receive normal and MC packets, and do
  830. best-effort filtering.
  831. */
  832. static void bmac_set_multicast(struct net_device *dev)
  833. {
  834. struct dev_mc_list *dmi;
  835. struct bmac_data *bp = netdev_priv(dev);
  836. int num_addrs = dev->mc_count;
  837. unsigned short rx_cfg;
  838. int i;
  839. if (bp->sleeping)
  840. return;
  841. XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs));
  842. if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
  843. for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff;
  844. bmac_update_hash_table_mask(dev, bp);
  845. rx_cfg = bmac_rx_on(dev, 1, 0);
  846. XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n"));
  847. } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) {
  848. rx_cfg = bmread(dev, RXCFG);
  849. rx_cfg |= RxPromiscEnable;
  850. bmwrite(dev, RXCFG, rx_cfg);
  851. rx_cfg = bmac_rx_on(dev, 0, 1);
  852. XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg));
  853. } else {
  854. for (i=0; i<4; i++) bp->hash_table_mask[i] = 0;
  855. for (i=0; i<64; i++) bp->hash_use_count[i] = 0;
  856. if (num_addrs == 0) {
  857. rx_cfg = bmac_rx_on(dev, 0, 0);
  858. XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg));
  859. } else {
  860. for (dmi=dev->mc_list; dmi!=NULL; dmi=dmi->next)
  861. bmac_addhash(bp, dmi->dmi_addr);
  862. bmac_update_hash_table_mask(dev, bp);
  863. rx_cfg = bmac_rx_on(dev, 1, 0);
  864. XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg));
  865. }
  866. }
  867. /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */
  868. }
  869. #else /* ifdef SUNHME_MULTICAST */
  870. /* The version of set_multicast below was lifted from sunhme.c */
  871. static void bmac_set_multicast(struct net_device *dev)
  872. {
  873. struct dev_mc_list *dmi = dev->mc_list;
  874. char *addrs;
  875. int i;
  876. unsigned short rx_cfg;
  877. u32 crc;
  878. if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
  879. bmwrite(dev, BHASH0, 0xffff);
  880. bmwrite(dev, BHASH1, 0xffff);
  881. bmwrite(dev, BHASH2, 0xffff);
  882. bmwrite(dev, BHASH3, 0xffff);
  883. } else if(dev->flags & IFF_PROMISC) {
  884. rx_cfg = bmread(dev, RXCFG);
  885. rx_cfg |= RxPromiscEnable;
  886. bmwrite(dev, RXCFG, rx_cfg);
  887. } else {
  888. u16 hash_table[4];
  889. rx_cfg = bmread(dev, RXCFG);
  890. rx_cfg &= ~RxPromiscEnable;
  891. bmwrite(dev, RXCFG, rx_cfg);
  892. for(i = 0; i < 4; i++) hash_table[i] = 0;
  893. for(i = 0; i < dev->mc_count; i++) {
  894. addrs = dmi->dmi_addr;
  895. dmi = dmi->next;
  896. if(!(*addrs & 1))
  897. continue;
  898. crc = ether_crc_le(6, addrs);
  899. crc >>= 26;
  900. hash_table[crc >> 4] |= 1 << (crc & 0xf);
  901. }
  902. bmwrite(dev, BHASH0, hash_table[0]);
  903. bmwrite(dev, BHASH1, hash_table[1]);
  904. bmwrite(dev, BHASH2, hash_table[2]);
  905. bmwrite(dev, BHASH3, hash_table[3]);
  906. }
  907. }
  908. #endif /* SUNHME_MULTICAST */
  909. static int miscintcount;
  910. static irqreturn_t bmac_misc_intr(int irq, void *dev_id)
  911. {
  912. struct net_device *dev = (struct net_device *) dev_id;
  913. struct bmac_data *bp = netdev_priv(dev);
  914. unsigned int status = bmread(dev, STATUS);
  915. if (miscintcount++ < 10) {
  916. XXDEBUG(("bmac_misc_intr\n"));
  917. }
  918. /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */
  919. /* bmac_txdma_intr_inner(irq, dev_id); */
  920. /* if (status & FrameReceived) bp->stats.rx_dropped++; */
  921. if (status & RxErrorMask) bp->stats.rx_errors++;
  922. if (status & RxCRCCntExp) bp->stats.rx_crc_errors++;
  923. if (status & RxLenCntExp) bp->stats.rx_length_errors++;
  924. if (status & RxOverFlow) bp->stats.rx_over_errors++;
  925. if (status & RxAlignCntExp) bp->stats.rx_frame_errors++;
  926. /* if (status & FrameSent) bp->stats.tx_dropped++; */
  927. if (status & TxErrorMask) bp->stats.tx_errors++;
  928. if (status & TxUnderrun) bp->stats.tx_fifo_errors++;
  929. if (status & TxNormalCollExp) bp->stats.collisions++;
  930. return IRQ_HANDLED;
  931. }
  932. /*
  933. * Procedure for reading EEPROM
  934. */
  935. #define SROMAddressLength 5
  936. #define DataInOn 0x0008
  937. #define DataInOff 0x0000
  938. #define Clk 0x0002
  939. #define ChipSelect 0x0001
  940. #define SDIShiftCount 3
  941. #define SD0ShiftCount 2
  942. #define DelayValue 1000 /* number of microseconds */
  943. #define SROMStartOffset 10 /* this is in words */
  944. #define SROMReadCount 3 /* number of words to read from SROM */
  945. #define SROMAddressBits 6
  946. #define EnetAddressOffset 20
  947. static unsigned char
  948. bmac_clock_out_bit(struct net_device *dev)
  949. {
  950. unsigned short data;
  951. unsigned short val;
  952. bmwrite(dev, SROMCSR, ChipSelect | Clk);
  953. udelay(DelayValue);
  954. data = bmread(dev, SROMCSR);
  955. udelay(DelayValue);
  956. val = (data >> SD0ShiftCount) & 1;
  957. bmwrite(dev, SROMCSR, ChipSelect);
  958. udelay(DelayValue);
  959. return val;
  960. }
  961. static void
  962. bmac_clock_in_bit(struct net_device *dev, unsigned int val)
  963. {
  964. unsigned short data;
  965. if (val != 0 && val != 1) return;
  966. data = (val << SDIShiftCount);
  967. bmwrite(dev, SROMCSR, data | ChipSelect );
  968. udelay(DelayValue);
  969. bmwrite(dev, SROMCSR, data | ChipSelect | Clk );
  970. udelay(DelayValue);
  971. bmwrite(dev, SROMCSR, data | ChipSelect);
  972. udelay(DelayValue);
  973. }
  974. static void
  975. reset_and_select_srom(struct net_device *dev)
  976. {
  977. /* first reset */
  978. bmwrite(dev, SROMCSR, 0);
  979. udelay(DelayValue);
  980. /* send it the read command (110) */
  981. bmac_clock_in_bit(dev, 1);
  982. bmac_clock_in_bit(dev, 1);
  983. bmac_clock_in_bit(dev, 0);
  984. }
  985. static unsigned short
  986. read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len)
  987. {
  988. unsigned short data, val;
  989. int i;
  990. /* send out the address we want to read from */
  991. for (i = 0; i < addr_len; i++) {
  992. val = addr >> (addr_len-i-1);
  993. bmac_clock_in_bit(dev, val & 1);
  994. }
  995. /* Now read in the 16-bit data */
  996. data = 0;
  997. for (i = 0; i < 16; i++) {
  998. val = bmac_clock_out_bit(dev);
  999. data <<= 1;
  1000. data |= val;
  1001. }
  1002. bmwrite(dev, SROMCSR, 0);
  1003. return data;
  1004. }
  1005. /*
  1006. * It looks like Cogent and SMC use different methods for calculating
  1007. * checksums. What a pain..
  1008. */
  1009. static int
  1010. bmac_verify_checksum(struct net_device *dev)
  1011. {
  1012. unsigned short data, storedCS;
  1013. reset_and_select_srom(dev);
  1014. data = read_srom(dev, 3, SROMAddressBits);
  1015. storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00);
  1016. return 0;
  1017. }
  1018. static void
  1019. bmac_get_station_address(struct net_device *dev, unsigned char *ea)
  1020. {
  1021. int i;
  1022. unsigned short data;
  1023. for (i = 0; i < 6; i++)
  1024. {
  1025. reset_and_select_srom(dev);
  1026. data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits);
  1027. ea[2*i] = bitrev8(data & 0x0ff);
  1028. ea[2*i+1] = bitrev8((data >> 8) & 0x0ff);
  1029. }
  1030. }
  1031. static void bmac_reset_and_enable(struct net_device *dev)
  1032. {
  1033. struct bmac_data *bp = netdev_priv(dev);
  1034. unsigned long flags;
  1035. struct sk_buff *skb;
  1036. unsigned char *data;
  1037. spin_lock_irqsave(&bp->lock, flags);
  1038. bmac_enable_and_reset_chip(dev);
  1039. bmac_init_tx_ring(bp);
  1040. bmac_init_rx_ring(bp);
  1041. bmac_init_chip(dev);
  1042. bmac_start_chip(dev);
  1043. bmwrite(dev, INTDISABLE, EnableNormal);
  1044. bp->sleeping = 0;
  1045. /*
  1046. * It seems that the bmac can't receive until it's transmitted
  1047. * a packet. So we give it a dummy packet to transmit.
  1048. */
  1049. skb = dev_alloc_skb(ETHERMINPACKET);
  1050. if (skb != NULL) {
  1051. data = skb_put(skb, ETHERMINPACKET);
  1052. memset(data, 0, ETHERMINPACKET);
  1053. memcpy(data, dev->dev_addr, 6);
  1054. memcpy(data+6, dev->dev_addr, 6);
  1055. bmac_transmit_packet(skb, dev);
  1056. }
  1057. spin_unlock_irqrestore(&bp->lock, flags);
  1058. }
  1059. static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_id *match)
  1060. {
  1061. int j, rev, ret;
  1062. struct bmac_data *bp;
  1063. const unsigned char *prop_addr;
  1064. unsigned char addr[6];
  1065. struct net_device *dev;
  1066. int is_bmac_plus = ((int)match->data) != 0;
  1067. if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
  1068. printk(KERN_ERR "BMAC: can't use, need 3 addrs and 3 intrs\n");
  1069. return -ENODEV;
  1070. }
  1071. prop_addr = get_property(macio_get_of_node(mdev), "mac-address", NULL);
  1072. if (prop_addr == NULL) {
  1073. prop_addr = get_property(macio_get_of_node(mdev),
  1074. "local-mac-address", NULL);
  1075. if (prop_addr == NULL) {
  1076. printk(KERN_ERR "BMAC: Can't get mac-address\n");
  1077. return -ENODEV;
  1078. }
  1079. }
  1080. memcpy(addr, prop_addr, sizeof(addr));
  1081. dev = alloc_etherdev(PRIV_BYTES);
  1082. if (!dev) {
  1083. printk(KERN_ERR "BMAC: alloc_etherdev failed, out of memory\n");
  1084. return -ENOMEM;
  1085. }
  1086. bp = netdev_priv(dev);
  1087. SET_MODULE_OWNER(dev);
  1088. SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
  1089. macio_set_drvdata(mdev, dev);
  1090. bp->mdev = mdev;
  1091. spin_lock_init(&bp->lock);
  1092. if (macio_request_resources(mdev, "bmac")) {
  1093. printk(KERN_ERR "BMAC: can't request IO resource !\n");
  1094. goto out_free;
  1095. }
  1096. dev->base_addr = (unsigned long)
  1097. ioremap(macio_resource_start(mdev, 0), macio_resource_len(mdev, 0));
  1098. if (dev->base_addr == 0)
  1099. goto out_release;
  1100. dev->irq = macio_irq(mdev, 0);
  1101. bmac_enable_and_reset_chip(dev);
  1102. bmwrite(dev, INTDISABLE, DisableAll);
  1103. rev = addr[0] == 0 && addr[1] == 0xA0;
  1104. for (j = 0; j < 6; ++j)
  1105. dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j];
  1106. /* Enable chip without interrupts for now */
  1107. bmac_enable_and_reset_chip(dev);
  1108. bmwrite(dev, INTDISABLE, DisableAll);
  1109. dev->open = bmac_open;
  1110. dev->stop = bmac_close;
  1111. dev->hard_start_xmit = bmac_output;
  1112. dev->get_stats = bmac_stats;
  1113. dev->set_multicast_list = bmac_set_multicast;
  1114. dev->set_mac_address = bmac_set_address;
  1115. bmac_get_station_address(dev, addr);
  1116. if (bmac_verify_checksum(dev) != 0)
  1117. goto err_out_iounmap;
  1118. bp->is_bmac_plus = is_bmac_plus;
  1119. bp->tx_dma = ioremap(macio_resource_start(mdev, 1), macio_resource_len(mdev, 1));
  1120. if (!bp->tx_dma)
  1121. goto err_out_iounmap;
  1122. bp->tx_dma_intr = macio_irq(mdev, 1);
  1123. bp->rx_dma = ioremap(macio_resource_start(mdev, 2), macio_resource_len(mdev, 2));
  1124. if (!bp->rx_dma)
  1125. goto err_out_iounmap_tx;
  1126. bp->rx_dma_intr = macio_irq(mdev, 2);
  1127. bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1);
  1128. bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1;
  1129. bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1);
  1130. skb_queue_head_init(bp->queue);
  1131. init_timer(&bp->tx_timeout);
  1132. ret = request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev);
  1133. if (ret) {
  1134. printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq);
  1135. goto err_out_iounmap_rx;
  1136. }
  1137. ret = request_irq(bp->tx_dma_intr, bmac_txdma_intr, 0, "BMAC-txdma", dev);
  1138. if (ret) {
  1139. printk(KERN_ERR "BMAC: can't get irq %d\n", bp->tx_dma_intr);
  1140. goto err_out_irq0;
  1141. }
  1142. ret = request_irq(bp->rx_dma_intr, bmac_rxdma_intr, 0, "BMAC-rxdma", dev);
  1143. if (ret) {
  1144. printk(KERN_ERR "BMAC: can't get irq %d\n", bp->rx_dma_intr);
  1145. goto err_out_irq1;
  1146. }
  1147. /* Mask chip interrupts and disable chip, will be
  1148. * re-enabled on open()
  1149. */
  1150. disable_irq(dev->irq);
  1151. pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
  1152. if (register_netdev(dev) != 0) {
  1153. printk(KERN_ERR "BMAC: Ethernet registration failed\n");
  1154. goto err_out_irq2;
  1155. }
  1156. printk(KERN_INFO "%s: BMAC%s at", dev->name, (is_bmac_plus? "+": ""));
  1157. for (j = 0; j < 6; ++j)
  1158. printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
  1159. XXDEBUG((", base_addr=%#0lx", dev->base_addr));
  1160. printk("\n");
  1161. return 0;
  1162. err_out_irq2:
  1163. free_irq(bp->rx_dma_intr, dev);
  1164. err_out_irq1:
  1165. free_irq(bp->tx_dma_intr, dev);
  1166. err_out_irq0:
  1167. free_irq(dev->irq, dev);
  1168. err_out_iounmap_rx:
  1169. iounmap(bp->rx_dma);
  1170. err_out_iounmap_tx:
  1171. iounmap(bp->tx_dma);
  1172. err_out_iounmap:
  1173. iounmap((void __iomem *)dev->base_addr);
  1174. out_release:
  1175. macio_release_resources(mdev);
  1176. out_free:
  1177. pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
  1178. free_netdev(dev);
  1179. return -ENODEV;
  1180. }
  1181. static int bmac_open(struct net_device *dev)
  1182. {
  1183. struct bmac_data *bp = netdev_priv(dev);
  1184. /* XXDEBUG(("bmac: enter open\n")); */
  1185. /* reset the chip */
  1186. bp->opened = 1;
  1187. bmac_reset_and_enable(dev);
  1188. enable_irq(dev->irq);
  1189. return 0;
  1190. }
  1191. static int bmac_close(struct net_device *dev)
  1192. {
  1193. struct bmac_data *bp = netdev_priv(dev);
  1194. volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
  1195. volatile struct dbdma_regs __iomem *td = bp->tx_dma;
  1196. unsigned short config;
  1197. int i;
  1198. bp->sleeping = 1;
  1199. /* disable rx and tx */
  1200. config = bmread(dev, RXCFG);
  1201. bmwrite(dev, RXCFG, (config & ~RxMACEnable));
  1202. config = bmread(dev, TXCFG);
  1203. bmwrite(dev, TXCFG, (config & ~TxMACEnable));
  1204. bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */
  1205. /* disable rx and tx dma */
  1206. st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
  1207. st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */
  1208. /* free some skb's */
  1209. XXDEBUG(("bmac: free rx bufs\n"));
  1210. for (i=0; i<N_RX_RING; i++) {
  1211. if (bp->rx_bufs[i] != NULL) {
  1212. dev_kfree_skb(bp->rx_bufs[i]);
  1213. bp->rx_bufs[i] = NULL;
  1214. }
  1215. }
  1216. XXDEBUG(("bmac: free tx bufs\n"));
  1217. for (i = 0; i<N_TX_RING; i++) {
  1218. if (bp->tx_bufs[i] != NULL) {
  1219. dev_kfree_skb(bp->tx_bufs[i]);
  1220. bp->tx_bufs[i] = NULL;
  1221. }
  1222. }
  1223. XXDEBUG(("bmac: all bufs freed\n"));
  1224. bp->opened = 0;
  1225. disable_irq(dev->irq);
  1226. pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0);
  1227. return 0;
  1228. }
  1229. static void
  1230. bmac_start(struct net_device *dev)
  1231. {
  1232. struct bmac_data *bp = netdev_priv(dev);
  1233. int i;
  1234. struct sk_buff *skb;
  1235. unsigned long flags;
  1236. if (bp->sleeping)
  1237. return;
  1238. spin_lock_irqsave(&bp->lock, flags);
  1239. while (1) {
  1240. i = bp->tx_fill + 1;
  1241. if (i >= N_TX_RING)
  1242. i = 0;
  1243. if (i == bp->tx_empty)
  1244. break;
  1245. skb = skb_dequeue(bp->queue);
  1246. if (skb == NULL)
  1247. break;
  1248. bmac_transmit_packet(skb, dev);
  1249. }
  1250. spin_unlock_irqrestore(&bp->lock, flags);
  1251. }
  1252. static int
  1253. bmac_output(struct sk_buff *skb, struct net_device *dev)
  1254. {
  1255. struct bmac_data *bp = netdev_priv(dev);
  1256. skb_queue_tail(bp->queue, skb);
  1257. bmac_start(dev);
  1258. return 0;
  1259. }
  1260. static void bmac_tx_timeout(unsigned long data)
  1261. {
  1262. struct net_device *dev = (struct net_device *) data;
  1263. struct bmac_data *bp = netdev_priv(dev);
  1264. volatile struct dbdma_regs __iomem *td = bp->tx_dma;
  1265. volatile struct dbdma_regs __iomem *rd = bp->rx_dma;
  1266. volatile struct dbdma_cmd *cp;
  1267. unsigned long flags;
  1268. unsigned short config, oldConfig;
  1269. int i;
  1270. XXDEBUG(("bmac: tx_timeout called\n"));
  1271. spin_lock_irqsave(&bp->lock, flags);
  1272. bp->timeout_active = 0;
  1273. /* update various counters */
  1274. /* bmac_handle_misc_intrs(bp, 0); */
  1275. cp = &bp->tx_cmds[bp->tx_empty];
  1276. /* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */
  1277. /* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */
  1278. /* mb->pr, mb->xmtfs, mb->fifofc)); */
  1279. /* turn off both tx and rx and reset the chip */
  1280. config = bmread(dev, RXCFG);
  1281. bmwrite(dev, RXCFG, (config & ~RxMACEnable));
  1282. config = bmread(dev, TXCFG);
  1283. bmwrite(dev, TXCFG, (config & ~TxMACEnable));
  1284. out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
  1285. printk(KERN_ERR "bmac: transmit timeout - resetting\n");
  1286. bmac_enable_and_reset_chip(dev);
  1287. /* restart rx dma */
  1288. cp = bus_to_virt(ld_le32(&rd->cmdptr));
  1289. out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD));
  1290. out_le16(&cp->xfer_status, 0);
  1291. out_le32(&rd->cmdptr, virt_to_bus(cp));
  1292. out_le32(&rd->control, DBDMA_SET(RUN|WAKE));
  1293. /* fix up the transmit side */
  1294. XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n",
  1295. bp->tx_empty, bp->tx_fill, bp->tx_fullup));
  1296. i = bp->tx_empty;
  1297. ++bp->stats.tx_errors;
  1298. if (i != bp->tx_fill) {
  1299. dev_kfree_skb(bp->tx_bufs[i]);
  1300. bp->tx_bufs[i] = NULL;
  1301. if (++i >= N_TX_RING) i = 0;
  1302. bp->tx_empty = i;
  1303. }
  1304. bp->tx_fullup = 0;
  1305. netif_wake_queue(dev);
  1306. if (i != bp->tx_fill) {
  1307. cp = &bp->tx_cmds[i];
  1308. out_le16(&cp->xfer_status, 0);
  1309. out_le16(&cp->command, OUTPUT_LAST);
  1310. out_le32(&td->cmdptr, virt_to_bus(cp));
  1311. out_le32(&td->control, DBDMA_SET(RUN));
  1312. /* bmac_set_timeout(dev); */
  1313. XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i));
  1314. }
  1315. /* turn it back on */
  1316. oldConfig = bmread(dev, RXCFG);
  1317. bmwrite(dev, RXCFG, oldConfig | RxMACEnable );
  1318. oldConfig = bmread(dev, TXCFG);
  1319. bmwrite(dev, TXCFG, oldConfig | TxMACEnable );
  1320. spin_unlock_irqrestore(&bp->lock, flags);
  1321. }
  1322. #if 0
  1323. static void dump_dbdma(volatile struct dbdma_cmd *cp,int count)
  1324. {
  1325. int i,*ip;
  1326. for (i=0;i< count;i++) {
  1327. ip = (int*)(cp+i);
  1328. printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n",
  1329. ld_le32(ip+0),
  1330. ld_le32(ip+1),
  1331. ld_le32(ip+2),
  1332. ld_le32(ip+3));
  1333. }
  1334. }
  1335. #endif
  1336. #if 0
  1337. static int
  1338. bmac_proc_info(char *buffer, char **start, off_t offset, int length)
  1339. {
  1340. int len = 0;
  1341. off_t pos = 0;
  1342. off_t begin = 0;
  1343. int i;
  1344. if (bmac_devs == NULL)
  1345. return (-ENOSYS);
  1346. len += sprintf(buffer, "BMAC counters & registers\n");
  1347. for (i = 0; i<N_REG_ENTRIES; i++) {
  1348. len += sprintf(buffer + len, "%s: %#08x\n",
  1349. reg_entries[i].name,
  1350. bmread(bmac_devs, reg_entries[i].reg_offset));
  1351. pos = begin + len;
  1352. if (pos < offset) {
  1353. len = 0;
  1354. begin = pos;
  1355. }
  1356. if (pos > offset+length) break;
  1357. }
  1358. *start = buffer + (offset - begin);
  1359. len -= (offset - begin);
  1360. if (len > length) len = length;
  1361. return len;
  1362. }
  1363. #endif
  1364. static int __devexit bmac_remove(struct macio_dev *mdev)
  1365. {
  1366. struct net_device *dev = macio_get_drvdata(mdev);
  1367. struct bmac_data *bp = netdev_priv(dev);
  1368. unregister_netdev(dev);
  1369. free_irq(dev->irq, dev);
  1370. free_irq(bp->tx_dma_intr, dev);
  1371. free_irq(bp->rx_dma_intr, dev);
  1372. iounmap((void __iomem *)dev->base_addr);
  1373. iounmap(bp->tx_dma);
  1374. iounmap(bp->rx_dma);
  1375. macio_release_resources(mdev);
  1376. free_netdev(dev);
  1377. return 0;
  1378. }
  1379. static struct of_device_id bmac_match[] =
  1380. {
  1381. {
  1382. .name = "bmac",
  1383. .data = (void *)0,
  1384. },
  1385. {
  1386. .type = "network",
  1387. .compatible = "bmac+",
  1388. .data = (void *)1,
  1389. },
  1390. {},
  1391. };
  1392. MODULE_DEVICE_TABLE (of, bmac_match);
  1393. static struct macio_driver bmac_driver =
  1394. {
  1395. .name = "bmac",
  1396. .match_table = bmac_match,
  1397. .probe = bmac_probe,
  1398. .remove = bmac_remove,
  1399. #ifdef CONFIG_PM
  1400. .suspend = bmac_suspend,
  1401. .resume = bmac_resume,
  1402. #endif
  1403. };
  1404. static int __init bmac_init(void)
  1405. {
  1406. if (bmac_emergency_rxbuf == NULL) {
  1407. bmac_emergency_rxbuf = kmalloc(RX_BUFLEN, GFP_KERNEL);
  1408. if (bmac_emergency_rxbuf == NULL) {
  1409. printk(KERN_ERR "BMAC: can't allocate emergency RX buffer\n");
  1410. return -ENOMEM;
  1411. }
  1412. }
  1413. return macio_register_driver(&bmac_driver);
  1414. }
  1415. static void __exit bmac_exit(void)
  1416. {
  1417. macio_unregister_driver(&bmac_driver);
  1418. kfree(bmac_emergency_rxbuf);
  1419. bmac_emergency_rxbuf = NULL;
  1420. }
  1421. MODULE_AUTHOR("Randy Gobbel/Paul Mackerras");
  1422. MODULE_DESCRIPTION("PowerMac BMAC ethernet driver.");
  1423. MODULE_LICENSE("GPL");
  1424. module_init(bmac_init);
  1425. module_exit(bmac_exit);