atp.h 8.5 KB

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  1. /* Linux header file for the ATP pocket ethernet adapter. */
  2. /* v1.09 8/9/2000 becker@scyld.com. */
  3. #include <linux/if_ether.h>
  4. #include <linux/types.h>
  5. /* The header prepended to received packets. */
  6. struct rx_header {
  7. ushort pad; /* Pad. */
  8. ushort rx_count;
  9. ushort rx_status; /* Unknown bit assignments :-<. */
  10. ushort cur_addr; /* Apparently the current buffer address(?) */
  11. };
  12. #define PAR_DATA 0
  13. #define PAR_STATUS 1
  14. #define PAR_CONTROL 2
  15. enum chip_type { RTL8002, RTL8012 };
  16. #define Ctrl_LNibRead 0x08 /* LP_PSELECP */
  17. #define Ctrl_HNibRead 0
  18. #define Ctrl_LNibWrite 0x08 /* LP_PSELECP */
  19. #define Ctrl_HNibWrite 0
  20. #define Ctrl_SelData 0x04 /* LP_PINITP */
  21. #define Ctrl_IRQEN 0x10 /* LP_PINTEN */
  22. #define EOW 0xE0
  23. #define EOC 0xE0
  24. #define WrAddr 0x40 /* Set address of EPLC read, write register. */
  25. #define RdAddr 0xC0
  26. #define HNib 0x10
  27. enum page0_regs
  28. {
  29. /* The first six registers hold the ethernet physical station address. */
  30. PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5,
  31. TxCNT0 = 6, TxCNT1 = 7, /* The transmit byte count. */
  32. TxSTAT = 8, RxSTAT = 9, /* Tx and Rx status. */
  33. ISR = 10, IMR = 11, /* Interrupt status and mask. */
  34. CMR1 = 12, /* Command register 1. */
  35. CMR2 = 13, /* Command register 2. */
  36. MODSEL = 14, /* Mode select register. */
  37. MAR = 14, /* Memory address register (?). */
  38. CMR2_h = 0x1d, };
  39. enum eepage_regs
  40. { PROM_CMD = 6, PROM_DATA = 7 }; /* Note that PROM_CMD is in the "high" bits. */
  41. #define ISR_TxOK 0x01
  42. #define ISR_RxOK 0x04
  43. #define ISR_TxErr 0x02
  44. #define ISRh_RxErr 0x11 /* ISR, high nibble */
  45. #define CMR1h_MUX 0x08 /* Select printer multiplexor on 8012. */
  46. #define CMR1h_RESET 0x04 /* Reset. */
  47. #define CMR1h_RxENABLE 0x02 /* Rx unit enable. */
  48. #define CMR1h_TxENABLE 0x01 /* Tx unit enable. */
  49. #define CMR1h_TxRxOFF 0x00
  50. #define CMR1_ReXmit 0x08 /* Trigger a retransmit. */
  51. #define CMR1_Xmit 0x04 /* Trigger a transmit. */
  52. #define CMR1_IRQ 0x02 /* Interrupt active. */
  53. #define CMR1_BufEnb 0x01 /* Enable the buffer(?). */
  54. #define CMR1_NextPkt 0x01 /* Enable the buffer(?). */
  55. #define CMR2_NULL 8
  56. #define CMR2_IRQOUT 9
  57. #define CMR2_RAMTEST 10
  58. #define CMR2_EEPROM 12 /* Set to page 1, for reading the EEPROM. */
  59. #define CMR2h_OFF 0 /* No accept mode. */
  60. #define CMR2h_Physical 1 /* Accept a physical address match only. */
  61. #define CMR2h_Normal 2 /* Accept physical and broadcast address. */
  62. #define CMR2h_PROMISC 3 /* Promiscuous mode. */
  63. /* An inline function used below: it differs from inb() by explicitly return an unsigned
  64. char, saving a truncation. */
  65. static inline unsigned char inbyte(unsigned short port)
  66. {
  67. unsigned char _v;
  68. __asm__ __volatile__ ("inb %w1,%b0" :"=a" (_v):"d" (port));
  69. return _v;
  70. }
  71. /* Read register OFFSET.
  72. This command should always be terminated with read_end(). */
  73. static inline unsigned char read_nibble(short port, unsigned char offset)
  74. {
  75. unsigned char retval;
  76. outb(EOC+offset, port + PAR_DATA);
  77. outb(RdAddr+offset, port + PAR_DATA);
  78. inbyte(port + PAR_STATUS); /* Settling time delay */
  79. retval = inbyte(port + PAR_STATUS);
  80. outb(EOC+offset, port + PAR_DATA);
  81. return retval;
  82. }
  83. /* Functions for bulk data read. The interrupt line is always disabled. */
  84. /* Get a byte using read mode 0, reading data from the control lines. */
  85. static inline unsigned char read_byte_mode0(short ioaddr)
  86. {
  87. unsigned char low_nib;
  88. outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
  89. inbyte(ioaddr + PAR_STATUS);
  90. low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
  91. outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
  92. inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
  93. inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
  94. return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
  95. }
  96. /* The same as read_byte_mode0(), but does multiple inb()s for stability. */
  97. static inline unsigned char read_byte_mode2(short ioaddr)
  98. {
  99. unsigned char low_nib;
  100. outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
  101. inbyte(ioaddr + PAR_STATUS);
  102. low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
  103. outb(Ctrl_HNibRead, ioaddr + PAR_CONTROL);
  104. inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */
  105. return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
  106. }
  107. /* Read a byte through the data register. */
  108. static inline unsigned char read_byte_mode4(short ioaddr)
  109. {
  110. unsigned char low_nib;
  111. outb(RdAddr | MAR, ioaddr + PAR_DATA);
  112. low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
  113. outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
  114. return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
  115. }
  116. /* Read a byte through the data register, double reading to allow settling. */
  117. static inline unsigned char read_byte_mode6(short ioaddr)
  118. {
  119. unsigned char low_nib;
  120. outb(RdAddr | MAR, ioaddr + PAR_DATA);
  121. inbyte(ioaddr + PAR_STATUS);
  122. low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;
  123. outb(RdAddr | HNib | MAR, ioaddr + PAR_DATA);
  124. inbyte(ioaddr + PAR_STATUS);
  125. return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);
  126. }
  127. static inline void
  128. write_reg(short port, unsigned char reg, unsigned char value)
  129. {
  130. unsigned char outval;
  131. outb(EOC | reg, port + PAR_DATA);
  132. outval = WrAddr | reg;
  133. outb(outval, port + PAR_DATA);
  134. outb(outval, port + PAR_DATA); /* Double write for PS/2. */
  135. outval &= 0xf0;
  136. outval |= value;
  137. outb(outval, port + PAR_DATA);
  138. outval &= 0x1f;
  139. outb(outval, port + PAR_DATA);
  140. outb(outval, port + PAR_DATA);
  141. outb(EOC | outval, port + PAR_DATA);
  142. }
  143. static inline void
  144. write_reg_high(short port, unsigned char reg, unsigned char value)
  145. {
  146. unsigned char outval = EOC | HNib | reg;
  147. outb(outval, port + PAR_DATA);
  148. outval &= WrAddr | HNib | 0x0f;
  149. outb(outval, port + PAR_DATA);
  150. outb(outval, port + PAR_DATA); /* Double write for PS/2. */
  151. outval = WrAddr | HNib | value;
  152. outb(outval, port + PAR_DATA);
  153. outval &= HNib | 0x0f; /* HNib | value */
  154. outb(outval, port + PAR_DATA);
  155. outb(outval, port + PAR_DATA);
  156. outb(EOC | HNib | outval, port + PAR_DATA);
  157. }
  158. /* Write a byte out using nibble mode. The low nibble is written first. */
  159. static inline void
  160. write_reg_byte(short port, unsigned char reg, unsigned char value)
  161. {
  162. unsigned char outval;
  163. outb(EOC | reg, port + PAR_DATA); /* Reset the address register. */
  164. outval = WrAddr | reg;
  165. outb(outval, port + PAR_DATA);
  166. outb(outval, port + PAR_DATA); /* Double write for PS/2. */
  167. outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA);
  168. outb(value & 0x0f, port + PAR_DATA);
  169. value >>= 4;
  170. outb(value, port + PAR_DATA);
  171. outb(0x10 | value, port + PAR_DATA);
  172. outb(0x10 | value, port + PAR_DATA);
  173. outb(EOC | value, port + PAR_DATA); /* Reset the address register. */
  174. }
  175. /*
  176. * Bulk data writes to the packet buffer. The interrupt line remains enabled.
  177. * The first, faster method uses only the dataport (data modes 0, 2 & 4).
  178. * The second (backup) method uses data and control regs (modes 1, 3 & 5).
  179. * It should only be needed when there is skew between the individual data
  180. * lines.
  181. */
  182. static inline void write_byte_mode0(short ioaddr, unsigned char value)
  183. {
  184. outb(value & 0x0f, ioaddr + PAR_DATA);
  185. outb((value>>4) | 0x10, ioaddr + PAR_DATA);
  186. }
  187. static inline void write_byte_mode1(short ioaddr, unsigned char value)
  188. {
  189. outb(value & 0x0f, ioaddr + PAR_DATA);
  190. outb(Ctrl_IRQEN | Ctrl_LNibWrite, ioaddr + PAR_CONTROL);
  191. outb((value>>4) | 0x10, ioaddr + PAR_DATA);
  192. outb(Ctrl_IRQEN | Ctrl_HNibWrite, ioaddr + PAR_CONTROL);
  193. }
  194. /* Write 16bit VALUE to the packet buffer: the same as above just doubled. */
  195. static inline void write_word_mode0(short ioaddr, unsigned short value)
  196. {
  197. outb(value & 0x0f, ioaddr + PAR_DATA);
  198. value >>= 4;
  199. outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
  200. value >>= 4;
  201. outb(value & 0x0f, ioaddr + PAR_DATA);
  202. value >>= 4;
  203. outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);
  204. }
  205. /* EEPROM_Ctrl bits. */
  206. #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
  207. #define EE_CS 0x02 /* EEPROM chip select. */
  208. #define EE_CLK_HIGH 0x12
  209. #define EE_CLK_LOW 0x16
  210. #define EE_DATA_WRITE 0x01 /* EEPROM chip data in. */
  211. #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
  212. /* Delay between EEPROM clock transitions. */
  213. #define eeprom_delay(ticks) \
  214. do { int _i = 40; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
  215. /* The EEPROM commands include the alway-set leading bit. */
  216. #define EE_WRITE_CMD(offset) (((5 << 6) + (offset)) << 17)
  217. #define EE_READ(offset) (((6 << 6) + (offset)) << 17)
  218. #define EE_ERASE(offset) (((7 << 6) + (offset)) << 17)
  219. #define EE_CMD_SIZE 27 /* The command+address+data size. */