amd8111e.h 20 KB

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  1. /*
  2. * Advanced Micro Devices Inc. AMD8111E Linux Network Driver
  3. * Copyright (C) 2003 Advanced Micro Devices
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  18. * USA
  19. Module Name:
  20. amd8111e.h
  21. Abstract:
  22. AMD8111 based 10/100 Ethernet Controller driver definitions.
  23. Environment:
  24. Kernel Mode
  25. Revision History:
  26. 3.0.0
  27. Initial Revision.
  28. 3.0.1
  29. */
  30. #ifndef _AMD811E_H
  31. #define _AMD811E_H
  32. /* Command style register access
  33. Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
  34. eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
  35. */
  36. /* Offset for Memory Mapped Registers. */
  37. /* 32 bit registers */
  38. #define ASF_STAT 0x00 /* ASF status register */
  39. #define CHIPID 0x04 /* Chip ID regsiter */
  40. #define MIB_DATA 0x10 /* MIB data register */
  41. #define MIB_ADDR 0x14 /* MIB address register */
  42. #define STAT0 0x30 /* Status0 register */
  43. #define INT0 0x38 /* Interrupt0 register */
  44. #define INTEN0 0x40 /* Interrupt0 enable register*/
  45. #define CMD0 0x48 /* Command0 register */
  46. #define CMD2 0x50 /* Command2 register */
  47. #define CMD3 0x54 /* Command3 resiter */
  48. #define CMD7 0x64 /* Command7 register */
  49. #define CTRL1 0x6C /* Control1 register */
  50. #define CTRL2 0x70 /* Control2 register */
  51. #define XMT_RING_LIMIT 0x7C /* Transmit ring limit register */
  52. #define AUTOPOLL0 0x88 /* Auto-poll0 register */
  53. #define AUTOPOLL1 0x8A /* Auto-poll1 register */
  54. #define AUTOPOLL2 0x8C /* Auto-poll2 register */
  55. #define AUTOPOLL3 0x8E /* Auto-poll3 register */
  56. #define AUTOPOLL4 0x90 /* Auto-poll4 register */
  57. #define AUTOPOLL5 0x92 /* Auto-poll5 register */
  58. #define AP_VALUE 0x98 /* Auto-poll value register */
  59. #define DLY_INT_A 0xA8 /* Group A delayed interrupt register */
  60. #define DLY_INT_B 0xAC /* Group B delayed interrupt register */
  61. #define FLOW_CONTROL 0xC8 /* Flow control register */
  62. #define PHY_ACCESS 0xD0 /* PHY access register */
  63. #define STVAL 0xD8 /* Software timer value register */
  64. #define XMT_RING_BASE_ADDR0 0x100 /* Transmit ring0 base addr register */
  65. #define XMT_RING_BASE_ADDR1 0x108 /* Transmit ring1 base addr register */
  66. #define XMT_RING_BASE_ADDR2 0x110 /* Transmit ring2 base addr register */
  67. #define XMT_RING_BASE_ADDR3 0x118 /* Transmit ring2 base addr register */
  68. #define RCV_RING_BASE_ADDR0 0x120 /* Transmit ring0 base addr register */
  69. #define PMAT0 0x190 /* OnNow pattern register0 */
  70. #define PMAT1 0x194 /* OnNow pattern register1 */
  71. /* 16bit registers */
  72. #define XMT_RING_LEN0 0x140 /* Transmit Ring0 length register */
  73. #define XMT_RING_LEN1 0x144 /* Transmit Ring1 length register */
  74. #define XMT_RING_LEN2 0x148 /* Transmit Ring2 length register */
  75. #define XMT_RING_LEN3 0x14C /* Transmit Ring3 length register */
  76. #define RCV_RING_LEN0 0x150 /* Receive Ring0 length register */
  77. #define SRAM_SIZE 0x178 /* SRAM size register */
  78. #define SRAM_BOUNDARY 0x17A /* SRAM boundary register */
  79. /* 48bit register */
  80. #define PADR 0x160 /* Physical address register */
  81. #define IFS1 0x18C /* Inter-frame spacing Part1 register */
  82. #define IFS 0x18D /* Inter-frame spacing register */
  83. #define IPG 0x18E /* Inter-frame gap register */
  84. /* 64bit register */
  85. #define LADRF 0x168 /* Logical address filter register */
  86. /* Register Bit Definitions */
  87. typedef enum {
  88. ASF_INIT_DONE = (1 << 1),
  89. ASF_INIT_PRESENT = (1 << 0),
  90. }STAT_ASF_BITS;
  91. typedef enum {
  92. MIB_CMD_ACTIVE = (1 << 15 ),
  93. MIB_RD_CMD = (1 << 13 ),
  94. MIB_CLEAR = (1 << 12 ),
  95. MIB_ADDRESS = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
  96. (1 << 4) | (1 << 5),
  97. }MIB_ADDR_BITS;
  98. typedef enum {
  99. PMAT_DET = (1 << 12),
  100. MP_DET = (1 << 11),
  101. LC_DET = (1 << 10),
  102. SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7),
  103. FULL_DPLX = (1 << 6),
  104. LINK_STATS = (1 << 5),
  105. AUTONEG_COMPLETE = (1 << 4),
  106. MIIPD = (1 << 3),
  107. RX_SUSPENDED = (1 << 2),
  108. TX_SUSPENDED = (1 << 1),
  109. RUNNING = (1 << 0),
  110. }STAT0_BITS;
  111. #define PHY_SPEED_10 0x2
  112. #define PHY_SPEED_100 0x3
  113. /* INT0 0x38, 32bit register */
  114. typedef enum {
  115. INTR = (1 << 31),
  116. PCSINT = (1 << 28),
  117. LCINT = (1 << 27),
  118. APINT5 = (1 << 26),
  119. APINT4 = (1 << 25),
  120. APINT3 = (1 << 24),
  121. TINT_SUM = (1 << 23),
  122. APINT2 = (1 << 22),
  123. APINT1 = (1 << 21),
  124. APINT0 = (1 << 20),
  125. MIIPDTINT = (1 << 19),
  126. MCCINT = (1 << 17),
  127. MREINT = (1 << 16),
  128. RINT_SUM = (1 << 15),
  129. SPNDINT = (1 << 14),
  130. MPINT = (1 << 13),
  131. SINT = (1 << 12),
  132. TINT3 = (1 << 11),
  133. TINT2 = (1 << 10),
  134. TINT1 = (1 << 9),
  135. TINT0 = (1 << 8),
  136. UINT = (1 << 7),
  137. STINT = (1 << 4),
  138. RINT0 = (1 << 0),
  139. }INT0_BITS;
  140. typedef enum {
  141. VAL3 = (1 << 31), /* VAL bit for byte 3 */
  142. VAL2 = (1 << 23), /* VAL bit for byte 2 */
  143. VAL1 = (1 << 15), /* VAL bit for byte 1 */
  144. VAL0 = (1 << 7), /* VAL bit for byte 0 */
  145. }VAL_BITS;
  146. typedef enum {
  147. /* VAL3 */
  148. LCINTEN = (1 << 27),
  149. APINT5EN = (1 << 26),
  150. APINT4EN = (1 << 25),
  151. APINT3EN = (1 << 24),
  152. /* VAL2 */
  153. APINT2EN = (1 << 22),
  154. APINT1EN = (1 << 21),
  155. APINT0EN = (1 << 20),
  156. MIIPDTINTEN = (1 << 19),
  157. MCCIINTEN = (1 << 18),
  158. MCCINTEN = (1 << 17),
  159. MREINTEN = (1 << 16),
  160. /* VAL1 */
  161. SPNDINTEN = (1 << 14),
  162. MPINTEN = (1 << 13),
  163. TINTEN3 = (1 << 11),
  164. SINTEN = (1 << 12),
  165. TINTEN2 = (1 << 10),
  166. TINTEN1 = (1 << 9),
  167. TINTEN0 = (1 << 8),
  168. /* VAL0 */
  169. STINTEN = (1 << 4),
  170. RINTEN0 = (1 << 0),
  171. INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */
  172. }INTEN0_BITS;
  173. typedef enum {
  174. /* VAL2 */
  175. RDMD0 = (1 << 16),
  176. /* VAL1 */
  177. TDMD3 = (1 << 11),
  178. TDMD2 = (1 << 10),
  179. TDMD1 = (1 << 9),
  180. TDMD0 = (1 << 8),
  181. /* VAL0 */
  182. UINTCMD = (1 << 6),
  183. RX_FAST_SPND = (1 << 5),
  184. TX_FAST_SPND = (1 << 4),
  185. RX_SPND = (1 << 3),
  186. TX_SPND = (1 << 2),
  187. INTREN = (1 << 1),
  188. RUN = (1 << 0),
  189. CMD0_CLEAR = 0x000F0F7F, /* Command style register */
  190. }CMD0_BITS;
  191. typedef enum {
  192. /* VAL3 */
  193. CONDUIT_MODE = (1 << 29),
  194. /* VAL2 */
  195. RPA = (1 << 19),
  196. DRCVPA = (1 << 18),
  197. DRCVBC = (1 << 17),
  198. PROM = (1 << 16),
  199. /* VAL1 */
  200. ASTRP_RCV = (1 << 13),
  201. RCV_DROP0 = (1 << 12),
  202. EMBA = (1 << 11),
  203. DXMT2PD = (1 << 10),
  204. LTINTEN = (1 << 9),
  205. DXMTFCS = (1 << 8),
  206. /* VAL0 */
  207. APAD_XMT = (1 << 6),
  208. DRTY = (1 << 5),
  209. INLOOP = (1 << 4),
  210. EXLOOP = (1 << 3),
  211. REX_RTRY = (1 << 2),
  212. REX_UFLO = (1 << 1),
  213. REX_LCOL = (1 << 0),
  214. CMD2_CLEAR = 0x3F7F3F7F, /* Command style register */
  215. }CMD2_BITS;
  216. typedef enum {
  217. /* VAL3 */
  218. ASF_INIT_DONE_ALIAS = (1 << 29),
  219. /* VAL2 */
  220. JUMBO = (1 << 21),
  221. VSIZE = (1 << 20),
  222. VLONLY = (1 << 19),
  223. VL_TAG_DEL = (1 << 18),
  224. /* VAL1 */
  225. EN_PMGR = (1 << 14),
  226. INTLEVEL = (1 << 13),
  227. FORCE_FULL_DUPLEX = (1 << 12),
  228. FORCE_LINK_STATUS = (1 << 11),
  229. APEP = (1 << 10),
  230. MPPLBA = (1 << 9),
  231. /* VAL0 */
  232. RESET_PHY_PULSE = (1 << 2),
  233. RESET_PHY = (1 << 1),
  234. PHY_RST_POL = (1 << 0),
  235. }CMD3_BITS;
  236. typedef enum {
  237. /* VAL0 */
  238. PMAT_SAVE_MATCH = (1 << 4),
  239. PMAT_MODE = (1 << 3),
  240. MPEN_SW = (1 << 1),
  241. LCMODE_SW = (1 << 0),
  242. CMD7_CLEAR = 0x0000001B /* Command style register */
  243. }CMD7_BITS;
  244. typedef enum {
  245. RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
  246. XMTSP_MASK = (1 << 9) | (1 << 8), /* 9:8 */
  247. XMTSP_128 = (1 << 9), /* 9 */
  248. XMTSP_64 = (1 << 8),
  249. CACHE_ALIGN = (1 << 4),
  250. BURST_LIMIT_MASK = (0xF << 0 ),
  251. CTRL1_DEFAULT = 0x00010111,
  252. }CTRL1_BITS;
  253. typedef enum {
  254. FMDC_MASK = (1 << 9)|(1 << 8), /* 9:8 */
  255. XPHYRST = (1 << 7),
  256. XPHYANE = (1 << 6),
  257. XPHYFD = (1 << 5),
  258. XPHYSP = (1 << 4) | (1 << 3), /* 4:3 */
  259. APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */
  260. }CTRL2_BITS;
  261. /* XMT_RING_LIMIT 0x7C, 32bit register */
  262. typedef enum {
  263. XMT_RING2_LIMIT = (0xFF << 16), /* 23:16 */
  264. XMT_RING1_LIMIT = (0xFF << 8), /* 15:8 */
  265. XMT_RING0_LIMIT = (0xFF << 0), /* 7:0 */
  266. }XMT_RING_LIMIT_BITS;
  267. typedef enum {
  268. AP_REG0_EN = (1 << 15),
  269. AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
  270. AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
  271. }AUTOPOLL0_BITS;
  272. /* AUTOPOLL1 0x8A, 16bit register */
  273. typedef enum {
  274. AP_REG1_EN = (1 << 15),
  275. AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
  276. AP_PRE_SUP1 = (1 << 6),
  277. AP_PHY1_DFLT = (1 << 5),
  278. AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
  279. }AUTOPOLL1_BITS;
  280. typedef enum {
  281. AP_REG2_EN = (1 << 15),
  282. AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
  283. AP_PRE_SUP2 = (1 << 6),
  284. AP_PHY2_DFLT = (1 << 5),
  285. AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
  286. }AUTOPOLL2_BITS;
  287. typedef enum {
  288. AP_REG3_EN = (1 << 15),
  289. AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
  290. AP_PRE_SUP3 = (1 << 6),
  291. AP_PHY3_DFLT = (1 << 5),
  292. AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
  293. }AUTOPOLL3_BITS;
  294. typedef enum {
  295. AP_REG4_EN = (1 << 15),
  296. AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
  297. AP_PRE_SUP4 = (1 << 6),
  298. AP_PHY4_DFLT = (1 << 5),
  299. AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
  300. }AUTOPOLL4_BITS;
  301. typedef enum {
  302. AP_REG5_EN = (1 << 15),
  303. AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
  304. AP_PRE_SUP5 = (1 << 6),
  305. AP_PHY5_DFLT = (1 << 5),
  306. AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
  307. }AUTOPOLL5_BITS;
  308. /* AP_VALUE 0x98, 32bit ragister */
  309. typedef enum {
  310. AP_VAL_ACTIVE = (1 << 31),
  311. AP_VAL_RD_CMD = ( 1 << 29),
  312. AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
  313. AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
  314. (0xF << 12), /* 15:0 */
  315. }AP_VALUE_BITS;
  316. typedef enum {
  317. DLY_INT_A_R3 = (1 << 31),
  318. DLY_INT_A_R2 = (1 << 30),
  319. DLY_INT_A_R1 = (1 << 29),
  320. DLY_INT_A_R0 = (1 << 28),
  321. DLY_INT_A_T3 = (1 << 27),
  322. DLY_INT_A_T2 = (1 << 26),
  323. DLY_INT_A_T1 = (1 << 25),
  324. DLY_INT_A_T0 = ( 1 << 24),
  325. EVENT_COUNT_A = (0xF << 16) | (0x1 << 20),/* 20:16 */
  326. MAX_DELAY_TIME_A = (0xF << 0) | (0xF << 4) | (1 << 8)|
  327. (1 << 9) | (1 << 10), /* 10:0 */
  328. }DLY_INT_A_BITS;
  329. typedef enum {
  330. DLY_INT_B_R3 = (1 << 31),
  331. DLY_INT_B_R2 = (1 << 30),
  332. DLY_INT_B_R1 = (1 << 29),
  333. DLY_INT_B_R0 = (1 << 28),
  334. DLY_INT_B_T3 = (1 << 27),
  335. DLY_INT_B_T2 = (1 << 26),
  336. DLY_INT_B_T1 = (1 << 25),
  337. DLY_INT_B_T0 = ( 1 << 24),
  338. EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),/* 20:16 */
  339. MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)|
  340. (1 << 9) | (1 << 10), /* 10:0 */
  341. }DLY_INT_B_BITS;
  342. /* FLOW_CONTROL 0xC8, 32bit register */
  343. typedef enum {
  344. PAUSE_LEN_CHG = (1 << 30),
  345. FTPE = (1 << 22),
  346. FRPE = (1 << 21),
  347. NAPA = (1 << 20),
  348. NPA = (1 << 19),
  349. FIXP = ( 1 << 18),
  350. FCCMD = ( 1 << 16),
  351. PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12), /* 15:0 */
  352. }FLOW_CONTROL_BITS;
  353. /* PHY_ ACCESS 0xD0, 32bit register */
  354. typedef enum {
  355. PHY_CMD_ACTIVE = (1 << 31),
  356. PHY_WR_CMD = (1 << 30),
  357. PHY_RD_CMD = (1 << 29),
  358. PHY_RD_ERR = (1 << 28),
  359. PHY_PRE_SUP = (1 << 27),
  360. PHY_ADDR = (1 << 21) | (1 << 22) | (1 << 23)|
  361. (1 << 24) |(1 << 25),/* 25:21 */
  362. PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20),/* 20:16 */
  363. PHY_DATA = (0xF << 0)|(0xF << 4) |(0xF << 8)|
  364. (0xF << 12),/* 15:0 */
  365. }PHY_ACCESS_BITS;
  366. /* PMAT0 0x190, 32bit register */
  367. typedef enum {
  368. PMR_ACTIVE = (1 << 31),
  369. PMR_WR_CMD = (1 << 30),
  370. PMR_RD_CMD = (1 << 29),
  371. PMR_BANK = (1 <<28),
  372. PMR_ADDR = (0xF << 16)|(1 << 20)|(1 << 21)|
  373. (1 << 22),/* 22:16 */
  374. PMR_B4 = (0xF << 0) | (0xF << 4),/* 15:0 */
  375. }PMAT0_BITS;
  376. /* PMAT1 0x194, 32bit register */
  377. typedef enum {
  378. PMR_B3 = (0xF << 24) | (0xF <<28),/* 31:24 */
  379. PMR_B2 = (0xF << 16) |(0xF << 20),/* 23:16 */
  380. PMR_B1 = (0xF << 8) | (0xF <<12), /* 15:8 */
  381. PMR_B0 = (0xF << 0)|(0xF << 4),/* 7:0 */
  382. }PMAT1_BITS;
  383. /************************************************************************/
  384. /* */
  385. /* MIB counter definitions */
  386. /* */
  387. /************************************************************************/
  388. #define rcv_miss_pkts 0x00
  389. #define rcv_octets 0x01
  390. #define rcv_broadcast_pkts 0x02
  391. #define rcv_multicast_pkts 0x03
  392. #define rcv_undersize_pkts 0x04
  393. #define rcv_oversize_pkts 0x05
  394. #define rcv_fragments 0x06
  395. #define rcv_jabbers 0x07
  396. #define rcv_unicast_pkts 0x08
  397. #define rcv_alignment_errors 0x09
  398. #define rcv_fcs_errors 0x0A
  399. #define rcv_good_octets 0x0B
  400. #define rcv_mac_ctrl 0x0C
  401. #define rcv_flow_ctrl 0x0D
  402. #define rcv_pkts_64_octets 0x0E
  403. #define rcv_pkts_65to127_octets 0x0F
  404. #define rcv_pkts_128to255_octets 0x10
  405. #define rcv_pkts_256to511_octets 0x11
  406. #define rcv_pkts_512to1023_octets 0x12
  407. #define rcv_pkts_1024to1518_octets 0x13
  408. #define rcv_unsupported_opcode 0x14
  409. #define rcv_symbol_errors 0x15
  410. #define rcv_drop_pkts_ring1 0x16
  411. #define rcv_drop_pkts_ring2 0x17
  412. #define rcv_drop_pkts_ring3 0x18
  413. #define rcv_drop_pkts_ring4 0x19
  414. #define rcv_jumbo_pkts 0x1A
  415. #define xmt_underrun_pkts 0x20
  416. #define xmt_octets 0x21
  417. #define xmt_packets 0x22
  418. #define xmt_broadcast_pkts 0x23
  419. #define xmt_multicast_pkts 0x24
  420. #define xmt_collisions 0x25
  421. #define xmt_unicast_pkts 0x26
  422. #define xmt_one_collision 0x27
  423. #define xmt_multiple_collision 0x28
  424. #define xmt_deferred_transmit 0x29
  425. #define xmt_late_collision 0x2A
  426. #define xmt_excessive_defer 0x2B
  427. #define xmt_loss_carrier 0x2C
  428. #define xmt_excessive_collision 0x2D
  429. #define xmt_back_pressure 0x2E
  430. #define xmt_flow_ctrl 0x2F
  431. #define xmt_pkts_64_octets 0x30
  432. #define xmt_pkts_65to127_octets 0x31
  433. #define xmt_pkts_128to255_octets 0x32
  434. #define xmt_pkts_256to511_octets 0x33
  435. #define xmt_pkts_512to1023_octets 0x34
  436. #define xmt_pkts_1024to1518_octet 0x35
  437. #define xmt_oversize_pkts 0x36
  438. #define xmt_jumbo_pkts 0x37
  439. /* Driver definitions */
  440. #define PCI_VENDOR_ID_AMD 0x1022
  441. #define PCI_DEVICE_ID_AMD8111E_7462 0x7462
  442. #define MAX_UNITS 8 /* Maximum number of devices possible */
  443. #define NUM_TX_BUFFERS 32 /* Number of transmit buffers */
  444. #define NUM_RX_BUFFERS 32 /* Number of receive buffers */
  445. #define TX_BUFF_MOD_MASK 31 /* (NUM_TX_BUFFERS -1) */
  446. #define RX_BUFF_MOD_MASK 31 /* (NUM_RX_BUFFERS -1) */
  447. #define NUM_TX_RING_DR 32
  448. #define NUM_RX_RING_DR 32
  449. #define TX_RING_DR_MOD_MASK 31 /* (NUM_TX_RING_DR -1) */
  450. #define RX_RING_DR_MOD_MASK 31 /* (NUM_RX_RING_DR -1) */
  451. #define MAX_FILTER_SIZE 64 /* Maximum multicast address */
  452. #define AMD8111E_MIN_MTU 60
  453. #define AMD8111E_MAX_MTU 9000
  454. #define PKT_BUFF_SZ 1536
  455. #define MIN_PKT_LEN 60
  456. #define ETH_ADDR_LEN 6
  457. #define AMD8111E_TX_TIMEOUT (3 * HZ)/* 3 sec */
  458. #define SOFT_TIMER_FREQ 0xBEBC /* 0.5 sec */
  459. #define DELAY_TIMER_CONV 50 /* msec to 10 usec conversion.
  460. Only 500 usec resolution */
  461. #define OPTION_VLAN_ENABLE 0x0001
  462. #define OPTION_JUMBO_ENABLE 0x0002
  463. #define OPTION_MULTICAST_ENABLE 0x0004
  464. #define OPTION_WOL_ENABLE 0x0008
  465. #define OPTION_WAKE_MAGIC_ENABLE 0x0010
  466. #define OPTION_WAKE_PHY_ENABLE 0x0020
  467. #define OPTION_INTR_COAL_ENABLE 0x0040
  468. #define OPTION_DYN_IPG_ENABLE 0x0080
  469. #define PHY_REG_ADDR_MASK 0x1f
  470. /* ipg parameters */
  471. #define DEFAULT_IPG 0x60
  472. #define IFS1_DELTA 36
  473. #define IPG_CONVERGE_JIFFIES (HZ/2)
  474. #define IPG_STABLE_TIME 5
  475. #define MIN_IPG 96
  476. #define MAX_IPG 255
  477. #define IPG_STEP 16
  478. #define CSTATE 1
  479. #define SSTATE 2
  480. /* Assume contoller gets data 10 times the maximum processing time */
  481. #define REPEAT_CNT 10;
  482. /* amd8111e decriptor flag definitions */
  483. typedef enum {
  484. OWN_BIT = (1 << 15),
  485. ADD_FCS_BIT = (1 << 13),
  486. LTINT_BIT = (1 << 12),
  487. STP_BIT = (1 << 9),
  488. ENP_BIT = (1 << 8),
  489. KILL_BIT = (1 << 6),
  490. TCC_VLAN_INSERT = (1 << 1),
  491. TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0),
  492. }TX_FLAG_BITS;
  493. typedef enum {
  494. ERR_BIT = (1 << 14),
  495. FRAM_BIT = (1 << 13),
  496. OFLO_BIT = (1 << 12),
  497. CRC_BIT = (1 << 11),
  498. PAM_BIT = (1 << 6),
  499. LAFM_BIT = (1 << 5),
  500. BAM_BIT = (1 << 4),
  501. TT_VLAN_TAGGED = (1 << 3) |(1 << 2),/* 0x000 */
  502. TT_PRTY_TAGGED = (1 << 3),/* 0x0008 */
  503. }RX_FLAG_BITS;
  504. #define RESET_RX_FLAGS 0x0000
  505. #define TT_MASK 0x000c
  506. #define TCC_MASK 0x0003
  507. /* driver ioctl parameters */
  508. #define AMD8111E_REG_DUMP_LEN 13*sizeof(u32)
  509. /* amd8111e desriptor format */
  510. struct amd8111e_tx_dr{
  511. u16 buff_count; /* Size of the buffer pointed by this descriptor */
  512. u16 tx_flags;
  513. u16 tag_ctrl_info;
  514. u16 tag_ctrl_cmd;
  515. u32 buff_phy_addr;
  516. u32 reserved;
  517. };
  518. struct amd8111e_rx_dr{
  519. u32 reserved;
  520. u16 msg_count; /* Received message len */
  521. u16 tag_ctrl_info;
  522. u16 buff_count; /* Len of the buffer pointed by descriptor. */
  523. u16 rx_flags;
  524. u32 buff_phy_addr;
  525. };
  526. struct amd8111e_link_config{
  527. #define SPEED_INVALID 0xffff
  528. #define DUPLEX_INVALID 0xff
  529. #define AUTONEG_INVALID 0xff
  530. unsigned long orig_phy_option;
  531. u16 speed;
  532. u8 duplex;
  533. u8 autoneg;
  534. u8 reserved; /* 32bit alignment */
  535. };
  536. enum coal_type{
  537. NO_COALESCE,
  538. LOW_COALESCE,
  539. MEDIUM_COALESCE,
  540. HIGH_COALESCE,
  541. };
  542. enum coal_mode{
  543. RX_INTR_COAL,
  544. TX_INTR_COAL,
  545. DISABLE_COAL,
  546. ENABLE_COAL,
  547. };
  548. #define MAX_TIMEOUT 40
  549. #define MAX_EVENT_COUNT 31
  550. struct amd8111e_coalesce_conf{
  551. unsigned int rx_timeout;
  552. unsigned int rx_event_count;
  553. unsigned long rx_packets;
  554. unsigned long rx_prev_packets;
  555. unsigned long rx_bytes;
  556. unsigned long rx_prev_bytes;
  557. unsigned int rx_coal_type;
  558. unsigned int tx_timeout;
  559. unsigned int tx_event_count;
  560. unsigned long tx_packets;
  561. unsigned long tx_prev_packets;
  562. unsigned long tx_bytes;
  563. unsigned long tx_prev_bytes;
  564. unsigned int tx_coal_type;
  565. };
  566. struct ipg_info{
  567. unsigned int ipg_state;
  568. unsigned int ipg;
  569. unsigned int current_ipg;
  570. unsigned int col_cnt;
  571. unsigned int diff_col_cnt;
  572. unsigned int timer_tick;
  573. unsigned int prev_ipg;
  574. struct timer_list ipg_timer;
  575. };
  576. struct amd8111e_priv{
  577. struct amd8111e_tx_dr* tx_ring;
  578. struct amd8111e_rx_dr* rx_ring;
  579. dma_addr_t tx_ring_dma_addr; /* tx descriptor ring base address */
  580. dma_addr_t rx_ring_dma_addr; /* rx descriptor ring base address */
  581. const char *name;
  582. struct pci_dev *pci_dev; /* Ptr to the associated pci_dev */
  583. struct net_device* amd8111e_net_dev; /* ptr to associated net_device */
  584. /* Transmit and recive skbs */
  585. struct sk_buff *tx_skbuff[NUM_TX_BUFFERS];
  586. struct sk_buff *rx_skbuff[NUM_RX_BUFFERS];
  587. /* Transmit and receive dma mapped addr */
  588. dma_addr_t tx_dma_addr[NUM_TX_BUFFERS];
  589. dma_addr_t rx_dma_addr[NUM_RX_BUFFERS];
  590. /* Reg memory mapped address */
  591. void __iomem *mmio;
  592. spinlock_t lock; /* Guard lock */
  593. unsigned long rx_idx, tx_idx; /* The next free ring entry */
  594. unsigned long tx_complete_idx;
  595. unsigned long tx_ring_complete_idx;
  596. unsigned long tx_ring_idx;
  597. unsigned int rx_buff_len; /* Buffer length of rx buffers */
  598. int options; /* Options enabled/disabled for the device */
  599. unsigned long ext_phy_option;
  600. int ext_phy_addr;
  601. u32 ext_phy_id;
  602. struct amd8111e_link_config link_config;
  603. int pm_cap;
  604. struct net_device *next;
  605. int mii;
  606. struct mii_if_info mii_if;
  607. #if AMD8111E_VLAN_TAG_USED
  608. struct vlan_group *vlgrp;
  609. #endif
  610. char opened;
  611. struct net_device_stats stats;
  612. unsigned int drv_rx_errors;
  613. struct dev_mc_list* mc_list;
  614. struct amd8111e_coalesce_conf coal_conf;
  615. struct ipg_info ipg_data;
  616. };
  617. /* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
  618. BUG? */
  619. #define amd8111e_writeq(_UlData,_memMap) \
  620. writel(*(u32*)(&_UlData), _memMap); \
  621. writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
  622. /* maps the external speed options to internal value */
  623. typedef enum {
  624. SPEED_AUTONEG,
  625. SPEED10_HALF,
  626. SPEED10_FULL,
  627. SPEED100_HALF,
  628. SPEED100_FULL,
  629. }EXT_PHY_OPTION;
  630. static int card_idx;
  631. static int speed_duplex[MAX_UNITS] = { 0, };
  632. static int coalesce[MAX_UNITS] = {1,1,1,1,1,1,1,1};
  633. static int dynamic_ipg[MAX_UNITS] = {0,0,0,0,0,0,0,0};
  634. static unsigned int chip_version;
  635. #endif /* _AMD8111E_H */