acenic.c 86 KB

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  1. /*
  2. * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
  3. * and other Tigon based cards.
  4. *
  5. * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
  6. *
  7. * Thanks to Alteon and 3Com for providing hardware and documentation
  8. * enabling me to write this driver.
  9. *
  10. * A mailing list for discussing the use of this driver has been
  11. * setup, please subscribe to the lists if you have any questions
  12. * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
  13. * see how to subscribe.
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * Additional credits:
  21. * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
  22. * dump support. The trace dump support has not been
  23. * integrated yet however.
  24. * Troy Benjegerdes: Big Endian (PPC) patches.
  25. * Nate Stahl: Better out of memory handling and stats support.
  26. * Aman Singla: Nasty race between interrupt handler and tx code dealing
  27. * with 'testing the tx_ret_csm and setting tx_full'
  28. * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
  29. * infrastructure and Sparc support
  30. * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
  31. * driver under Linux/Sparc64
  32. * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
  33. * ETHTOOL_GDRVINFO support
  34. * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
  35. * handler and close() cleanup.
  36. * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
  37. * memory mapped IO is enabled to
  38. * make the driver work on RS/6000.
  39. * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
  40. * where the driver would disable
  41. * bus master mode if it had to disable
  42. * write and invalidate.
  43. * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
  44. * endian systems.
  45. * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
  46. * rx producer index when
  47. * flushing the Jumbo ring.
  48. * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
  49. * driver init path.
  50. * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
  51. */
  52. #include <linux/module.h>
  53. #include <linux/moduleparam.h>
  54. #include <linux/version.h>
  55. #include <linux/types.h>
  56. #include <linux/errno.h>
  57. #include <linux/ioport.h>
  58. #include <linux/pci.h>
  59. #include <linux/dma-mapping.h>
  60. #include <linux/kernel.h>
  61. #include <linux/netdevice.h>
  62. #include <linux/etherdevice.h>
  63. #include <linux/skbuff.h>
  64. #include <linux/init.h>
  65. #include <linux/delay.h>
  66. #include <linux/mm.h>
  67. #include <linux/highmem.h>
  68. #include <linux/sockios.h>
  69. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  70. #include <linux/if_vlan.h>
  71. #endif
  72. #ifdef SIOCETHTOOL
  73. #include <linux/ethtool.h>
  74. #endif
  75. #include <net/sock.h>
  76. #include <net/ip.h>
  77. #include <asm/system.h>
  78. #include <asm/io.h>
  79. #include <asm/irq.h>
  80. #include <asm/byteorder.h>
  81. #include <asm/uaccess.h>
  82. #define DRV_NAME "acenic"
  83. #undef INDEX_DEBUG
  84. #ifdef CONFIG_ACENIC_OMIT_TIGON_I
  85. #define ACE_IS_TIGON_I(ap) 0
  86. #define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
  87. #else
  88. #define ACE_IS_TIGON_I(ap) (ap->version == 1)
  89. #define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
  90. #endif
  91. #ifndef PCI_VENDOR_ID_ALTEON
  92. #define PCI_VENDOR_ID_ALTEON 0x12ae
  93. #endif
  94. #ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
  95. #define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
  96. #define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
  97. #endif
  98. #ifndef PCI_DEVICE_ID_3COM_3C985
  99. #define PCI_DEVICE_ID_3COM_3C985 0x0001
  100. #endif
  101. #ifndef PCI_VENDOR_ID_NETGEAR
  102. #define PCI_VENDOR_ID_NETGEAR 0x1385
  103. #define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
  104. #endif
  105. #ifndef PCI_DEVICE_ID_NETGEAR_GA620T
  106. #define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
  107. #endif
  108. /*
  109. * Farallon used the DEC vendor ID by mistake and they seem not
  110. * to care - stinky!
  111. */
  112. #ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
  113. #define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
  114. #endif
  115. #ifndef PCI_DEVICE_ID_FARALLON_PN9100T
  116. #define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
  117. #endif
  118. #ifndef PCI_VENDOR_ID_SGI
  119. #define PCI_VENDOR_ID_SGI 0x10a9
  120. #endif
  121. #ifndef PCI_DEVICE_ID_SGI_ACENIC
  122. #define PCI_DEVICE_ID_SGI_ACENIC 0x0009
  123. #endif
  124. static struct pci_device_id acenic_pci_tbl[] = {
  125. { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
  126. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  127. { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
  128. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  129. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
  130. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  131. { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
  132. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  133. { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
  134. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  135. /*
  136. * Farallon used the DEC vendor ID on their cards incorrectly,
  137. * then later Alteon's ID.
  138. */
  139. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
  140. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  141. { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
  142. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  143. { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
  144. PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
  145. { }
  146. };
  147. MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
  148. #ifndef SET_NETDEV_DEV
  149. #define SET_NETDEV_DEV(net, pdev) do{} while(0)
  150. #endif
  151. #define ace_sync_irq(irq) synchronize_irq(irq)
  152. #ifndef offset_in_page
  153. #define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
  154. #endif
  155. #define ACE_MAX_MOD_PARMS 8
  156. #define BOARD_IDX_STATIC 0
  157. #define BOARD_IDX_OVERFLOW -1
  158. #if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
  159. defined(NETIF_F_HW_VLAN_RX)
  160. #define ACENIC_DO_VLAN 1
  161. #define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
  162. #else
  163. #define ACENIC_DO_VLAN 0
  164. #define ACE_RCB_VLAN_FLAG 0
  165. #endif
  166. #include "acenic.h"
  167. /*
  168. * These must be defined before the firmware is included.
  169. */
  170. #define MAX_TEXT_LEN 96*1024
  171. #define MAX_RODATA_LEN 8*1024
  172. #define MAX_DATA_LEN 2*1024
  173. #include "acenic_firmware.h"
  174. #ifndef tigon2FwReleaseLocal
  175. #define tigon2FwReleaseLocal 0
  176. #endif
  177. /*
  178. * This driver currently supports Tigon I and Tigon II based cards
  179. * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
  180. * GA620. The driver should also work on the SGI, DEC and Farallon
  181. * versions of the card, however I have not been able to test that
  182. * myself.
  183. *
  184. * This card is really neat, it supports receive hardware checksumming
  185. * and jumbo frames (up to 9000 bytes) and does a lot of work in the
  186. * firmware. Also the programming interface is quite neat, except for
  187. * the parts dealing with the i2c eeprom on the card ;-)
  188. *
  189. * Using jumbo frames:
  190. *
  191. * To enable jumbo frames, simply specify an mtu between 1500 and 9000
  192. * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
  193. * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
  194. * interface number and <MTU> being the MTU value.
  195. *
  196. * Module parameters:
  197. *
  198. * When compiled as a loadable module, the driver allows for a number
  199. * of module parameters to be specified. The driver supports the
  200. * following module parameters:
  201. *
  202. * trace=<val> - Firmware trace level. This requires special traced
  203. * firmware to replace the firmware supplied with
  204. * the driver - for debugging purposes only.
  205. *
  206. * link=<val> - Link state. Normally you want to use the default link
  207. * parameters set by the driver. This can be used to
  208. * override these in case your switch doesn't negotiate
  209. * the link properly. Valid values are:
  210. * 0x0001 - Force half duplex link.
  211. * 0x0002 - Do not negotiate line speed with the other end.
  212. * 0x0010 - 10Mbit/sec link.
  213. * 0x0020 - 100Mbit/sec link.
  214. * 0x0040 - 1000Mbit/sec link.
  215. * 0x0100 - Do not negotiate flow control.
  216. * 0x0200 - Enable RX flow control Y
  217. * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
  218. * Default value is 0x0270, ie. enable link+flow
  219. * control negotiation. Negotiating the highest
  220. * possible link speed with RX flow control enabled.
  221. *
  222. * When disabling link speed negotiation, only one link
  223. * speed is allowed to be specified!
  224. *
  225. * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
  226. * to wait for more packets to arive before
  227. * interrupting the host, from the time the first
  228. * packet arrives.
  229. *
  230. * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
  231. * to wait for more packets to arive in the transmit ring,
  232. * before interrupting the host, after transmitting the
  233. * first packet in the ring.
  234. *
  235. * max_tx_desc=<val> - maximum number of transmit descriptors
  236. * (packets) transmitted before interrupting the host.
  237. *
  238. * max_rx_desc=<val> - maximum number of receive descriptors
  239. * (packets) received before interrupting the host.
  240. *
  241. * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
  242. * increments of the NIC's on board memory to be used for
  243. * transmit and receive buffers. For the 1MB NIC app. 800KB
  244. * is available, on the 1/2MB NIC app. 300KB is available.
  245. * 68KB will always be available as a minimum for both
  246. * directions. The default value is a 50/50 split.
  247. * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
  248. * operations, default (1) is to always disable this as
  249. * that is what Alteon does on NT. I have not been able
  250. * to measure any real performance differences with
  251. * this on my systems. Set <val>=0 if you want to
  252. * enable these operations.
  253. *
  254. * If you use more than one NIC, specify the parameters for the
  255. * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
  256. * run tracing on NIC #2 but not on NIC #1 and #3.
  257. *
  258. * TODO:
  259. *
  260. * - Proper multicast support.
  261. * - NIC dump support.
  262. * - More tuning parameters.
  263. *
  264. * The mini ring is not used under Linux and I am not sure it makes sense
  265. * to actually use it.
  266. *
  267. * New interrupt handler strategy:
  268. *
  269. * The old interrupt handler worked using the traditional method of
  270. * replacing an skbuff with a new one when a packet arrives. However
  271. * the rx rings do not need to contain a static number of buffer
  272. * descriptors, thus it makes sense to move the memory allocation out
  273. * of the main interrupt handler and do it in a bottom half handler
  274. * and only allocate new buffers when the number of buffers in the
  275. * ring is below a certain threshold. In order to avoid starving the
  276. * NIC under heavy load it is however necessary to force allocation
  277. * when hitting a minimum threshold. The strategy for alloction is as
  278. * follows:
  279. *
  280. * RX_LOW_BUF_THRES - allocate buffers in the bottom half
  281. * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
  282. * the buffers in the interrupt handler
  283. * RX_RING_THRES - maximum number of buffers in the rx ring
  284. * RX_MINI_THRES - maximum number of buffers in the mini ring
  285. * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
  286. *
  287. * One advantagous side effect of this allocation approach is that the
  288. * entire rx processing can be done without holding any spin lock
  289. * since the rx rings and registers are totally independent of the tx
  290. * ring and its registers. This of course includes the kmalloc's of
  291. * new skb's. Thus start_xmit can run in parallel with rx processing
  292. * and the memory allocation on SMP systems.
  293. *
  294. * Note that running the skb reallocation in a bottom half opens up
  295. * another can of races which needs to be handled properly. In
  296. * particular it can happen that the interrupt handler tries to run
  297. * the reallocation while the bottom half is either running on another
  298. * CPU or was interrupted on the same CPU. To get around this the
  299. * driver uses bitops to prevent the reallocation routines from being
  300. * reentered.
  301. *
  302. * TX handling can also be done without holding any spin lock, wheee
  303. * this is fun! since tx_ret_csm is only written to by the interrupt
  304. * handler. The case to be aware of is when shutting down the device
  305. * and cleaning up where it is necessary to make sure that
  306. * start_xmit() is not running while this is happening. Well DaveM
  307. * informs me that this case is already protected against ... bye bye
  308. * Mr. Spin Lock, it was nice to know you.
  309. *
  310. * TX interrupts are now partly disabled so the NIC will only generate
  311. * TX interrupts for the number of coal ticks, not for the number of
  312. * TX packets in the queue. This should reduce the number of TX only,
  313. * ie. when no RX processing is done, interrupts seen.
  314. */
  315. /*
  316. * Threshold values for RX buffer allocation - the low water marks for
  317. * when to start refilling the rings are set to 75% of the ring
  318. * sizes. It seems to make sense to refill the rings entirely from the
  319. * intrrupt handler once it gets below the panic threshold, that way
  320. * we don't risk that the refilling is moved to another CPU when the
  321. * one running the interrupt handler just got the slab code hot in its
  322. * cache.
  323. */
  324. #define RX_RING_SIZE 72
  325. #define RX_MINI_SIZE 64
  326. #define RX_JUMBO_SIZE 48
  327. #define RX_PANIC_STD_THRES 16
  328. #define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
  329. #define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
  330. #define RX_PANIC_MINI_THRES 12
  331. #define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
  332. #define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
  333. #define RX_PANIC_JUMBO_THRES 6
  334. #define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
  335. #define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
  336. /*
  337. * Size of the mini ring entries, basically these just should be big
  338. * enough to take TCP ACKs
  339. */
  340. #define ACE_MINI_SIZE 100
  341. #define ACE_MINI_BUFSIZE ACE_MINI_SIZE
  342. #define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
  343. #define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
  344. /*
  345. * There seems to be a magic difference in the effect between 995 and 996
  346. * but little difference between 900 and 995 ... no idea why.
  347. *
  348. * There is now a default set of tuning parameters which is set, depending
  349. * on whether or not the user enables Jumbo frames. It's assumed that if
  350. * Jumbo frames are enabled, the user wants optimal tuning for that case.
  351. */
  352. #define DEF_TX_COAL 400 /* 996 */
  353. #define DEF_TX_MAX_DESC 60 /* was 40 */
  354. #define DEF_RX_COAL 120 /* 1000 */
  355. #define DEF_RX_MAX_DESC 25
  356. #define DEF_TX_RATIO 21 /* 24 */
  357. #define DEF_JUMBO_TX_COAL 20
  358. #define DEF_JUMBO_TX_MAX_DESC 60
  359. #define DEF_JUMBO_RX_COAL 30
  360. #define DEF_JUMBO_RX_MAX_DESC 6
  361. #define DEF_JUMBO_TX_RATIO 21
  362. #if tigon2FwReleaseLocal < 20001118
  363. /*
  364. * Standard firmware and early modifications duplicate
  365. * IRQ load without this flag (coal timer is never reset).
  366. * Note that with this flag tx_coal should be less than
  367. * time to xmit full tx ring.
  368. * 400usec is not so bad for tx ring size of 128.
  369. */
  370. #define TX_COAL_INTS_ONLY 1 /* worth it */
  371. #else
  372. /*
  373. * With modified firmware, this is not necessary, but still useful.
  374. */
  375. #define TX_COAL_INTS_ONLY 1
  376. #endif
  377. #define DEF_TRACE 0
  378. #define DEF_STAT (2 * TICKS_PER_SEC)
  379. static int link[ACE_MAX_MOD_PARMS];
  380. static int trace[ACE_MAX_MOD_PARMS];
  381. static int tx_coal_tick[ACE_MAX_MOD_PARMS];
  382. static int rx_coal_tick[ACE_MAX_MOD_PARMS];
  383. static int max_tx_desc[ACE_MAX_MOD_PARMS];
  384. static int max_rx_desc[ACE_MAX_MOD_PARMS];
  385. static int tx_ratio[ACE_MAX_MOD_PARMS];
  386. static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
  387. MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
  388. MODULE_LICENSE("GPL");
  389. MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
  390. module_param_array(link, int, NULL, 0);
  391. module_param_array(trace, int, NULL, 0);
  392. module_param_array(tx_coal_tick, int, NULL, 0);
  393. module_param_array(max_tx_desc, int, NULL, 0);
  394. module_param_array(rx_coal_tick, int, NULL, 0);
  395. module_param_array(max_rx_desc, int, NULL, 0);
  396. module_param_array(tx_ratio, int, NULL, 0);
  397. MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
  398. MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
  399. MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
  400. MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
  401. MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
  402. MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
  403. MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
  404. static char version[] __devinitdata =
  405. "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
  406. " http://home.cern.ch/~jes/gige/acenic.html\n";
  407. static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
  408. static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
  409. static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
  410. static const struct ethtool_ops ace_ethtool_ops = {
  411. .get_settings = ace_get_settings,
  412. .set_settings = ace_set_settings,
  413. .get_drvinfo = ace_get_drvinfo,
  414. };
  415. static void ace_watchdog(struct net_device *dev);
  416. static int __devinit acenic_probe_one(struct pci_dev *pdev,
  417. const struct pci_device_id *id)
  418. {
  419. struct net_device *dev;
  420. struct ace_private *ap;
  421. static int boards_found;
  422. dev = alloc_etherdev(sizeof(struct ace_private));
  423. if (dev == NULL) {
  424. printk(KERN_ERR "acenic: Unable to allocate "
  425. "net_device structure!\n");
  426. return -ENOMEM;
  427. }
  428. SET_MODULE_OWNER(dev);
  429. SET_NETDEV_DEV(dev, &pdev->dev);
  430. ap = dev->priv;
  431. ap->pdev = pdev;
  432. ap->name = pci_name(pdev);
  433. dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
  434. #if ACENIC_DO_VLAN
  435. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  436. dev->vlan_rx_register = ace_vlan_rx_register;
  437. dev->vlan_rx_kill_vid = ace_vlan_rx_kill_vid;
  438. #endif
  439. if (1) {
  440. dev->tx_timeout = &ace_watchdog;
  441. dev->watchdog_timeo = 5*HZ;
  442. }
  443. dev->open = &ace_open;
  444. dev->stop = &ace_close;
  445. dev->hard_start_xmit = &ace_start_xmit;
  446. dev->get_stats = &ace_get_stats;
  447. dev->set_multicast_list = &ace_set_multicast_list;
  448. SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
  449. dev->set_mac_address = &ace_set_mac_addr;
  450. dev->change_mtu = &ace_change_mtu;
  451. /* we only display this string ONCE */
  452. if (!boards_found)
  453. printk(version);
  454. if (pci_enable_device(pdev))
  455. goto fail_free_netdev;
  456. /*
  457. * Enable master mode before we start playing with the
  458. * pci_command word since pci_set_master() will modify
  459. * it.
  460. */
  461. pci_set_master(pdev);
  462. pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
  463. /* OpenFirmware on Mac's does not set this - DOH.. */
  464. if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
  465. printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
  466. "access - was not enabled by BIOS/Firmware\n",
  467. ap->name);
  468. ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
  469. pci_write_config_word(ap->pdev, PCI_COMMAND,
  470. ap->pci_command);
  471. wmb();
  472. }
  473. pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
  474. if (ap->pci_latency <= 0x40) {
  475. ap->pci_latency = 0x40;
  476. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
  477. }
  478. /*
  479. * Remap the regs into kernel space - this is abuse of
  480. * dev->base_addr since it was means for I/O port
  481. * addresses but who gives a damn.
  482. */
  483. dev->base_addr = pci_resource_start(pdev, 0);
  484. ap->regs = ioremap(dev->base_addr, 0x4000);
  485. if (!ap->regs) {
  486. printk(KERN_ERR "%s: Unable to map I/O register, "
  487. "AceNIC %i will be disabled.\n",
  488. ap->name, boards_found);
  489. goto fail_free_netdev;
  490. }
  491. switch(pdev->vendor) {
  492. case PCI_VENDOR_ID_ALTEON:
  493. if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
  494. printk(KERN_INFO "%s: Farallon PN9100-T ",
  495. ap->name);
  496. } else {
  497. printk(KERN_INFO "%s: Alteon AceNIC ",
  498. ap->name);
  499. }
  500. break;
  501. case PCI_VENDOR_ID_3COM:
  502. printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
  503. break;
  504. case PCI_VENDOR_ID_NETGEAR:
  505. printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
  506. break;
  507. case PCI_VENDOR_ID_DEC:
  508. if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
  509. printk(KERN_INFO "%s: Farallon PN9000-SX ",
  510. ap->name);
  511. break;
  512. }
  513. case PCI_VENDOR_ID_SGI:
  514. printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
  515. break;
  516. default:
  517. printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
  518. break;
  519. }
  520. printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
  521. printk("irq %d\n", pdev->irq);
  522. #ifdef CONFIG_ACENIC_OMIT_TIGON_I
  523. if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
  524. printk(KERN_ERR "%s: Driver compiled without Tigon I"
  525. " support - NIC disabled\n", dev->name);
  526. goto fail_uninit;
  527. }
  528. #endif
  529. if (ace_allocate_descriptors(dev))
  530. goto fail_free_netdev;
  531. #ifdef MODULE
  532. if (boards_found >= ACE_MAX_MOD_PARMS)
  533. ap->board_idx = BOARD_IDX_OVERFLOW;
  534. else
  535. ap->board_idx = boards_found;
  536. #else
  537. ap->board_idx = BOARD_IDX_STATIC;
  538. #endif
  539. if (ace_init(dev))
  540. goto fail_free_netdev;
  541. if (register_netdev(dev)) {
  542. printk(KERN_ERR "acenic: device registration failed\n");
  543. goto fail_uninit;
  544. }
  545. ap->name = dev->name;
  546. if (ap->pci_using_dac)
  547. dev->features |= NETIF_F_HIGHDMA;
  548. pci_set_drvdata(pdev, dev);
  549. boards_found++;
  550. return 0;
  551. fail_uninit:
  552. ace_init_cleanup(dev);
  553. fail_free_netdev:
  554. free_netdev(dev);
  555. return -ENODEV;
  556. }
  557. static void __devexit acenic_remove_one(struct pci_dev *pdev)
  558. {
  559. struct net_device *dev = pci_get_drvdata(pdev);
  560. struct ace_private *ap = netdev_priv(dev);
  561. struct ace_regs __iomem *regs = ap->regs;
  562. short i;
  563. unregister_netdev(dev);
  564. writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
  565. if (ap->version >= 2)
  566. writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
  567. /*
  568. * This clears any pending interrupts
  569. */
  570. writel(1, &regs->Mb0Lo);
  571. readl(&regs->CpuCtrl); /* flush */
  572. /*
  573. * Make sure no other CPUs are processing interrupts
  574. * on the card before the buffers are being released.
  575. * Otherwise one might experience some `interesting'
  576. * effects.
  577. *
  578. * Then release the RX buffers - jumbo buffers were
  579. * already released in ace_close().
  580. */
  581. ace_sync_irq(dev->irq);
  582. for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
  583. struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
  584. if (skb) {
  585. struct ring_info *ringp;
  586. dma_addr_t mapping;
  587. ringp = &ap->skb->rx_std_skbuff[i];
  588. mapping = pci_unmap_addr(ringp, mapping);
  589. pci_unmap_page(ap->pdev, mapping,
  590. ACE_STD_BUFSIZE,
  591. PCI_DMA_FROMDEVICE);
  592. ap->rx_std_ring[i].size = 0;
  593. ap->skb->rx_std_skbuff[i].skb = NULL;
  594. dev_kfree_skb(skb);
  595. }
  596. }
  597. if (ap->version >= 2) {
  598. for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
  599. struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
  600. if (skb) {
  601. struct ring_info *ringp;
  602. dma_addr_t mapping;
  603. ringp = &ap->skb->rx_mini_skbuff[i];
  604. mapping = pci_unmap_addr(ringp,mapping);
  605. pci_unmap_page(ap->pdev, mapping,
  606. ACE_MINI_BUFSIZE,
  607. PCI_DMA_FROMDEVICE);
  608. ap->rx_mini_ring[i].size = 0;
  609. ap->skb->rx_mini_skbuff[i].skb = NULL;
  610. dev_kfree_skb(skb);
  611. }
  612. }
  613. }
  614. for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
  615. struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
  616. if (skb) {
  617. struct ring_info *ringp;
  618. dma_addr_t mapping;
  619. ringp = &ap->skb->rx_jumbo_skbuff[i];
  620. mapping = pci_unmap_addr(ringp, mapping);
  621. pci_unmap_page(ap->pdev, mapping,
  622. ACE_JUMBO_BUFSIZE,
  623. PCI_DMA_FROMDEVICE);
  624. ap->rx_jumbo_ring[i].size = 0;
  625. ap->skb->rx_jumbo_skbuff[i].skb = NULL;
  626. dev_kfree_skb(skb);
  627. }
  628. }
  629. ace_init_cleanup(dev);
  630. free_netdev(dev);
  631. }
  632. static struct pci_driver acenic_pci_driver = {
  633. .name = "acenic",
  634. .id_table = acenic_pci_tbl,
  635. .probe = acenic_probe_one,
  636. .remove = __devexit_p(acenic_remove_one),
  637. };
  638. static int __init acenic_init(void)
  639. {
  640. return pci_register_driver(&acenic_pci_driver);
  641. }
  642. static void __exit acenic_exit(void)
  643. {
  644. pci_unregister_driver(&acenic_pci_driver);
  645. }
  646. module_init(acenic_init);
  647. module_exit(acenic_exit);
  648. static void ace_free_descriptors(struct net_device *dev)
  649. {
  650. struct ace_private *ap = netdev_priv(dev);
  651. int size;
  652. if (ap->rx_std_ring != NULL) {
  653. size = (sizeof(struct rx_desc) *
  654. (RX_STD_RING_ENTRIES +
  655. RX_JUMBO_RING_ENTRIES +
  656. RX_MINI_RING_ENTRIES +
  657. RX_RETURN_RING_ENTRIES));
  658. pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
  659. ap->rx_ring_base_dma);
  660. ap->rx_std_ring = NULL;
  661. ap->rx_jumbo_ring = NULL;
  662. ap->rx_mini_ring = NULL;
  663. ap->rx_return_ring = NULL;
  664. }
  665. if (ap->evt_ring != NULL) {
  666. size = (sizeof(struct event) * EVT_RING_ENTRIES);
  667. pci_free_consistent(ap->pdev, size, ap->evt_ring,
  668. ap->evt_ring_dma);
  669. ap->evt_ring = NULL;
  670. }
  671. if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
  672. size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
  673. pci_free_consistent(ap->pdev, size, ap->tx_ring,
  674. ap->tx_ring_dma);
  675. }
  676. ap->tx_ring = NULL;
  677. if (ap->evt_prd != NULL) {
  678. pci_free_consistent(ap->pdev, sizeof(u32),
  679. (void *)ap->evt_prd, ap->evt_prd_dma);
  680. ap->evt_prd = NULL;
  681. }
  682. if (ap->rx_ret_prd != NULL) {
  683. pci_free_consistent(ap->pdev, sizeof(u32),
  684. (void *)ap->rx_ret_prd,
  685. ap->rx_ret_prd_dma);
  686. ap->rx_ret_prd = NULL;
  687. }
  688. if (ap->tx_csm != NULL) {
  689. pci_free_consistent(ap->pdev, sizeof(u32),
  690. (void *)ap->tx_csm, ap->tx_csm_dma);
  691. ap->tx_csm = NULL;
  692. }
  693. }
  694. static int ace_allocate_descriptors(struct net_device *dev)
  695. {
  696. struct ace_private *ap = netdev_priv(dev);
  697. int size;
  698. size = (sizeof(struct rx_desc) *
  699. (RX_STD_RING_ENTRIES +
  700. RX_JUMBO_RING_ENTRIES +
  701. RX_MINI_RING_ENTRIES +
  702. RX_RETURN_RING_ENTRIES));
  703. ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
  704. &ap->rx_ring_base_dma);
  705. if (ap->rx_std_ring == NULL)
  706. goto fail;
  707. ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
  708. ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
  709. ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
  710. size = (sizeof(struct event) * EVT_RING_ENTRIES);
  711. ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
  712. if (ap->evt_ring == NULL)
  713. goto fail;
  714. /*
  715. * Only allocate a host TX ring for the Tigon II, the Tigon I
  716. * has to use PCI registers for this ;-(
  717. */
  718. if (!ACE_IS_TIGON_I(ap)) {
  719. size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
  720. ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
  721. &ap->tx_ring_dma);
  722. if (ap->tx_ring == NULL)
  723. goto fail;
  724. }
  725. ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
  726. &ap->evt_prd_dma);
  727. if (ap->evt_prd == NULL)
  728. goto fail;
  729. ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
  730. &ap->rx_ret_prd_dma);
  731. if (ap->rx_ret_prd == NULL)
  732. goto fail;
  733. ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
  734. &ap->tx_csm_dma);
  735. if (ap->tx_csm == NULL)
  736. goto fail;
  737. return 0;
  738. fail:
  739. /* Clean up. */
  740. ace_init_cleanup(dev);
  741. return 1;
  742. }
  743. /*
  744. * Generic cleanup handling data allocated during init. Used when the
  745. * module is unloaded or if an error occurs during initialization
  746. */
  747. static void ace_init_cleanup(struct net_device *dev)
  748. {
  749. struct ace_private *ap;
  750. ap = netdev_priv(dev);
  751. ace_free_descriptors(dev);
  752. if (ap->info)
  753. pci_free_consistent(ap->pdev, sizeof(struct ace_info),
  754. ap->info, ap->info_dma);
  755. kfree(ap->skb);
  756. kfree(ap->trace_buf);
  757. if (dev->irq)
  758. free_irq(dev->irq, dev);
  759. iounmap(ap->regs);
  760. }
  761. /*
  762. * Commands are considered to be slow.
  763. */
  764. static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
  765. {
  766. u32 idx;
  767. idx = readl(&regs->CmdPrd);
  768. writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
  769. idx = (idx + 1) % CMD_RING_ENTRIES;
  770. writel(idx, &regs->CmdPrd);
  771. }
  772. static int __devinit ace_init(struct net_device *dev)
  773. {
  774. struct ace_private *ap;
  775. struct ace_regs __iomem *regs;
  776. struct ace_info *info = NULL;
  777. struct pci_dev *pdev;
  778. unsigned long myjif;
  779. u64 tmp_ptr;
  780. u32 tig_ver, mac1, mac2, tmp, pci_state;
  781. int board_idx, ecode = 0;
  782. short i;
  783. unsigned char cache_size;
  784. ap = netdev_priv(dev);
  785. regs = ap->regs;
  786. board_idx = ap->board_idx;
  787. /*
  788. * aman@sgi.com - its useful to do a NIC reset here to
  789. * address the `Firmware not running' problem subsequent
  790. * to any crashes involving the NIC
  791. */
  792. writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
  793. readl(&regs->HostCtrl); /* PCI write posting */
  794. udelay(5);
  795. /*
  796. * Don't access any other registers before this point!
  797. */
  798. #ifdef __BIG_ENDIAN
  799. /*
  800. * This will most likely need BYTE_SWAP once we switch
  801. * to using __raw_writel()
  802. */
  803. writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
  804. &regs->HostCtrl);
  805. #else
  806. writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
  807. &regs->HostCtrl);
  808. #endif
  809. readl(&regs->HostCtrl); /* PCI write posting */
  810. /*
  811. * Stop the NIC CPU and clear pending interrupts
  812. */
  813. writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
  814. readl(&regs->CpuCtrl); /* PCI write posting */
  815. writel(0, &regs->Mb0Lo);
  816. tig_ver = readl(&regs->HostCtrl) >> 28;
  817. switch(tig_ver){
  818. #ifndef CONFIG_ACENIC_OMIT_TIGON_I
  819. case 4:
  820. case 5:
  821. printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
  822. tig_ver, tigonFwReleaseMajor, tigonFwReleaseMinor,
  823. tigonFwReleaseFix);
  824. writel(0, &regs->LocalCtrl);
  825. ap->version = 1;
  826. ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
  827. break;
  828. #endif
  829. case 6:
  830. printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
  831. tig_ver, tigon2FwReleaseMajor, tigon2FwReleaseMinor,
  832. tigon2FwReleaseFix);
  833. writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
  834. readl(&regs->CpuBCtrl); /* PCI write posting */
  835. /*
  836. * The SRAM bank size does _not_ indicate the amount
  837. * of memory on the card, it controls the _bank_ size!
  838. * Ie. a 1MB AceNIC will have two banks of 512KB.
  839. */
  840. writel(SRAM_BANK_512K, &regs->LocalCtrl);
  841. writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
  842. ap->version = 2;
  843. ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
  844. break;
  845. default:
  846. printk(KERN_WARNING " Unsupported Tigon version detected "
  847. "(%i)\n", tig_ver);
  848. ecode = -ENODEV;
  849. goto init_error;
  850. }
  851. /*
  852. * ModeStat _must_ be set after the SRAM settings as this change
  853. * seems to corrupt the ModeStat and possible other registers.
  854. * The SRAM settings survive resets and setting it to the same
  855. * value a second time works as well. This is what caused the
  856. * `Firmware not running' problem on the Tigon II.
  857. */
  858. #ifdef __BIG_ENDIAN
  859. writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
  860. ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
  861. #else
  862. writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
  863. ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
  864. #endif
  865. readl(&regs->ModeStat); /* PCI write posting */
  866. mac1 = 0;
  867. for(i = 0; i < 4; i++) {
  868. int tmp;
  869. mac1 = mac1 << 8;
  870. tmp = read_eeprom_byte(dev, 0x8c+i);
  871. if (tmp < 0) {
  872. ecode = -EIO;
  873. goto init_error;
  874. } else
  875. mac1 |= (tmp & 0xff);
  876. }
  877. mac2 = 0;
  878. for(i = 4; i < 8; i++) {
  879. int tmp;
  880. mac2 = mac2 << 8;
  881. tmp = read_eeprom_byte(dev, 0x8c+i);
  882. if (tmp < 0) {
  883. ecode = -EIO;
  884. goto init_error;
  885. } else
  886. mac2 |= (tmp & 0xff);
  887. }
  888. writel(mac1, &regs->MacAddrHi);
  889. writel(mac2, &regs->MacAddrLo);
  890. printk("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
  891. (mac1 >> 8) & 0xff, mac1 & 0xff, (mac2 >> 24) &0xff,
  892. (mac2 >> 16) & 0xff, (mac2 >> 8) & 0xff, mac2 & 0xff);
  893. dev->dev_addr[0] = (mac1 >> 8) & 0xff;
  894. dev->dev_addr[1] = mac1 & 0xff;
  895. dev->dev_addr[2] = (mac2 >> 24) & 0xff;
  896. dev->dev_addr[3] = (mac2 >> 16) & 0xff;
  897. dev->dev_addr[4] = (mac2 >> 8) & 0xff;
  898. dev->dev_addr[5] = mac2 & 0xff;
  899. /*
  900. * Looks like this is necessary to deal with on all architectures,
  901. * even this %$#%$# N440BX Intel based thing doesn't get it right.
  902. * Ie. having two NICs in the machine, one will have the cache
  903. * line set at boot time, the other will not.
  904. */
  905. pdev = ap->pdev;
  906. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
  907. cache_size <<= 2;
  908. if (cache_size != SMP_CACHE_BYTES) {
  909. printk(KERN_INFO " PCI cache line size set incorrectly "
  910. "(%i bytes) by BIOS/FW, ", cache_size);
  911. if (cache_size > SMP_CACHE_BYTES)
  912. printk("expecting %i\n", SMP_CACHE_BYTES);
  913. else {
  914. printk("correcting to %i\n", SMP_CACHE_BYTES);
  915. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
  916. SMP_CACHE_BYTES >> 2);
  917. }
  918. }
  919. pci_state = readl(&regs->PciState);
  920. printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
  921. "latency: %i clks\n",
  922. (pci_state & PCI_32BIT) ? 32 : 64,
  923. (pci_state & PCI_66MHZ) ? 66 : 33,
  924. ap->pci_latency);
  925. /*
  926. * Set the max DMA transfer size. Seems that for most systems
  927. * the performance is better when no MAX parameter is
  928. * set. However for systems enabling PCI write and invalidate,
  929. * DMA writes must be set to the L1 cache line size to get
  930. * optimal performance.
  931. *
  932. * The default is now to turn the PCI write and invalidate off
  933. * - that is what Alteon does for NT.
  934. */
  935. tmp = READ_CMD_MEM | WRITE_CMD_MEM;
  936. if (ap->version >= 2) {
  937. tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
  938. /*
  939. * Tuning parameters only supported for 8 cards
  940. */
  941. if (board_idx == BOARD_IDX_OVERFLOW ||
  942. dis_pci_mem_inval[board_idx]) {
  943. if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
  944. ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
  945. pci_write_config_word(pdev, PCI_COMMAND,
  946. ap->pci_command);
  947. printk(KERN_INFO " Disabling PCI memory "
  948. "write and invalidate\n");
  949. }
  950. } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
  951. printk(KERN_INFO " PCI memory write & invalidate "
  952. "enabled by BIOS, enabling counter measures\n");
  953. switch(SMP_CACHE_BYTES) {
  954. case 16:
  955. tmp |= DMA_WRITE_MAX_16;
  956. break;
  957. case 32:
  958. tmp |= DMA_WRITE_MAX_32;
  959. break;
  960. case 64:
  961. tmp |= DMA_WRITE_MAX_64;
  962. break;
  963. case 128:
  964. tmp |= DMA_WRITE_MAX_128;
  965. break;
  966. default:
  967. printk(KERN_INFO " Cache line size %i not "
  968. "supported, PCI write and invalidate "
  969. "disabled\n", SMP_CACHE_BYTES);
  970. ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
  971. pci_write_config_word(pdev, PCI_COMMAND,
  972. ap->pci_command);
  973. }
  974. }
  975. }
  976. #ifdef __sparc__
  977. /*
  978. * On this platform, we know what the best dma settings
  979. * are. We use 64-byte maximum bursts, because if we
  980. * burst larger than the cache line size (or even cross
  981. * a 64byte boundary in a single burst) the UltraSparc
  982. * PCI controller will disconnect at 64-byte multiples.
  983. *
  984. * Read-multiple will be properly enabled above, and when
  985. * set will give the PCI controller proper hints about
  986. * prefetching.
  987. */
  988. tmp &= ~DMA_READ_WRITE_MASK;
  989. tmp |= DMA_READ_MAX_64;
  990. tmp |= DMA_WRITE_MAX_64;
  991. #endif
  992. #ifdef __alpha__
  993. tmp &= ~DMA_READ_WRITE_MASK;
  994. tmp |= DMA_READ_MAX_128;
  995. /*
  996. * All the docs say MUST NOT. Well, I did.
  997. * Nothing terrible happens, if we load wrong size.
  998. * Bit w&i still works better!
  999. */
  1000. tmp |= DMA_WRITE_MAX_128;
  1001. #endif
  1002. writel(tmp, &regs->PciState);
  1003. #if 0
  1004. /*
  1005. * The Host PCI bus controller driver has to set FBB.
  1006. * If all devices on that PCI bus support FBB, then the controller
  1007. * can enable FBB support in the Host PCI Bus controller (or on
  1008. * the PCI-PCI bridge if that applies).
  1009. * -ggg
  1010. */
  1011. /*
  1012. * I have received reports from people having problems when this
  1013. * bit is enabled.
  1014. */
  1015. if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
  1016. printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
  1017. ap->pci_command |= PCI_COMMAND_FAST_BACK;
  1018. pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
  1019. }
  1020. #endif
  1021. /*
  1022. * Configure DMA attributes.
  1023. */
  1024. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  1025. ap->pci_using_dac = 1;
  1026. } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  1027. ap->pci_using_dac = 0;
  1028. } else {
  1029. ecode = -ENODEV;
  1030. goto init_error;
  1031. }
  1032. /*
  1033. * Initialize the generic info block and the command+event rings
  1034. * and the control blocks for the transmit and receive rings
  1035. * as they need to be setup once and for all.
  1036. */
  1037. if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
  1038. &ap->info_dma))) {
  1039. ecode = -EAGAIN;
  1040. goto init_error;
  1041. }
  1042. ap->info = info;
  1043. /*
  1044. * Get the memory for the skb rings.
  1045. */
  1046. if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
  1047. ecode = -EAGAIN;
  1048. goto init_error;
  1049. }
  1050. ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
  1051. DRV_NAME, dev);
  1052. if (ecode) {
  1053. printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
  1054. DRV_NAME, pdev->irq);
  1055. goto init_error;
  1056. } else
  1057. dev->irq = pdev->irq;
  1058. #ifdef INDEX_DEBUG
  1059. spin_lock_init(&ap->debug_lock);
  1060. ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
  1061. ap->last_std_rx = 0;
  1062. ap->last_mini_rx = 0;
  1063. #endif
  1064. memset(ap->info, 0, sizeof(struct ace_info));
  1065. memset(ap->skb, 0, sizeof(struct ace_skb));
  1066. ace_load_firmware(dev);
  1067. ap->fw_running = 0;
  1068. tmp_ptr = ap->info_dma;
  1069. writel(tmp_ptr >> 32, &regs->InfoPtrHi);
  1070. writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
  1071. memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
  1072. set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
  1073. info->evt_ctrl.flags = 0;
  1074. *(ap->evt_prd) = 0;
  1075. wmb();
  1076. set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
  1077. writel(0, &regs->EvtCsm);
  1078. set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
  1079. info->cmd_ctrl.flags = 0;
  1080. info->cmd_ctrl.max_len = 0;
  1081. for (i = 0; i < CMD_RING_ENTRIES; i++)
  1082. writel(0, &regs->CmdRng[i]);
  1083. writel(0, &regs->CmdPrd);
  1084. writel(0, &regs->CmdCsm);
  1085. tmp_ptr = ap->info_dma;
  1086. tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
  1087. set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
  1088. set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
  1089. info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
  1090. info->rx_std_ctrl.flags =
  1091. RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
  1092. memset(ap->rx_std_ring, 0,
  1093. RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
  1094. for (i = 0; i < RX_STD_RING_ENTRIES; i++)
  1095. ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
  1096. ap->rx_std_skbprd = 0;
  1097. atomic_set(&ap->cur_rx_bufs, 0);
  1098. set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
  1099. (ap->rx_ring_base_dma +
  1100. (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
  1101. info->rx_jumbo_ctrl.max_len = 0;
  1102. info->rx_jumbo_ctrl.flags =
  1103. RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
  1104. memset(ap->rx_jumbo_ring, 0,
  1105. RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
  1106. for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
  1107. ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
  1108. ap->rx_jumbo_skbprd = 0;
  1109. atomic_set(&ap->cur_jumbo_bufs, 0);
  1110. memset(ap->rx_mini_ring, 0,
  1111. RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
  1112. if (ap->version >= 2) {
  1113. set_aceaddr(&info->rx_mini_ctrl.rngptr,
  1114. (ap->rx_ring_base_dma +
  1115. (sizeof(struct rx_desc) *
  1116. (RX_STD_RING_ENTRIES +
  1117. RX_JUMBO_RING_ENTRIES))));
  1118. info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
  1119. info->rx_mini_ctrl.flags =
  1120. RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
  1121. for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
  1122. ap->rx_mini_ring[i].flags =
  1123. BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
  1124. } else {
  1125. set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
  1126. info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
  1127. info->rx_mini_ctrl.max_len = 0;
  1128. }
  1129. ap->rx_mini_skbprd = 0;
  1130. atomic_set(&ap->cur_mini_bufs, 0);
  1131. set_aceaddr(&info->rx_return_ctrl.rngptr,
  1132. (ap->rx_ring_base_dma +
  1133. (sizeof(struct rx_desc) *
  1134. (RX_STD_RING_ENTRIES +
  1135. RX_JUMBO_RING_ENTRIES +
  1136. RX_MINI_RING_ENTRIES))));
  1137. info->rx_return_ctrl.flags = 0;
  1138. info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
  1139. memset(ap->rx_return_ring, 0,
  1140. RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
  1141. set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
  1142. *(ap->rx_ret_prd) = 0;
  1143. writel(TX_RING_BASE, &regs->WinBase);
  1144. if (ACE_IS_TIGON_I(ap)) {
  1145. ap->tx_ring = (struct tx_desc *) regs->Window;
  1146. for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
  1147. * sizeof(struct tx_desc)) / sizeof(u32); i++)
  1148. writel(0, (void __iomem *)ap->tx_ring + i * 4);
  1149. set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
  1150. } else {
  1151. memset(ap->tx_ring, 0,
  1152. MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
  1153. set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
  1154. }
  1155. info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
  1156. tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
  1157. /*
  1158. * The Tigon I does not like having the TX ring in host memory ;-(
  1159. */
  1160. if (!ACE_IS_TIGON_I(ap))
  1161. tmp |= RCB_FLG_TX_HOST_RING;
  1162. #if TX_COAL_INTS_ONLY
  1163. tmp |= RCB_FLG_COAL_INT_ONLY;
  1164. #endif
  1165. info->tx_ctrl.flags = tmp;
  1166. set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
  1167. /*
  1168. * Potential item for tuning parameter
  1169. */
  1170. #if 0 /* NO */
  1171. writel(DMA_THRESH_16W, &regs->DmaReadCfg);
  1172. writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
  1173. #else
  1174. writel(DMA_THRESH_8W, &regs->DmaReadCfg);
  1175. writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
  1176. #endif
  1177. writel(0, &regs->MaskInt);
  1178. writel(1, &regs->IfIdx);
  1179. #if 0
  1180. /*
  1181. * McKinley boxes do not like us fiddling with AssistState
  1182. * this early
  1183. */
  1184. writel(1, &regs->AssistState);
  1185. #endif
  1186. writel(DEF_STAT, &regs->TuneStatTicks);
  1187. writel(DEF_TRACE, &regs->TuneTrace);
  1188. ace_set_rxtx_parms(dev, 0);
  1189. if (board_idx == BOARD_IDX_OVERFLOW) {
  1190. printk(KERN_WARNING "%s: more than %i NICs detected, "
  1191. "ignoring module parameters!\n",
  1192. ap->name, ACE_MAX_MOD_PARMS);
  1193. } else if (board_idx >= 0) {
  1194. if (tx_coal_tick[board_idx])
  1195. writel(tx_coal_tick[board_idx],
  1196. &regs->TuneTxCoalTicks);
  1197. if (max_tx_desc[board_idx])
  1198. writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
  1199. if (rx_coal_tick[board_idx])
  1200. writel(rx_coal_tick[board_idx],
  1201. &regs->TuneRxCoalTicks);
  1202. if (max_rx_desc[board_idx])
  1203. writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
  1204. if (trace[board_idx])
  1205. writel(trace[board_idx], &regs->TuneTrace);
  1206. if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
  1207. writel(tx_ratio[board_idx], &regs->TxBufRat);
  1208. }
  1209. /*
  1210. * Default link parameters
  1211. */
  1212. tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
  1213. LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
  1214. if(ap->version >= 2)
  1215. tmp |= LNK_TX_FLOW_CTL_Y;
  1216. /*
  1217. * Override link default parameters
  1218. */
  1219. if ((board_idx >= 0) && link[board_idx]) {
  1220. int option = link[board_idx];
  1221. tmp = LNK_ENABLE;
  1222. if (option & 0x01) {
  1223. printk(KERN_INFO "%s: Setting half duplex link\n",
  1224. ap->name);
  1225. tmp &= ~LNK_FULL_DUPLEX;
  1226. }
  1227. if (option & 0x02)
  1228. tmp &= ~LNK_NEGOTIATE;
  1229. if (option & 0x10)
  1230. tmp |= LNK_10MB;
  1231. if (option & 0x20)
  1232. tmp |= LNK_100MB;
  1233. if (option & 0x40)
  1234. tmp |= LNK_1000MB;
  1235. if ((option & 0x70) == 0) {
  1236. printk(KERN_WARNING "%s: No media speed specified, "
  1237. "forcing auto negotiation\n", ap->name);
  1238. tmp |= LNK_NEGOTIATE | LNK_1000MB |
  1239. LNK_100MB | LNK_10MB;
  1240. }
  1241. if ((option & 0x100) == 0)
  1242. tmp |= LNK_NEG_FCTL;
  1243. else
  1244. printk(KERN_INFO "%s: Disabling flow control "
  1245. "negotiation\n", ap->name);
  1246. if (option & 0x200)
  1247. tmp |= LNK_RX_FLOW_CTL_Y;
  1248. if ((option & 0x400) && (ap->version >= 2)) {
  1249. printk(KERN_INFO "%s: Enabling TX flow control\n",
  1250. ap->name);
  1251. tmp |= LNK_TX_FLOW_CTL_Y;
  1252. }
  1253. }
  1254. ap->link = tmp;
  1255. writel(tmp, &regs->TuneLink);
  1256. if (ap->version >= 2)
  1257. writel(tmp, &regs->TuneFastLink);
  1258. if (ACE_IS_TIGON_I(ap))
  1259. writel(tigonFwStartAddr, &regs->Pc);
  1260. if (ap->version == 2)
  1261. writel(tigon2FwStartAddr, &regs->Pc);
  1262. writel(0, &regs->Mb0Lo);
  1263. /*
  1264. * Set tx_csm before we start receiving interrupts, otherwise
  1265. * the interrupt handler might think it is supposed to process
  1266. * tx ints before we are up and running, which may cause a null
  1267. * pointer access in the int handler.
  1268. */
  1269. ap->cur_rx = 0;
  1270. ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
  1271. wmb();
  1272. ace_set_txprd(regs, ap, 0);
  1273. writel(0, &regs->RxRetCsm);
  1274. /*
  1275. * Zero the stats before starting the interface
  1276. */
  1277. memset(&ap->stats, 0, sizeof(ap->stats));
  1278. /*
  1279. * Enable DMA engine now.
  1280. * If we do this sooner, Mckinley box pukes.
  1281. * I assume it's because Tigon II DMA engine wants to check
  1282. * *something* even before the CPU is started.
  1283. */
  1284. writel(1, &regs->AssistState); /* enable DMA */
  1285. /*
  1286. * Start the NIC CPU
  1287. */
  1288. writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
  1289. readl(&regs->CpuCtrl);
  1290. /*
  1291. * Wait for the firmware to spin up - max 3 seconds.
  1292. */
  1293. myjif = jiffies + 3 * HZ;
  1294. while (time_before(jiffies, myjif) && !ap->fw_running)
  1295. cpu_relax();
  1296. if (!ap->fw_running) {
  1297. printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
  1298. ace_dump_trace(ap);
  1299. writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
  1300. readl(&regs->CpuCtrl);
  1301. /* aman@sgi.com - account for badly behaving firmware/NIC:
  1302. * - have observed that the NIC may continue to generate
  1303. * interrupts for some reason; attempt to stop it - halt
  1304. * second CPU for Tigon II cards, and also clear Mb0
  1305. * - if we're a module, we'll fail to load if this was
  1306. * the only GbE card in the system => if the kernel does
  1307. * see an interrupt from the NIC, code to handle it is
  1308. * gone and OOps! - so free_irq also
  1309. */
  1310. if (ap->version >= 2)
  1311. writel(readl(&regs->CpuBCtrl) | CPU_HALT,
  1312. &regs->CpuBCtrl);
  1313. writel(0, &regs->Mb0Lo);
  1314. readl(&regs->Mb0Lo);
  1315. ecode = -EBUSY;
  1316. goto init_error;
  1317. }
  1318. /*
  1319. * We load the ring here as there seem to be no way to tell the
  1320. * firmware to wipe the ring without re-initializing it.
  1321. */
  1322. if (!test_and_set_bit(0, &ap->std_refill_busy))
  1323. ace_load_std_rx_ring(ap, RX_RING_SIZE);
  1324. else
  1325. printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
  1326. ap->name);
  1327. if (ap->version >= 2) {
  1328. if (!test_and_set_bit(0, &ap->mini_refill_busy))
  1329. ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
  1330. else
  1331. printk(KERN_ERR "%s: Someone is busy refilling "
  1332. "the RX mini ring\n", ap->name);
  1333. }
  1334. return 0;
  1335. init_error:
  1336. ace_init_cleanup(dev);
  1337. return ecode;
  1338. }
  1339. static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
  1340. {
  1341. struct ace_private *ap = netdev_priv(dev);
  1342. struct ace_regs __iomem *regs = ap->regs;
  1343. int board_idx = ap->board_idx;
  1344. if (board_idx >= 0) {
  1345. if (!jumbo) {
  1346. if (!tx_coal_tick[board_idx])
  1347. writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
  1348. if (!max_tx_desc[board_idx])
  1349. writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
  1350. if (!rx_coal_tick[board_idx])
  1351. writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
  1352. if (!max_rx_desc[board_idx])
  1353. writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
  1354. if (!tx_ratio[board_idx])
  1355. writel(DEF_TX_RATIO, &regs->TxBufRat);
  1356. } else {
  1357. if (!tx_coal_tick[board_idx])
  1358. writel(DEF_JUMBO_TX_COAL,
  1359. &regs->TuneTxCoalTicks);
  1360. if (!max_tx_desc[board_idx])
  1361. writel(DEF_JUMBO_TX_MAX_DESC,
  1362. &regs->TuneMaxTxDesc);
  1363. if (!rx_coal_tick[board_idx])
  1364. writel(DEF_JUMBO_RX_COAL,
  1365. &regs->TuneRxCoalTicks);
  1366. if (!max_rx_desc[board_idx])
  1367. writel(DEF_JUMBO_RX_MAX_DESC,
  1368. &regs->TuneMaxRxDesc);
  1369. if (!tx_ratio[board_idx])
  1370. writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
  1371. }
  1372. }
  1373. }
  1374. static void ace_watchdog(struct net_device *data)
  1375. {
  1376. struct net_device *dev = data;
  1377. struct ace_private *ap = netdev_priv(dev);
  1378. struct ace_regs __iomem *regs = ap->regs;
  1379. /*
  1380. * We haven't received a stats update event for more than 2.5
  1381. * seconds and there is data in the transmit queue, thus we
  1382. * asume the card is stuck.
  1383. */
  1384. if (*ap->tx_csm != ap->tx_ret_csm) {
  1385. printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
  1386. dev->name, (unsigned int)readl(&regs->HostCtrl));
  1387. /* This can happen due to ieee flow control. */
  1388. } else {
  1389. printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
  1390. dev->name);
  1391. #if 0
  1392. netif_wake_queue(dev);
  1393. #endif
  1394. }
  1395. }
  1396. static void ace_tasklet(unsigned long dev)
  1397. {
  1398. struct ace_private *ap = netdev_priv((struct net_device *)dev);
  1399. int cur_size;
  1400. cur_size = atomic_read(&ap->cur_rx_bufs);
  1401. if ((cur_size < RX_LOW_STD_THRES) &&
  1402. !test_and_set_bit(0, &ap->std_refill_busy)) {
  1403. #ifdef DEBUG
  1404. printk("refilling buffers (current %i)\n", cur_size);
  1405. #endif
  1406. ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
  1407. }
  1408. if (ap->version >= 2) {
  1409. cur_size = atomic_read(&ap->cur_mini_bufs);
  1410. if ((cur_size < RX_LOW_MINI_THRES) &&
  1411. !test_and_set_bit(0, &ap->mini_refill_busy)) {
  1412. #ifdef DEBUG
  1413. printk("refilling mini buffers (current %i)\n",
  1414. cur_size);
  1415. #endif
  1416. ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
  1417. }
  1418. }
  1419. cur_size = atomic_read(&ap->cur_jumbo_bufs);
  1420. if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
  1421. !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
  1422. #ifdef DEBUG
  1423. printk("refilling jumbo buffers (current %i)\n", cur_size);
  1424. #endif
  1425. ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
  1426. }
  1427. ap->tasklet_pending = 0;
  1428. }
  1429. /*
  1430. * Copy the contents of the NIC's trace buffer to kernel memory.
  1431. */
  1432. static void ace_dump_trace(struct ace_private *ap)
  1433. {
  1434. #if 0
  1435. if (!ap->trace_buf)
  1436. if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
  1437. return;
  1438. #endif
  1439. }
  1440. /*
  1441. * Load the standard rx ring.
  1442. *
  1443. * Loading rings is safe without holding the spin lock since this is
  1444. * done only before the device is enabled, thus no interrupts are
  1445. * generated and by the interrupt handler/tasklet handler.
  1446. */
  1447. static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
  1448. {
  1449. struct ace_regs __iomem *regs = ap->regs;
  1450. short i, idx;
  1451. prefetchw(&ap->cur_rx_bufs);
  1452. idx = ap->rx_std_skbprd;
  1453. for (i = 0; i < nr_bufs; i++) {
  1454. struct sk_buff *skb;
  1455. struct rx_desc *rd;
  1456. dma_addr_t mapping;
  1457. skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
  1458. if (!skb)
  1459. break;
  1460. skb_reserve(skb, NET_IP_ALIGN);
  1461. mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
  1462. offset_in_page(skb->data),
  1463. ACE_STD_BUFSIZE,
  1464. PCI_DMA_FROMDEVICE);
  1465. ap->skb->rx_std_skbuff[idx].skb = skb;
  1466. pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
  1467. mapping, mapping);
  1468. rd = &ap->rx_std_ring[idx];
  1469. set_aceaddr(&rd->addr, mapping);
  1470. rd->size = ACE_STD_BUFSIZE;
  1471. rd->idx = idx;
  1472. idx = (idx + 1) % RX_STD_RING_ENTRIES;
  1473. }
  1474. if (!i)
  1475. goto error_out;
  1476. atomic_add(i, &ap->cur_rx_bufs);
  1477. ap->rx_std_skbprd = idx;
  1478. if (ACE_IS_TIGON_I(ap)) {
  1479. struct cmd cmd;
  1480. cmd.evt = C_SET_RX_PRD_IDX;
  1481. cmd.code = 0;
  1482. cmd.idx = ap->rx_std_skbprd;
  1483. ace_issue_cmd(regs, &cmd);
  1484. } else {
  1485. writel(idx, &regs->RxStdPrd);
  1486. wmb();
  1487. }
  1488. out:
  1489. clear_bit(0, &ap->std_refill_busy);
  1490. return;
  1491. error_out:
  1492. printk(KERN_INFO "Out of memory when allocating "
  1493. "standard receive buffers\n");
  1494. goto out;
  1495. }
  1496. static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
  1497. {
  1498. struct ace_regs __iomem *regs = ap->regs;
  1499. short i, idx;
  1500. prefetchw(&ap->cur_mini_bufs);
  1501. idx = ap->rx_mini_skbprd;
  1502. for (i = 0; i < nr_bufs; i++) {
  1503. struct sk_buff *skb;
  1504. struct rx_desc *rd;
  1505. dma_addr_t mapping;
  1506. skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
  1507. if (!skb)
  1508. break;
  1509. skb_reserve(skb, NET_IP_ALIGN);
  1510. mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
  1511. offset_in_page(skb->data),
  1512. ACE_MINI_BUFSIZE,
  1513. PCI_DMA_FROMDEVICE);
  1514. ap->skb->rx_mini_skbuff[idx].skb = skb;
  1515. pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
  1516. mapping, mapping);
  1517. rd = &ap->rx_mini_ring[idx];
  1518. set_aceaddr(&rd->addr, mapping);
  1519. rd->size = ACE_MINI_BUFSIZE;
  1520. rd->idx = idx;
  1521. idx = (idx + 1) % RX_MINI_RING_ENTRIES;
  1522. }
  1523. if (!i)
  1524. goto error_out;
  1525. atomic_add(i, &ap->cur_mini_bufs);
  1526. ap->rx_mini_skbprd = idx;
  1527. writel(idx, &regs->RxMiniPrd);
  1528. wmb();
  1529. out:
  1530. clear_bit(0, &ap->mini_refill_busy);
  1531. return;
  1532. error_out:
  1533. printk(KERN_INFO "Out of memory when allocating "
  1534. "mini receive buffers\n");
  1535. goto out;
  1536. }
  1537. /*
  1538. * Load the jumbo rx ring, this may happen at any time if the MTU
  1539. * is changed to a value > 1500.
  1540. */
  1541. static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
  1542. {
  1543. struct ace_regs __iomem *regs = ap->regs;
  1544. short i, idx;
  1545. idx = ap->rx_jumbo_skbprd;
  1546. for (i = 0; i < nr_bufs; i++) {
  1547. struct sk_buff *skb;
  1548. struct rx_desc *rd;
  1549. dma_addr_t mapping;
  1550. skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
  1551. if (!skb)
  1552. break;
  1553. skb_reserve(skb, NET_IP_ALIGN);
  1554. mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
  1555. offset_in_page(skb->data),
  1556. ACE_JUMBO_BUFSIZE,
  1557. PCI_DMA_FROMDEVICE);
  1558. ap->skb->rx_jumbo_skbuff[idx].skb = skb;
  1559. pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
  1560. mapping, mapping);
  1561. rd = &ap->rx_jumbo_ring[idx];
  1562. set_aceaddr(&rd->addr, mapping);
  1563. rd->size = ACE_JUMBO_BUFSIZE;
  1564. rd->idx = idx;
  1565. idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
  1566. }
  1567. if (!i)
  1568. goto error_out;
  1569. atomic_add(i, &ap->cur_jumbo_bufs);
  1570. ap->rx_jumbo_skbprd = idx;
  1571. if (ACE_IS_TIGON_I(ap)) {
  1572. struct cmd cmd;
  1573. cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
  1574. cmd.code = 0;
  1575. cmd.idx = ap->rx_jumbo_skbprd;
  1576. ace_issue_cmd(regs, &cmd);
  1577. } else {
  1578. writel(idx, &regs->RxJumboPrd);
  1579. wmb();
  1580. }
  1581. out:
  1582. clear_bit(0, &ap->jumbo_refill_busy);
  1583. return;
  1584. error_out:
  1585. if (net_ratelimit())
  1586. printk(KERN_INFO "Out of memory when allocating "
  1587. "jumbo receive buffers\n");
  1588. goto out;
  1589. }
  1590. /*
  1591. * All events are considered to be slow (RX/TX ints do not generate
  1592. * events) and are handled here, outside the main interrupt handler,
  1593. * to reduce the size of the handler.
  1594. */
  1595. static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
  1596. {
  1597. struct ace_private *ap;
  1598. ap = netdev_priv(dev);
  1599. while (evtcsm != evtprd) {
  1600. switch (ap->evt_ring[evtcsm].evt) {
  1601. case E_FW_RUNNING:
  1602. printk(KERN_INFO "%s: Firmware up and running\n",
  1603. ap->name);
  1604. ap->fw_running = 1;
  1605. wmb();
  1606. break;
  1607. case E_STATS_UPDATED:
  1608. break;
  1609. case E_LNK_STATE:
  1610. {
  1611. u16 code = ap->evt_ring[evtcsm].code;
  1612. switch (code) {
  1613. case E_C_LINK_UP:
  1614. {
  1615. u32 state = readl(&ap->regs->GigLnkState);
  1616. printk(KERN_WARNING "%s: Optical link UP "
  1617. "(%s Duplex, Flow Control: %s%s)\n",
  1618. ap->name,
  1619. state & LNK_FULL_DUPLEX ? "Full":"Half",
  1620. state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
  1621. state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
  1622. break;
  1623. }
  1624. case E_C_LINK_DOWN:
  1625. printk(KERN_WARNING "%s: Optical link DOWN\n",
  1626. ap->name);
  1627. break;
  1628. case E_C_LINK_10_100:
  1629. printk(KERN_WARNING "%s: 10/100BaseT link "
  1630. "UP\n", ap->name);
  1631. break;
  1632. default:
  1633. printk(KERN_ERR "%s: Unknown optical link "
  1634. "state %02x\n", ap->name, code);
  1635. }
  1636. break;
  1637. }
  1638. case E_ERROR:
  1639. switch(ap->evt_ring[evtcsm].code) {
  1640. case E_C_ERR_INVAL_CMD:
  1641. printk(KERN_ERR "%s: invalid command error\n",
  1642. ap->name);
  1643. break;
  1644. case E_C_ERR_UNIMP_CMD:
  1645. printk(KERN_ERR "%s: unimplemented command "
  1646. "error\n", ap->name);
  1647. break;
  1648. case E_C_ERR_BAD_CFG:
  1649. printk(KERN_ERR "%s: bad config error\n",
  1650. ap->name);
  1651. break;
  1652. default:
  1653. printk(KERN_ERR "%s: unknown error %02x\n",
  1654. ap->name, ap->evt_ring[evtcsm].code);
  1655. }
  1656. break;
  1657. case E_RESET_JUMBO_RNG:
  1658. {
  1659. int i;
  1660. for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
  1661. if (ap->skb->rx_jumbo_skbuff[i].skb) {
  1662. ap->rx_jumbo_ring[i].size = 0;
  1663. set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
  1664. dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
  1665. ap->skb->rx_jumbo_skbuff[i].skb = NULL;
  1666. }
  1667. }
  1668. if (ACE_IS_TIGON_I(ap)) {
  1669. struct cmd cmd;
  1670. cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
  1671. cmd.code = 0;
  1672. cmd.idx = 0;
  1673. ace_issue_cmd(ap->regs, &cmd);
  1674. } else {
  1675. writel(0, &((ap->regs)->RxJumboPrd));
  1676. wmb();
  1677. }
  1678. ap->jumbo = 0;
  1679. ap->rx_jumbo_skbprd = 0;
  1680. printk(KERN_INFO "%s: Jumbo ring flushed\n",
  1681. ap->name);
  1682. clear_bit(0, &ap->jumbo_refill_busy);
  1683. break;
  1684. }
  1685. default:
  1686. printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
  1687. ap->name, ap->evt_ring[evtcsm].evt);
  1688. }
  1689. evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
  1690. }
  1691. return evtcsm;
  1692. }
  1693. static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
  1694. {
  1695. struct ace_private *ap = netdev_priv(dev);
  1696. u32 idx;
  1697. int mini_count = 0, std_count = 0;
  1698. idx = rxretcsm;
  1699. prefetchw(&ap->cur_rx_bufs);
  1700. prefetchw(&ap->cur_mini_bufs);
  1701. while (idx != rxretprd) {
  1702. struct ring_info *rip;
  1703. struct sk_buff *skb;
  1704. struct rx_desc *rxdesc, *retdesc;
  1705. u32 skbidx;
  1706. int bd_flags, desc_type, mapsize;
  1707. u16 csum;
  1708. /* make sure the rx descriptor isn't read before rxretprd */
  1709. if (idx == rxretcsm)
  1710. rmb();
  1711. retdesc = &ap->rx_return_ring[idx];
  1712. skbidx = retdesc->idx;
  1713. bd_flags = retdesc->flags;
  1714. desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
  1715. switch(desc_type) {
  1716. /*
  1717. * Normal frames do not have any flags set
  1718. *
  1719. * Mini and normal frames arrive frequently,
  1720. * so use a local counter to avoid doing
  1721. * atomic operations for each packet arriving.
  1722. */
  1723. case 0:
  1724. rip = &ap->skb->rx_std_skbuff[skbidx];
  1725. mapsize = ACE_STD_BUFSIZE;
  1726. rxdesc = &ap->rx_std_ring[skbidx];
  1727. std_count++;
  1728. break;
  1729. case BD_FLG_JUMBO:
  1730. rip = &ap->skb->rx_jumbo_skbuff[skbidx];
  1731. mapsize = ACE_JUMBO_BUFSIZE;
  1732. rxdesc = &ap->rx_jumbo_ring[skbidx];
  1733. atomic_dec(&ap->cur_jumbo_bufs);
  1734. break;
  1735. case BD_FLG_MINI:
  1736. rip = &ap->skb->rx_mini_skbuff[skbidx];
  1737. mapsize = ACE_MINI_BUFSIZE;
  1738. rxdesc = &ap->rx_mini_ring[skbidx];
  1739. mini_count++;
  1740. break;
  1741. default:
  1742. printk(KERN_INFO "%s: unknown frame type (0x%02x) "
  1743. "returned by NIC\n", dev->name,
  1744. retdesc->flags);
  1745. goto error;
  1746. }
  1747. skb = rip->skb;
  1748. rip->skb = NULL;
  1749. pci_unmap_page(ap->pdev,
  1750. pci_unmap_addr(rip, mapping),
  1751. mapsize,
  1752. PCI_DMA_FROMDEVICE);
  1753. skb_put(skb, retdesc->size);
  1754. /*
  1755. * Fly baby, fly!
  1756. */
  1757. csum = retdesc->tcp_udp_csum;
  1758. skb->dev = dev;
  1759. skb->protocol = eth_type_trans(skb, dev);
  1760. /*
  1761. * Instead of forcing the poor tigon mips cpu to calculate
  1762. * pseudo hdr checksum, we do this ourselves.
  1763. */
  1764. if (bd_flags & BD_FLG_TCP_UDP_SUM) {
  1765. skb->csum = htons(csum);
  1766. skb->ip_summed = CHECKSUM_COMPLETE;
  1767. } else {
  1768. skb->ip_summed = CHECKSUM_NONE;
  1769. }
  1770. /* send it up */
  1771. #if ACENIC_DO_VLAN
  1772. if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
  1773. vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
  1774. } else
  1775. #endif
  1776. netif_rx(skb);
  1777. dev->last_rx = jiffies;
  1778. ap->stats.rx_packets++;
  1779. ap->stats.rx_bytes += retdesc->size;
  1780. idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
  1781. }
  1782. atomic_sub(std_count, &ap->cur_rx_bufs);
  1783. if (!ACE_IS_TIGON_I(ap))
  1784. atomic_sub(mini_count, &ap->cur_mini_bufs);
  1785. out:
  1786. /*
  1787. * According to the documentation RxRetCsm is obsolete with
  1788. * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
  1789. */
  1790. if (ACE_IS_TIGON_I(ap)) {
  1791. writel(idx, &ap->regs->RxRetCsm);
  1792. }
  1793. ap->cur_rx = idx;
  1794. return;
  1795. error:
  1796. idx = rxretprd;
  1797. goto out;
  1798. }
  1799. static inline void ace_tx_int(struct net_device *dev,
  1800. u32 txcsm, u32 idx)
  1801. {
  1802. struct ace_private *ap = netdev_priv(dev);
  1803. do {
  1804. struct sk_buff *skb;
  1805. dma_addr_t mapping;
  1806. struct tx_ring_info *info;
  1807. info = ap->skb->tx_skbuff + idx;
  1808. skb = info->skb;
  1809. mapping = pci_unmap_addr(info, mapping);
  1810. if (mapping) {
  1811. pci_unmap_page(ap->pdev, mapping,
  1812. pci_unmap_len(info, maplen),
  1813. PCI_DMA_TODEVICE);
  1814. pci_unmap_addr_set(info, mapping, 0);
  1815. }
  1816. if (skb) {
  1817. ap->stats.tx_packets++;
  1818. ap->stats.tx_bytes += skb->len;
  1819. dev_kfree_skb_irq(skb);
  1820. info->skb = NULL;
  1821. }
  1822. idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
  1823. } while (idx != txcsm);
  1824. if (netif_queue_stopped(dev))
  1825. netif_wake_queue(dev);
  1826. wmb();
  1827. ap->tx_ret_csm = txcsm;
  1828. /* So... tx_ret_csm is advanced _after_ check for device wakeup.
  1829. *
  1830. * We could try to make it before. In this case we would get
  1831. * the following race condition: hard_start_xmit on other cpu
  1832. * enters after we advanced tx_ret_csm and fills space,
  1833. * which we have just freed, so that we make illegal device wakeup.
  1834. * There is no good way to workaround this (at entry
  1835. * to ace_start_xmit detects this condition and prevents
  1836. * ring corruption, but it is not a good workaround.)
  1837. *
  1838. * When tx_ret_csm is advanced after, we wake up device _only_
  1839. * if we really have some space in ring (though the core doing
  1840. * hard_start_xmit can see full ring for some period and has to
  1841. * synchronize.) Superb.
  1842. * BUT! We get another subtle race condition. hard_start_xmit
  1843. * may think that ring is full between wakeup and advancing
  1844. * tx_ret_csm and will stop device instantly! It is not so bad.
  1845. * We are guaranteed that there is something in ring, so that
  1846. * the next irq will resume transmission. To speedup this we could
  1847. * mark descriptor, which closes ring with BD_FLG_COAL_NOW
  1848. * (see ace_start_xmit).
  1849. *
  1850. * Well, this dilemma exists in all lock-free devices.
  1851. * We, following scheme used in drivers by Donald Becker,
  1852. * select the least dangerous.
  1853. * --ANK
  1854. */
  1855. }
  1856. static irqreturn_t ace_interrupt(int irq, void *dev_id)
  1857. {
  1858. struct net_device *dev = (struct net_device *)dev_id;
  1859. struct ace_private *ap = netdev_priv(dev);
  1860. struct ace_regs __iomem *regs = ap->regs;
  1861. u32 idx;
  1862. u32 txcsm, rxretcsm, rxretprd;
  1863. u32 evtcsm, evtprd;
  1864. /*
  1865. * In case of PCI shared interrupts or spurious interrupts,
  1866. * we want to make sure it is actually our interrupt before
  1867. * spending any time in here.
  1868. */
  1869. if (!(readl(&regs->HostCtrl) & IN_INT))
  1870. return IRQ_NONE;
  1871. /*
  1872. * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
  1873. * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
  1874. * writel(0, &regs->Mb0Lo).
  1875. *
  1876. * "IRQ avoidance" recommended in docs applies to IRQs served
  1877. * threads and it is wrong even for that case.
  1878. */
  1879. writel(0, &regs->Mb0Lo);
  1880. readl(&regs->Mb0Lo);
  1881. /*
  1882. * There is no conflict between transmit handling in
  1883. * start_xmit and receive processing, thus there is no reason
  1884. * to take a spin lock for RX handling. Wait until we start
  1885. * working on the other stuff - hey we don't need a spin lock
  1886. * anymore.
  1887. */
  1888. rxretprd = *ap->rx_ret_prd;
  1889. rxretcsm = ap->cur_rx;
  1890. if (rxretprd != rxretcsm)
  1891. ace_rx_int(dev, rxretprd, rxretcsm);
  1892. txcsm = *ap->tx_csm;
  1893. idx = ap->tx_ret_csm;
  1894. if (txcsm != idx) {
  1895. /*
  1896. * If each skb takes only one descriptor this check degenerates
  1897. * to identity, because new space has just been opened.
  1898. * But if skbs are fragmented we must check that this index
  1899. * update releases enough of space, otherwise we just
  1900. * wait for device to make more work.
  1901. */
  1902. if (!tx_ring_full(ap, txcsm, ap->tx_prd))
  1903. ace_tx_int(dev, txcsm, idx);
  1904. }
  1905. evtcsm = readl(&regs->EvtCsm);
  1906. evtprd = *ap->evt_prd;
  1907. if (evtcsm != evtprd) {
  1908. evtcsm = ace_handle_event(dev, evtcsm, evtprd);
  1909. writel(evtcsm, &regs->EvtCsm);
  1910. }
  1911. /*
  1912. * This has to go last in the interrupt handler and run with
  1913. * the spin lock released ... what lock?
  1914. */
  1915. if (netif_running(dev)) {
  1916. int cur_size;
  1917. int run_tasklet = 0;
  1918. cur_size = atomic_read(&ap->cur_rx_bufs);
  1919. if (cur_size < RX_LOW_STD_THRES) {
  1920. if ((cur_size < RX_PANIC_STD_THRES) &&
  1921. !test_and_set_bit(0, &ap->std_refill_busy)) {
  1922. #ifdef DEBUG
  1923. printk("low on std buffers %i\n", cur_size);
  1924. #endif
  1925. ace_load_std_rx_ring(ap,
  1926. RX_RING_SIZE - cur_size);
  1927. } else
  1928. run_tasklet = 1;
  1929. }
  1930. if (!ACE_IS_TIGON_I(ap)) {
  1931. cur_size = atomic_read(&ap->cur_mini_bufs);
  1932. if (cur_size < RX_LOW_MINI_THRES) {
  1933. if ((cur_size < RX_PANIC_MINI_THRES) &&
  1934. !test_and_set_bit(0,
  1935. &ap->mini_refill_busy)) {
  1936. #ifdef DEBUG
  1937. printk("low on mini buffers %i\n",
  1938. cur_size);
  1939. #endif
  1940. ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
  1941. } else
  1942. run_tasklet = 1;
  1943. }
  1944. }
  1945. if (ap->jumbo) {
  1946. cur_size = atomic_read(&ap->cur_jumbo_bufs);
  1947. if (cur_size < RX_LOW_JUMBO_THRES) {
  1948. if ((cur_size < RX_PANIC_JUMBO_THRES) &&
  1949. !test_and_set_bit(0,
  1950. &ap->jumbo_refill_busy)){
  1951. #ifdef DEBUG
  1952. printk("low on jumbo buffers %i\n",
  1953. cur_size);
  1954. #endif
  1955. ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
  1956. } else
  1957. run_tasklet = 1;
  1958. }
  1959. }
  1960. if (run_tasklet && !ap->tasklet_pending) {
  1961. ap->tasklet_pending = 1;
  1962. tasklet_schedule(&ap->ace_tasklet);
  1963. }
  1964. }
  1965. return IRQ_HANDLED;
  1966. }
  1967. #if ACENIC_DO_VLAN
  1968. static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  1969. {
  1970. struct ace_private *ap = netdev_priv(dev);
  1971. unsigned long flags;
  1972. local_irq_save(flags);
  1973. ace_mask_irq(dev);
  1974. ap->vlgrp = grp;
  1975. ace_unmask_irq(dev);
  1976. local_irq_restore(flags);
  1977. }
  1978. static void ace_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
  1979. {
  1980. struct ace_private *ap = netdev_priv(dev);
  1981. unsigned long flags;
  1982. local_irq_save(flags);
  1983. ace_mask_irq(dev);
  1984. vlan_group_set_device(ap->vlgrp, vid, NULL);
  1985. ace_unmask_irq(dev);
  1986. local_irq_restore(flags);
  1987. }
  1988. #endif /* ACENIC_DO_VLAN */
  1989. static int ace_open(struct net_device *dev)
  1990. {
  1991. struct ace_private *ap = netdev_priv(dev);
  1992. struct ace_regs __iomem *regs = ap->regs;
  1993. struct cmd cmd;
  1994. if (!(ap->fw_running)) {
  1995. printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
  1996. return -EBUSY;
  1997. }
  1998. writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
  1999. cmd.evt = C_CLEAR_STATS;
  2000. cmd.code = 0;
  2001. cmd.idx = 0;
  2002. ace_issue_cmd(regs, &cmd);
  2003. cmd.evt = C_HOST_STATE;
  2004. cmd.code = C_C_STACK_UP;
  2005. cmd.idx = 0;
  2006. ace_issue_cmd(regs, &cmd);
  2007. if (ap->jumbo &&
  2008. !test_and_set_bit(0, &ap->jumbo_refill_busy))
  2009. ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
  2010. if (dev->flags & IFF_PROMISC) {
  2011. cmd.evt = C_SET_PROMISC_MODE;
  2012. cmd.code = C_C_PROMISC_ENABLE;
  2013. cmd.idx = 0;
  2014. ace_issue_cmd(regs, &cmd);
  2015. ap->promisc = 1;
  2016. }else
  2017. ap->promisc = 0;
  2018. ap->mcast_all = 0;
  2019. #if 0
  2020. cmd.evt = C_LNK_NEGOTIATION;
  2021. cmd.code = 0;
  2022. cmd.idx = 0;
  2023. ace_issue_cmd(regs, &cmd);
  2024. #endif
  2025. netif_start_queue(dev);
  2026. /*
  2027. * Setup the bottom half rx ring refill handler
  2028. */
  2029. tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
  2030. return 0;
  2031. }
  2032. static int ace_close(struct net_device *dev)
  2033. {
  2034. struct ace_private *ap = netdev_priv(dev);
  2035. struct ace_regs __iomem *regs = ap->regs;
  2036. struct cmd cmd;
  2037. unsigned long flags;
  2038. short i;
  2039. /*
  2040. * Without (or before) releasing irq and stopping hardware, this
  2041. * is an absolute non-sense, by the way. It will be reset instantly
  2042. * by the first irq.
  2043. */
  2044. netif_stop_queue(dev);
  2045. if (ap->promisc) {
  2046. cmd.evt = C_SET_PROMISC_MODE;
  2047. cmd.code = C_C_PROMISC_DISABLE;
  2048. cmd.idx = 0;
  2049. ace_issue_cmd(regs, &cmd);
  2050. ap->promisc = 0;
  2051. }
  2052. cmd.evt = C_HOST_STATE;
  2053. cmd.code = C_C_STACK_DOWN;
  2054. cmd.idx = 0;
  2055. ace_issue_cmd(regs, &cmd);
  2056. tasklet_kill(&ap->ace_tasklet);
  2057. /*
  2058. * Make sure one CPU is not processing packets while
  2059. * buffers are being released by another.
  2060. */
  2061. local_irq_save(flags);
  2062. ace_mask_irq(dev);
  2063. for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
  2064. struct sk_buff *skb;
  2065. dma_addr_t mapping;
  2066. struct tx_ring_info *info;
  2067. info = ap->skb->tx_skbuff + i;
  2068. skb = info->skb;
  2069. mapping = pci_unmap_addr(info, mapping);
  2070. if (mapping) {
  2071. if (ACE_IS_TIGON_I(ap)) {
  2072. struct tx_desc __iomem *tx
  2073. = (struct tx_desc __iomem *) &ap->tx_ring[i];
  2074. writel(0, &tx->addr.addrhi);
  2075. writel(0, &tx->addr.addrlo);
  2076. writel(0, &tx->flagsize);
  2077. } else
  2078. memset(ap->tx_ring + i, 0,
  2079. sizeof(struct tx_desc));
  2080. pci_unmap_page(ap->pdev, mapping,
  2081. pci_unmap_len(info, maplen),
  2082. PCI_DMA_TODEVICE);
  2083. pci_unmap_addr_set(info, mapping, 0);
  2084. }
  2085. if (skb) {
  2086. dev_kfree_skb(skb);
  2087. info->skb = NULL;
  2088. }
  2089. }
  2090. if (ap->jumbo) {
  2091. cmd.evt = C_RESET_JUMBO_RNG;
  2092. cmd.code = 0;
  2093. cmd.idx = 0;
  2094. ace_issue_cmd(regs, &cmd);
  2095. }
  2096. ace_unmask_irq(dev);
  2097. local_irq_restore(flags);
  2098. return 0;
  2099. }
  2100. static inline dma_addr_t
  2101. ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
  2102. struct sk_buff *tail, u32 idx)
  2103. {
  2104. dma_addr_t mapping;
  2105. struct tx_ring_info *info;
  2106. mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
  2107. offset_in_page(skb->data),
  2108. skb->len, PCI_DMA_TODEVICE);
  2109. info = ap->skb->tx_skbuff + idx;
  2110. info->skb = tail;
  2111. pci_unmap_addr_set(info, mapping, mapping);
  2112. pci_unmap_len_set(info, maplen, skb->len);
  2113. return mapping;
  2114. }
  2115. static inline void
  2116. ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
  2117. u32 flagsize, u32 vlan_tag)
  2118. {
  2119. #if !USE_TX_COAL_NOW
  2120. flagsize &= ~BD_FLG_COAL_NOW;
  2121. #endif
  2122. if (ACE_IS_TIGON_I(ap)) {
  2123. struct tx_desc __iomem *io = (struct tx_desc __iomem *) desc;
  2124. writel(addr >> 32, &io->addr.addrhi);
  2125. writel(addr & 0xffffffff, &io->addr.addrlo);
  2126. writel(flagsize, &io->flagsize);
  2127. #if ACENIC_DO_VLAN
  2128. writel(vlan_tag, &io->vlanres);
  2129. #endif
  2130. } else {
  2131. desc->addr.addrhi = addr >> 32;
  2132. desc->addr.addrlo = addr;
  2133. desc->flagsize = flagsize;
  2134. #if ACENIC_DO_VLAN
  2135. desc->vlanres = vlan_tag;
  2136. #endif
  2137. }
  2138. }
  2139. static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev)
  2140. {
  2141. struct ace_private *ap = netdev_priv(dev);
  2142. struct ace_regs __iomem *regs = ap->regs;
  2143. struct tx_desc *desc;
  2144. u32 idx, flagsize;
  2145. unsigned long maxjiff = jiffies + 3*HZ;
  2146. restart:
  2147. idx = ap->tx_prd;
  2148. if (tx_ring_full(ap, ap->tx_ret_csm, idx))
  2149. goto overflow;
  2150. if (!skb_shinfo(skb)->nr_frags) {
  2151. dma_addr_t mapping;
  2152. u32 vlan_tag = 0;
  2153. mapping = ace_map_tx_skb(ap, skb, skb, idx);
  2154. flagsize = (skb->len << 16) | (BD_FLG_END);
  2155. if (skb->ip_summed == CHECKSUM_PARTIAL)
  2156. flagsize |= BD_FLG_TCP_UDP_SUM;
  2157. #if ACENIC_DO_VLAN
  2158. if (vlan_tx_tag_present(skb)) {
  2159. flagsize |= BD_FLG_VLAN_TAG;
  2160. vlan_tag = vlan_tx_tag_get(skb);
  2161. }
  2162. #endif
  2163. desc = ap->tx_ring + idx;
  2164. idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
  2165. /* Look at ace_tx_int for explanations. */
  2166. if (tx_ring_full(ap, ap->tx_ret_csm, idx))
  2167. flagsize |= BD_FLG_COAL_NOW;
  2168. ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
  2169. } else {
  2170. dma_addr_t mapping;
  2171. u32 vlan_tag = 0;
  2172. int i, len = 0;
  2173. mapping = ace_map_tx_skb(ap, skb, NULL, idx);
  2174. flagsize = (skb_headlen(skb) << 16);
  2175. if (skb->ip_summed == CHECKSUM_PARTIAL)
  2176. flagsize |= BD_FLG_TCP_UDP_SUM;
  2177. #if ACENIC_DO_VLAN
  2178. if (vlan_tx_tag_present(skb)) {
  2179. flagsize |= BD_FLG_VLAN_TAG;
  2180. vlan_tag = vlan_tx_tag_get(skb);
  2181. }
  2182. #endif
  2183. ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
  2184. idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
  2185. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2186. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2187. struct tx_ring_info *info;
  2188. len += frag->size;
  2189. info = ap->skb->tx_skbuff + idx;
  2190. desc = ap->tx_ring + idx;
  2191. mapping = pci_map_page(ap->pdev, frag->page,
  2192. frag->page_offset, frag->size,
  2193. PCI_DMA_TODEVICE);
  2194. flagsize = (frag->size << 16);
  2195. if (skb->ip_summed == CHECKSUM_PARTIAL)
  2196. flagsize |= BD_FLG_TCP_UDP_SUM;
  2197. idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
  2198. if (i == skb_shinfo(skb)->nr_frags - 1) {
  2199. flagsize |= BD_FLG_END;
  2200. if (tx_ring_full(ap, ap->tx_ret_csm, idx))
  2201. flagsize |= BD_FLG_COAL_NOW;
  2202. /*
  2203. * Only the last fragment frees
  2204. * the skb!
  2205. */
  2206. info->skb = skb;
  2207. } else {
  2208. info->skb = NULL;
  2209. }
  2210. pci_unmap_addr_set(info, mapping, mapping);
  2211. pci_unmap_len_set(info, maplen, frag->size);
  2212. ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
  2213. }
  2214. }
  2215. wmb();
  2216. ap->tx_prd = idx;
  2217. ace_set_txprd(regs, ap, idx);
  2218. if (flagsize & BD_FLG_COAL_NOW) {
  2219. netif_stop_queue(dev);
  2220. /*
  2221. * A TX-descriptor producer (an IRQ) might have gotten
  2222. * inbetween, making the ring free again. Since xmit is
  2223. * serialized, this is the only situation we have to
  2224. * re-test.
  2225. */
  2226. if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
  2227. netif_wake_queue(dev);
  2228. }
  2229. dev->trans_start = jiffies;
  2230. return NETDEV_TX_OK;
  2231. overflow:
  2232. /*
  2233. * This race condition is unavoidable with lock-free drivers.
  2234. * We wake up the queue _before_ tx_prd is advanced, so that we can
  2235. * enter hard_start_xmit too early, while tx ring still looks closed.
  2236. * This happens ~1-4 times per 100000 packets, so that we can allow
  2237. * to loop syncing to other CPU. Probably, we need an additional
  2238. * wmb() in ace_tx_intr as well.
  2239. *
  2240. * Note that this race is relieved by reserving one more entry
  2241. * in tx ring than it is necessary (see original non-SG driver).
  2242. * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
  2243. * is already overkill.
  2244. *
  2245. * Alternative is to return with 1 not throttling queue. In this
  2246. * case loop becomes longer, no more useful effects.
  2247. */
  2248. if (time_before(jiffies, maxjiff)) {
  2249. barrier();
  2250. cpu_relax();
  2251. goto restart;
  2252. }
  2253. /* The ring is stuck full. */
  2254. printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
  2255. return NETDEV_TX_BUSY;
  2256. }
  2257. static int ace_change_mtu(struct net_device *dev, int new_mtu)
  2258. {
  2259. struct ace_private *ap = netdev_priv(dev);
  2260. struct ace_regs __iomem *regs = ap->regs;
  2261. if (new_mtu > ACE_JUMBO_MTU)
  2262. return -EINVAL;
  2263. writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
  2264. dev->mtu = new_mtu;
  2265. if (new_mtu > ACE_STD_MTU) {
  2266. if (!(ap->jumbo)) {
  2267. printk(KERN_INFO "%s: Enabling Jumbo frame "
  2268. "support\n", dev->name);
  2269. ap->jumbo = 1;
  2270. if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
  2271. ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
  2272. ace_set_rxtx_parms(dev, 1);
  2273. }
  2274. } else {
  2275. while (test_and_set_bit(0, &ap->jumbo_refill_busy));
  2276. ace_sync_irq(dev->irq);
  2277. ace_set_rxtx_parms(dev, 0);
  2278. if (ap->jumbo) {
  2279. struct cmd cmd;
  2280. cmd.evt = C_RESET_JUMBO_RNG;
  2281. cmd.code = 0;
  2282. cmd.idx = 0;
  2283. ace_issue_cmd(regs, &cmd);
  2284. }
  2285. }
  2286. return 0;
  2287. }
  2288. static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2289. {
  2290. struct ace_private *ap = netdev_priv(dev);
  2291. struct ace_regs __iomem *regs = ap->regs;
  2292. u32 link;
  2293. memset(ecmd, 0, sizeof(struct ethtool_cmd));
  2294. ecmd->supported =
  2295. (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
  2296. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  2297. SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
  2298. SUPPORTED_Autoneg | SUPPORTED_FIBRE);
  2299. ecmd->port = PORT_FIBRE;
  2300. ecmd->transceiver = XCVR_INTERNAL;
  2301. link = readl(&regs->GigLnkState);
  2302. if (link & LNK_1000MB)
  2303. ecmd->speed = SPEED_1000;
  2304. else {
  2305. link = readl(&regs->FastLnkState);
  2306. if (link & LNK_100MB)
  2307. ecmd->speed = SPEED_100;
  2308. else if (link & LNK_10MB)
  2309. ecmd->speed = SPEED_10;
  2310. else
  2311. ecmd->speed = 0;
  2312. }
  2313. if (link & LNK_FULL_DUPLEX)
  2314. ecmd->duplex = DUPLEX_FULL;
  2315. else
  2316. ecmd->duplex = DUPLEX_HALF;
  2317. if (link & LNK_NEGOTIATE)
  2318. ecmd->autoneg = AUTONEG_ENABLE;
  2319. else
  2320. ecmd->autoneg = AUTONEG_DISABLE;
  2321. #if 0
  2322. /*
  2323. * Current struct ethtool_cmd is insufficient
  2324. */
  2325. ecmd->trace = readl(&regs->TuneTrace);
  2326. ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
  2327. ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
  2328. #endif
  2329. ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
  2330. ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
  2331. return 0;
  2332. }
  2333. static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2334. {
  2335. struct ace_private *ap = netdev_priv(dev);
  2336. struct ace_regs __iomem *regs = ap->regs;
  2337. u32 link, speed;
  2338. link = readl(&regs->GigLnkState);
  2339. if (link & LNK_1000MB)
  2340. speed = SPEED_1000;
  2341. else {
  2342. link = readl(&regs->FastLnkState);
  2343. if (link & LNK_100MB)
  2344. speed = SPEED_100;
  2345. else if (link & LNK_10MB)
  2346. speed = SPEED_10;
  2347. else
  2348. speed = SPEED_100;
  2349. }
  2350. link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
  2351. LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
  2352. if (!ACE_IS_TIGON_I(ap))
  2353. link |= LNK_TX_FLOW_CTL_Y;
  2354. if (ecmd->autoneg == AUTONEG_ENABLE)
  2355. link |= LNK_NEGOTIATE;
  2356. if (ecmd->speed != speed) {
  2357. link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
  2358. switch (speed) {
  2359. case SPEED_1000:
  2360. link |= LNK_1000MB;
  2361. break;
  2362. case SPEED_100:
  2363. link |= LNK_100MB;
  2364. break;
  2365. case SPEED_10:
  2366. link |= LNK_10MB;
  2367. break;
  2368. }
  2369. }
  2370. if (ecmd->duplex == DUPLEX_FULL)
  2371. link |= LNK_FULL_DUPLEX;
  2372. if (link != ap->link) {
  2373. struct cmd cmd;
  2374. printk(KERN_INFO "%s: Renegotiating link state\n",
  2375. dev->name);
  2376. ap->link = link;
  2377. writel(link, &regs->TuneLink);
  2378. if (!ACE_IS_TIGON_I(ap))
  2379. writel(link, &regs->TuneFastLink);
  2380. wmb();
  2381. cmd.evt = C_LNK_NEGOTIATION;
  2382. cmd.code = 0;
  2383. cmd.idx = 0;
  2384. ace_issue_cmd(regs, &cmd);
  2385. }
  2386. return 0;
  2387. }
  2388. static void ace_get_drvinfo(struct net_device *dev,
  2389. struct ethtool_drvinfo *info)
  2390. {
  2391. struct ace_private *ap = netdev_priv(dev);
  2392. strlcpy(info->driver, "acenic", sizeof(info->driver));
  2393. snprintf(info->version, sizeof(info->version), "%i.%i.%i",
  2394. tigonFwReleaseMajor, tigonFwReleaseMinor,
  2395. tigonFwReleaseFix);
  2396. if (ap->pdev)
  2397. strlcpy(info->bus_info, pci_name(ap->pdev),
  2398. sizeof(info->bus_info));
  2399. }
  2400. /*
  2401. * Set the hardware MAC address.
  2402. */
  2403. static int ace_set_mac_addr(struct net_device *dev, void *p)
  2404. {
  2405. struct ace_private *ap = netdev_priv(dev);
  2406. struct ace_regs __iomem *regs = ap->regs;
  2407. struct sockaddr *addr=p;
  2408. u8 *da;
  2409. struct cmd cmd;
  2410. if(netif_running(dev))
  2411. return -EBUSY;
  2412. memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
  2413. da = (u8 *)dev->dev_addr;
  2414. writel(da[0] << 8 | da[1], &regs->MacAddrHi);
  2415. writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
  2416. &regs->MacAddrLo);
  2417. cmd.evt = C_SET_MAC_ADDR;
  2418. cmd.code = 0;
  2419. cmd.idx = 0;
  2420. ace_issue_cmd(regs, &cmd);
  2421. return 0;
  2422. }
  2423. static void ace_set_multicast_list(struct net_device *dev)
  2424. {
  2425. struct ace_private *ap = netdev_priv(dev);
  2426. struct ace_regs __iomem *regs = ap->regs;
  2427. struct cmd cmd;
  2428. if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
  2429. cmd.evt = C_SET_MULTICAST_MODE;
  2430. cmd.code = C_C_MCAST_ENABLE;
  2431. cmd.idx = 0;
  2432. ace_issue_cmd(regs, &cmd);
  2433. ap->mcast_all = 1;
  2434. } else if (ap->mcast_all) {
  2435. cmd.evt = C_SET_MULTICAST_MODE;
  2436. cmd.code = C_C_MCAST_DISABLE;
  2437. cmd.idx = 0;
  2438. ace_issue_cmd(regs, &cmd);
  2439. ap->mcast_all = 0;
  2440. }
  2441. if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
  2442. cmd.evt = C_SET_PROMISC_MODE;
  2443. cmd.code = C_C_PROMISC_ENABLE;
  2444. cmd.idx = 0;
  2445. ace_issue_cmd(regs, &cmd);
  2446. ap->promisc = 1;
  2447. }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
  2448. cmd.evt = C_SET_PROMISC_MODE;
  2449. cmd.code = C_C_PROMISC_DISABLE;
  2450. cmd.idx = 0;
  2451. ace_issue_cmd(regs, &cmd);
  2452. ap->promisc = 0;
  2453. }
  2454. /*
  2455. * For the time being multicast relies on the upper layers
  2456. * filtering it properly. The Firmware does not allow one to
  2457. * set the entire multicast list at a time and keeping track of
  2458. * it here is going to be messy.
  2459. */
  2460. if ((dev->mc_count) && !(ap->mcast_all)) {
  2461. cmd.evt = C_SET_MULTICAST_MODE;
  2462. cmd.code = C_C_MCAST_ENABLE;
  2463. cmd.idx = 0;
  2464. ace_issue_cmd(regs, &cmd);
  2465. }else if (!ap->mcast_all) {
  2466. cmd.evt = C_SET_MULTICAST_MODE;
  2467. cmd.code = C_C_MCAST_DISABLE;
  2468. cmd.idx = 0;
  2469. ace_issue_cmd(regs, &cmd);
  2470. }
  2471. }
  2472. static struct net_device_stats *ace_get_stats(struct net_device *dev)
  2473. {
  2474. struct ace_private *ap = netdev_priv(dev);
  2475. struct ace_mac_stats __iomem *mac_stats =
  2476. (struct ace_mac_stats __iomem *)ap->regs->Stats;
  2477. ap->stats.rx_missed_errors = readl(&mac_stats->drop_space);
  2478. ap->stats.multicast = readl(&mac_stats->kept_mc);
  2479. ap->stats.collisions = readl(&mac_stats->coll);
  2480. return &ap->stats;
  2481. }
  2482. static void __devinit ace_copy(struct ace_regs __iomem *regs, void *src,
  2483. u32 dest, int size)
  2484. {
  2485. void __iomem *tdest;
  2486. u32 *wsrc;
  2487. short tsize, i;
  2488. if (size <= 0)
  2489. return;
  2490. while (size > 0) {
  2491. tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
  2492. min_t(u32, size, ACE_WINDOW_SIZE));
  2493. tdest = (void __iomem *) &regs->Window +
  2494. (dest & (ACE_WINDOW_SIZE - 1));
  2495. writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
  2496. /*
  2497. * This requires byte swapping on big endian, however
  2498. * writel does that for us
  2499. */
  2500. wsrc = src;
  2501. for (i = 0; i < (tsize / 4); i++) {
  2502. writel(wsrc[i], tdest + i*4);
  2503. }
  2504. dest += tsize;
  2505. src += tsize;
  2506. size -= tsize;
  2507. }
  2508. return;
  2509. }
  2510. static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
  2511. {
  2512. void __iomem *tdest;
  2513. short tsize = 0, i;
  2514. if (size <= 0)
  2515. return;
  2516. while (size > 0) {
  2517. tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
  2518. min_t(u32, size, ACE_WINDOW_SIZE));
  2519. tdest = (void __iomem *) &regs->Window +
  2520. (dest & (ACE_WINDOW_SIZE - 1));
  2521. writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
  2522. for (i = 0; i < (tsize / 4); i++) {
  2523. writel(0, tdest + i*4);
  2524. }
  2525. dest += tsize;
  2526. size -= tsize;
  2527. }
  2528. return;
  2529. }
  2530. /*
  2531. * Download the firmware into the SRAM on the NIC
  2532. *
  2533. * This operation requires the NIC to be halted and is performed with
  2534. * interrupts disabled and with the spinlock hold.
  2535. */
  2536. int __devinit ace_load_firmware(struct net_device *dev)
  2537. {
  2538. struct ace_private *ap = netdev_priv(dev);
  2539. struct ace_regs __iomem *regs = ap->regs;
  2540. if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
  2541. printk(KERN_ERR "%s: trying to download firmware while the "
  2542. "CPU is running!\n", ap->name);
  2543. return -EFAULT;
  2544. }
  2545. /*
  2546. * Do not try to clear more than 512KB or we end up seeing
  2547. * funny things on NICs with only 512KB SRAM
  2548. */
  2549. ace_clear(regs, 0x2000, 0x80000-0x2000);
  2550. if (ACE_IS_TIGON_I(ap)) {
  2551. ace_copy(regs, tigonFwText, tigonFwTextAddr, tigonFwTextLen);
  2552. ace_copy(regs, tigonFwData, tigonFwDataAddr, tigonFwDataLen);
  2553. ace_copy(regs, tigonFwRodata, tigonFwRodataAddr,
  2554. tigonFwRodataLen);
  2555. ace_clear(regs, tigonFwBssAddr, tigonFwBssLen);
  2556. ace_clear(regs, tigonFwSbssAddr, tigonFwSbssLen);
  2557. }else if (ap->version == 2) {
  2558. ace_clear(regs, tigon2FwBssAddr, tigon2FwBssLen);
  2559. ace_clear(regs, tigon2FwSbssAddr, tigon2FwSbssLen);
  2560. ace_copy(regs, tigon2FwText, tigon2FwTextAddr,tigon2FwTextLen);
  2561. ace_copy(regs, tigon2FwRodata, tigon2FwRodataAddr,
  2562. tigon2FwRodataLen);
  2563. ace_copy(regs, tigon2FwData, tigon2FwDataAddr,tigon2FwDataLen);
  2564. }
  2565. return 0;
  2566. }
  2567. /*
  2568. * The eeprom on the AceNIC is an Atmel i2c EEPROM.
  2569. *
  2570. * Accessing the EEPROM is `interesting' to say the least - don't read
  2571. * this code right after dinner.
  2572. *
  2573. * This is all about black magic and bit-banging the device .... I
  2574. * wonder in what hospital they have put the guy who designed the i2c
  2575. * specs.
  2576. *
  2577. * Oh yes, this is only the beginning!
  2578. *
  2579. * Thanks to Stevarino Webinski for helping tracking down the bugs in the
  2580. * code i2c readout code by beta testing all my hacks.
  2581. */
  2582. static void __devinit eeprom_start(struct ace_regs __iomem *regs)
  2583. {
  2584. u32 local;
  2585. readl(&regs->LocalCtrl);
  2586. udelay(ACE_SHORT_DELAY);
  2587. local = readl(&regs->LocalCtrl);
  2588. local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
  2589. writel(local, &regs->LocalCtrl);
  2590. readl(&regs->LocalCtrl);
  2591. mb();
  2592. udelay(ACE_SHORT_DELAY);
  2593. local |= EEPROM_CLK_OUT;
  2594. writel(local, &regs->LocalCtrl);
  2595. readl(&regs->LocalCtrl);
  2596. mb();
  2597. udelay(ACE_SHORT_DELAY);
  2598. local &= ~EEPROM_DATA_OUT;
  2599. writel(local, &regs->LocalCtrl);
  2600. readl(&regs->LocalCtrl);
  2601. mb();
  2602. udelay(ACE_SHORT_DELAY);
  2603. local &= ~EEPROM_CLK_OUT;
  2604. writel(local, &regs->LocalCtrl);
  2605. readl(&regs->LocalCtrl);
  2606. mb();
  2607. }
  2608. static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
  2609. {
  2610. short i;
  2611. u32 local;
  2612. udelay(ACE_SHORT_DELAY);
  2613. local = readl(&regs->LocalCtrl);
  2614. local &= ~EEPROM_DATA_OUT;
  2615. local |= EEPROM_WRITE_ENABLE;
  2616. writel(local, &regs->LocalCtrl);
  2617. readl(&regs->LocalCtrl);
  2618. mb();
  2619. for (i = 0; i < 8; i++, magic <<= 1) {
  2620. udelay(ACE_SHORT_DELAY);
  2621. if (magic & 0x80)
  2622. local |= EEPROM_DATA_OUT;
  2623. else
  2624. local &= ~EEPROM_DATA_OUT;
  2625. writel(local, &regs->LocalCtrl);
  2626. readl(&regs->LocalCtrl);
  2627. mb();
  2628. udelay(ACE_SHORT_DELAY);
  2629. local |= EEPROM_CLK_OUT;
  2630. writel(local, &regs->LocalCtrl);
  2631. readl(&regs->LocalCtrl);
  2632. mb();
  2633. udelay(ACE_SHORT_DELAY);
  2634. local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
  2635. writel(local, &regs->LocalCtrl);
  2636. readl(&regs->LocalCtrl);
  2637. mb();
  2638. }
  2639. }
  2640. static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
  2641. {
  2642. int state;
  2643. u32 local;
  2644. local = readl(&regs->LocalCtrl);
  2645. local &= ~EEPROM_WRITE_ENABLE;
  2646. writel(local, &regs->LocalCtrl);
  2647. readl(&regs->LocalCtrl);
  2648. mb();
  2649. udelay(ACE_LONG_DELAY);
  2650. local |= EEPROM_CLK_OUT;
  2651. writel(local, &regs->LocalCtrl);
  2652. readl(&regs->LocalCtrl);
  2653. mb();
  2654. udelay(ACE_SHORT_DELAY);
  2655. /* sample data in middle of high clk */
  2656. state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
  2657. udelay(ACE_SHORT_DELAY);
  2658. mb();
  2659. writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
  2660. readl(&regs->LocalCtrl);
  2661. mb();
  2662. return state;
  2663. }
  2664. static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
  2665. {
  2666. u32 local;
  2667. udelay(ACE_SHORT_DELAY);
  2668. local = readl(&regs->LocalCtrl);
  2669. local |= EEPROM_WRITE_ENABLE;
  2670. writel(local, &regs->LocalCtrl);
  2671. readl(&regs->LocalCtrl);
  2672. mb();
  2673. udelay(ACE_SHORT_DELAY);
  2674. local &= ~EEPROM_DATA_OUT;
  2675. writel(local, &regs->LocalCtrl);
  2676. readl(&regs->LocalCtrl);
  2677. mb();
  2678. udelay(ACE_SHORT_DELAY);
  2679. local |= EEPROM_CLK_OUT;
  2680. writel(local, &regs->LocalCtrl);
  2681. readl(&regs->LocalCtrl);
  2682. mb();
  2683. udelay(ACE_SHORT_DELAY);
  2684. local |= EEPROM_DATA_OUT;
  2685. writel(local, &regs->LocalCtrl);
  2686. readl(&regs->LocalCtrl);
  2687. mb();
  2688. udelay(ACE_LONG_DELAY);
  2689. local &= ~EEPROM_CLK_OUT;
  2690. writel(local, &regs->LocalCtrl);
  2691. mb();
  2692. }
  2693. /*
  2694. * Read a whole byte from the EEPROM.
  2695. */
  2696. static int __devinit read_eeprom_byte(struct net_device *dev,
  2697. unsigned long offset)
  2698. {
  2699. struct ace_private *ap = netdev_priv(dev);
  2700. struct ace_regs __iomem *regs = ap->regs;
  2701. unsigned long flags;
  2702. u32 local;
  2703. int result = 0;
  2704. short i;
  2705. if (!dev) {
  2706. printk(KERN_ERR "No device!\n");
  2707. result = -ENODEV;
  2708. goto out;
  2709. }
  2710. /*
  2711. * Don't take interrupts on this CPU will bit banging
  2712. * the %#%#@$ I2C device
  2713. */
  2714. local_irq_save(flags);
  2715. eeprom_start(regs);
  2716. eeprom_prep(regs, EEPROM_WRITE_SELECT);
  2717. if (eeprom_check_ack(regs)) {
  2718. local_irq_restore(flags);
  2719. printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
  2720. result = -EIO;
  2721. goto eeprom_read_error;
  2722. }
  2723. eeprom_prep(regs, (offset >> 8) & 0xff);
  2724. if (eeprom_check_ack(regs)) {
  2725. local_irq_restore(flags);
  2726. printk(KERN_ERR "%s: Unable to set address byte 0\n",
  2727. ap->name);
  2728. result = -EIO;
  2729. goto eeprom_read_error;
  2730. }
  2731. eeprom_prep(regs, offset & 0xff);
  2732. if (eeprom_check_ack(regs)) {
  2733. local_irq_restore(flags);
  2734. printk(KERN_ERR "%s: Unable to set address byte 1\n",
  2735. ap->name);
  2736. result = -EIO;
  2737. goto eeprom_read_error;
  2738. }
  2739. eeprom_start(regs);
  2740. eeprom_prep(regs, EEPROM_READ_SELECT);
  2741. if (eeprom_check_ack(regs)) {
  2742. local_irq_restore(flags);
  2743. printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
  2744. ap->name);
  2745. result = -EIO;
  2746. goto eeprom_read_error;
  2747. }
  2748. for (i = 0; i < 8; i++) {
  2749. local = readl(&regs->LocalCtrl);
  2750. local &= ~EEPROM_WRITE_ENABLE;
  2751. writel(local, &regs->LocalCtrl);
  2752. readl(&regs->LocalCtrl);
  2753. udelay(ACE_LONG_DELAY);
  2754. mb();
  2755. local |= EEPROM_CLK_OUT;
  2756. writel(local, &regs->LocalCtrl);
  2757. readl(&regs->LocalCtrl);
  2758. mb();
  2759. udelay(ACE_SHORT_DELAY);
  2760. /* sample data mid high clk */
  2761. result = (result << 1) |
  2762. ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
  2763. udelay(ACE_SHORT_DELAY);
  2764. mb();
  2765. local = readl(&regs->LocalCtrl);
  2766. local &= ~EEPROM_CLK_OUT;
  2767. writel(local, &regs->LocalCtrl);
  2768. readl(&regs->LocalCtrl);
  2769. udelay(ACE_SHORT_DELAY);
  2770. mb();
  2771. if (i == 7) {
  2772. local |= EEPROM_WRITE_ENABLE;
  2773. writel(local, &regs->LocalCtrl);
  2774. readl(&regs->LocalCtrl);
  2775. mb();
  2776. udelay(ACE_SHORT_DELAY);
  2777. }
  2778. }
  2779. local |= EEPROM_DATA_OUT;
  2780. writel(local, &regs->LocalCtrl);
  2781. readl(&regs->LocalCtrl);
  2782. mb();
  2783. udelay(ACE_SHORT_DELAY);
  2784. writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
  2785. readl(&regs->LocalCtrl);
  2786. udelay(ACE_LONG_DELAY);
  2787. writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
  2788. readl(&regs->LocalCtrl);
  2789. mb();
  2790. udelay(ACE_SHORT_DELAY);
  2791. eeprom_stop(regs);
  2792. local_irq_restore(flags);
  2793. out:
  2794. return result;
  2795. eeprom_read_error:
  2796. printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
  2797. ap->name, offset);
  2798. goto out;
  2799. }
  2800. /*
  2801. * Local variables:
  2802. * compile-command: "gcc -D__SMP__ -D__KERNEL__ -DMODULE -I../../include -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer -pipe -fno-strength-reduce -DMODVERSIONS -include ../../include/linux/modversions.h -c -o acenic.o acenic.c"
  2803. * End:
  2804. */