a2065.h 5.0 KB

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  1. /*
  2. * Amiga Linux/68k A2065 Ethernet Driver
  3. *
  4. * (C) Copyright 1995 by Geert Uytterhoeven <geert@linux-m68k.org>
  5. *
  6. * ---------------------------------------------------------------------------
  7. *
  8. * This program is based on
  9. *
  10. * ariadne.?: Amiga Linux/68k Ariadne Ethernet Driver
  11. * (C) Copyright 1995 by Geert Uytterhoeven,
  12. * Peter De Schrijver
  13. *
  14. * lance.c: An AMD LANCE ethernet driver for linux.
  15. * Written 1993-94 by Donald Becker.
  16. *
  17. * Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller
  18. * Advanced Micro Devices
  19. * Publication #16907, Rev. B, Amendment/0, May 1994
  20. *
  21. * ---------------------------------------------------------------------------
  22. *
  23. * This file is subject to the terms and conditions of the GNU General Public
  24. * License. See the file COPYING in the main directory of the Linux
  25. * distribution for more details.
  26. *
  27. * ---------------------------------------------------------------------------
  28. *
  29. * The A2065 is a Zorro-II board made by Commodore/Ameristar. It contains:
  30. *
  31. * - an Am7990 Local Area Network Controller for Ethernet (LANCE) with
  32. * both 10BASE-2 (thin coax) and AUI (DB-15) connectors
  33. */
  34. /*
  35. * Am7990 Local Area Network Controller for Ethernet (LANCE)
  36. */
  37. struct lance_regs {
  38. unsigned short rdp; /* Register Data Port */
  39. unsigned short rap; /* Register Address Port */
  40. };
  41. /*
  42. * Am7990 Control and Status Registers
  43. */
  44. #define LE_CSR0 0x0000 /* LANCE Controller Status */
  45. #define LE_CSR1 0x0001 /* IADR[15:0] */
  46. #define LE_CSR2 0x0002 /* IADR[23:16] */
  47. #define LE_CSR3 0x0003 /* Misc */
  48. /*
  49. * Bit definitions for CSR0 (LANCE Controller Status)
  50. */
  51. #define LE_C0_ERR 0x8000 /* Error */
  52. #define LE_C0_BABL 0x4000 /* Babble: Transmitted too many bits */
  53. #define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */
  54. #define LE_C0_MISS 0x1000 /* Missed Frame */
  55. #define LE_C0_MERR 0x0800 /* Memory Error */
  56. #define LE_C0_RINT 0x0400 /* Receive Interrupt */
  57. #define LE_C0_TINT 0x0200 /* Transmit Interrupt */
  58. #define LE_C0_IDON 0x0100 /* Initialization Done */
  59. #define LE_C0_INTR 0x0080 /* Interrupt Flag */
  60. #define LE_C0_INEA 0x0040 /* Interrupt Enable */
  61. #define LE_C0_RXON 0x0020 /* Receive On */
  62. #define LE_C0_TXON 0x0010 /* Transmit On */
  63. #define LE_C0_TDMD 0x0008 /* Transmit Demand */
  64. #define LE_C0_STOP 0x0004 /* Stop */
  65. #define LE_C0_STRT 0x0002 /* Start */
  66. #define LE_C0_INIT 0x0001 /* Initialize */
  67. /*
  68. * Bit definitions for CSR3
  69. */
  70. #define LE_C3_BSWP 0x0004 /* Byte Swap
  71. (on for big endian byte order) */
  72. #define LE_C3_ACON 0x0002 /* ALE Control
  73. (on for active low ALE) */
  74. #define LE_C3_BCON 0x0001 /* Byte Control */
  75. /*
  76. * Mode Flags
  77. */
  78. #define LE_MO_PROM 0x8000 /* Promiscuous Mode */
  79. #define LE_MO_INTL 0x0040 /* Internal Loopback */
  80. #define LE_MO_DRTY 0x0020 /* Disable Retry */
  81. #define LE_MO_FCOLL 0x0010 /* Force Collision */
  82. #define LE_MO_DXMTFCS 0x0008 /* Disable Transmit CRC */
  83. #define LE_MO_LOOP 0x0004 /* Loopback Enable */
  84. #define LE_MO_DTX 0x0002 /* Disable Transmitter */
  85. #define LE_MO_DRX 0x0001 /* Disable Receiver */
  86. struct lance_rx_desc {
  87. unsigned short rmd0; /* low address of packet */
  88. unsigned char rmd1_bits; /* descriptor bits */
  89. unsigned char rmd1_hadr; /* high address of packet */
  90. short length; /* This length is 2s complement (negative)!
  91. * Buffer length
  92. */
  93. unsigned short mblength; /* Aactual number of bytes received */
  94. };
  95. struct lance_tx_desc {
  96. unsigned short tmd0; /* low address of packet */
  97. unsigned char tmd1_bits; /* descriptor bits */
  98. unsigned char tmd1_hadr; /* high address of packet */
  99. short length; /* Length is 2s complement (negative)! */
  100. unsigned short misc;
  101. };
  102. /*
  103. * Receive Flags
  104. */
  105. #define LE_R1_OWN 0x80 /* LANCE owns the descriptor */
  106. #define LE_R1_ERR 0x40 /* Error */
  107. #define LE_R1_FRA 0x20 /* Framing Error */
  108. #define LE_R1_OFL 0x10 /* Overflow Error */
  109. #define LE_R1_CRC 0x08 /* CRC Error */
  110. #define LE_R1_BUF 0x04 /* Buffer Error */
  111. #define LE_R1_SOP 0x02 /* Start of Packet */
  112. #define LE_R1_EOP 0x01 /* End of Packet */
  113. #define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
  114. /*
  115. * Transmit Flags
  116. */
  117. #define LE_T1_OWN 0x80 /* LANCE owns the descriptor */
  118. #define LE_T1_ERR 0x40 /* Error */
  119. #define LE_T1_RES 0x20 /* Reserved,
  120. LANCE writes this with a zero */
  121. #define LE_T1_EMORE 0x10 /* More than one retry needed */
  122. #define LE_T1_EONE 0x08 /* One retry needed */
  123. #define LE_T1_EDEF 0x04 /* Deferred */
  124. #define LE_T1_SOP 0x02 /* Start of Packet */
  125. #define LE_T1_EOP 0x01 /* End of Packet */
  126. #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
  127. /*
  128. * Error Flags
  129. */
  130. #define LE_T3_BUF 0x8000 /* Buffer Error */
  131. #define LE_T3_UFL 0x4000 /* Underflow Error */
  132. #define LE_T3_LCOL 0x1000 /* Late Collision */
  133. #define LE_T3_CLOS 0x0800 /* Loss of Carrier */
  134. #define LE_T3_RTY 0x0400 /* Retry Error */
  135. #define LE_T3_TDR 0x03ff /* Time Domain Reflectometry */
  136. /*
  137. * A2065 Expansion Board Structure
  138. */
  139. #define A2065_LANCE 0x4000
  140. #define A2065_RAM 0x8000
  141. #define A2065_RAM_SIZE 0x8000