8390.h 8.1 KB

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  1. /* Generic NS8390 register definitions. */
  2. /* This file is part of Donald Becker's 8390 drivers, and is distributed
  3. under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
  4. Some of these names and comments originated from the Crynwr
  5. packet drivers, which are distributed under the GPL. */
  6. #ifndef _8390_h
  7. #define _8390_h
  8. #include <linux/if_ether.h>
  9. #include <linux/ioport.h>
  10. #include <linux/skbuff.h>
  11. #define TX_PAGES 12 /* Two Tx slots */
  12. #define ETHER_ADDR_LEN 6
  13. /* The 8390 specific per-packet-header format. */
  14. struct e8390_pkt_hdr {
  15. unsigned char status; /* status */
  16. unsigned char next; /* pointer to next packet. */
  17. unsigned short count; /* header + packet length in bytes */
  18. };
  19. #ifdef notdef
  20. extern int ei_debug;
  21. #else
  22. #define ei_debug 1
  23. #endif
  24. #ifdef CONFIG_NET_POLL_CONTROLLER
  25. extern void ei_poll(struct net_device *dev);
  26. #endif
  27. extern void NS8390_init(struct net_device *dev, int startp);
  28. extern int ei_open(struct net_device *dev);
  29. extern int ei_close(struct net_device *dev);
  30. extern irqreturn_t ei_interrupt(int irq, void *dev_id);
  31. extern struct net_device *__alloc_ei_netdev(int size);
  32. static inline struct net_device *alloc_ei_netdev(void)
  33. {
  34. return __alloc_ei_netdev(0);
  35. }
  36. /* You have one of these per-board */
  37. struct ei_device {
  38. const char *name;
  39. void (*reset_8390)(struct net_device *);
  40. void (*get_8390_hdr)(struct net_device *, struct e8390_pkt_hdr *, int);
  41. void (*block_output)(struct net_device *, int, const unsigned char *, int);
  42. void (*block_input)(struct net_device *, int, struct sk_buff *, int);
  43. unsigned long rmem_start;
  44. unsigned long rmem_end;
  45. void __iomem *mem;
  46. unsigned char mcfilter[8];
  47. unsigned open:1;
  48. unsigned word16:1; /* We have the 16-bit (vs 8-bit) version of the card. */
  49. unsigned bigendian:1; /* 16-bit big endian mode. Do NOT */
  50. /* set this on random 8390 clones! */
  51. unsigned txing:1; /* Transmit Active */
  52. unsigned irqlock:1; /* 8390's intrs disabled when '1'. */
  53. unsigned dmaing:1; /* Remote DMA Active */
  54. unsigned char tx_start_page, rx_start_page, stop_page;
  55. unsigned char current_page; /* Read pointer in buffer */
  56. unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */
  57. unsigned char txqueue; /* Tx Packet buffer queue length. */
  58. short tx1, tx2; /* Packet lengths for ping-pong tx. */
  59. short lasttx; /* Alpha version consistency check. */
  60. unsigned char reg0; /* Register '0' in a WD8013 */
  61. unsigned char reg5; /* Register '5' in a WD8013 */
  62. unsigned char saved_irq; /* Original dev->irq value. */
  63. struct net_device_stats stat; /* The new statistics table. */
  64. u32 *reg_offset; /* Register mapping table */
  65. spinlock_t page_lock; /* Page register locks */
  66. unsigned long priv; /* Private field to store bus IDs etc. */
  67. };
  68. /* The maximum number of 8390 interrupt service routines called per IRQ. */
  69. #define MAX_SERVICE 12
  70. /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
  71. #define TX_TIMEOUT (20*HZ/100)
  72. #define ei_status (*(struct ei_device *)netdev_priv(dev))
  73. /* Some generic ethernet register configurations. */
  74. #define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */
  75. #define E8390_RX_IRQ_MASK 0x5
  76. #define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */
  77. #define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */
  78. #define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */
  79. #define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */
  80. /* Register accessed at EN_CMD, the 8390 base addr. */
  81. #define E8390_STOP 0x01 /* Stop and reset the chip */
  82. #define E8390_START 0x02 /* Start the chip, clear reset */
  83. #define E8390_TRANS 0x04 /* Transmit a frame */
  84. #define E8390_RREAD 0x08 /* Remote read */
  85. #define E8390_RWRITE 0x10 /* Remote write */
  86. #define E8390_NODMA 0x20 /* Remote DMA */
  87. #define E8390_PAGE0 0x00 /* Select page chip registers */
  88. #define E8390_PAGE1 0x40 /* using the two high-order bits */
  89. #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
  90. /*
  91. * Only generate indirect loads given a machine that needs them.
  92. * - removed AMIGA_PCMCIA from this list, handled as ISA io now
  93. */
  94. #ifndef ei_inb
  95. #define ei_inb(_p) inb(_p)
  96. #define ei_outb(_v,_p) outb(_v,_p)
  97. #define ei_inb_p(_p) inb_p(_p)
  98. #define ei_outb_p(_v,_p) outb_p(_v,_p)
  99. #endif
  100. #ifndef EI_SHIFT
  101. #define EI_SHIFT(x) (x)
  102. #endif
  103. #define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */
  104. /* Page 0 register offsets. */
  105. #define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */
  106. #define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */
  107. #define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */
  108. #define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */
  109. #define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */
  110. #define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */
  111. #define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
  112. #define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */
  113. #define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */
  114. #define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */
  115. #define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */
  116. #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */
  117. #define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */
  118. #define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */
  119. #define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */
  120. #define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */
  121. #define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */
  122. #define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */
  123. #define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */
  124. #define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */
  125. #define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */
  126. #define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */
  127. #define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */
  128. #define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */
  129. #define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */
  130. #define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */
  131. /* Bits in EN0_ISR - Interrupt status register */
  132. #define ENISR_RX 0x01 /* Receiver, no error */
  133. #define ENISR_TX 0x02 /* Transmitter, no error */
  134. #define ENISR_RX_ERR 0x04 /* Receiver, with error */
  135. #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
  136. #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
  137. #define ENISR_COUNTERS 0x20 /* Counters need emptying */
  138. #define ENISR_RDC 0x40 /* remote dma complete */
  139. #define ENISR_RESET 0x80 /* Reset completed */
  140. #define ENISR_ALL 0x3f /* Interrupts we will enable */
  141. /* Bits in EN0_DCFG - Data config register */
  142. #define ENDCFG_WTS 0x01 /* word transfer mode selection */
  143. #define ENDCFG_BOS 0x02 /* byte order selection */
  144. /* Page 1 register offsets. */
  145. #define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */
  146. #define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */
  147. #define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */
  148. #define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */
  149. #define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */
  150. /* Bits in received packet status byte and EN0_RSR*/
  151. #define ENRSR_RXOK 0x01 /* Received a good packet */
  152. #define ENRSR_CRC 0x02 /* CRC error */
  153. #define ENRSR_FAE 0x04 /* frame alignment error */
  154. #define ENRSR_FO 0x08 /* FIFO overrun */
  155. #define ENRSR_MPA 0x10 /* missed pkt */
  156. #define ENRSR_PHY 0x20 /* physical/multicast address */
  157. #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
  158. #define ENRSR_DEF 0x80 /* deferring */
  159. /* Transmitted packet status, EN0_TSR. */
  160. #define ENTSR_PTX 0x01 /* Packet transmitted without error */
  161. #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
  162. #define ENTSR_COL 0x04 /* The transmit collided at least once. */
  163. #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
  164. #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
  165. #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
  166. #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
  167. #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
  168. #endif /* _8390_h */