8139too.c 69 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635
  1. /*
  2. 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
  3. Maintained by Jeff Garzik <jgarzik@pobox.com>
  4. Copyright 2000-2002 Jeff Garzik
  5. Much code comes from Donald Becker's rtl8139.c driver,
  6. versions 1.13 and older. This driver was originally based
  7. on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
  8. -----<snip>-----
  9. Written 1997-2001 by Donald Becker.
  10. This software may be used and distributed according to the
  11. terms of the GNU General Public License (GPL), incorporated
  12. herein by reference. Drivers based on or derived from this
  13. code fall under the GPL and must retain the authorship,
  14. copyright and license notice. This file is not a complete
  15. program and may only be used when the entire operating
  16. system is licensed under the GPL.
  17. This driver is for boards based on the RTL8129 and RTL8139
  18. PCI ethernet chips.
  19. The author may be reached as becker@scyld.com, or C/O Scyld
  20. Computing Corporation 410 Severn Ave., Suite 210 Annapolis
  21. MD 21403
  22. Support and updates available at
  23. http://www.scyld.com/network/rtl8139.html
  24. Twister-tuning table provided by Kinston
  25. <shangh@realtek.com.tw>.
  26. -----<snip>-----
  27. This software may be used and distributed according to the terms
  28. of the GNU General Public License, incorporated herein by reference.
  29. Contributors:
  30. Donald Becker - he wrote the original driver, kudos to him!
  31. (but please don't e-mail him for support, this isn't his driver)
  32. Tigran Aivazian - bug fixes, skbuff free cleanup
  33. Martin Mares - suggestions for PCI cleanup
  34. David S. Miller - PCI DMA and softnet updates
  35. Ernst Gill - fixes ported from BSD driver
  36. Daniel Kobras - identified specific locations of
  37. posted MMIO write bugginess
  38. Gerard Sharp - bug fix, testing and feedback
  39. David Ford - Rx ring wrap fix
  40. Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
  41. to find and fix a crucial bug on older chipsets.
  42. Donald Becker/Chris Butterworth/Marcus Westergren -
  43. Noticed various Rx packet size-related buglets.
  44. Santiago Garcia Mantinan - testing and feedback
  45. Jens David - 2.2.x kernel backports
  46. Martin Dennett - incredibly helpful insight on undocumented
  47. features of the 8139 chips
  48. Jean-Jacques Michel - bug fix
  49. Tobias Ringström - Rx interrupt status checking suggestion
  50. Andrew Morton - Clear blocked signals, avoid
  51. buffer overrun setting current->comm.
  52. Kalle Olavi Niemitalo - Wake-on-LAN ioctls
  53. Robert Kuebel - Save kernel thread from dying on any signal.
  54. Submitting bug reports:
  55. "rtl8139-diag -mmmaaavvveefN" output
  56. enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
  57. */
  58. #define DRV_NAME "8139too"
  59. #define DRV_VERSION "0.9.28"
  60. #include <linux/module.h>
  61. #include <linux/kernel.h>
  62. #include <linux/compiler.h>
  63. #include <linux/pci.h>
  64. #include <linux/init.h>
  65. #include <linux/ioport.h>
  66. #include <linux/netdevice.h>
  67. #include <linux/etherdevice.h>
  68. #include <linux/rtnetlink.h>
  69. #include <linux/delay.h>
  70. #include <linux/ethtool.h>
  71. #include <linux/mii.h>
  72. #include <linux/completion.h>
  73. #include <linux/crc32.h>
  74. #include <asm/io.h>
  75. #include <asm/uaccess.h>
  76. #include <asm/irq.h>
  77. #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
  78. #define PFX DRV_NAME ": "
  79. /* Default Message level */
  80. #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
  81. NETIF_MSG_PROBE | \
  82. NETIF_MSG_LINK)
  83. /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
  84. #ifdef CONFIG_8139TOO_PIO
  85. #define USE_IO_OPS 1
  86. #endif
  87. /* define to 1, 2 or 3 to enable copious debugging info */
  88. #define RTL8139_DEBUG 0
  89. /* define to 1 to disable lightweight runtime debugging checks */
  90. #undef RTL8139_NDEBUG
  91. #if RTL8139_DEBUG
  92. /* note: prints function name for you */
  93. # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
  94. #else
  95. # define DPRINTK(fmt, args...)
  96. #endif
  97. #ifdef RTL8139_NDEBUG
  98. # define assert(expr) do {} while (0)
  99. #else
  100. # define assert(expr) \
  101. if(unlikely(!(expr))) { \
  102. printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
  103. #expr,__FILE__,__FUNCTION__,__LINE__); \
  104. }
  105. #endif
  106. /* A few user-configurable values. */
  107. /* media options */
  108. #define MAX_UNITS 8
  109. static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
  110. static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
  111. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  112. The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  113. static int multicast_filter_limit = 32;
  114. /* bitmapped message enable number */
  115. static int debug = -1;
  116. /*
  117. * Receive ring size
  118. * Warning: 64K ring has hardware issues and may lock up.
  119. */
  120. #if defined(CONFIG_SH_DREAMCAST)
  121. #define RX_BUF_IDX 1 /* 16K ring */
  122. #else
  123. #define RX_BUF_IDX 2 /* 32K ring */
  124. #endif
  125. #define RX_BUF_LEN (8192 << RX_BUF_IDX)
  126. #define RX_BUF_PAD 16
  127. #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
  128. #if RX_BUF_LEN == 65536
  129. #define RX_BUF_TOT_LEN RX_BUF_LEN
  130. #else
  131. #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
  132. #endif
  133. /* Number of Tx descriptor registers. */
  134. #define NUM_TX_DESC 4
  135. /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
  136. #define MAX_ETH_FRAME_SIZE 1536
  137. /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
  138. #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
  139. #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
  140. /* PCI Tuning Parameters
  141. Threshold is bytes transferred to chip before transmission starts. */
  142. #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
  143. /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
  144. #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
  145. #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
  146. #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
  147. #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
  148. /* Operational parameters that usually are not changed. */
  149. /* Time in jiffies before concluding the transmitter is hung. */
  150. #define TX_TIMEOUT (6*HZ)
  151. enum {
  152. HAS_MII_XCVR = 0x010000,
  153. HAS_CHIP_XCVR = 0x020000,
  154. HAS_LNK_CHNG = 0x040000,
  155. };
  156. #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
  157. #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
  158. #define RTL_MIN_IO_SIZE 0x80
  159. #define RTL8139B_IO_SIZE 256
  160. #define RTL8129_CAPS HAS_MII_XCVR
  161. #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
  162. typedef enum {
  163. RTL8139 = 0,
  164. RTL8129,
  165. } board_t;
  166. /* indexed by board_t, above */
  167. static const struct {
  168. const char *name;
  169. u32 hw_flags;
  170. } board_info[] __devinitdata = {
  171. { "RealTek RTL8139", RTL8139_CAPS },
  172. { "RealTek RTL8129", RTL8129_CAPS },
  173. };
  174. static struct pci_device_id rtl8139_pci_tbl[] = {
  175. {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  176. {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  177. {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  178. {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  179. {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  180. {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  181. {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  182. {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  183. {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  184. {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  185. {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  186. {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  187. {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  188. {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  189. {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  190. {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  191. {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  192. {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  193. {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  194. #ifdef CONFIG_SH_SECUREEDGE5410
  195. /* Bogus 8139 silicon reports 8129 without external PROM :-( */
  196. {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
  197. #endif
  198. #ifdef CONFIG_8139TOO_8129
  199. {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
  200. #endif
  201. /* some crazy cards report invalid vendor ids like
  202. * 0x0001 here. The other ids are valid and constant,
  203. * so we simply don't match on the main vendor id.
  204. */
  205. {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
  206. {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
  207. {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
  208. {0,}
  209. };
  210. MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
  211. static struct {
  212. const char str[ETH_GSTRING_LEN];
  213. } ethtool_stats_keys[] = {
  214. { "early_rx" },
  215. { "tx_buf_mapped" },
  216. { "tx_timeouts" },
  217. { "rx_lost_in_ring" },
  218. };
  219. /* The rest of these values should never change. */
  220. /* Symbolic offsets to registers. */
  221. enum RTL8139_registers {
  222. MAC0 = 0, /* Ethernet hardware address. */
  223. MAR0 = 8, /* Multicast filter. */
  224. TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
  225. TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
  226. RxBuf = 0x30,
  227. ChipCmd = 0x37,
  228. RxBufPtr = 0x38,
  229. RxBufAddr = 0x3A,
  230. IntrMask = 0x3C,
  231. IntrStatus = 0x3E,
  232. TxConfig = 0x40,
  233. RxConfig = 0x44,
  234. Timer = 0x48, /* A general-purpose counter. */
  235. RxMissed = 0x4C, /* 24 bits valid, write clears. */
  236. Cfg9346 = 0x50,
  237. Config0 = 0x51,
  238. Config1 = 0x52,
  239. FlashReg = 0x54,
  240. MediaStatus = 0x58,
  241. Config3 = 0x59,
  242. Config4 = 0x5A, /* absent on RTL-8139A */
  243. HltClk = 0x5B,
  244. MultiIntr = 0x5C,
  245. TxSummary = 0x60,
  246. BasicModeCtrl = 0x62,
  247. BasicModeStatus = 0x64,
  248. NWayAdvert = 0x66,
  249. NWayLPAR = 0x68,
  250. NWayExpansion = 0x6A,
  251. /* Undocumented registers, but required for proper operation. */
  252. FIFOTMS = 0x70, /* FIFO Control and test. */
  253. CSCR = 0x74, /* Chip Status and Configuration Register. */
  254. PARA78 = 0x78,
  255. PARA7c = 0x7c, /* Magic transceiver parameter register. */
  256. Config5 = 0xD8, /* absent on RTL-8139A */
  257. };
  258. enum ClearBitMasks {
  259. MultiIntrClear = 0xF000,
  260. ChipCmdClear = 0xE2,
  261. Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
  262. };
  263. enum ChipCmdBits {
  264. CmdReset = 0x10,
  265. CmdRxEnb = 0x08,
  266. CmdTxEnb = 0x04,
  267. RxBufEmpty = 0x01,
  268. };
  269. /* Interrupt register bits, using my own meaningful names. */
  270. enum IntrStatusBits {
  271. PCIErr = 0x8000,
  272. PCSTimeout = 0x4000,
  273. RxFIFOOver = 0x40,
  274. RxUnderrun = 0x20,
  275. RxOverflow = 0x10,
  276. TxErr = 0x08,
  277. TxOK = 0x04,
  278. RxErr = 0x02,
  279. RxOK = 0x01,
  280. RxAckBits = RxFIFOOver | RxOverflow | RxOK,
  281. };
  282. enum TxStatusBits {
  283. TxHostOwns = 0x2000,
  284. TxUnderrun = 0x4000,
  285. TxStatOK = 0x8000,
  286. TxOutOfWindow = 0x20000000,
  287. TxAborted = 0x40000000,
  288. TxCarrierLost = 0x80000000,
  289. };
  290. enum RxStatusBits {
  291. RxMulticast = 0x8000,
  292. RxPhysical = 0x4000,
  293. RxBroadcast = 0x2000,
  294. RxBadSymbol = 0x0020,
  295. RxRunt = 0x0010,
  296. RxTooLong = 0x0008,
  297. RxCRCErr = 0x0004,
  298. RxBadAlign = 0x0002,
  299. RxStatusOK = 0x0001,
  300. };
  301. /* Bits in RxConfig. */
  302. enum rx_mode_bits {
  303. AcceptErr = 0x20,
  304. AcceptRunt = 0x10,
  305. AcceptBroadcast = 0x08,
  306. AcceptMulticast = 0x04,
  307. AcceptMyPhys = 0x02,
  308. AcceptAllPhys = 0x01,
  309. };
  310. /* Bits in TxConfig. */
  311. enum tx_config_bits {
  312. /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
  313. TxIFGShift = 24,
  314. TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
  315. TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
  316. TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
  317. TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
  318. TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
  319. TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
  320. TxClearAbt = (1 << 0), /* Clear abort (WO) */
  321. TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
  322. TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
  323. TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
  324. };
  325. /* Bits in Config1 */
  326. enum Config1Bits {
  327. Cfg1_PM_Enable = 0x01,
  328. Cfg1_VPD_Enable = 0x02,
  329. Cfg1_PIO = 0x04,
  330. Cfg1_MMIO = 0x08,
  331. LWAKE = 0x10, /* not on 8139, 8139A */
  332. Cfg1_Driver_Load = 0x20,
  333. Cfg1_LED0 = 0x40,
  334. Cfg1_LED1 = 0x80,
  335. SLEEP = (1 << 1), /* only on 8139, 8139A */
  336. PWRDN = (1 << 0), /* only on 8139, 8139A */
  337. };
  338. /* Bits in Config3 */
  339. enum Config3Bits {
  340. Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
  341. Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
  342. Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
  343. Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
  344. Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
  345. Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
  346. Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
  347. Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
  348. };
  349. /* Bits in Config4 */
  350. enum Config4Bits {
  351. LWPTN = (1 << 2), /* not on 8139, 8139A */
  352. };
  353. /* Bits in Config5 */
  354. enum Config5Bits {
  355. Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
  356. Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
  357. Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
  358. Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
  359. Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
  360. Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
  361. Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
  362. };
  363. enum RxConfigBits {
  364. /* rx fifo threshold */
  365. RxCfgFIFOShift = 13,
  366. RxCfgFIFONone = (7 << RxCfgFIFOShift),
  367. /* Max DMA burst */
  368. RxCfgDMAShift = 8,
  369. RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
  370. /* rx ring buffer length */
  371. RxCfgRcv8K = 0,
  372. RxCfgRcv16K = (1 << 11),
  373. RxCfgRcv32K = (1 << 12),
  374. RxCfgRcv64K = (1 << 11) | (1 << 12),
  375. /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
  376. RxNoWrap = (1 << 7),
  377. };
  378. /* Twister tuning parameters from RealTek.
  379. Completely undocumented, but required to tune bad links on some boards. */
  380. enum CSCRBits {
  381. CSCR_LinkOKBit = 0x0400,
  382. CSCR_LinkChangeBit = 0x0800,
  383. CSCR_LinkStatusBits = 0x0f000,
  384. CSCR_LinkDownOffCmd = 0x003c0,
  385. CSCR_LinkDownCmd = 0x0f3c0,
  386. };
  387. enum Cfg9346Bits {
  388. Cfg9346_Lock = 0x00,
  389. Cfg9346_Unlock = 0xC0,
  390. };
  391. typedef enum {
  392. CH_8139 = 0,
  393. CH_8139_K,
  394. CH_8139A,
  395. CH_8139A_G,
  396. CH_8139B,
  397. CH_8130,
  398. CH_8139C,
  399. CH_8100,
  400. CH_8100B_8139D,
  401. CH_8101,
  402. } chip_t;
  403. enum chip_flags {
  404. HasHltClk = (1 << 0),
  405. HasLWake = (1 << 1),
  406. };
  407. #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
  408. (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
  409. #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
  410. /* directly indexed by chip_t, above */
  411. static const struct {
  412. const char *name;
  413. u32 version; /* from RTL8139C/RTL8139D docs */
  414. u32 flags;
  415. } rtl_chip_info[] = {
  416. { "RTL-8139",
  417. HW_REVID(1, 0, 0, 0, 0, 0, 0),
  418. HasHltClk,
  419. },
  420. { "RTL-8139 rev K",
  421. HW_REVID(1, 1, 0, 0, 0, 0, 0),
  422. HasHltClk,
  423. },
  424. { "RTL-8139A",
  425. HW_REVID(1, 1, 1, 0, 0, 0, 0),
  426. HasHltClk, /* XXX undocumented? */
  427. },
  428. { "RTL-8139A rev G",
  429. HW_REVID(1, 1, 1, 0, 0, 1, 0),
  430. HasHltClk, /* XXX undocumented? */
  431. },
  432. { "RTL-8139B",
  433. HW_REVID(1, 1, 1, 1, 0, 0, 0),
  434. HasLWake,
  435. },
  436. { "RTL-8130",
  437. HW_REVID(1, 1, 1, 1, 1, 0, 0),
  438. HasLWake,
  439. },
  440. { "RTL-8139C",
  441. HW_REVID(1, 1, 1, 0, 1, 0, 0),
  442. HasLWake,
  443. },
  444. { "RTL-8100",
  445. HW_REVID(1, 1, 1, 1, 0, 1, 0),
  446. HasLWake,
  447. },
  448. { "RTL-8100B/8139D",
  449. HW_REVID(1, 1, 1, 0, 1, 0, 1),
  450. HasHltClk /* XXX undocumented? */
  451. | HasLWake,
  452. },
  453. { "RTL-8101",
  454. HW_REVID(1, 1, 1, 0, 1, 1, 1),
  455. HasLWake,
  456. },
  457. };
  458. struct rtl_extra_stats {
  459. unsigned long early_rx;
  460. unsigned long tx_buf_mapped;
  461. unsigned long tx_timeouts;
  462. unsigned long rx_lost_in_ring;
  463. };
  464. struct rtl8139_private {
  465. void __iomem *mmio_addr;
  466. int drv_flags;
  467. struct pci_dev *pci_dev;
  468. u32 msg_enable;
  469. struct net_device_stats stats;
  470. unsigned char *rx_ring;
  471. unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
  472. unsigned int tx_flag;
  473. unsigned long cur_tx;
  474. unsigned long dirty_tx;
  475. unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
  476. unsigned char *tx_bufs; /* Tx bounce buffer region. */
  477. dma_addr_t rx_ring_dma;
  478. dma_addr_t tx_bufs_dma;
  479. signed char phys[4]; /* MII device addresses. */
  480. char twistie, twist_row, twist_col; /* Twister tune state. */
  481. unsigned int watchdog_fired : 1;
  482. unsigned int default_port : 4; /* Last dev->if_port value. */
  483. unsigned int have_thread : 1;
  484. spinlock_t lock;
  485. spinlock_t rx_lock;
  486. chip_t chipset;
  487. u32 rx_config;
  488. struct rtl_extra_stats xstats;
  489. struct delayed_work thread;
  490. struct mii_if_info mii;
  491. unsigned int regs_len;
  492. unsigned long fifo_copy_timeout;
  493. };
  494. MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
  495. MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
  496. MODULE_LICENSE("GPL");
  497. MODULE_VERSION(DRV_VERSION);
  498. module_param(multicast_filter_limit, int, 0);
  499. module_param_array(media, int, NULL, 0);
  500. module_param_array(full_duplex, int, NULL, 0);
  501. module_param(debug, int, 0);
  502. MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
  503. MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
  504. MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
  505. MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
  506. static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
  507. static int rtl8139_open (struct net_device *dev);
  508. static int mdio_read (struct net_device *dev, int phy_id, int location);
  509. static void mdio_write (struct net_device *dev, int phy_id, int location,
  510. int val);
  511. static void rtl8139_start_thread(struct rtl8139_private *tp);
  512. static void rtl8139_tx_timeout (struct net_device *dev);
  513. static void rtl8139_init_ring (struct net_device *dev);
  514. static int rtl8139_start_xmit (struct sk_buff *skb,
  515. struct net_device *dev);
  516. static int rtl8139_poll(struct net_device *dev, int *budget);
  517. #ifdef CONFIG_NET_POLL_CONTROLLER
  518. static void rtl8139_poll_controller(struct net_device *dev);
  519. #endif
  520. static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
  521. static int rtl8139_close (struct net_device *dev);
  522. static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  523. static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
  524. static void rtl8139_set_rx_mode (struct net_device *dev);
  525. static void __set_rx_mode (struct net_device *dev);
  526. static void rtl8139_hw_start (struct net_device *dev);
  527. static void rtl8139_thread (struct work_struct *work);
  528. static void rtl8139_tx_timeout_task(struct work_struct *work);
  529. static const struct ethtool_ops rtl8139_ethtool_ops;
  530. /* write MMIO register, with flush */
  531. /* Flush avoids rtl8139 bug w/ posted MMIO writes */
  532. #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
  533. #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
  534. #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
  535. #define MMIO_FLUSH_AUDIT_COMPLETE 1
  536. #if MMIO_FLUSH_AUDIT_COMPLETE
  537. /* write MMIO register */
  538. #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
  539. #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
  540. #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
  541. #else
  542. /* write MMIO register, then flush */
  543. #define RTL_W8 RTL_W8_F
  544. #define RTL_W16 RTL_W16_F
  545. #define RTL_W32 RTL_W32_F
  546. #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
  547. /* read MMIO register */
  548. #define RTL_R8(reg) ioread8 (ioaddr + (reg))
  549. #define RTL_R16(reg) ioread16 (ioaddr + (reg))
  550. #define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
  551. static const u16 rtl8139_intr_mask =
  552. PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
  553. TxErr | TxOK | RxErr | RxOK;
  554. static const u16 rtl8139_norx_intr_mask =
  555. PCIErr | PCSTimeout | RxUnderrun |
  556. TxErr | TxOK | RxErr ;
  557. #if RX_BUF_IDX == 0
  558. static const unsigned int rtl8139_rx_config =
  559. RxCfgRcv8K | RxNoWrap |
  560. (RX_FIFO_THRESH << RxCfgFIFOShift) |
  561. (RX_DMA_BURST << RxCfgDMAShift);
  562. #elif RX_BUF_IDX == 1
  563. static const unsigned int rtl8139_rx_config =
  564. RxCfgRcv16K | RxNoWrap |
  565. (RX_FIFO_THRESH << RxCfgFIFOShift) |
  566. (RX_DMA_BURST << RxCfgDMAShift);
  567. #elif RX_BUF_IDX == 2
  568. static const unsigned int rtl8139_rx_config =
  569. RxCfgRcv32K | RxNoWrap |
  570. (RX_FIFO_THRESH << RxCfgFIFOShift) |
  571. (RX_DMA_BURST << RxCfgDMAShift);
  572. #elif RX_BUF_IDX == 3
  573. static const unsigned int rtl8139_rx_config =
  574. RxCfgRcv64K |
  575. (RX_FIFO_THRESH << RxCfgFIFOShift) |
  576. (RX_DMA_BURST << RxCfgDMAShift);
  577. #else
  578. #error "Invalid configuration for 8139_RXBUF_IDX"
  579. #endif
  580. static const unsigned int rtl8139_tx_config =
  581. TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
  582. static void __rtl8139_cleanup_dev (struct net_device *dev)
  583. {
  584. struct rtl8139_private *tp = netdev_priv(dev);
  585. struct pci_dev *pdev;
  586. assert (dev != NULL);
  587. assert (tp->pci_dev != NULL);
  588. pdev = tp->pci_dev;
  589. #ifdef USE_IO_OPS
  590. if (tp->mmio_addr)
  591. ioport_unmap (tp->mmio_addr);
  592. #else
  593. if (tp->mmio_addr)
  594. pci_iounmap (pdev, tp->mmio_addr);
  595. #endif /* USE_IO_OPS */
  596. /* it's ok to call this even if we have no regions to free */
  597. pci_release_regions (pdev);
  598. free_netdev(dev);
  599. pci_set_drvdata (pdev, NULL);
  600. }
  601. static void rtl8139_chip_reset (void __iomem *ioaddr)
  602. {
  603. int i;
  604. /* Soft reset the chip. */
  605. RTL_W8 (ChipCmd, CmdReset);
  606. /* Check that the chip has finished the reset. */
  607. for (i = 1000; i > 0; i--) {
  608. barrier();
  609. if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
  610. break;
  611. udelay (10);
  612. }
  613. }
  614. static int __devinit rtl8139_init_board (struct pci_dev *pdev,
  615. struct net_device **dev_out)
  616. {
  617. void __iomem *ioaddr;
  618. struct net_device *dev;
  619. struct rtl8139_private *tp;
  620. u8 tmp8;
  621. int rc, disable_dev_on_err = 0;
  622. unsigned int i;
  623. unsigned long pio_start, pio_end, pio_flags, pio_len;
  624. unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
  625. u32 version;
  626. assert (pdev != NULL);
  627. *dev_out = NULL;
  628. /* dev and priv zeroed in alloc_etherdev */
  629. dev = alloc_etherdev (sizeof (*tp));
  630. if (dev == NULL) {
  631. dev_err(&pdev->dev, "Unable to alloc new net device\n");
  632. return -ENOMEM;
  633. }
  634. SET_MODULE_OWNER(dev);
  635. SET_NETDEV_DEV(dev, &pdev->dev);
  636. tp = netdev_priv(dev);
  637. tp->pci_dev = pdev;
  638. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  639. rc = pci_enable_device (pdev);
  640. if (rc)
  641. goto err_out;
  642. pio_start = pci_resource_start (pdev, 0);
  643. pio_end = pci_resource_end (pdev, 0);
  644. pio_flags = pci_resource_flags (pdev, 0);
  645. pio_len = pci_resource_len (pdev, 0);
  646. mmio_start = pci_resource_start (pdev, 1);
  647. mmio_end = pci_resource_end (pdev, 1);
  648. mmio_flags = pci_resource_flags (pdev, 1);
  649. mmio_len = pci_resource_len (pdev, 1);
  650. /* set this immediately, we need to know before
  651. * we talk to the chip directly */
  652. DPRINTK("PIO region size == 0x%02X\n", pio_len);
  653. DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
  654. #ifdef USE_IO_OPS
  655. /* make sure PCI base addr 0 is PIO */
  656. if (!(pio_flags & IORESOURCE_IO)) {
  657. dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
  658. rc = -ENODEV;
  659. goto err_out;
  660. }
  661. /* check for weird/broken PCI region reporting */
  662. if (pio_len < RTL_MIN_IO_SIZE) {
  663. dev_err(&pdev->dev, "Invalid PCI I/O region size(s), aborting\n");
  664. rc = -ENODEV;
  665. goto err_out;
  666. }
  667. #else
  668. /* make sure PCI base addr 1 is MMIO */
  669. if (!(mmio_flags & IORESOURCE_MEM)) {
  670. dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
  671. rc = -ENODEV;
  672. goto err_out;
  673. }
  674. if (mmio_len < RTL_MIN_IO_SIZE) {
  675. dev_err(&pdev->dev, "Invalid PCI mem region size(s), aborting\n");
  676. rc = -ENODEV;
  677. goto err_out;
  678. }
  679. #endif
  680. rc = pci_request_regions (pdev, DRV_NAME);
  681. if (rc)
  682. goto err_out;
  683. disable_dev_on_err = 1;
  684. /* enable PCI bus-mastering */
  685. pci_set_master (pdev);
  686. #ifdef USE_IO_OPS
  687. ioaddr = ioport_map(pio_start, pio_len);
  688. if (!ioaddr) {
  689. dev_err(&pdev->dev, "cannot map PIO, aborting\n");
  690. rc = -EIO;
  691. goto err_out;
  692. }
  693. dev->base_addr = pio_start;
  694. tp->mmio_addr = ioaddr;
  695. tp->regs_len = pio_len;
  696. #else
  697. /* ioremap MMIO region */
  698. ioaddr = pci_iomap(pdev, 1, 0);
  699. if (ioaddr == NULL) {
  700. dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
  701. rc = -EIO;
  702. goto err_out;
  703. }
  704. dev->base_addr = (long) ioaddr;
  705. tp->mmio_addr = ioaddr;
  706. tp->regs_len = mmio_len;
  707. #endif /* USE_IO_OPS */
  708. /* Bring old chips out of low-power mode. */
  709. RTL_W8 (HltClk, 'R');
  710. /* check for missing/broken hardware */
  711. if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
  712. dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
  713. rc = -EIO;
  714. goto err_out;
  715. }
  716. /* identify chip attached to board */
  717. version = RTL_R32 (TxConfig) & HW_REVID_MASK;
  718. for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
  719. if (version == rtl_chip_info[i].version) {
  720. tp->chipset = i;
  721. goto match;
  722. }
  723. /* if unknown chip, assume array element #0, original RTL-8139 in this case */
  724. dev_printk (KERN_DEBUG, &pdev->dev,
  725. "unknown chip version, assuming RTL-8139\n");
  726. dev_printk (KERN_DEBUG, &pdev->dev,
  727. "TxConfig = 0x%lx\n", RTL_R32 (TxConfig));
  728. tp->chipset = 0;
  729. match:
  730. DPRINTK ("chipset id (%d) == index %d, '%s'\n",
  731. version, i, rtl_chip_info[i].name);
  732. if (tp->chipset >= CH_8139B) {
  733. u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
  734. DPRINTK("PCI PM wakeup\n");
  735. if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
  736. (tmp8 & LWAKE))
  737. new_tmp8 &= ~LWAKE;
  738. new_tmp8 |= Cfg1_PM_Enable;
  739. if (new_tmp8 != tmp8) {
  740. RTL_W8 (Cfg9346, Cfg9346_Unlock);
  741. RTL_W8 (Config1, tmp8);
  742. RTL_W8 (Cfg9346, Cfg9346_Lock);
  743. }
  744. if (rtl_chip_info[tp->chipset].flags & HasLWake) {
  745. tmp8 = RTL_R8 (Config4);
  746. if (tmp8 & LWPTN) {
  747. RTL_W8 (Cfg9346, Cfg9346_Unlock);
  748. RTL_W8 (Config4, tmp8 & ~LWPTN);
  749. RTL_W8 (Cfg9346, Cfg9346_Lock);
  750. }
  751. }
  752. } else {
  753. DPRINTK("Old chip wakeup\n");
  754. tmp8 = RTL_R8 (Config1);
  755. tmp8 &= ~(SLEEP | PWRDN);
  756. RTL_W8 (Config1, tmp8);
  757. }
  758. rtl8139_chip_reset (ioaddr);
  759. *dev_out = dev;
  760. return 0;
  761. err_out:
  762. __rtl8139_cleanup_dev (dev);
  763. if (disable_dev_on_err)
  764. pci_disable_device (pdev);
  765. return rc;
  766. }
  767. static int __devinit rtl8139_init_one (struct pci_dev *pdev,
  768. const struct pci_device_id *ent)
  769. {
  770. struct net_device *dev = NULL;
  771. struct rtl8139_private *tp;
  772. int i, addr_len, option;
  773. void __iomem *ioaddr;
  774. static int board_idx = -1;
  775. u8 pci_rev;
  776. assert (pdev != NULL);
  777. assert (ent != NULL);
  778. board_idx++;
  779. /* when we're built into the kernel, the driver version message
  780. * is only printed if at least one 8139 board has been found
  781. */
  782. #ifndef MODULE
  783. {
  784. static int printed_version;
  785. if (!printed_version++)
  786. printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
  787. }
  788. #endif
  789. pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
  790. if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
  791. pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
  792. dev_info(&pdev->dev,
  793. "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
  794. pdev->vendor, pdev->device, pci_rev);
  795. dev_info(&pdev->dev,
  796. "Use the \"8139cp\" driver for improved performance and stability.\n");
  797. }
  798. i = rtl8139_init_board (pdev, &dev);
  799. if (i < 0)
  800. return i;
  801. assert (dev != NULL);
  802. tp = netdev_priv(dev);
  803. ioaddr = tp->mmio_addr;
  804. assert (ioaddr != NULL);
  805. addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
  806. for (i = 0; i < 3; i++)
  807. ((u16 *) (dev->dev_addr))[i] =
  808. le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
  809. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  810. /* The Rtl8139-specific entries in the device structure. */
  811. dev->open = rtl8139_open;
  812. dev->hard_start_xmit = rtl8139_start_xmit;
  813. dev->poll = rtl8139_poll;
  814. dev->weight = 64;
  815. dev->stop = rtl8139_close;
  816. dev->get_stats = rtl8139_get_stats;
  817. dev->set_multicast_list = rtl8139_set_rx_mode;
  818. dev->do_ioctl = netdev_ioctl;
  819. dev->ethtool_ops = &rtl8139_ethtool_ops;
  820. dev->tx_timeout = rtl8139_tx_timeout;
  821. dev->watchdog_timeo = TX_TIMEOUT;
  822. #ifdef CONFIG_NET_POLL_CONTROLLER
  823. dev->poll_controller = rtl8139_poll_controller;
  824. #endif
  825. /* note: the hardware is not capable of sg/csum/highdma, however
  826. * through the use of skb_copy_and_csum_dev we enable these
  827. * features
  828. */
  829. dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
  830. dev->irq = pdev->irq;
  831. /* tp zeroed and aligned in alloc_etherdev */
  832. tp = netdev_priv(dev);
  833. /* note: tp->chipset set in rtl8139_init_board */
  834. tp->drv_flags = board_info[ent->driver_data].hw_flags;
  835. tp->mmio_addr = ioaddr;
  836. tp->msg_enable =
  837. (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
  838. spin_lock_init (&tp->lock);
  839. spin_lock_init (&tp->rx_lock);
  840. INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
  841. tp->mii.dev = dev;
  842. tp->mii.mdio_read = mdio_read;
  843. tp->mii.mdio_write = mdio_write;
  844. tp->mii.phy_id_mask = 0x3f;
  845. tp->mii.reg_num_mask = 0x1f;
  846. /* dev is fully set up and ready to use now */
  847. DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
  848. i = register_netdev (dev);
  849. if (i) goto err_out;
  850. pci_set_drvdata (pdev, dev);
  851. printk (KERN_INFO "%s: %s at 0x%lx, "
  852. "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
  853. "IRQ %d\n",
  854. dev->name,
  855. board_info[ent->driver_data].name,
  856. dev->base_addr,
  857. dev->dev_addr[0], dev->dev_addr[1],
  858. dev->dev_addr[2], dev->dev_addr[3],
  859. dev->dev_addr[4], dev->dev_addr[5],
  860. dev->irq);
  861. printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
  862. dev->name, rtl_chip_info[tp->chipset].name);
  863. /* Find the connected MII xcvrs.
  864. Doing this in open() would allow detecting external xcvrs later, but
  865. takes too much time. */
  866. #ifdef CONFIG_8139TOO_8129
  867. if (tp->drv_flags & HAS_MII_XCVR) {
  868. int phy, phy_idx = 0;
  869. for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
  870. int mii_status = mdio_read(dev, phy, 1);
  871. if (mii_status != 0xffff && mii_status != 0x0000) {
  872. u16 advertising = mdio_read(dev, phy, 4);
  873. tp->phys[phy_idx++] = phy;
  874. printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
  875. "advertising %4.4x.\n",
  876. dev->name, phy, mii_status, advertising);
  877. }
  878. }
  879. if (phy_idx == 0) {
  880. printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
  881. "transceiver.\n",
  882. dev->name);
  883. tp->phys[0] = 32;
  884. }
  885. } else
  886. #endif
  887. tp->phys[0] = 32;
  888. tp->mii.phy_id = tp->phys[0];
  889. /* The lower four bits are the media type. */
  890. option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
  891. if (option > 0) {
  892. tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
  893. tp->default_port = option & 0xFF;
  894. if (tp->default_port)
  895. tp->mii.force_media = 1;
  896. }
  897. if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
  898. tp->mii.full_duplex = full_duplex[board_idx];
  899. if (tp->mii.full_duplex) {
  900. printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
  901. /* Changing the MII-advertised media because might prevent
  902. re-connection. */
  903. tp->mii.force_media = 1;
  904. }
  905. if (tp->default_port) {
  906. printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
  907. (option & 0x20 ? 100 : 10),
  908. (option & 0x10 ? "full" : "half"));
  909. mdio_write(dev, tp->phys[0], 0,
  910. ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
  911. ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
  912. }
  913. /* Put the chip into low-power mode. */
  914. if (rtl_chip_info[tp->chipset].flags & HasHltClk)
  915. RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
  916. return 0;
  917. err_out:
  918. __rtl8139_cleanup_dev (dev);
  919. pci_disable_device (pdev);
  920. return i;
  921. }
  922. static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
  923. {
  924. struct net_device *dev = pci_get_drvdata (pdev);
  925. assert (dev != NULL);
  926. flush_scheduled_work();
  927. unregister_netdev (dev);
  928. __rtl8139_cleanup_dev (dev);
  929. pci_disable_device (pdev);
  930. }
  931. /* Serial EEPROM section. */
  932. /* EEPROM_Ctrl bits. */
  933. #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
  934. #define EE_CS 0x08 /* EEPROM chip select. */
  935. #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
  936. #define EE_WRITE_0 0x00
  937. #define EE_WRITE_1 0x02
  938. #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
  939. #define EE_ENB (0x80 | EE_CS)
  940. /* Delay between EEPROM clock transitions.
  941. No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
  942. */
  943. #define eeprom_delay() (void)RTL_R32(Cfg9346)
  944. /* The EEPROM commands include the alway-set leading bit. */
  945. #define EE_WRITE_CMD (5)
  946. #define EE_READ_CMD (6)
  947. #define EE_ERASE_CMD (7)
  948. static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
  949. {
  950. int i;
  951. unsigned retval = 0;
  952. int read_cmd = location | (EE_READ_CMD << addr_len);
  953. RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
  954. RTL_W8 (Cfg9346, EE_ENB);
  955. eeprom_delay ();
  956. /* Shift the read command bits out. */
  957. for (i = 4 + addr_len; i >= 0; i--) {
  958. int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  959. RTL_W8 (Cfg9346, EE_ENB | dataval);
  960. eeprom_delay ();
  961. RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
  962. eeprom_delay ();
  963. }
  964. RTL_W8 (Cfg9346, EE_ENB);
  965. eeprom_delay ();
  966. for (i = 16; i > 0; i--) {
  967. RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
  968. eeprom_delay ();
  969. retval =
  970. (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
  971. 0);
  972. RTL_W8 (Cfg9346, EE_ENB);
  973. eeprom_delay ();
  974. }
  975. /* Terminate the EEPROM access. */
  976. RTL_W8 (Cfg9346, ~EE_CS);
  977. eeprom_delay ();
  978. return retval;
  979. }
  980. /* MII serial management: mostly bogus for now. */
  981. /* Read and write the MII management registers using software-generated
  982. serial MDIO protocol.
  983. The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
  984. met by back-to-back PCI I/O cycles, but we insert a delay to avoid
  985. "overclocking" issues. */
  986. #define MDIO_DIR 0x80
  987. #define MDIO_DATA_OUT 0x04
  988. #define MDIO_DATA_IN 0x02
  989. #define MDIO_CLK 0x01
  990. #define MDIO_WRITE0 (MDIO_DIR)
  991. #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
  992. #define mdio_delay() RTL_R8(Config4)
  993. static const char mii_2_8139_map[8] = {
  994. BasicModeCtrl,
  995. BasicModeStatus,
  996. 0,
  997. 0,
  998. NWayAdvert,
  999. NWayLPAR,
  1000. NWayExpansion,
  1001. 0
  1002. };
  1003. #ifdef CONFIG_8139TOO_8129
  1004. /* Syncronize the MII management interface by shifting 32 one bits out. */
  1005. static void mdio_sync (void __iomem *ioaddr)
  1006. {
  1007. int i;
  1008. for (i = 32; i >= 0; i--) {
  1009. RTL_W8 (Config4, MDIO_WRITE1);
  1010. mdio_delay ();
  1011. RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
  1012. mdio_delay ();
  1013. }
  1014. }
  1015. #endif
  1016. static int mdio_read (struct net_device *dev, int phy_id, int location)
  1017. {
  1018. struct rtl8139_private *tp = netdev_priv(dev);
  1019. int retval = 0;
  1020. #ifdef CONFIG_8139TOO_8129
  1021. void __iomem *ioaddr = tp->mmio_addr;
  1022. int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
  1023. int i;
  1024. #endif
  1025. if (phy_id > 31) { /* Really a 8139. Use internal registers. */
  1026. void __iomem *ioaddr = tp->mmio_addr;
  1027. return location < 8 && mii_2_8139_map[location] ?
  1028. RTL_R16 (mii_2_8139_map[location]) : 0;
  1029. }
  1030. #ifdef CONFIG_8139TOO_8129
  1031. mdio_sync (ioaddr);
  1032. /* Shift the read command bits out. */
  1033. for (i = 15; i >= 0; i--) {
  1034. int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
  1035. RTL_W8 (Config4, MDIO_DIR | dataval);
  1036. mdio_delay ();
  1037. RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
  1038. mdio_delay ();
  1039. }
  1040. /* Read the two transition, 16 data, and wire-idle bits. */
  1041. for (i = 19; i > 0; i--) {
  1042. RTL_W8 (Config4, 0);
  1043. mdio_delay ();
  1044. retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
  1045. RTL_W8 (Config4, MDIO_CLK);
  1046. mdio_delay ();
  1047. }
  1048. #endif
  1049. return (retval >> 1) & 0xffff;
  1050. }
  1051. static void mdio_write (struct net_device *dev, int phy_id, int location,
  1052. int value)
  1053. {
  1054. struct rtl8139_private *tp = netdev_priv(dev);
  1055. #ifdef CONFIG_8139TOO_8129
  1056. void __iomem *ioaddr = tp->mmio_addr;
  1057. int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
  1058. int i;
  1059. #endif
  1060. if (phy_id > 31) { /* Really a 8139. Use internal registers. */
  1061. void __iomem *ioaddr = tp->mmio_addr;
  1062. if (location == 0) {
  1063. RTL_W8 (Cfg9346, Cfg9346_Unlock);
  1064. RTL_W16 (BasicModeCtrl, value);
  1065. RTL_W8 (Cfg9346, Cfg9346_Lock);
  1066. } else if (location < 8 && mii_2_8139_map[location])
  1067. RTL_W16 (mii_2_8139_map[location], value);
  1068. return;
  1069. }
  1070. #ifdef CONFIG_8139TOO_8129
  1071. mdio_sync (ioaddr);
  1072. /* Shift the command bits out. */
  1073. for (i = 31; i >= 0; i--) {
  1074. int dataval =
  1075. (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
  1076. RTL_W8 (Config4, dataval);
  1077. mdio_delay ();
  1078. RTL_W8 (Config4, dataval | MDIO_CLK);
  1079. mdio_delay ();
  1080. }
  1081. /* Clear out extra bits. */
  1082. for (i = 2; i > 0; i--) {
  1083. RTL_W8 (Config4, 0);
  1084. mdio_delay ();
  1085. RTL_W8 (Config4, MDIO_CLK);
  1086. mdio_delay ();
  1087. }
  1088. #endif
  1089. }
  1090. static int rtl8139_open (struct net_device *dev)
  1091. {
  1092. struct rtl8139_private *tp = netdev_priv(dev);
  1093. int retval;
  1094. void __iomem *ioaddr = tp->mmio_addr;
  1095. retval = request_irq (dev->irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
  1096. if (retval)
  1097. return retval;
  1098. tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
  1099. &tp->tx_bufs_dma);
  1100. tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
  1101. &tp->rx_ring_dma);
  1102. if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
  1103. free_irq(dev->irq, dev);
  1104. if (tp->tx_bufs)
  1105. pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
  1106. tp->tx_bufs, tp->tx_bufs_dma);
  1107. if (tp->rx_ring)
  1108. pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
  1109. tp->rx_ring, tp->rx_ring_dma);
  1110. return -ENOMEM;
  1111. }
  1112. tp->mii.full_duplex = tp->mii.force_media;
  1113. tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
  1114. rtl8139_init_ring (dev);
  1115. rtl8139_hw_start (dev);
  1116. netif_start_queue (dev);
  1117. if (netif_msg_ifup(tp))
  1118. printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#llx IRQ %d"
  1119. " GP Pins %2.2x %s-duplex.\n", dev->name,
  1120. (unsigned long long)pci_resource_start (tp->pci_dev, 1),
  1121. dev->irq, RTL_R8 (MediaStatus),
  1122. tp->mii.full_duplex ? "full" : "half");
  1123. rtl8139_start_thread(tp);
  1124. return 0;
  1125. }
  1126. static void rtl_check_media (struct net_device *dev, unsigned int init_media)
  1127. {
  1128. struct rtl8139_private *tp = netdev_priv(dev);
  1129. if (tp->phys[0] >= 0) {
  1130. mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
  1131. }
  1132. }
  1133. /* Start the hardware at open or resume. */
  1134. static void rtl8139_hw_start (struct net_device *dev)
  1135. {
  1136. struct rtl8139_private *tp = netdev_priv(dev);
  1137. void __iomem *ioaddr = tp->mmio_addr;
  1138. u32 i;
  1139. u8 tmp;
  1140. /* Bring old chips out of low-power mode. */
  1141. if (rtl_chip_info[tp->chipset].flags & HasHltClk)
  1142. RTL_W8 (HltClk, 'R');
  1143. rtl8139_chip_reset (ioaddr);
  1144. /* unlock Config[01234] and BMCR register writes */
  1145. RTL_W8_F (Cfg9346, Cfg9346_Unlock);
  1146. /* Restore our idea of the MAC address. */
  1147. RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
  1148. RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
  1149. /* Must enable Tx/Rx before setting transfer thresholds! */
  1150. RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
  1151. tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
  1152. RTL_W32 (RxConfig, tp->rx_config);
  1153. RTL_W32 (TxConfig, rtl8139_tx_config);
  1154. tp->cur_rx = 0;
  1155. rtl_check_media (dev, 1);
  1156. if (tp->chipset >= CH_8139B) {
  1157. /* Disable magic packet scanning, which is enabled
  1158. * when PM is enabled in Config1. It can be reenabled
  1159. * via ETHTOOL_SWOL if desired. */
  1160. RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
  1161. }
  1162. DPRINTK("init buffer addresses\n");
  1163. /* Lock Config[01234] and BMCR register writes */
  1164. RTL_W8 (Cfg9346, Cfg9346_Lock);
  1165. /* init Rx ring buffer DMA address */
  1166. RTL_W32_F (RxBuf, tp->rx_ring_dma);
  1167. /* init Tx buffer DMA addresses */
  1168. for (i = 0; i < NUM_TX_DESC; i++)
  1169. RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
  1170. RTL_W32 (RxMissed, 0);
  1171. rtl8139_set_rx_mode (dev);
  1172. /* no early-rx interrupts */
  1173. RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
  1174. /* make sure RxTx has started */
  1175. tmp = RTL_R8 (ChipCmd);
  1176. if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
  1177. RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
  1178. /* Enable all known interrupts by setting the interrupt mask. */
  1179. RTL_W16 (IntrMask, rtl8139_intr_mask);
  1180. }
  1181. /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
  1182. static void rtl8139_init_ring (struct net_device *dev)
  1183. {
  1184. struct rtl8139_private *tp = netdev_priv(dev);
  1185. int i;
  1186. tp->cur_rx = 0;
  1187. tp->cur_tx = 0;
  1188. tp->dirty_tx = 0;
  1189. for (i = 0; i < NUM_TX_DESC; i++)
  1190. tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
  1191. }
  1192. /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
  1193. static int next_tick = 3 * HZ;
  1194. #ifndef CONFIG_8139TOO_TUNE_TWISTER
  1195. static inline void rtl8139_tune_twister (struct net_device *dev,
  1196. struct rtl8139_private *tp) {}
  1197. #else
  1198. enum TwisterParamVals {
  1199. PARA78_default = 0x78fa8388,
  1200. PARA7c_default = 0xcb38de43, /* param[0][3] */
  1201. PARA7c_xxx = 0xcb38de43,
  1202. };
  1203. static const unsigned long param[4][4] = {
  1204. {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
  1205. {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
  1206. {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
  1207. {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
  1208. };
  1209. static void rtl8139_tune_twister (struct net_device *dev,
  1210. struct rtl8139_private *tp)
  1211. {
  1212. int linkcase;
  1213. void __iomem *ioaddr = tp->mmio_addr;
  1214. /* This is a complicated state machine to configure the "twister" for
  1215. impedance/echos based on the cable length.
  1216. All of this is magic and undocumented.
  1217. */
  1218. switch (tp->twistie) {
  1219. case 1:
  1220. if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
  1221. /* We have link beat, let us tune the twister. */
  1222. RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
  1223. tp->twistie = 2; /* Change to state 2. */
  1224. next_tick = HZ / 10;
  1225. } else {
  1226. /* Just put in some reasonable defaults for when beat returns. */
  1227. RTL_W16 (CSCR, CSCR_LinkDownCmd);
  1228. RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
  1229. RTL_W32 (PARA78, PARA78_default);
  1230. RTL_W32 (PARA7c, PARA7c_default);
  1231. tp->twistie = 0; /* Bail from future actions. */
  1232. }
  1233. break;
  1234. case 2:
  1235. /* Read how long it took to hear the echo. */
  1236. linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
  1237. if (linkcase == 0x7000)
  1238. tp->twist_row = 3;
  1239. else if (linkcase == 0x3000)
  1240. tp->twist_row = 2;
  1241. else if (linkcase == 0x1000)
  1242. tp->twist_row = 1;
  1243. else
  1244. tp->twist_row = 0;
  1245. tp->twist_col = 0;
  1246. tp->twistie = 3; /* Change to state 2. */
  1247. next_tick = HZ / 10;
  1248. break;
  1249. case 3:
  1250. /* Put out four tuning parameters, one per 100msec. */
  1251. if (tp->twist_col == 0)
  1252. RTL_W16 (FIFOTMS, 0);
  1253. RTL_W32 (PARA7c, param[(int) tp->twist_row]
  1254. [(int) tp->twist_col]);
  1255. next_tick = HZ / 10;
  1256. if (++tp->twist_col >= 4) {
  1257. /* For short cables we are done.
  1258. For long cables (row == 3) check for mistune. */
  1259. tp->twistie =
  1260. (tp->twist_row == 3) ? 4 : 0;
  1261. }
  1262. break;
  1263. case 4:
  1264. /* Special case for long cables: check for mistune. */
  1265. if ((RTL_R16 (CSCR) &
  1266. CSCR_LinkStatusBits) == 0x7000) {
  1267. tp->twistie = 0;
  1268. break;
  1269. } else {
  1270. RTL_W32 (PARA7c, 0xfb38de03);
  1271. tp->twistie = 5;
  1272. next_tick = HZ / 10;
  1273. }
  1274. break;
  1275. case 5:
  1276. /* Retune for shorter cable (column 2). */
  1277. RTL_W32 (FIFOTMS, 0x20);
  1278. RTL_W32 (PARA78, PARA78_default);
  1279. RTL_W32 (PARA7c, PARA7c_default);
  1280. RTL_W32 (FIFOTMS, 0x00);
  1281. tp->twist_row = 2;
  1282. tp->twist_col = 0;
  1283. tp->twistie = 3;
  1284. next_tick = HZ / 10;
  1285. break;
  1286. default:
  1287. /* do nothing */
  1288. break;
  1289. }
  1290. }
  1291. #endif /* CONFIG_8139TOO_TUNE_TWISTER */
  1292. static inline void rtl8139_thread_iter (struct net_device *dev,
  1293. struct rtl8139_private *tp,
  1294. void __iomem *ioaddr)
  1295. {
  1296. int mii_lpa;
  1297. mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
  1298. if (!tp->mii.force_media && mii_lpa != 0xffff) {
  1299. int duplex = (mii_lpa & LPA_100FULL)
  1300. || (mii_lpa & 0x01C0) == 0x0040;
  1301. if (tp->mii.full_duplex != duplex) {
  1302. tp->mii.full_duplex = duplex;
  1303. if (mii_lpa) {
  1304. printk (KERN_INFO
  1305. "%s: Setting %s-duplex based on MII #%d link"
  1306. " partner ability of %4.4x.\n",
  1307. dev->name,
  1308. tp->mii.full_duplex ? "full" : "half",
  1309. tp->phys[0], mii_lpa);
  1310. } else {
  1311. printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
  1312. dev->name);
  1313. }
  1314. #if 0
  1315. RTL_W8 (Cfg9346, Cfg9346_Unlock);
  1316. RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
  1317. RTL_W8 (Cfg9346, Cfg9346_Lock);
  1318. #endif
  1319. }
  1320. }
  1321. next_tick = HZ * 60;
  1322. rtl8139_tune_twister (dev, tp);
  1323. DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
  1324. dev->name, RTL_R16 (NWayLPAR));
  1325. DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
  1326. dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
  1327. DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
  1328. dev->name, RTL_R8 (Config0),
  1329. RTL_R8 (Config1));
  1330. }
  1331. static void rtl8139_thread (struct work_struct *work)
  1332. {
  1333. struct rtl8139_private *tp =
  1334. container_of(work, struct rtl8139_private, thread.work);
  1335. struct net_device *dev = tp->mii.dev;
  1336. unsigned long thr_delay = next_tick;
  1337. rtnl_lock();
  1338. if (!netif_running(dev))
  1339. goto out_unlock;
  1340. if (tp->watchdog_fired) {
  1341. tp->watchdog_fired = 0;
  1342. rtl8139_tx_timeout_task(work);
  1343. } else
  1344. rtl8139_thread_iter(dev, tp, tp->mmio_addr);
  1345. if (tp->have_thread)
  1346. schedule_delayed_work(&tp->thread, thr_delay);
  1347. out_unlock:
  1348. rtnl_unlock ();
  1349. }
  1350. static void rtl8139_start_thread(struct rtl8139_private *tp)
  1351. {
  1352. tp->twistie = 0;
  1353. if (tp->chipset == CH_8139_K)
  1354. tp->twistie = 1;
  1355. else if (tp->drv_flags & HAS_LNK_CHNG)
  1356. return;
  1357. tp->have_thread = 1;
  1358. tp->watchdog_fired = 0;
  1359. schedule_delayed_work(&tp->thread, next_tick);
  1360. }
  1361. static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
  1362. {
  1363. tp->cur_tx = 0;
  1364. tp->dirty_tx = 0;
  1365. /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
  1366. }
  1367. static void rtl8139_tx_timeout_task (struct work_struct *work)
  1368. {
  1369. struct rtl8139_private *tp =
  1370. container_of(work, struct rtl8139_private, thread.work);
  1371. struct net_device *dev = tp->mii.dev;
  1372. void __iomem *ioaddr = tp->mmio_addr;
  1373. int i;
  1374. u8 tmp8;
  1375. printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
  1376. "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
  1377. RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
  1378. /* Emit info to figure out what went wrong. */
  1379. printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
  1380. dev->name, tp->cur_tx, tp->dirty_tx);
  1381. for (i = 0; i < NUM_TX_DESC; i++)
  1382. printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
  1383. dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
  1384. i == tp->dirty_tx % NUM_TX_DESC ?
  1385. " (queue head)" : "");
  1386. tp->xstats.tx_timeouts++;
  1387. /* disable Tx ASAP, if not already */
  1388. tmp8 = RTL_R8 (ChipCmd);
  1389. if (tmp8 & CmdTxEnb)
  1390. RTL_W8 (ChipCmd, CmdRxEnb);
  1391. spin_lock_bh(&tp->rx_lock);
  1392. /* Disable interrupts by clearing the interrupt mask. */
  1393. RTL_W16 (IntrMask, 0x0000);
  1394. /* Stop a shared interrupt from scavenging while we are. */
  1395. spin_lock_irq(&tp->lock);
  1396. rtl8139_tx_clear (tp);
  1397. spin_unlock_irq(&tp->lock);
  1398. /* ...and finally, reset everything */
  1399. if (netif_running(dev)) {
  1400. rtl8139_hw_start (dev);
  1401. netif_wake_queue (dev);
  1402. }
  1403. spin_unlock_bh(&tp->rx_lock);
  1404. }
  1405. static void rtl8139_tx_timeout (struct net_device *dev)
  1406. {
  1407. struct rtl8139_private *tp = netdev_priv(dev);
  1408. tp->watchdog_fired = 1;
  1409. if (!tp->have_thread) {
  1410. INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
  1411. schedule_delayed_work(&tp->thread, next_tick);
  1412. }
  1413. }
  1414. static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
  1415. {
  1416. struct rtl8139_private *tp = netdev_priv(dev);
  1417. void __iomem *ioaddr = tp->mmio_addr;
  1418. unsigned int entry;
  1419. unsigned int len = skb->len;
  1420. unsigned long flags;
  1421. /* Calculate the next Tx descriptor entry. */
  1422. entry = tp->cur_tx % NUM_TX_DESC;
  1423. /* Note: the chip doesn't have auto-pad! */
  1424. if (likely(len < TX_BUF_SIZE)) {
  1425. if (len < ETH_ZLEN)
  1426. memset(tp->tx_buf[entry], 0, ETH_ZLEN);
  1427. skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
  1428. dev_kfree_skb(skb);
  1429. } else {
  1430. dev_kfree_skb(skb);
  1431. tp->stats.tx_dropped++;
  1432. return 0;
  1433. }
  1434. spin_lock_irqsave(&tp->lock, flags);
  1435. RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
  1436. tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
  1437. dev->trans_start = jiffies;
  1438. tp->cur_tx++;
  1439. wmb();
  1440. if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
  1441. netif_stop_queue (dev);
  1442. spin_unlock_irqrestore(&tp->lock, flags);
  1443. if (netif_msg_tx_queued(tp))
  1444. printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
  1445. dev->name, len, entry);
  1446. return 0;
  1447. }
  1448. static void rtl8139_tx_interrupt (struct net_device *dev,
  1449. struct rtl8139_private *tp,
  1450. void __iomem *ioaddr)
  1451. {
  1452. unsigned long dirty_tx, tx_left;
  1453. assert (dev != NULL);
  1454. assert (ioaddr != NULL);
  1455. dirty_tx = tp->dirty_tx;
  1456. tx_left = tp->cur_tx - dirty_tx;
  1457. while (tx_left > 0) {
  1458. int entry = dirty_tx % NUM_TX_DESC;
  1459. int txstatus;
  1460. txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
  1461. if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
  1462. break; /* It still hasn't been Txed */
  1463. /* Note: TxCarrierLost is always asserted at 100mbps. */
  1464. if (txstatus & (TxOutOfWindow | TxAborted)) {
  1465. /* There was an major error, log it. */
  1466. if (netif_msg_tx_err(tp))
  1467. printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
  1468. dev->name, txstatus);
  1469. tp->stats.tx_errors++;
  1470. if (txstatus & TxAborted) {
  1471. tp->stats.tx_aborted_errors++;
  1472. RTL_W32 (TxConfig, TxClearAbt);
  1473. RTL_W16 (IntrStatus, TxErr);
  1474. wmb();
  1475. }
  1476. if (txstatus & TxCarrierLost)
  1477. tp->stats.tx_carrier_errors++;
  1478. if (txstatus & TxOutOfWindow)
  1479. tp->stats.tx_window_errors++;
  1480. } else {
  1481. if (txstatus & TxUnderrun) {
  1482. /* Add 64 to the Tx FIFO threshold. */
  1483. if (tp->tx_flag < 0x00300000)
  1484. tp->tx_flag += 0x00020000;
  1485. tp->stats.tx_fifo_errors++;
  1486. }
  1487. tp->stats.collisions += (txstatus >> 24) & 15;
  1488. tp->stats.tx_bytes += txstatus & 0x7ff;
  1489. tp->stats.tx_packets++;
  1490. }
  1491. dirty_tx++;
  1492. tx_left--;
  1493. }
  1494. #ifndef RTL8139_NDEBUG
  1495. if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
  1496. printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
  1497. dev->name, dirty_tx, tp->cur_tx);
  1498. dirty_tx += NUM_TX_DESC;
  1499. }
  1500. #endif /* RTL8139_NDEBUG */
  1501. /* only wake the queue if we did work, and the queue is stopped */
  1502. if (tp->dirty_tx != dirty_tx) {
  1503. tp->dirty_tx = dirty_tx;
  1504. mb();
  1505. netif_wake_queue (dev);
  1506. }
  1507. }
  1508. /* TODO: clean this up! Rx reset need not be this intensive */
  1509. static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
  1510. struct rtl8139_private *tp, void __iomem *ioaddr)
  1511. {
  1512. u8 tmp8;
  1513. #ifdef CONFIG_8139_OLD_RX_RESET
  1514. int tmp_work;
  1515. #endif
  1516. if (netif_msg_rx_err (tp))
  1517. printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
  1518. dev->name, rx_status);
  1519. tp->stats.rx_errors++;
  1520. if (!(rx_status & RxStatusOK)) {
  1521. if (rx_status & RxTooLong) {
  1522. DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
  1523. dev->name, rx_status);
  1524. /* A.C.: The chip hangs here. */
  1525. }
  1526. if (rx_status & (RxBadSymbol | RxBadAlign))
  1527. tp->stats.rx_frame_errors++;
  1528. if (rx_status & (RxRunt | RxTooLong))
  1529. tp->stats.rx_length_errors++;
  1530. if (rx_status & RxCRCErr)
  1531. tp->stats.rx_crc_errors++;
  1532. } else {
  1533. tp->xstats.rx_lost_in_ring++;
  1534. }
  1535. #ifndef CONFIG_8139_OLD_RX_RESET
  1536. tmp8 = RTL_R8 (ChipCmd);
  1537. RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
  1538. RTL_W8 (ChipCmd, tmp8);
  1539. RTL_W32 (RxConfig, tp->rx_config);
  1540. tp->cur_rx = 0;
  1541. #else
  1542. /* Reset the receiver, based on RealTek recommendation. (Bug?) */
  1543. /* disable receive */
  1544. RTL_W8_F (ChipCmd, CmdTxEnb);
  1545. tmp_work = 200;
  1546. while (--tmp_work > 0) {
  1547. udelay(1);
  1548. tmp8 = RTL_R8 (ChipCmd);
  1549. if (!(tmp8 & CmdRxEnb))
  1550. break;
  1551. }
  1552. if (tmp_work <= 0)
  1553. printk (KERN_WARNING PFX "rx stop wait too long\n");
  1554. /* restart receive */
  1555. tmp_work = 200;
  1556. while (--tmp_work > 0) {
  1557. RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
  1558. udelay(1);
  1559. tmp8 = RTL_R8 (ChipCmd);
  1560. if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
  1561. break;
  1562. }
  1563. if (tmp_work <= 0)
  1564. printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
  1565. /* and reinitialize all rx related registers */
  1566. RTL_W8_F (Cfg9346, Cfg9346_Unlock);
  1567. /* Must enable Tx/Rx before setting transfer thresholds! */
  1568. RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
  1569. tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
  1570. RTL_W32 (RxConfig, tp->rx_config);
  1571. tp->cur_rx = 0;
  1572. DPRINTK("init buffer addresses\n");
  1573. /* Lock Config[01234] and BMCR register writes */
  1574. RTL_W8 (Cfg9346, Cfg9346_Lock);
  1575. /* init Rx ring buffer DMA address */
  1576. RTL_W32_F (RxBuf, tp->rx_ring_dma);
  1577. /* A.C.: Reset the multicast list. */
  1578. __set_rx_mode (dev);
  1579. #endif
  1580. }
  1581. #if RX_BUF_IDX == 3
  1582. static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
  1583. u32 offset, unsigned int size)
  1584. {
  1585. u32 left = RX_BUF_LEN - offset;
  1586. if (size > left) {
  1587. memcpy(skb->data, ring + offset, left);
  1588. memcpy(skb->data+left, ring, size - left);
  1589. } else
  1590. memcpy(skb->data, ring + offset, size);
  1591. }
  1592. #endif
  1593. static void rtl8139_isr_ack(struct rtl8139_private *tp)
  1594. {
  1595. void __iomem *ioaddr = tp->mmio_addr;
  1596. u16 status;
  1597. status = RTL_R16 (IntrStatus) & RxAckBits;
  1598. /* Clear out errors and receive interrupts */
  1599. if (likely(status != 0)) {
  1600. if (unlikely(status & (RxFIFOOver | RxOverflow))) {
  1601. tp->stats.rx_errors++;
  1602. if (status & RxFIFOOver)
  1603. tp->stats.rx_fifo_errors++;
  1604. }
  1605. RTL_W16_F (IntrStatus, RxAckBits);
  1606. }
  1607. }
  1608. static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
  1609. int budget)
  1610. {
  1611. void __iomem *ioaddr = tp->mmio_addr;
  1612. int received = 0;
  1613. unsigned char *rx_ring = tp->rx_ring;
  1614. unsigned int cur_rx = tp->cur_rx;
  1615. unsigned int rx_size = 0;
  1616. DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
  1617. " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
  1618. RTL_R16 (RxBufAddr),
  1619. RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
  1620. while (netif_running(dev) && received < budget
  1621. && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
  1622. u32 ring_offset = cur_rx % RX_BUF_LEN;
  1623. u32 rx_status;
  1624. unsigned int pkt_size;
  1625. struct sk_buff *skb;
  1626. rmb();
  1627. /* read size+status of next frame from DMA ring buffer */
  1628. rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
  1629. rx_size = rx_status >> 16;
  1630. pkt_size = rx_size - 4;
  1631. if (netif_msg_rx_status(tp))
  1632. printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
  1633. " cur %4.4x.\n", dev->name, rx_status,
  1634. rx_size, cur_rx);
  1635. #if RTL8139_DEBUG > 2
  1636. {
  1637. int i;
  1638. DPRINTK ("%s: Frame contents ", dev->name);
  1639. for (i = 0; i < 70; i++)
  1640. printk (" %2.2x",
  1641. rx_ring[ring_offset + i]);
  1642. printk (".\n");
  1643. }
  1644. #endif
  1645. /* Packet copy from FIFO still in progress.
  1646. * Theoretically, this should never happen
  1647. * since EarlyRx is disabled.
  1648. */
  1649. if (unlikely(rx_size == 0xfff0)) {
  1650. if (!tp->fifo_copy_timeout)
  1651. tp->fifo_copy_timeout = jiffies + 2;
  1652. else if (time_after(jiffies, tp->fifo_copy_timeout)) {
  1653. DPRINTK ("%s: hung FIFO. Reset.", dev->name);
  1654. rx_size = 0;
  1655. goto no_early_rx;
  1656. }
  1657. if (netif_msg_intr(tp)) {
  1658. printk(KERN_DEBUG "%s: fifo copy in progress.",
  1659. dev->name);
  1660. }
  1661. tp->xstats.early_rx++;
  1662. break;
  1663. }
  1664. no_early_rx:
  1665. tp->fifo_copy_timeout = 0;
  1666. /* If Rx err or invalid rx_size/rx_status received
  1667. * (which happens if we get lost in the ring),
  1668. * Rx process gets reset, so we abort any further
  1669. * Rx processing.
  1670. */
  1671. if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
  1672. (rx_size < 8) ||
  1673. (!(rx_status & RxStatusOK)))) {
  1674. rtl8139_rx_err (rx_status, dev, tp, ioaddr);
  1675. received = -1;
  1676. goto out;
  1677. }
  1678. /* Malloc up new buffer, compatible with net-2e. */
  1679. /* Omit the four octet CRC from the length. */
  1680. skb = dev_alloc_skb (pkt_size + 2);
  1681. if (likely(skb)) {
  1682. skb->dev = dev;
  1683. skb_reserve (skb, 2); /* 16 byte align the IP fields. */
  1684. #if RX_BUF_IDX == 3
  1685. wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
  1686. #else
  1687. eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
  1688. #endif
  1689. skb_put (skb, pkt_size);
  1690. skb->protocol = eth_type_trans (skb, dev);
  1691. dev->last_rx = jiffies;
  1692. tp->stats.rx_bytes += pkt_size;
  1693. tp->stats.rx_packets++;
  1694. netif_receive_skb (skb);
  1695. } else {
  1696. if (net_ratelimit())
  1697. printk (KERN_WARNING
  1698. "%s: Memory squeeze, dropping packet.\n",
  1699. dev->name);
  1700. tp->stats.rx_dropped++;
  1701. }
  1702. received++;
  1703. cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
  1704. RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
  1705. rtl8139_isr_ack(tp);
  1706. }
  1707. if (unlikely(!received || rx_size == 0xfff0))
  1708. rtl8139_isr_ack(tp);
  1709. #if RTL8139_DEBUG > 1
  1710. DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
  1711. " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
  1712. RTL_R16 (RxBufAddr),
  1713. RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
  1714. #endif
  1715. tp->cur_rx = cur_rx;
  1716. /*
  1717. * The receive buffer should be mostly empty.
  1718. * Tell NAPI to reenable the Rx irq.
  1719. */
  1720. if (tp->fifo_copy_timeout)
  1721. received = budget;
  1722. out:
  1723. return received;
  1724. }
  1725. static void rtl8139_weird_interrupt (struct net_device *dev,
  1726. struct rtl8139_private *tp,
  1727. void __iomem *ioaddr,
  1728. int status, int link_changed)
  1729. {
  1730. DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
  1731. dev->name, status);
  1732. assert (dev != NULL);
  1733. assert (tp != NULL);
  1734. assert (ioaddr != NULL);
  1735. /* Update the error count. */
  1736. tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  1737. RTL_W32 (RxMissed, 0);
  1738. if ((status & RxUnderrun) && link_changed &&
  1739. (tp->drv_flags & HAS_LNK_CHNG)) {
  1740. rtl_check_media(dev, 0);
  1741. status &= ~RxUnderrun;
  1742. }
  1743. if (status & (RxUnderrun | RxErr))
  1744. tp->stats.rx_errors++;
  1745. if (status & PCSTimeout)
  1746. tp->stats.rx_length_errors++;
  1747. if (status & RxUnderrun)
  1748. tp->stats.rx_fifo_errors++;
  1749. if (status & PCIErr) {
  1750. u16 pci_cmd_status;
  1751. pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
  1752. pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
  1753. printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
  1754. dev->name, pci_cmd_status);
  1755. }
  1756. }
  1757. static int rtl8139_poll(struct net_device *dev, int *budget)
  1758. {
  1759. struct rtl8139_private *tp = netdev_priv(dev);
  1760. void __iomem *ioaddr = tp->mmio_addr;
  1761. int orig_budget = min(*budget, dev->quota);
  1762. int done = 1;
  1763. spin_lock(&tp->rx_lock);
  1764. if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
  1765. int work_done;
  1766. work_done = rtl8139_rx(dev, tp, orig_budget);
  1767. if (likely(work_done > 0)) {
  1768. *budget -= work_done;
  1769. dev->quota -= work_done;
  1770. done = (work_done < orig_budget);
  1771. }
  1772. }
  1773. if (done) {
  1774. unsigned long flags;
  1775. /*
  1776. * Order is important since data can get interrupted
  1777. * again when we think we are done.
  1778. */
  1779. local_irq_save(flags);
  1780. RTL_W16_F(IntrMask, rtl8139_intr_mask);
  1781. __netif_rx_complete(dev);
  1782. local_irq_restore(flags);
  1783. }
  1784. spin_unlock(&tp->rx_lock);
  1785. return !done;
  1786. }
  1787. /* The interrupt handler does all of the Rx thread work and cleans up
  1788. after the Tx thread. */
  1789. static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
  1790. {
  1791. struct net_device *dev = (struct net_device *) dev_instance;
  1792. struct rtl8139_private *tp = netdev_priv(dev);
  1793. void __iomem *ioaddr = tp->mmio_addr;
  1794. u16 status, ackstat;
  1795. int link_changed = 0; /* avoid bogus "uninit" warning */
  1796. int handled = 0;
  1797. spin_lock (&tp->lock);
  1798. status = RTL_R16 (IntrStatus);
  1799. /* shared irq? */
  1800. if (unlikely((status & rtl8139_intr_mask) == 0))
  1801. goto out;
  1802. handled = 1;
  1803. /* h/w no longer present (hotplug?) or major error, bail */
  1804. if (unlikely(status == 0xFFFF))
  1805. goto out;
  1806. /* close possible race's with dev_close */
  1807. if (unlikely(!netif_running(dev))) {
  1808. RTL_W16 (IntrMask, 0);
  1809. goto out;
  1810. }
  1811. /* Acknowledge all of the current interrupt sources ASAP, but
  1812. an first get an additional status bit from CSCR. */
  1813. if (unlikely(status & RxUnderrun))
  1814. link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
  1815. ackstat = status & ~(RxAckBits | TxErr);
  1816. if (ackstat)
  1817. RTL_W16 (IntrStatus, ackstat);
  1818. /* Receive packets are processed by poll routine.
  1819. If not running start it now. */
  1820. if (status & RxAckBits){
  1821. if (netif_rx_schedule_prep(dev)) {
  1822. RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
  1823. __netif_rx_schedule (dev);
  1824. }
  1825. }
  1826. /* Check uncommon events with one test. */
  1827. if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
  1828. rtl8139_weird_interrupt (dev, tp, ioaddr,
  1829. status, link_changed);
  1830. if (status & (TxOK | TxErr)) {
  1831. rtl8139_tx_interrupt (dev, tp, ioaddr);
  1832. if (status & TxErr)
  1833. RTL_W16 (IntrStatus, TxErr);
  1834. }
  1835. out:
  1836. spin_unlock (&tp->lock);
  1837. DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
  1838. dev->name, RTL_R16 (IntrStatus));
  1839. return IRQ_RETVAL(handled);
  1840. }
  1841. #ifdef CONFIG_NET_POLL_CONTROLLER
  1842. /*
  1843. * Polling receive - used by netconsole and other diagnostic tools
  1844. * to allow network i/o with interrupts disabled.
  1845. */
  1846. static void rtl8139_poll_controller(struct net_device *dev)
  1847. {
  1848. disable_irq(dev->irq);
  1849. rtl8139_interrupt(dev->irq, dev);
  1850. enable_irq(dev->irq);
  1851. }
  1852. #endif
  1853. static int rtl8139_close (struct net_device *dev)
  1854. {
  1855. struct rtl8139_private *tp = netdev_priv(dev);
  1856. void __iomem *ioaddr = tp->mmio_addr;
  1857. unsigned long flags;
  1858. netif_stop_queue (dev);
  1859. if (netif_msg_ifdown(tp))
  1860. printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
  1861. dev->name, RTL_R16 (IntrStatus));
  1862. spin_lock_irqsave (&tp->lock, flags);
  1863. /* Stop the chip's Tx and Rx DMA processes. */
  1864. RTL_W8 (ChipCmd, 0);
  1865. /* Disable interrupts by clearing the interrupt mask. */
  1866. RTL_W16 (IntrMask, 0);
  1867. /* Update the error counts. */
  1868. tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  1869. RTL_W32 (RxMissed, 0);
  1870. spin_unlock_irqrestore (&tp->lock, flags);
  1871. synchronize_irq (dev->irq); /* racy, but that's ok here */
  1872. free_irq (dev->irq, dev);
  1873. rtl8139_tx_clear (tp);
  1874. pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
  1875. tp->rx_ring, tp->rx_ring_dma);
  1876. pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
  1877. tp->tx_bufs, tp->tx_bufs_dma);
  1878. tp->rx_ring = NULL;
  1879. tp->tx_bufs = NULL;
  1880. /* Green! Put the chip in low-power mode. */
  1881. RTL_W8 (Cfg9346, Cfg9346_Unlock);
  1882. if (rtl_chip_info[tp->chipset].flags & HasHltClk)
  1883. RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
  1884. return 0;
  1885. }
  1886. /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
  1887. kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
  1888. other threads or interrupts aren't messing with the 8139. */
  1889. static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  1890. {
  1891. struct rtl8139_private *np = netdev_priv(dev);
  1892. void __iomem *ioaddr = np->mmio_addr;
  1893. spin_lock_irq(&np->lock);
  1894. if (rtl_chip_info[np->chipset].flags & HasLWake) {
  1895. u8 cfg3 = RTL_R8 (Config3);
  1896. u8 cfg5 = RTL_R8 (Config5);
  1897. wol->supported = WAKE_PHY | WAKE_MAGIC
  1898. | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
  1899. wol->wolopts = 0;
  1900. if (cfg3 & Cfg3_LinkUp)
  1901. wol->wolopts |= WAKE_PHY;
  1902. if (cfg3 & Cfg3_Magic)
  1903. wol->wolopts |= WAKE_MAGIC;
  1904. /* (KON)FIXME: See how netdev_set_wol() handles the
  1905. following constants. */
  1906. if (cfg5 & Cfg5_UWF)
  1907. wol->wolopts |= WAKE_UCAST;
  1908. if (cfg5 & Cfg5_MWF)
  1909. wol->wolopts |= WAKE_MCAST;
  1910. if (cfg5 & Cfg5_BWF)
  1911. wol->wolopts |= WAKE_BCAST;
  1912. }
  1913. spin_unlock_irq(&np->lock);
  1914. }
  1915. /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
  1916. that wol points to kernel memory and other threads or interrupts
  1917. aren't messing with the 8139. */
  1918. static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  1919. {
  1920. struct rtl8139_private *np = netdev_priv(dev);
  1921. void __iomem *ioaddr = np->mmio_addr;
  1922. u32 support;
  1923. u8 cfg3, cfg5;
  1924. support = ((rtl_chip_info[np->chipset].flags & HasLWake)
  1925. ? (WAKE_PHY | WAKE_MAGIC
  1926. | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
  1927. : 0);
  1928. if (wol->wolopts & ~support)
  1929. return -EINVAL;
  1930. spin_lock_irq(&np->lock);
  1931. cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
  1932. if (wol->wolopts & WAKE_PHY)
  1933. cfg3 |= Cfg3_LinkUp;
  1934. if (wol->wolopts & WAKE_MAGIC)
  1935. cfg3 |= Cfg3_Magic;
  1936. RTL_W8 (Cfg9346, Cfg9346_Unlock);
  1937. RTL_W8 (Config3, cfg3);
  1938. RTL_W8 (Cfg9346, Cfg9346_Lock);
  1939. cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
  1940. /* (KON)FIXME: These are untested. We may have to set the
  1941. CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
  1942. documentation. */
  1943. if (wol->wolopts & WAKE_UCAST)
  1944. cfg5 |= Cfg5_UWF;
  1945. if (wol->wolopts & WAKE_MCAST)
  1946. cfg5 |= Cfg5_MWF;
  1947. if (wol->wolopts & WAKE_BCAST)
  1948. cfg5 |= Cfg5_BWF;
  1949. RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
  1950. spin_unlock_irq(&np->lock);
  1951. return 0;
  1952. }
  1953. static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1954. {
  1955. struct rtl8139_private *np = netdev_priv(dev);
  1956. strcpy(info->driver, DRV_NAME);
  1957. strcpy(info->version, DRV_VERSION);
  1958. strcpy(info->bus_info, pci_name(np->pci_dev));
  1959. info->regdump_len = np->regs_len;
  1960. }
  1961. static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1962. {
  1963. struct rtl8139_private *np = netdev_priv(dev);
  1964. spin_lock_irq(&np->lock);
  1965. mii_ethtool_gset(&np->mii, cmd);
  1966. spin_unlock_irq(&np->lock);
  1967. return 0;
  1968. }
  1969. static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1970. {
  1971. struct rtl8139_private *np = netdev_priv(dev);
  1972. int rc;
  1973. spin_lock_irq(&np->lock);
  1974. rc = mii_ethtool_sset(&np->mii, cmd);
  1975. spin_unlock_irq(&np->lock);
  1976. return rc;
  1977. }
  1978. static int rtl8139_nway_reset(struct net_device *dev)
  1979. {
  1980. struct rtl8139_private *np = netdev_priv(dev);
  1981. return mii_nway_restart(&np->mii);
  1982. }
  1983. static u32 rtl8139_get_link(struct net_device *dev)
  1984. {
  1985. struct rtl8139_private *np = netdev_priv(dev);
  1986. return mii_link_ok(&np->mii);
  1987. }
  1988. static u32 rtl8139_get_msglevel(struct net_device *dev)
  1989. {
  1990. struct rtl8139_private *np = netdev_priv(dev);
  1991. return np->msg_enable;
  1992. }
  1993. static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
  1994. {
  1995. struct rtl8139_private *np = netdev_priv(dev);
  1996. np->msg_enable = datum;
  1997. }
  1998. /* TODO: we are too slack to do reg dumping for pio, for now */
  1999. #ifdef CONFIG_8139TOO_PIO
  2000. #define rtl8139_get_regs_len NULL
  2001. #define rtl8139_get_regs NULL
  2002. #else
  2003. static int rtl8139_get_regs_len(struct net_device *dev)
  2004. {
  2005. struct rtl8139_private *np = netdev_priv(dev);
  2006. return np->regs_len;
  2007. }
  2008. static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
  2009. {
  2010. struct rtl8139_private *np = netdev_priv(dev);
  2011. regs->version = RTL_REGS_VER;
  2012. spin_lock_irq(&np->lock);
  2013. memcpy_fromio(regbuf, np->mmio_addr, regs->len);
  2014. spin_unlock_irq(&np->lock);
  2015. }
  2016. #endif /* CONFIG_8139TOO_MMIO */
  2017. static int rtl8139_get_stats_count(struct net_device *dev)
  2018. {
  2019. return RTL_NUM_STATS;
  2020. }
  2021. static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
  2022. {
  2023. struct rtl8139_private *np = netdev_priv(dev);
  2024. data[0] = np->xstats.early_rx;
  2025. data[1] = np->xstats.tx_buf_mapped;
  2026. data[2] = np->xstats.tx_timeouts;
  2027. data[3] = np->xstats.rx_lost_in_ring;
  2028. }
  2029. static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  2030. {
  2031. memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
  2032. }
  2033. static const struct ethtool_ops rtl8139_ethtool_ops = {
  2034. .get_drvinfo = rtl8139_get_drvinfo,
  2035. .get_settings = rtl8139_get_settings,
  2036. .set_settings = rtl8139_set_settings,
  2037. .get_regs_len = rtl8139_get_regs_len,
  2038. .get_regs = rtl8139_get_regs,
  2039. .nway_reset = rtl8139_nway_reset,
  2040. .get_link = rtl8139_get_link,
  2041. .get_msglevel = rtl8139_get_msglevel,
  2042. .set_msglevel = rtl8139_set_msglevel,
  2043. .get_wol = rtl8139_get_wol,
  2044. .set_wol = rtl8139_set_wol,
  2045. .get_strings = rtl8139_get_strings,
  2046. .get_stats_count = rtl8139_get_stats_count,
  2047. .get_ethtool_stats = rtl8139_get_ethtool_stats,
  2048. .get_perm_addr = ethtool_op_get_perm_addr,
  2049. };
  2050. static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  2051. {
  2052. struct rtl8139_private *np = netdev_priv(dev);
  2053. int rc;
  2054. if (!netif_running(dev))
  2055. return -EINVAL;
  2056. spin_lock_irq(&np->lock);
  2057. rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
  2058. spin_unlock_irq(&np->lock);
  2059. return rc;
  2060. }
  2061. static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
  2062. {
  2063. struct rtl8139_private *tp = netdev_priv(dev);
  2064. void __iomem *ioaddr = tp->mmio_addr;
  2065. unsigned long flags;
  2066. if (netif_running(dev)) {
  2067. spin_lock_irqsave (&tp->lock, flags);
  2068. tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  2069. RTL_W32 (RxMissed, 0);
  2070. spin_unlock_irqrestore (&tp->lock, flags);
  2071. }
  2072. return &tp->stats;
  2073. }
  2074. /* Set or clear the multicast filter for this adaptor.
  2075. This routine is not state sensitive and need not be SMP locked. */
  2076. static void __set_rx_mode (struct net_device *dev)
  2077. {
  2078. struct rtl8139_private *tp = netdev_priv(dev);
  2079. void __iomem *ioaddr = tp->mmio_addr;
  2080. u32 mc_filter[2]; /* Multicast hash filter */
  2081. int i, rx_mode;
  2082. u32 tmp;
  2083. DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
  2084. dev->name, dev->flags, RTL_R32 (RxConfig));
  2085. /* Note: do not reorder, GCC is clever about common statements. */
  2086. if (dev->flags & IFF_PROMISC) {
  2087. rx_mode =
  2088. AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
  2089. AcceptAllPhys;
  2090. mc_filter[1] = mc_filter[0] = 0xffffffff;
  2091. } else if ((dev->mc_count > multicast_filter_limit)
  2092. || (dev->flags & IFF_ALLMULTI)) {
  2093. /* Too many to filter perfectly -- accept all multicasts. */
  2094. rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  2095. mc_filter[1] = mc_filter[0] = 0xffffffff;
  2096. } else {
  2097. struct dev_mc_list *mclist;
  2098. rx_mode = AcceptBroadcast | AcceptMyPhys;
  2099. mc_filter[1] = mc_filter[0] = 0;
  2100. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  2101. i++, mclist = mclist->next) {
  2102. int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
  2103. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  2104. rx_mode |= AcceptMulticast;
  2105. }
  2106. }
  2107. /* We can safely update without stopping the chip. */
  2108. tmp = rtl8139_rx_config | rx_mode;
  2109. if (tp->rx_config != tmp) {
  2110. RTL_W32_F (RxConfig, tmp);
  2111. tp->rx_config = tmp;
  2112. }
  2113. RTL_W32_F (MAR0 + 0, mc_filter[0]);
  2114. RTL_W32_F (MAR0 + 4, mc_filter[1]);
  2115. }
  2116. static void rtl8139_set_rx_mode (struct net_device *dev)
  2117. {
  2118. unsigned long flags;
  2119. struct rtl8139_private *tp = netdev_priv(dev);
  2120. spin_lock_irqsave (&tp->lock, flags);
  2121. __set_rx_mode(dev);
  2122. spin_unlock_irqrestore (&tp->lock, flags);
  2123. }
  2124. #ifdef CONFIG_PM
  2125. static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
  2126. {
  2127. struct net_device *dev = pci_get_drvdata (pdev);
  2128. struct rtl8139_private *tp = netdev_priv(dev);
  2129. void __iomem *ioaddr = tp->mmio_addr;
  2130. unsigned long flags;
  2131. pci_save_state (pdev);
  2132. if (!netif_running (dev))
  2133. return 0;
  2134. netif_device_detach (dev);
  2135. spin_lock_irqsave (&tp->lock, flags);
  2136. /* Disable interrupts, stop Tx and Rx. */
  2137. RTL_W16 (IntrMask, 0);
  2138. RTL_W8 (ChipCmd, 0);
  2139. /* Update the error counts. */
  2140. tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  2141. RTL_W32 (RxMissed, 0);
  2142. spin_unlock_irqrestore (&tp->lock, flags);
  2143. pci_set_power_state (pdev, PCI_D3hot);
  2144. return 0;
  2145. }
  2146. static int rtl8139_resume (struct pci_dev *pdev)
  2147. {
  2148. struct net_device *dev = pci_get_drvdata (pdev);
  2149. pci_restore_state (pdev);
  2150. if (!netif_running (dev))
  2151. return 0;
  2152. pci_set_power_state (pdev, PCI_D0);
  2153. rtl8139_init_ring (dev);
  2154. rtl8139_hw_start (dev);
  2155. netif_device_attach (dev);
  2156. return 0;
  2157. }
  2158. #endif /* CONFIG_PM */
  2159. static struct pci_driver rtl8139_pci_driver = {
  2160. .name = DRV_NAME,
  2161. .id_table = rtl8139_pci_tbl,
  2162. .probe = rtl8139_init_one,
  2163. .remove = __devexit_p(rtl8139_remove_one),
  2164. #ifdef CONFIG_PM
  2165. .suspend = rtl8139_suspend,
  2166. .resume = rtl8139_resume,
  2167. #endif /* CONFIG_PM */
  2168. };
  2169. static int __init rtl8139_init_module (void)
  2170. {
  2171. /* when we're a module, we always print a version message,
  2172. * even if no 8139 board is found.
  2173. */
  2174. #ifdef MODULE
  2175. printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
  2176. #endif
  2177. return pci_register_driver(&rtl8139_pci_driver);
  2178. }
  2179. static void __exit rtl8139_cleanup_module (void)
  2180. {
  2181. pci_unregister_driver (&rtl8139_pci_driver);
  2182. }
  2183. module_init(rtl8139_init_module);
  2184. module_exit(rtl8139_cleanup_module);