7990.c 22 KB

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  1. /*
  2. * 7990.c -- LANCE ethernet IC generic routines.
  3. * This is an attempt to separate out the bits of various ethernet
  4. * drivers that are common because they all use the AMD 7990 LANCE
  5. * (Local Area Network Controller for Ethernet) chip.
  6. *
  7. * Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk>
  8. *
  9. * Most of this stuff was obtained by looking at other LANCE drivers,
  10. * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
  11. * NB: this was made easy by the fact that Jes Sorensen had cleaned up
  12. * most of a2025 and sunlance with the aim of merging them, so the
  13. * common code was pretty obvious.
  14. */
  15. #include <linux/crc32.h>
  16. #include <linux/delay.h>
  17. #include <linux/errno.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/etherdevice.h>
  20. #include <linux/init.h>
  21. #include <linux/module.h>
  22. #include <linux/kernel.h>
  23. #include <linux/types.h>
  24. #include <linux/fcntl.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/ioport.h>
  27. #include <linux/in.h>
  28. #include <linux/route.h>
  29. #include <linux/slab.h>
  30. #include <linux/string.h>
  31. #include <linux/skbuff.h>
  32. #include <asm/irq.h>
  33. /* Used for the temporal inet entries and routing */
  34. #include <linux/socket.h>
  35. #include <linux/bitops.h>
  36. #include <asm/system.h>
  37. #include <asm/io.h>
  38. #include <asm/dma.h>
  39. #include <asm/pgtable.h>
  40. #ifdef CONFIG_HP300
  41. #include <asm/blinken.h>
  42. #endif
  43. #include "7990.h"
  44. #define WRITERAP(lp,x) out_be16(lp->base + LANCE_RAP, (x))
  45. #define WRITERDP(lp,x) out_be16(lp->base + LANCE_RDP, (x))
  46. #define READRDP(lp) in_be16(lp->base + LANCE_RDP)
  47. #if defined(CONFIG_HPLANCE) || defined(CONFIG_HPLANCE_MODULE)
  48. #include "hplance.h"
  49. #undef WRITERAP
  50. #undef WRITERDP
  51. #undef READRDP
  52. #if defined(CONFIG_MVME147_NET) || defined(CONFIG_MVME147_NET_MODULE)
  53. /* Lossage Factor Nine, Mr Sulu. */
  54. #define WRITERAP(lp,x) (lp->writerap(lp,x))
  55. #define WRITERDP(lp,x) (lp->writerdp(lp,x))
  56. #define READRDP(lp) (lp->readrdp(lp))
  57. #else
  58. /* These inlines can be used if only CONFIG_HPLANCE is defined */
  59. static inline void WRITERAP(struct lance_private *lp, __u16 value)
  60. {
  61. do {
  62. out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value);
  63. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  64. }
  65. static inline void WRITERDP(struct lance_private *lp, __u16 value)
  66. {
  67. do {
  68. out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value);
  69. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  70. }
  71. static inline __u16 READRDP(struct lance_private *lp)
  72. {
  73. __u16 value;
  74. do {
  75. value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP);
  76. } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
  77. return value;
  78. }
  79. #endif
  80. #endif /* CONFIG_HPLANCE || CONFIG_HPLANCE_MODULE */
  81. /* debugging output macros, various flavours */
  82. /* #define TEST_HITS */
  83. #ifdef UNDEF
  84. #define PRINT_RINGS() \
  85. do { \
  86. int t; \
  87. for (t=0; t < RX_RING_SIZE; t++) { \
  88. printk("R%d: @(%02X %04X) len %04X, mblen %04X, bits %02X\n",\
  89. t, ib->brx_ring[t].rmd1_hadr, ib->brx_ring[t].rmd0,\
  90. ib->brx_ring[t].length,\
  91. ib->brx_ring[t].mblength, ib->brx_ring[t].rmd1_bits);\
  92. }\
  93. for (t=0; t < TX_RING_SIZE; t++) { \
  94. printk("T%d: @(%02X %04X) len %04X, misc %04X, bits %02X\n",\
  95. t, ib->btx_ring[t].tmd1_hadr, ib->btx_ring[t].tmd0,\
  96. ib->btx_ring[t].length,\
  97. ib->btx_ring[t].misc, ib->btx_ring[t].tmd1_bits);\
  98. }\
  99. } while (0)
  100. #else
  101. #define PRINT_RINGS()
  102. #endif
  103. /* Load the CSR registers. The LANCE has to be STOPped when we do this! */
  104. static void load_csrs (struct lance_private *lp)
  105. {
  106. volatile struct lance_init_block *aib = lp->lance_init_block;
  107. int leptr;
  108. leptr = LANCE_ADDR (aib);
  109. WRITERAP(lp, LE_CSR1); /* load address of init block */
  110. WRITERDP(lp, leptr & 0xFFFF);
  111. WRITERAP(lp, LE_CSR2);
  112. WRITERDP(lp, leptr >> 16);
  113. WRITERAP(lp, LE_CSR3);
  114. WRITERDP(lp, lp->busmaster_regval); /* set byteswap/ALEctrl/byte ctrl */
  115. /* Point back to csr0 */
  116. WRITERAP(lp, LE_CSR0);
  117. }
  118. /* #define to 0 or 1 appropriately */
  119. #define DEBUG_IRING 0
  120. /* Set up the Lance Rx and Tx rings and the init block */
  121. static void lance_init_ring (struct net_device *dev)
  122. {
  123. struct lance_private *lp = netdev_priv(dev);
  124. volatile struct lance_init_block *ib = lp->init_block;
  125. volatile struct lance_init_block *aib; /* for LANCE_ADDR computations */
  126. int leptr;
  127. int i;
  128. aib = lp->lance_init_block;
  129. lp->rx_new = lp->tx_new = 0;
  130. lp->rx_old = lp->tx_old = 0;
  131. ib->mode = LE_MO_PROM; /* normal, enable Tx & Rx */
  132. /* Copy the ethernet address to the lance init block
  133. * Notice that we do a byteswap if we're big endian.
  134. * [I think this is the right criterion; at least, sunlance,
  135. * a2065 and atarilance do the byteswap and lance.c (PC) doesn't.
  136. * However, the datasheet says that the BSWAP bit doesn't affect
  137. * the init block, so surely it should be low byte first for
  138. * everybody? Um.]
  139. * We could define the ib->physaddr as three 16bit values and
  140. * use (addr[1] << 8) | addr[0] & co, but this is more efficient.
  141. */
  142. #ifdef __BIG_ENDIAN
  143. ib->phys_addr [0] = dev->dev_addr [1];
  144. ib->phys_addr [1] = dev->dev_addr [0];
  145. ib->phys_addr [2] = dev->dev_addr [3];
  146. ib->phys_addr [3] = dev->dev_addr [2];
  147. ib->phys_addr [4] = dev->dev_addr [5];
  148. ib->phys_addr [5] = dev->dev_addr [4];
  149. #else
  150. for (i=0; i<6; i++)
  151. ib->phys_addr[i] = dev->dev_addr[i];
  152. #endif
  153. if (DEBUG_IRING)
  154. printk ("TX rings:\n");
  155. lp->tx_full = 0;
  156. /* Setup the Tx ring entries */
  157. for (i = 0; i < (1<<lp->lance_log_tx_bufs); i++) {
  158. leptr = LANCE_ADDR(&aib->tx_buf[i][0]);
  159. ib->btx_ring [i].tmd0 = leptr;
  160. ib->btx_ring [i].tmd1_hadr = leptr >> 16;
  161. ib->btx_ring [i].tmd1_bits = 0;
  162. ib->btx_ring [i].length = 0xf000; /* The ones required by tmd2 */
  163. ib->btx_ring [i].misc = 0;
  164. if (DEBUG_IRING)
  165. printk ("%d: 0x%8.8x\n", i, leptr);
  166. }
  167. /* Setup the Rx ring entries */
  168. if (DEBUG_IRING)
  169. printk ("RX rings:\n");
  170. for (i = 0; i < (1<<lp->lance_log_rx_bufs); i++) {
  171. leptr = LANCE_ADDR(&aib->rx_buf[i][0]);
  172. ib->brx_ring [i].rmd0 = leptr;
  173. ib->brx_ring [i].rmd1_hadr = leptr >> 16;
  174. ib->brx_ring [i].rmd1_bits = LE_R1_OWN;
  175. /* 0xf000 == bits that must be one (reserved, presumably) */
  176. ib->brx_ring [i].length = -RX_BUFF_SIZE | 0xf000;
  177. ib->brx_ring [i].mblength = 0;
  178. if (DEBUG_IRING)
  179. printk ("%d: 0x%8.8x\n", i, leptr);
  180. }
  181. /* Setup the initialization block */
  182. /* Setup rx descriptor pointer */
  183. leptr = LANCE_ADDR(&aib->brx_ring);
  184. ib->rx_len = (lp->lance_log_rx_bufs << 13) | (leptr >> 16);
  185. ib->rx_ptr = leptr;
  186. if (DEBUG_IRING)
  187. printk ("RX ptr: %8.8x\n", leptr);
  188. /* Setup tx descriptor pointer */
  189. leptr = LANCE_ADDR(&aib->btx_ring);
  190. ib->tx_len = (lp->lance_log_tx_bufs << 13) | (leptr >> 16);
  191. ib->tx_ptr = leptr;
  192. if (DEBUG_IRING)
  193. printk ("TX ptr: %8.8x\n", leptr);
  194. /* Clear the multicast filter */
  195. ib->filter [0] = 0;
  196. ib->filter [1] = 0;
  197. PRINT_RINGS();
  198. }
  199. /* LANCE must be STOPped before we do this, too... */
  200. static int init_restart_lance (struct lance_private *lp)
  201. {
  202. int i;
  203. WRITERAP(lp, LE_CSR0);
  204. WRITERDP(lp, LE_C0_INIT);
  205. /* Need a hook here for sunlance ledma stuff */
  206. /* Wait for the lance to complete initialization */
  207. for (i = 0; (i < 100) && !(READRDP(lp) & (LE_C0_ERR | LE_C0_IDON)); i++)
  208. barrier();
  209. if ((i == 100) || (READRDP(lp) & LE_C0_ERR)) {
  210. printk ("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp));
  211. return -1;
  212. }
  213. /* Clear IDON by writing a "1", enable interrupts and start lance */
  214. WRITERDP(lp, LE_C0_IDON);
  215. WRITERDP(lp, LE_C0_INEA | LE_C0_STRT);
  216. return 0;
  217. }
  218. static int lance_reset (struct net_device *dev)
  219. {
  220. struct lance_private *lp = netdev_priv(dev);
  221. int status;
  222. /* Stop the lance */
  223. WRITERAP(lp, LE_CSR0);
  224. WRITERDP(lp, LE_C0_STOP);
  225. load_csrs (lp);
  226. lance_init_ring (dev);
  227. dev->trans_start = jiffies;
  228. status = init_restart_lance (lp);
  229. #ifdef DEBUG_DRIVER
  230. printk ("Lance restart=%d\n", status);
  231. #endif
  232. return status;
  233. }
  234. static int lance_rx (struct net_device *dev)
  235. {
  236. struct lance_private *lp = netdev_priv(dev);
  237. volatile struct lance_init_block *ib = lp->init_block;
  238. volatile struct lance_rx_desc *rd;
  239. unsigned char bits;
  240. int len = 0; /* XXX shut up gcc warnings */
  241. struct sk_buff *skb = 0; /* XXX shut up gcc warnings */
  242. #ifdef TEST_HITS
  243. int i;
  244. #endif
  245. #ifdef TEST_HITS
  246. printk ("[");
  247. for (i = 0; i < RX_RING_SIZE; i++) {
  248. if (i == lp->rx_new)
  249. printk ("%s",
  250. ib->brx_ring [i].rmd1_bits & LE_R1_OWN ? "_" : "X");
  251. else
  252. printk ("%s",
  253. ib->brx_ring [i].rmd1_bits & LE_R1_OWN ? "." : "1");
  254. }
  255. printk ("]");
  256. #endif
  257. #ifdef CONFIG_HP300
  258. blinken_leds(0x40, 0);
  259. #endif
  260. WRITERDP(lp, LE_C0_RINT | LE_C0_INEA); /* ack Rx int, reenable ints */
  261. for (rd = &ib->brx_ring [lp->rx_new]; /* For each Rx ring we own... */
  262. !((bits = rd->rmd1_bits) & LE_R1_OWN);
  263. rd = &ib->brx_ring [lp->rx_new]) {
  264. /* We got an incomplete frame? */
  265. if ((bits & LE_R1_POK) != LE_R1_POK) {
  266. lp->stats.rx_over_errors++;
  267. lp->stats.rx_errors++;
  268. continue;
  269. } else if (bits & LE_R1_ERR) {
  270. /* Count only the end frame as a rx error,
  271. * not the beginning
  272. */
  273. if (bits & LE_R1_BUF) lp->stats.rx_fifo_errors++;
  274. if (bits & LE_R1_CRC) lp->stats.rx_crc_errors++;
  275. if (bits & LE_R1_OFL) lp->stats.rx_over_errors++;
  276. if (bits & LE_R1_FRA) lp->stats.rx_frame_errors++;
  277. if (bits & LE_R1_EOP) lp->stats.rx_errors++;
  278. } else {
  279. len = (rd->mblength & 0xfff) - 4;
  280. skb = dev_alloc_skb (len+2);
  281. if (skb == 0) {
  282. printk ("%s: Memory squeeze, deferring packet.\n",
  283. dev->name);
  284. lp->stats.rx_dropped++;
  285. rd->mblength = 0;
  286. rd->rmd1_bits = LE_R1_OWN;
  287. lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
  288. return 0;
  289. }
  290. skb->dev = dev;
  291. skb_reserve (skb, 2); /* 16 byte align */
  292. skb_put (skb, len); /* make room */
  293. eth_copy_and_sum(skb,
  294. (unsigned char *)&(ib->rx_buf [lp->rx_new][0]),
  295. len, 0);
  296. skb->protocol = eth_type_trans (skb, dev);
  297. netif_rx (skb);
  298. dev->last_rx = jiffies;
  299. lp->stats.rx_packets++;
  300. lp->stats.rx_bytes += len;
  301. }
  302. /* Return the packet to the pool */
  303. rd->mblength = 0;
  304. rd->rmd1_bits = LE_R1_OWN;
  305. lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
  306. }
  307. return 0;
  308. }
  309. static int lance_tx (struct net_device *dev)
  310. {
  311. struct lance_private *lp = netdev_priv(dev);
  312. volatile struct lance_init_block *ib = lp->init_block;
  313. volatile struct lance_tx_desc *td;
  314. int i, j;
  315. int status;
  316. #ifdef CONFIG_HP300
  317. blinken_leds(0x80, 0);
  318. #endif
  319. /* csr0 is 2f3 */
  320. WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
  321. /* csr0 is 73 */
  322. j = lp->tx_old;
  323. for (i = j; i != lp->tx_new; i = j) {
  324. td = &ib->btx_ring [i];
  325. /* If we hit a packet not owned by us, stop */
  326. if (td->tmd1_bits & LE_T1_OWN)
  327. break;
  328. if (td->tmd1_bits & LE_T1_ERR) {
  329. status = td->misc;
  330. lp->stats.tx_errors++;
  331. if (status & LE_T3_RTY) lp->stats.tx_aborted_errors++;
  332. if (status & LE_T3_LCOL) lp->stats.tx_window_errors++;
  333. if (status & LE_T3_CLOS) {
  334. lp->stats.tx_carrier_errors++;
  335. if (lp->auto_select) {
  336. lp->tpe = 1 - lp->tpe;
  337. printk("%s: Carrier Lost, trying %s\n",
  338. dev->name, lp->tpe?"TPE":"AUI");
  339. /* Stop the lance */
  340. WRITERAP(lp, LE_CSR0);
  341. WRITERDP(lp, LE_C0_STOP);
  342. lance_init_ring (dev);
  343. load_csrs (lp);
  344. init_restart_lance (lp);
  345. return 0;
  346. }
  347. }
  348. /* buffer errors and underflows turn off the transmitter */
  349. /* Restart the adapter */
  350. if (status & (LE_T3_BUF|LE_T3_UFL)) {
  351. lp->stats.tx_fifo_errors++;
  352. printk ("%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
  353. dev->name);
  354. /* Stop the lance */
  355. WRITERAP(lp, LE_CSR0);
  356. WRITERDP(lp, LE_C0_STOP);
  357. lance_init_ring (dev);
  358. load_csrs (lp);
  359. init_restart_lance (lp);
  360. return 0;
  361. }
  362. } else if ((td->tmd1_bits & LE_T1_POK) == LE_T1_POK) {
  363. /*
  364. * So we don't count the packet more than once.
  365. */
  366. td->tmd1_bits &= ~(LE_T1_POK);
  367. /* One collision before packet was sent. */
  368. if (td->tmd1_bits & LE_T1_EONE)
  369. lp->stats.collisions++;
  370. /* More than one collision, be optimistic. */
  371. if (td->tmd1_bits & LE_T1_EMORE)
  372. lp->stats.collisions += 2;
  373. lp->stats.tx_packets++;
  374. }
  375. j = (j + 1) & lp->tx_ring_mod_mask;
  376. }
  377. lp->tx_old = j;
  378. WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
  379. return 0;
  380. }
  381. static irqreturn_t
  382. lance_interrupt (int irq, void *dev_id)
  383. {
  384. struct net_device *dev = (struct net_device *)dev_id;
  385. struct lance_private *lp = netdev_priv(dev);
  386. int csr0;
  387. spin_lock (&lp->devlock);
  388. WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */
  389. csr0 = READRDP(lp);
  390. PRINT_RINGS();
  391. if (!(csr0 & LE_C0_INTR)) { /* Check if any interrupt has */
  392. spin_unlock (&lp->devlock);
  393. return IRQ_NONE; /* been generated by the Lance. */
  394. }
  395. /* Acknowledge all the interrupt sources ASAP */
  396. WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT));
  397. if ((csr0 & LE_C0_ERR)) {
  398. /* Clear the error condition */
  399. WRITERDP(lp, LE_C0_BABL|LE_C0_ERR|LE_C0_MISS|LE_C0_INEA);
  400. }
  401. if (csr0 & LE_C0_RINT)
  402. lance_rx (dev);
  403. if (csr0 & LE_C0_TINT)
  404. lance_tx (dev);
  405. /* Log misc errors. */
  406. if (csr0 & LE_C0_BABL)
  407. lp->stats.tx_errors++; /* Tx babble. */
  408. if (csr0 & LE_C0_MISS)
  409. lp->stats.rx_errors++; /* Missed a Rx frame. */
  410. if (csr0 & LE_C0_MERR) {
  411. printk("%s: Bus master arbitration failure, status %4.4x.\n",
  412. dev->name, csr0);
  413. /* Restart the chip. */
  414. WRITERDP(lp, LE_C0_STRT);
  415. }
  416. if (lp->tx_full && netif_queue_stopped(dev) && (TX_BUFFS_AVAIL >= 0)) {
  417. lp->tx_full = 0;
  418. netif_wake_queue (dev);
  419. }
  420. WRITERAP(lp, LE_CSR0);
  421. WRITERDP(lp, LE_C0_BABL|LE_C0_CERR|LE_C0_MISS|LE_C0_MERR|LE_C0_IDON|LE_C0_INEA);
  422. spin_unlock (&lp->devlock);
  423. return IRQ_HANDLED;
  424. }
  425. int lance_open (struct net_device *dev)
  426. {
  427. struct lance_private *lp = netdev_priv(dev);
  428. int res;
  429. /* Install the Interrupt handler. Or we could shunt this out to specific drivers? */
  430. if (request_irq(lp->irq, lance_interrupt, IRQF_SHARED, lp->name, dev))
  431. return -EAGAIN;
  432. res = lance_reset(dev);
  433. spin_lock_init(&lp->devlock);
  434. netif_start_queue (dev);
  435. return res;
  436. }
  437. int lance_close (struct net_device *dev)
  438. {
  439. struct lance_private *lp = netdev_priv(dev);
  440. netif_stop_queue (dev);
  441. /* Stop the LANCE */
  442. WRITERAP(lp, LE_CSR0);
  443. WRITERDP(lp, LE_C0_STOP);
  444. free_irq(lp->irq, dev);
  445. return 0;
  446. }
  447. void lance_tx_timeout(struct net_device *dev)
  448. {
  449. printk("lance_tx_timeout\n");
  450. lance_reset(dev);
  451. dev->trans_start = jiffies;
  452. netif_wake_queue (dev);
  453. }
  454. int lance_start_xmit (struct sk_buff *skb, struct net_device *dev)
  455. {
  456. struct lance_private *lp = netdev_priv(dev);
  457. volatile struct lance_init_block *ib = lp->init_block;
  458. int entry, skblen, len;
  459. static int outs;
  460. unsigned long flags;
  461. if (!TX_BUFFS_AVAIL)
  462. return -1;
  463. netif_stop_queue (dev);
  464. skblen = skb->len;
  465. #ifdef DEBUG_DRIVER
  466. /* dump the packet */
  467. {
  468. int i;
  469. for (i = 0; i < 64; i++) {
  470. if ((i % 16) == 0)
  471. printk ("\n");
  472. printk ("%2.2x ", skb->data [i]);
  473. }
  474. }
  475. #endif
  476. len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen;
  477. entry = lp->tx_new & lp->tx_ring_mod_mask;
  478. ib->btx_ring [entry].length = (-len) | 0xf000;
  479. ib->btx_ring [entry].misc = 0;
  480. if (skb->len < ETH_ZLEN)
  481. memset((char *)&ib->tx_buf[entry][0], 0, ETH_ZLEN);
  482. memcpy ((char *)&ib->tx_buf [entry][0], skb->data, skblen);
  483. /* Now, give the packet to the lance */
  484. ib->btx_ring [entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN);
  485. lp->tx_new = (lp->tx_new+1) & lp->tx_ring_mod_mask;
  486. outs++;
  487. /* Kick the lance: transmit now */
  488. WRITERDP(lp, LE_C0_INEA | LE_C0_TDMD);
  489. dev->trans_start = jiffies;
  490. dev_kfree_skb (skb);
  491. spin_lock_irqsave (&lp->devlock, flags);
  492. if (TX_BUFFS_AVAIL)
  493. netif_start_queue (dev);
  494. else
  495. lp->tx_full = 1;
  496. spin_unlock_irqrestore (&lp->devlock, flags);
  497. return 0;
  498. }
  499. struct net_device_stats *lance_get_stats (struct net_device *dev)
  500. {
  501. struct lance_private *lp = netdev_priv(dev);
  502. return &lp->stats;
  503. }
  504. /* taken from the depca driver via a2065.c */
  505. static void lance_load_multicast (struct net_device *dev)
  506. {
  507. struct lance_private *lp = netdev_priv(dev);
  508. volatile struct lance_init_block *ib = lp->init_block;
  509. volatile u16 *mcast_table = (u16 *)&ib->filter;
  510. struct dev_mc_list *dmi=dev->mc_list;
  511. char *addrs;
  512. int i;
  513. u32 crc;
  514. /* set all multicast bits */
  515. if (dev->flags & IFF_ALLMULTI){
  516. ib->filter [0] = 0xffffffff;
  517. ib->filter [1] = 0xffffffff;
  518. return;
  519. }
  520. /* clear the multicast filter */
  521. ib->filter [0] = 0;
  522. ib->filter [1] = 0;
  523. /* Add addresses */
  524. for (i = 0; i < dev->mc_count; i++){
  525. addrs = dmi->dmi_addr;
  526. dmi = dmi->next;
  527. /* multicast address? */
  528. if (!(*addrs & 1))
  529. continue;
  530. crc = ether_crc_le(6, addrs);
  531. crc = crc >> 26;
  532. mcast_table [crc >> 4] |= 1 << (crc & 0xf);
  533. }
  534. return;
  535. }
  536. void lance_set_multicast (struct net_device *dev)
  537. {
  538. struct lance_private *lp = netdev_priv(dev);
  539. volatile struct lance_init_block *ib = lp->init_block;
  540. int stopped;
  541. stopped = netif_queue_stopped(dev);
  542. if (!stopped)
  543. netif_stop_queue (dev);
  544. while (lp->tx_old != lp->tx_new)
  545. schedule();
  546. WRITERAP(lp, LE_CSR0);
  547. WRITERDP(lp, LE_C0_STOP);
  548. lance_init_ring (dev);
  549. if (dev->flags & IFF_PROMISC) {
  550. ib->mode |= LE_MO_PROM;
  551. } else {
  552. ib->mode &= ~LE_MO_PROM;
  553. lance_load_multicast (dev);
  554. }
  555. load_csrs (lp);
  556. init_restart_lance (lp);
  557. if (!stopped)
  558. netif_start_queue (dev);
  559. }
  560. #ifdef CONFIG_NET_POLL_CONTROLLER
  561. void lance_poll(struct net_device *dev)
  562. {
  563. struct lance_private *lp = netdev_priv(dev);
  564. spin_lock (&lp->devlock);
  565. WRITERAP(lp, LE_CSR0);
  566. WRITERDP(lp, LE_C0_STRT);
  567. spin_unlock (&lp->devlock);
  568. lance_interrupt(dev->irq, dev);
  569. }
  570. #endif
  571. MODULE_LICENSE("GPL");