3c523.h 11 KB

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  1. #ifndef _3c523_INCLUDE_
  2. #define _3c523_INCLUDE_
  3. /*
  4. This is basically a hacked version of ni52.h, for the 3c523
  5. Etherlink/MC.
  6. */
  7. /*
  8. * Intel i82586 Ethernet definitions
  9. *
  10. * This is an extension to the Linux operating system, and is covered by the
  11. * same GNU General Public License that covers that work.
  12. *
  13. * Copyright 1995 by Chris Beauregard (cpbeaure@undergrad.math.uwaterloo.ca)
  14. *
  15. * See 3c523.c for details.
  16. *
  17. * $Header: /home/cvs/s3c-linux-2.6.21/drivers/net/3c523.h,v 1.1.1.1 2007/06/12 07:27:10 eyryu Exp $
  18. */
  19. /*
  20. * where to find the System Configuration Pointer (SCP)
  21. */
  22. #define SCP_DEFAULT_ADDRESS 0xfffff4
  23. /*
  24. * System Configuration Pointer Struct
  25. */
  26. struct scp_struct
  27. {
  28. unsigned short zero_dum0; /* has to be zero */
  29. unsigned char sysbus; /* 0=16Bit,1=8Bit */
  30. unsigned char zero_dum1; /* has to be zero for 586 */
  31. unsigned short zero_dum2;
  32. unsigned short zero_dum3;
  33. char *iscp; /* pointer to the iscp-block */
  34. };
  35. /*
  36. * Intermediate System Configuration Pointer (ISCP)
  37. */
  38. struct iscp_struct
  39. {
  40. unsigned char busy; /* 586 clears after successful init */
  41. unsigned char zero_dummy; /* hast to be zero */
  42. unsigned short scb_offset; /* pointeroffset to the scb_base */
  43. char *scb_base; /* base-address of all 16-bit offsets */
  44. };
  45. /*
  46. * System Control Block (SCB)
  47. */
  48. struct scb_struct
  49. {
  50. unsigned short status; /* status word */
  51. unsigned short cmd; /* command word */
  52. unsigned short cbl_offset; /* pointeroffset, command block list */
  53. unsigned short rfa_offset; /* pointeroffset, receive frame area */
  54. unsigned short crc_errs; /* CRC-Error counter */
  55. unsigned short aln_errs; /* alignmenterror counter */
  56. unsigned short rsc_errs; /* Resourceerror counter */
  57. unsigned short ovrn_errs; /* OVerrunerror counter */
  58. };
  59. /*
  60. * possible command values for the command word
  61. */
  62. #define RUC_MASK 0x0070 /* mask for RU commands */
  63. #define RUC_NOP 0x0000 /* NOP-command */
  64. #define RUC_START 0x0010 /* start RU */
  65. #define RUC_RESUME 0x0020 /* resume RU after suspend */
  66. #define RUC_SUSPEND 0x0030 /* suspend RU */
  67. #define RUC_ABORT 0x0040 /* abort receiver operation immediately */
  68. #define CUC_MASK 0x0700 /* mask for CU command */
  69. #define CUC_NOP 0x0000 /* NOP-command */
  70. #define CUC_START 0x0100 /* start execution of 1. cmd on the CBL */
  71. #define CUC_RESUME 0x0200 /* resume after suspend */
  72. #define CUC_SUSPEND 0x0300 /* Suspend CU */
  73. #define CUC_ABORT 0x0400 /* abort command operation immediately */
  74. #define ACK_MASK 0xf000 /* mask for ACK command */
  75. #define ACK_CX 0x8000 /* acknowledges STAT_CX */
  76. #define ACK_FR 0x4000 /* ack. STAT_FR */
  77. #define ACK_CNA 0x2000 /* ack. STAT_CNA */
  78. #define ACK_RNR 0x1000 /* ack. STAT_RNR */
  79. /*
  80. * possible status values for the status word
  81. */
  82. #define STAT_MASK 0xf000 /* mask for cause of interrupt */
  83. #define STAT_CX 0x8000 /* CU finished cmd with its I bit set */
  84. #define STAT_FR 0x4000 /* RU finished receiving a frame */
  85. #define STAT_CNA 0x2000 /* CU left active state */
  86. #define STAT_RNR 0x1000 /* RU left ready state */
  87. #define CU_STATUS 0x700 /* CU status, 0=idle */
  88. #define CU_SUSPEND 0x100 /* CU is suspended */
  89. #define CU_ACTIVE 0x200 /* CU is active */
  90. #define RU_STATUS 0x70 /* RU status, 0=idle */
  91. #define RU_SUSPEND 0x10 /* RU suspended */
  92. #define RU_NOSPACE 0x20 /* RU no resources */
  93. #define RU_READY 0x40 /* RU is ready */
  94. /*
  95. * Receive Frame Descriptor (RFD)
  96. */
  97. struct rfd_struct
  98. {
  99. unsigned short status; /* status word */
  100. unsigned short last; /* Bit15,Last Frame on List / Bit14,suspend */
  101. unsigned short next; /* linkoffset to next RFD */
  102. unsigned short rbd_offset; /* pointeroffset to RBD-buffer */
  103. unsigned char dest[6]; /* ethernet-address, destination */
  104. unsigned char source[6]; /* ethernet-address, source */
  105. unsigned short length; /* 802.3 frame-length */
  106. unsigned short zero_dummy; /* dummy */
  107. };
  108. #define RFD_LAST 0x8000 /* last: last rfd in the list */
  109. #define RFD_SUSP 0x4000 /* last: suspend RU after */
  110. #define RFD_ERRMASK 0x0fe1 /* status: errormask */
  111. #define RFD_MATCHADD 0x0002 /* status: Destinationaddress !matches IA */
  112. #define RFD_RNR 0x0200 /* status: receiver out of resources */
  113. /*
  114. * Receive Buffer Descriptor (RBD)
  115. */
  116. struct rbd_struct
  117. {
  118. unsigned short status; /* status word,number of used bytes in buff */
  119. unsigned short next; /* pointeroffset to next RBD */
  120. char *buffer; /* receive buffer address pointer */
  121. unsigned short size; /* size of this buffer */
  122. unsigned short zero_dummy; /* dummy */
  123. };
  124. #define RBD_LAST 0x8000 /* last buffer */
  125. #define RBD_USED 0x4000 /* this buffer has data */
  126. #define RBD_MASK 0x3fff /* size-mask for length */
  127. /*
  128. * Statusvalues for Commands/RFD
  129. */
  130. #define STAT_COMPL 0x8000 /* status: frame/command is complete */
  131. #define STAT_BUSY 0x4000 /* status: frame/command is busy */
  132. #define STAT_OK 0x2000 /* status: frame/command is ok */
  133. /*
  134. * Action-Commands
  135. */
  136. #define CMD_NOP 0x0000 /* NOP */
  137. #define CMD_IASETUP 0x0001 /* initial address setup command */
  138. #define CMD_CONFIGURE 0x0002 /* configure command */
  139. #define CMD_MCSETUP 0x0003 /* MC setup command */
  140. #define CMD_XMIT 0x0004 /* transmit command */
  141. #define CMD_TDR 0x0005 /* time domain reflectometer (TDR) command */
  142. #define CMD_DUMP 0x0006 /* dump command */
  143. #define CMD_DIAGNOSE 0x0007 /* diagnose command */
  144. /*
  145. * Action command bits
  146. */
  147. #define CMD_LAST 0x8000 /* indicates last command in the CBL */
  148. #define CMD_SUSPEND 0x4000 /* suspend CU after this CB */
  149. #define CMD_INT 0x2000 /* generate interrupt after execution */
  150. /*
  151. * NOP - command
  152. */
  153. struct nop_cmd_struct
  154. {
  155. unsigned short cmd_status; /* status of this command */
  156. unsigned short cmd_cmd; /* the command itself (+bits) */
  157. unsigned short cmd_link; /* offsetpointer to next command */
  158. };
  159. /*
  160. * IA Setup command
  161. */
  162. struct iasetup_cmd_struct
  163. {
  164. unsigned short cmd_status;
  165. unsigned short cmd_cmd;
  166. unsigned short cmd_link;
  167. unsigned char iaddr[6];
  168. };
  169. /*
  170. * Configure command
  171. */
  172. struct configure_cmd_struct
  173. {
  174. unsigned short cmd_status;
  175. unsigned short cmd_cmd;
  176. unsigned short cmd_link;
  177. unsigned char byte_cnt; /* size of the config-cmd */
  178. unsigned char fifo; /* fifo/recv monitor */
  179. unsigned char sav_bf; /* save bad frames (bit7=1)*/
  180. unsigned char adr_len; /* adr_len(0-2),al_loc(3),pream(4-5),loopbak(6-7)*/
  181. unsigned char priority; /* lin_prio(0-2),exp_prio(4-6),bof_metd(7) */
  182. unsigned char ifs; /* inter frame spacing */
  183. unsigned char time_low; /* slot time low */
  184. unsigned char time_high; /* slot time high(0-2) and max. retries(4-7) */
  185. unsigned char promisc; /* promisc-mode(0) , et al (1-7) */
  186. unsigned char carr_coll; /* carrier(0-3)/collision(4-7) stuff */
  187. unsigned char fram_len; /* minimal frame len */
  188. unsigned char dummy; /* dummy */
  189. };
  190. /*
  191. * Multicast Setup command
  192. */
  193. struct mcsetup_cmd_struct
  194. {
  195. unsigned short cmd_status;
  196. unsigned short cmd_cmd;
  197. unsigned short cmd_link;
  198. unsigned short mc_cnt; /* number of bytes in the MC-List */
  199. unsigned char mc_list[0][6]; /* pointer to 6 bytes entries */
  200. };
  201. /*
  202. * transmit command
  203. */
  204. struct transmit_cmd_struct
  205. {
  206. unsigned short cmd_status;
  207. unsigned short cmd_cmd;
  208. unsigned short cmd_link;
  209. unsigned short tbd_offset; /* pointeroffset to TBD */
  210. unsigned char dest[6]; /* destination address of the frame */
  211. unsigned short length; /* user defined: 802.3 length / Ether type */
  212. };
  213. #define TCMD_ERRMASK 0x0fa0
  214. #define TCMD_MAXCOLLMASK 0x000f
  215. #define TCMD_MAXCOLL 0x0020
  216. #define TCMD_HEARTBEAT 0x0040
  217. #define TCMD_DEFERRED 0x0080
  218. #define TCMD_UNDERRUN 0x0100
  219. #define TCMD_LOSTCTS 0x0200
  220. #define TCMD_NOCARRIER 0x0400
  221. #define TCMD_LATECOLL 0x0800
  222. struct tdr_cmd_struct
  223. {
  224. unsigned short cmd_status;
  225. unsigned short cmd_cmd;
  226. unsigned short cmd_link;
  227. unsigned short status;
  228. };
  229. #define TDR_LNK_OK 0x8000 /* No link problem identified */
  230. #define TDR_XCVR_PRB 0x4000 /* indicates a transceiver problem */
  231. #define TDR_ET_OPN 0x2000 /* open, no correct termination */
  232. #define TDR_ET_SRT 0x1000 /* TDR detected a short circuit */
  233. #define TDR_TIMEMASK 0x07ff /* mask for the time field */
  234. /*
  235. * Transmit Buffer Descriptor (TBD)
  236. */
  237. struct tbd_struct
  238. {
  239. unsigned short size; /* size + EOF-Flag(15) */
  240. unsigned short next; /* pointeroffset to next TBD */
  241. char *buffer; /* pointer to buffer */
  242. };
  243. #define TBD_LAST 0x8000 /* EOF-Flag, indicates last buffer in list */
  244. /*************************************************************************/
  245. /*
  246. Verbatim from the Crynwyr stuff:
  247. The 3c523 responds with adapter code 0x6042 at slot
  248. registers xxx0 and xxx1. The setup register is at xxx2 and
  249. contains the following bits:
  250. 0: card enable
  251. 2,1: csr address select
  252. 00 = 0300
  253. 01 = 1300
  254. 10 = 2300
  255. 11 = 3300
  256. 4,3: shared memory address select
  257. 00 = 0c0000
  258. 01 = 0c8000
  259. 10 = 0d0000
  260. 11 = 0d8000
  261. 5: set to disable on-board thinnet
  262. 7,6: (read-only) shows selected irq
  263. 00 = 12
  264. 01 = 7
  265. 10 = 3
  266. 11 = 9
  267. The interrupt-select register is at xxx3 and uses one bit per irq.
  268. 0: int 12
  269. 1: int 7
  270. 2: int 3
  271. 3: int 9
  272. Again, the documentation stresses that the setup register
  273. should never be written. The interrupt-select register may be
  274. written with the value corresponding to bits 7.6 in
  275. the setup register to insure corret setup.
  276. */
  277. /* Offsets from the base I/O address. */
  278. #define ELMC_SA 0 /* first 6 bytes are IEEE network address */
  279. #define ELMC_CTRL 6 /* control & status register */
  280. #define ELMC_REVISION 7 /* revision register, first 4 bits only */
  281. #define ELMC_IO_EXTENT 8
  282. /* these are the bit selects for the port register 2 */
  283. #define ELMC_STATUS_ENABLED 0x01
  284. #define ELMC_STATUS_CSR_SELECT 0x06
  285. #define ELMC_STATUS_MEMORY_SELECT 0x18
  286. #define ELMC_STATUS_DISABLE_THIN 0x20
  287. #define ELMC_STATUS_IRQ_SELECT 0xc0
  288. /* this is the card id used in the detection code. You might recognize
  289. it from @6042.adf */
  290. #define ELMC_MCA_ID 0x6042
  291. /*
  292. The following define the bits for the control & status register
  293. The bank select registers can be used if more than 16K of memory is
  294. on the card. For some stupid reason, bank 3 is the one for the
  295. bottom 16K, and the card defaults to bank 0. So we have to set the
  296. bank to 3 before the card will even think of operating. To get bank
  297. 3, set BS0 and BS1 to high (of course...)
  298. */
  299. #define ELMC_CTRL_BS0 0x01 /* RW bank select */
  300. #define ELMC_CTRL_BS1 0x02 /* RW bank select */
  301. #define ELMC_CTRL_INTE 0x04 /* RW interrupt enable, assert high */
  302. #define ELMC_CTRL_INT 0x08 /* R interrupt active, assert high */
  303. /*#define ELMC_CTRL_* 0x10*/ /* reserved */
  304. #define ELMC_CTRL_LBK 0x20 /* RW loopback enable, assert high */
  305. #define ELMC_CTRL_CA 0x40 /* RW channel attention, assert high */
  306. #define ELMC_CTRL_RST 0x80 /* RW 82586 reset, assert low */
  307. /* some handy compound bits */
  308. /* normal operation should have bank 3 and RST high, ints enabled */
  309. #define ELMC_NORMAL (ELMC_CTRL_INTE|ELMC_CTRL_RST|0x3)
  310. #endif /* _3c523_INCLUDE_ */