vmx.h 12 KB

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  1. #ifndef VMX_H
  2. #define VMX_H
  3. /*
  4. * vmx.h: VMX Architecture related definitions
  5. * Copyright (c) 2004, Intel Corporation.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  18. * Place - Suite 330, Boston, MA 02111-1307 USA.
  19. *
  20. * A few random additions are:
  21. * Copyright (C) 2006 Qumranet
  22. * Avi Kivity <avi@qumranet.com>
  23. * Yaniv Kamay <yaniv@qumranet.com>
  24. *
  25. */
  26. #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
  27. #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
  28. #define CPU_BASED_HLT_EXITING 0x00000080
  29. #define CPU_BASED_INVDPG_EXITING 0x00000200
  30. #define CPU_BASED_MWAIT_EXITING 0x00000400
  31. #define CPU_BASED_RDPMC_EXITING 0x00000800
  32. #define CPU_BASED_RDTSC_EXITING 0x00001000
  33. #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
  34. #define CPU_BASED_CR8_STORE_EXITING 0x00100000
  35. #define CPU_BASED_TPR_SHADOW 0x00200000
  36. #define CPU_BASED_MOV_DR_EXITING 0x00800000
  37. #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
  38. #define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000
  39. #define CPU_BASED_MSR_BITMAPS 0x10000000
  40. #define CPU_BASED_MONITOR_EXITING 0x20000000
  41. #define CPU_BASED_PAUSE_EXITING 0x40000000
  42. #define PIN_BASED_EXT_INTR_MASK 0x1
  43. #define PIN_BASED_NMI_EXITING 0x8
  44. #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
  45. #define VM_EXIT_HOST_ADD_SPACE_SIZE 0x00000200
  46. /* VMCS Encodings */
  47. enum vmcs_field {
  48. GUEST_ES_SELECTOR = 0x00000800,
  49. GUEST_CS_SELECTOR = 0x00000802,
  50. GUEST_SS_SELECTOR = 0x00000804,
  51. GUEST_DS_SELECTOR = 0x00000806,
  52. GUEST_FS_SELECTOR = 0x00000808,
  53. GUEST_GS_SELECTOR = 0x0000080a,
  54. GUEST_LDTR_SELECTOR = 0x0000080c,
  55. GUEST_TR_SELECTOR = 0x0000080e,
  56. HOST_ES_SELECTOR = 0x00000c00,
  57. HOST_CS_SELECTOR = 0x00000c02,
  58. HOST_SS_SELECTOR = 0x00000c04,
  59. HOST_DS_SELECTOR = 0x00000c06,
  60. HOST_FS_SELECTOR = 0x00000c08,
  61. HOST_GS_SELECTOR = 0x00000c0a,
  62. HOST_TR_SELECTOR = 0x00000c0c,
  63. IO_BITMAP_A = 0x00002000,
  64. IO_BITMAP_A_HIGH = 0x00002001,
  65. IO_BITMAP_B = 0x00002002,
  66. IO_BITMAP_B_HIGH = 0x00002003,
  67. MSR_BITMAP = 0x00002004,
  68. MSR_BITMAP_HIGH = 0x00002005,
  69. VM_EXIT_MSR_STORE_ADDR = 0x00002006,
  70. VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
  71. VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
  72. VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
  73. VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
  74. VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
  75. TSC_OFFSET = 0x00002010,
  76. TSC_OFFSET_HIGH = 0x00002011,
  77. VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
  78. VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
  79. VMCS_LINK_POINTER = 0x00002800,
  80. VMCS_LINK_POINTER_HIGH = 0x00002801,
  81. GUEST_IA32_DEBUGCTL = 0x00002802,
  82. GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
  83. PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
  84. CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
  85. EXCEPTION_BITMAP = 0x00004004,
  86. PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
  87. PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
  88. CR3_TARGET_COUNT = 0x0000400a,
  89. VM_EXIT_CONTROLS = 0x0000400c,
  90. VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
  91. VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
  92. VM_ENTRY_CONTROLS = 0x00004012,
  93. VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
  94. VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
  95. VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
  96. VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
  97. TPR_THRESHOLD = 0x0000401c,
  98. SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
  99. VM_INSTRUCTION_ERROR = 0x00004400,
  100. VM_EXIT_REASON = 0x00004402,
  101. VM_EXIT_INTR_INFO = 0x00004404,
  102. VM_EXIT_INTR_ERROR_CODE = 0x00004406,
  103. IDT_VECTORING_INFO_FIELD = 0x00004408,
  104. IDT_VECTORING_ERROR_CODE = 0x0000440a,
  105. VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
  106. VMX_INSTRUCTION_INFO = 0x0000440e,
  107. GUEST_ES_LIMIT = 0x00004800,
  108. GUEST_CS_LIMIT = 0x00004802,
  109. GUEST_SS_LIMIT = 0x00004804,
  110. GUEST_DS_LIMIT = 0x00004806,
  111. GUEST_FS_LIMIT = 0x00004808,
  112. GUEST_GS_LIMIT = 0x0000480a,
  113. GUEST_LDTR_LIMIT = 0x0000480c,
  114. GUEST_TR_LIMIT = 0x0000480e,
  115. GUEST_GDTR_LIMIT = 0x00004810,
  116. GUEST_IDTR_LIMIT = 0x00004812,
  117. GUEST_ES_AR_BYTES = 0x00004814,
  118. GUEST_CS_AR_BYTES = 0x00004816,
  119. GUEST_SS_AR_BYTES = 0x00004818,
  120. GUEST_DS_AR_BYTES = 0x0000481a,
  121. GUEST_FS_AR_BYTES = 0x0000481c,
  122. GUEST_GS_AR_BYTES = 0x0000481e,
  123. GUEST_LDTR_AR_BYTES = 0x00004820,
  124. GUEST_TR_AR_BYTES = 0x00004822,
  125. GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
  126. GUEST_ACTIVITY_STATE = 0X00004826,
  127. GUEST_SYSENTER_CS = 0x0000482A,
  128. HOST_IA32_SYSENTER_CS = 0x00004c00,
  129. CR0_GUEST_HOST_MASK = 0x00006000,
  130. CR4_GUEST_HOST_MASK = 0x00006002,
  131. CR0_READ_SHADOW = 0x00006004,
  132. CR4_READ_SHADOW = 0x00006006,
  133. CR3_TARGET_VALUE0 = 0x00006008,
  134. CR3_TARGET_VALUE1 = 0x0000600a,
  135. CR3_TARGET_VALUE2 = 0x0000600c,
  136. CR3_TARGET_VALUE3 = 0x0000600e,
  137. EXIT_QUALIFICATION = 0x00006400,
  138. GUEST_LINEAR_ADDRESS = 0x0000640a,
  139. GUEST_CR0 = 0x00006800,
  140. GUEST_CR3 = 0x00006802,
  141. GUEST_CR4 = 0x00006804,
  142. GUEST_ES_BASE = 0x00006806,
  143. GUEST_CS_BASE = 0x00006808,
  144. GUEST_SS_BASE = 0x0000680a,
  145. GUEST_DS_BASE = 0x0000680c,
  146. GUEST_FS_BASE = 0x0000680e,
  147. GUEST_GS_BASE = 0x00006810,
  148. GUEST_LDTR_BASE = 0x00006812,
  149. GUEST_TR_BASE = 0x00006814,
  150. GUEST_GDTR_BASE = 0x00006816,
  151. GUEST_IDTR_BASE = 0x00006818,
  152. GUEST_DR7 = 0x0000681a,
  153. GUEST_RSP = 0x0000681c,
  154. GUEST_RIP = 0x0000681e,
  155. GUEST_RFLAGS = 0x00006820,
  156. GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
  157. GUEST_SYSENTER_ESP = 0x00006824,
  158. GUEST_SYSENTER_EIP = 0x00006826,
  159. HOST_CR0 = 0x00006c00,
  160. HOST_CR3 = 0x00006c02,
  161. HOST_CR4 = 0x00006c04,
  162. HOST_FS_BASE = 0x00006c06,
  163. HOST_GS_BASE = 0x00006c08,
  164. HOST_TR_BASE = 0x00006c0a,
  165. HOST_GDTR_BASE = 0x00006c0c,
  166. HOST_IDTR_BASE = 0x00006c0e,
  167. HOST_IA32_SYSENTER_ESP = 0x00006c10,
  168. HOST_IA32_SYSENTER_EIP = 0x00006c12,
  169. HOST_RSP = 0x00006c14,
  170. HOST_RIP = 0x00006c16,
  171. };
  172. #define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
  173. #define EXIT_REASON_EXCEPTION_NMI 0
  174. #define EXIT_REASON_EXTERNAL_INTERRUPT 1
  175. #define EXIT_REASON_TRIPLE_FAULT 2
  176. #define EXIT_REASON_PENDING_INTERRUPT 7
  177. #define EXIT_REASON_TASK_SWITCH 9
  178. #define EXIT_REASON_CPUID 10
  179. #define EXIT_REASON_HLT 12
  180. #define EXIT_REASON_INVLPG 14
  181. #define EXIT_REASON_RDPMC 15
  182. #define EXIT_REASON_RDTSC 16
  183. #define EXIT_REASON_VMCALL 18
  184. #define EXIT_REASON_VMCLEAR 19
  185. #define EXIT_REASON_VMLAUNCH 20
  186. #define EXIT_REASON_VMPTRLD 21
  187. #define EXIT_REASON_VMPTRST 22
  188. #define EXIT_REASON_VMREAD 23
  189. #define EXIT_REASON_VMRESUME 24
  190. #define EXIT_REASON_VMWRITE 25
  191. #define EXIT_REASON_VMOFF 26
  192. #define EXIT_REASON_VMON 27
  193. #define EXIT_REASON_CR_ACCESS 28
  194. #define EXIT_REASON_DR_ACCESS 29
  195. #define EXIT_REASON_IO_INSTRUCTION 30
  196. #define EXIT_REASON_MSR_READ 31
  197. #define EXIT_REASON_MSR_WRITE 32
  198. #define EXIT_REASON_MWAIT_INSTRUCTION 36
  199. /*
  200. * Interruption-information format
  201. */
  202. #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
  203. #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
  204. #define INTR_INFO_DELIEVER_CODE_MASK 0x800 /* 11 */
  205. #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
  206. #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
  207. #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
  208. #define VECTORING_INFO_DELIEVER_CODE_MASK INTR_INFO_DELIEVER_CODE_MASK
  209. #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
  210. #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
  211. #define INTR_TYPE_EXCEPTION (3 << 8) /* processor exception */
  212. /*
  213. * Exit Qualifications for MOV for Control Register Access
  214. */
  215. #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control register */
  216. #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
  217. #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose register */
  218. #define LMSW_SOURCE_DATA_SHIFT 16
  219. #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
  220. #define REG_EAX (0 << 8)
  221. #define REG_ECX (1 << 8)
  222. #define REG_EDX (2 << 8)
  223. #define REG_EBX (3 << 8)
  224. #define REG_ESP (4 << 8)
  225. #define REG_EBP (5 << 8)
  226. #define REG_ESI (6 << 8)
  227. #define REG_EDI (7 << 8)
  228. #define REG_R8 (8 << 8)
  229. #define REG_R9 (9 << 8)
  230. #define REG_R10 (10 << 8)
  231. #define REG_R11 (11 << 8)
  232. #define REG_R12 (12 << 8)
  233. #define REG_R13 (13 << 8)
  234. #define REG_R14 (14 << 8)
  235. #define REG_R15 (15 << 8)
  236. /*
  237. * Exit Qualifications for MOV for Debug Register Access
  238. */
  239. #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug register */
  240. #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
  241. #define TYPE_MOV_TO_DR (0 << 4)
  242. #define TYPE_MOV_FROM_DR (1 << 4)
  243. #define DEBUG_REG_ACCESS_REG 0xf00 /* 11:8, general purpose register */
  244. /* segment AR */
  245. #define SEGMENT_AR_L_MASK (1 << 13)
  246. /* entry controls */
  247. #define VM_ENTRY_CONTROLS_IA32E_MASK (1 << 9)
  248. #define AR_TYPE_ACCESSES_MASK 1
  249. #define AR_TYPE_READABLE_MASK (1 << 1)
  250. #define AR_TYPE_WRITEABLE_MASK (1 << 2)
  251. #define AR_TYPE_CODE_MASK (1 << 3)
  252. #define AR_TYPE_MASK 0x0f
  253. #define AR_TYPE_BUSY_64_TSS 11
  254. #define AR_TYPE_BUSY_32_TSS 11
  255. #define AR_TYPE_BUSY_16_TSS 3
  256. #define AR_TYPE_LDT 2
  257. #define AR_UNUSABLE_MASK (1 << 16)
  258. #define AR_S_MASK (1 << 4)
  259. #define AR_P_MASK (1 << 7)
  260. #define AR_L_MASK (1 << 13)
  261. #define AR_DB_MASK (1 << 14)
  262. #define AR_G_MASK (1 << 15)
  263. #define AR_DPL_SHIFT 5
  264. #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
  265. #define AR_RESERVD_MASK 0xfffe0f00
  266. #define CR4_VMXE 0x2000
  267. #define MSR_IA32_VMX_BASIC 0x480
  268. #define MSR_IA32_FEATURE_CONTROL 0x03a
  269. #define MSR_IA32_VMX_PINBASED_CTLS 0x481
  270. #define MSR_IA32_VMX_PROCBASED_CTLS 0x482
  271. #define MSR_IA32_VMX_EXIT_CTLS 0x483
  272. #define MSR_IA32_VMX_ENTRY_CTLS 0x484
  273. #endif