dcdbas.h 2.8 KB

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  1. /*
  2. * dcdbas.h: Definitions for Dell Systems Management Base driver
  3. *
  4. * Copyright (C) 1995-2005 Dell Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License v2.0 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #ifndef _DCDBAS_H_
  16. #define _DCDBAS_H_
  17. #include <linux/device.h>
  18. #include <linux/input.h>
  19. #include <linux/sysfs.h>
  20. #include <linux/types.h>
  21. #define MAX_SMI_DATA_BUF_SIZE (256 * 1024)
  22. #define HC_ACTION_NONE (0)
  23. #define HC_ACTION_HOST_CONTROL_POWEROFF BIT(1)
  24. #define HC_ACTION_HOST_CONTROL_POWERCYCLE BIT(2)
  25. #define HC_SMITYPE_NONE (0)
  26. #define HC_SMITYPE_TYPE1 (1)
  27. #define HC_SMITYPE_TYPE2 (2)
  28. #define HC_SMITYPE_TYPE3 (3)
  29. #define ESM_APM_CMD (0x0A0)
  30. #define ESM_APM_POWER_CYCLE (0x10)
  31. #define ESM_STATUS_CMD_UNSUCCESSFUL (-1)
  32. #define CMOS_BASE_PORT (0x070)
  33. #define CMOS_PAGE1_INDEX_PORT (0)
  34. #define CMOS_PAGE1_DATA_PORT (1)
  35. #define CMOS_PAGE2_INDEX_PORT_PIIX4 (2)
  36. #define CMOS_PAGE2_DATA_PORT_PIIX4 (3)
  37. #define PE1400_APM_CONTROL_PORT (0x0B0)
  38. #define PCAT_APM_CONTROL_PORT (0x0B2)
  39. #define PCAT_APM_STATUS_PORT (0x0B3)
  40. #define PE1300_CMOS_CMD_STRUCT_PTR (0x38)
  41. #define PE1400_CMOS_CMD_STRUCT_PTR (0x70)
  42. #define MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN (14)
  43. #define MAX_SYSMGMT_LONGCMD_SGENTRY_NUM (16)
  44. #define TIMEOUT_USEC_SHORT_SEMA_BLOCKING (10000)
  45. #define EXPIRED_TIMER (0)
  46. #define SMI_CMD_MAGIC (0x534D4931)
  47. #define DCDBAS_DEV_ATTR_RW(_name) \
  48. DEVICE_ATTR(_name,0600,_name##_show,_name##_store);
  49. #define DCDBAS_DEV_ATTR_RO(_name) \
  50. DEVICE_ATTR(_name,0400,_name##_show,NULL);
  51. #define DCDBAS_DEV_ATTR_WO(_name) \
  52. DEVICE_ATTR(_name,0200,NULL,_name##_store);
  53. #define DCDBAS_BIN_ATTR_RW(_name) \
  54. struct bin_attribute bin_attr_##_name = { \
  55. .attr = { .name = __stringify(_name), \
  56. .mode = 0600, \
  57. .owner = THIS_MODULE }, \
  58. .read = _name##_read, \
  59. .write = _name##_write, \
  60. }
  61. struct smi_cmd {
  62. __u32 magic;
  63. __u32 ebx;
  64. __u32 ecx;
  65. __u16 command_address;
  66. __u8 command_code;
  67. __u8 reserved;
  68. __u8 command_buffer[1];
  69. } __attribute__ ((packed));
  70. struct apm_cmd {
  71. __u8 command;
  72. __s8 status;
  73. __u16 reserved;
  74. union {
  75. struct {
  76. __u8 parm[MAX_SYSMGMT_SHORTCMD_PARMBUF_LEN];
  77. } __attribute__ ((packed)) shortreq;
  78. struct {
  79. __u16 num_sg_entries;
  80. struct {
  81. __u32 size;
  82. __u64 addr;
  83. } __attribute__ ((packed))
  84. sglist[MAX_SYSMGMT_LONGCMD_SGENTRY_NUM];
  85. } __attribute__ ((packed)) longreq;
  86. } __attribute__ ((packed)) parameters;
  87. } __attribute__ ((packed));
  88. #endif /* _DCDBAS_H_ */