cyclone.c 3.0 KB

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  1. #include <linux/clocksource.h>
  2. #include <linux/string.h>
  3. #include <linux/errno.h>
  4. #include <linux/timex.h>
  5. #include <linux/init.h>
  6. #include <asm/pgtable.h>
  7. #include <asm/io.h>
  8. #include "mach_timer.h"
  9. #define CYCLONE_CBAR_ADDR 0xFEB00CD0 /* base address ptr */
  10. #define CYCLONE_PMCC_OFFSET 0x51A0 /* offset to control register */
  11. #define CYCLONE_MPCS_OFFSET 0x51A8 /* offset to select register */
  12. #define CYCLONE_MPMC_OFFSET 0x51D0 /* offset to count register */
  13. #define CYCLONE_TIMER_FREQ 99780000 /* 100Mhz, but not really */
  14. #define CYCLONE_TIMER_MASK CLOCKSOURCE_MASK(32) /* 32 bit mask */
  15. int use_cyclone = 0;
  16. static void __iomem *cyclone_ptr;
  17. static cycle_t read_cyclone(void)
  18. {
  19. return (cycle_t)readl(cyclone_ptr);
  20. }
  21. static struct clocksource clocksource_cyclone = {
  22. .name = "cyclone",
  23. .rating = 250,
  24. .read = read_cyclone,
  25. .mask = CYCLONE_TIMER_MASK,
  26. .mult = 10,
  27. .shift = 0,
  28. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  29. };
  30. static int __init init_cyclone_clocksource(void)
  31. {
  32. unsigned long base; /* saved value from CBAR */
  33. unsigned long offset;
  34. u32 __iomem* volatile cyclone_timer; /* Cyclone MPMC0 register */
  35. u32 __iomem* reg;
  36. int i;
  37. /* make sure we're on a summit box: */
  38. if (!use_cyclone)
  39. return -ENODEV;
  40. printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
  41. /* find base address: */
  42. offset = CYCLONE_CBAR_ADDR;
  43. reg = ioremap_nocache(offset, sizeof(reg));
  44. if (!reg) {
  45. printk(KERN_ERR "Summit chipset: Could not find valid CBAR register.\n");
  46. return -ENODEV;
  47. }
  48. /* even on 64bit systems, this is only 32bits: */
  49. base = readl(reg);
  50. if (!base) {
  51. printk(KERN_ERR "Summit chipset: Could not find valid CBAR value.\n");
  52. return -ENODEV;
  53. }
  54. iounmap(reg);
  55. /* setup PMCC: */
  56. offset = base + CYCLONE_PMCC_OFFSET;
  57. reg = ioremap_nocache(offset, sizeof(reg));
  58. if (!reg) {
  59. printk(KERN_ERR "Summit chipset: Could not find valid PMCC register.\n");
  60. return -ENODEV;
  61. }
  62. writel(0x00000001,reg);
  63. iounmap(reg);
  64. /* setup MPCS: */
  65. offset = base + CYCLONE_MPCS_OFFSET;
  66. reg = ioremap_nocache(offset, sizeof(reg));
  67. if (!reg) {
  68. printk(KERN_ERR "Summit chipset: Could not find valid MPCS register.\n");
  69. return -ENODEV;
  70. }
  71. writel(0x00000001,reg);
  72. iounmap(reg);
  73. /* map in cyclone_timer: */
  74. offset = base + CYCLONE_MPMC_OFFSET;
  75. cyclone_timer = ioremap_nocache(offset, sizeof(u64));
  76. if (!cyclone_timer) {
  77. printk(KERN_ERR "Summit chipset: Could not find valid MPMC register.\n");
  78. return -ENODEV;
  79. }
  80. /* quick test to make sure its ticking: */
  81. for (i = 0; i < 3; i++){
  82. u32 old = readl(cyclone_timer);
  83. int stall = 100;
  84. while (stall--)
  85. barrier();
  86. if (readl(cyclone_timer) == old) {
  87. printk(KERN_ERR "Summit chipset: Counter not counting! DISABLED\n");
  88. iounmap(cyclone_timer);
  89. cyclone_timer = NULL;
  90. return -ENODEV;
  91. }
  92. }
  93. cyclone_ptr = cyclone_timer;
  94. /* sort out mult/shift values: */
  95. clocksource_cyclone.shift = 22;
  96. clocksource_cyclone.mult = clocksource_hz2mult(CYCLONE_TIMER_FREQ,
  97. clocksource_cyclone.shift);
  98. return clocksource_register(&clocksource_cyclone);
  99. }
  100. arch_initcall(init_cyclone_clocksource);